arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/clock/rk3399-cru.h>
  43 #include <dt-bindings/gpio/gpio.h>
  44 #include <dt-bindings/interrupt-controller/arm-gic.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/pinctrl/rockchip.h>
  47 #include <dt-bindings/thermal/thermal.h>
  48
  49 / {
  50         compatible = "rockchip,rk3399";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 i2c6 = &i2c6;
  63                 i2c7 = &i2c7;
  64                 i2c8 = &i2c8;
  65                 serial0 = &uart0;
  66                 serial1 = &uart1;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69         };
  70
  71         cpus {
  72                 #address-cells = <2>;
  73                 #size-cells = <0>;
  74
  75                 cpu-map {
  76                         cluster0 {
  77                                 core0 {
  78                                         cpu = <&cpu_l0>;
  79                                 };
  80                                 core1 {
  81                                         cpu = <&cpu_l1>;
  82                                 };
  83                                 core2 {
  84                                         cpu = <&cpu_l2>;
  85                                 };
  86                                 core3 {
  87                                         cpu = <&cpu_l3>;
  88                                 };
  89                         };
  90
  91                         cluster1 {
  92                                 core0 {
  93                                         cpu = <&cpu_b0>;
  94                                 };
  95                                 core1 {
  96                                         cpu = <&cpu_b1>;
  97                                 };
  98                         };
  99                 };
 100
 101                 cpu_l0: cpu@0 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53", "arm,armv8";
 104                         reg = <0x0 0x0>;
 105
 106                         #cooling-cells = <2>; /* min followed by max */
 107                 };
 108
 109                 cpu_l1: cpu@1 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x1>;
 113                 };
 114
 115                 cpu_l2: cpu@2 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x2>;
 119                 };
 120
 121                 cpu_l3: cpu@3 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a53", "arm,armv8";
 124                         reg = <0x0 0x3>;
 125                 };
 126
 127                 cpu_b0: cpu@100 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a72", "arm,armv8";
 130                         reg = <0x0 0x100>;
 131
 132                         #cooling-cells = <2>; /* min followed by max */
 133                 };
 134
 135                 cpu_b1: cpu@101 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a72", "arm,armv8";
 138                         reg = <0x0 0x101>;
 139                 };
 140         };
 141
 142         timer {
 143                 compatible = "arm,armv8-timer";
 144                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
 145                              <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
 148         };
 149
 150         xin24m: xin24m {
 151                 compatible = "fixed-clock";
 152                 #clock-cells = <0>;
 153                 clock-frequency = <24000000>;
 154                 clock-output-names = "xin24m";
 155         };
 156
 157         gic: interrupt-controller@fee00000 {
 158                 compatible = "arm,gic-v3";
 159                 #interrupt-cells = <3>;
 160                 #address-cells = <2>;
 161                 #size-cells = <2>;
 162                 ranges;
 163                 interrupt-controller;
 164
 165                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 166                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 167                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 168                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 169                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 170                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 171                 its: interrupt-controller@fee20000 {
 172                         compatible = "arm,gic-v3-its";
 173                         msi-controller;
 174                         reg = <0x0 0xfee20000 0x0 0x20000>;
 175                 };
 176         };
 177
 178         amba {
 179                 compatible = "arm,amba-bus";
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 ranges;
 183
 184                 dmac_bus: dma-controller@ff6d0000 {
 185                         compatible = "arm,pl330", "arm,primecell";
 186                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 187                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 188                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 189                         #dma-cells = <1>;
 190                         clocks = <&cru ACLK_DMAC0_PERILP>;
 191                         clock-names = "apb_pclk";
 192                 };
 193
 194                 dmac_peri: dma-controller@ff6e0000 {
 195                         compatible = "arm,pl330", "arm,primecell";
 196                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 197                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 198                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 199                         #dma-cells = <1>;
 200                         clocks = <&cru ACLK_DMAC1_PERILP>;
 201                         clock-names = "apb_pclk";
 202                 };
 203         };
 204
 205         saradc: saradc@ff100000 {
 206                 compatible = "rockchip,rk3399-saradc";
 207                 reg = <0x0 0xff100000 0x0 0x100>;
 208                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 209                 #io-channel-cells = <1>;
 210                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 211                 clock-names = "saradc", "apb_pclk";
 212                 status = "disabled";
 213         };
 214
 215         i2c0: i2c@ff3c0000 {
 216                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 217                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 218                 clocks = <&cru PCLK_I2C0_PMU>, <&cru SCLK_I2C0_PMU>;
 219                 clock-names = "i2c", "i2c_sclk";
 220                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 221                 pinctrl-names = "default";
 222                 pinctrl-0 = <&i2c0_xfer>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 status = "disabled";
 226         };
 227
 228         i2c1: i2c@ff110000 {
 229                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru PCLK_I2C1>, <&cru SCLK_I2C1>;
 232                 clock-names = "i2c", "i2c_sclk";
 233                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&i2c1_xfer>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         i2c2: i2c@ff120000 {
 242                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru PCLK_I2C2>, <&cru SCLK_I2C2>;
 245                 clock-names = "i2c", "i2c_sclk";
 246                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&i2c2_xfer>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         i2c3: i2c@ff130000 {
 255                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 256                 reg = <0x0 0xff130000 0x0 0x1000>;
 257                 clocks = <&cru PCLK_I2C3>, <&cru SCLK_I2C3>;
 258                 clock-names = "i2c", "i2c_sclk";
 259                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&i2c3_xfer>;
 262                 #address-cells = <1>;
 263                 #size-cells = <0>;
 264                 status = "disabled";
 265         };
 266
 267         i2c5: i2c@ff140000 {
 268                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 269                 reg = <0x0 0xff140000 0x0 0x1000>;
 270                 clocks = <&cru PCLK_I2C5>, <&cru SCLK_I2C5>;
 271                 clock-names = "i2c", "i2c_sclk";
 272                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&i2c5_xfer>;
 275                 #address-cells = <1>;
 276                 #size-cells = <0>;
 277                 status = "disabled";
 278         };
 279
 280         i2c6: i2c@ff150000 {
 281                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 282                 reg = <0x0 0xff150000 0x0 0x1000>;
 283                 clocks = <&cru PCLK_I2C6>, <&cru SCLK_I2C6>;
 284                 clock-names = "i2c", "i2c_sclk";
 285                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&i2c6_xfer>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 status = "disabled";
 291         };
 292
 293         i2c7: i2c@ff160000 {
 294                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 295                 reg = <0x0 0xff160000 0x0 0x1000>;
 296                 clocks = <&cru PCLK_I2C7>, <&cru SCLK_I2C7>;
 297                 clock-names = "i2c", "i2c_sclk";
 298                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&i2c7_xfer>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 status = "disabled";
 304         };
 305
 306         uart0: serial@ff180000 {
 307                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 308                 reg = <0x0 0xff180000 0x0 0x100>;
 309                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 310                 clock-names = "baudclk", "apb_pclk";
 311                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 312                 reg-shift = <2>;
 313                 reg-io-width = <4>;
 314                 status = "disabled";
 315         };
 316
 317         uart1: serial@ff190000 {
 318                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 319                 reg = <0x0 0xff190000 0x0 0x100>;
 320                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 321                 clock-names = "baudclk", "apb_pclk";
 322                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 323                 reg-shift = <2>;
 324                 reg-io-width = <4>;
 325                 status = "disabled";
 326         };
 327
 328         uart2: serial@ff1a0000 {
 329                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 330                 reg = <0x0 0xff1a0000 0x0 0x100>;
 331                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 332                 clock-names = "baudclk", "apb_pclk";
 333                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 334                 reg-shift = <2>;
 335                 reg-io-width = <4>;
 336                 status = "disabled";
 337         };
 338
 339         uart3: serial@ff1b0000 {
 340                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 341                 reg = <0x0 0xff1b0000 0x0 0x100>;
 342                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 345                 reg-shift = <2>;
 346                 reg-io-width = <4>;
 347                 status = "disabled";
 348         };
 349
 350         spi0: spi@ff1c0000 {
 351                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 352                 reg = <0x0 0xff110000 0x0 0x1000>;
 353                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 354                 clock-names = "spiclk", "apb_pclk";
 355                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 356                 pinctrl-names = "default";
 357                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 status = "disabled";
 361         };
 362
 363         spi1: spi@ff1d0000 {
 364                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 365                 reg = <0x0 0xff120000 0x0 0x1000>;
 366                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 367                 clock-names = "spiclk", "apb_pclk";
 368                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 371                 #address-cells = <1>;
 372                 #size-cells = <0>;
 373                 status = "disabled";
 374         };
 375
 376         spi2: spi@ff1e0000 {
 377                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 378                 reg = <0x0 0xff130000 0x0 0x1000>;
 379                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 380                 clock-names = "spiclk", "apb_pclk";
 381                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 status = "disabled";
 387         };
 388
 389         spi4: spi@ff1f0000 {
 390                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 391                 reg = <0x0 0xff120000 0x0 0x1000>;
 392                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 393                 clock-names = "spiclk", "apb_pclk";
 394                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 397                 #address-cells = <1>;
 398                 #size-cells = <0>;
 399                 status = "disabled";
 400         };
 401
 402         spi5: spi@ff200000 {
 403                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 404                 reg = <0x0 0xff130000 0x0 0x1000>;
 405                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 406                 clock-names = "spiclk", "apb_pclk";
 407                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 410                 #address-cells = <1>;
 411                 #size-cells = <0>;
 412                 status = "disabled";
 413         };
 414
 415         thermal-zones {
 416                 #include "rk3368-thermal.dtsi"
 417         };
 418
 419         tsadc: tsadc@ff260000 {
 420                 compatible = "rockchip,rk3399-tsadc";
 421                 reg = <0x0 0xff260000 0x0 0x100>;
 422                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 423                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 424                 clock-names = "tsadc", "apb_pclk";
 425                 resets = <&cru SRST_TSADC>;
 426                 reset-names = "tsadc-apb";
 427                 pinctrl-names = "init", "default", "sleep";
 428                 pinctrl-0 = <&otp_gpio>;
 429                 pinctrl-1 = <&otp_out>;
 430                 pinctrl-2 = <&otp_gpio>;
 431                 #thermal-sensor-cells = <1>;
 432                 rockchip,hw-tshut-temp = <95000>;
 433                 status = "disabled";
 434         };
 435
 436         pmugrf: syscon@ff320000 {
 437                 compatible = "rockchip,rk3399-pmugrf", "syscon";
 438                 reg = <0x0 0xff320000 0x0 0x1000>;
 439         };
 440
 441         spi3: spi@ff350000 {
 442                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 443                 reg = <0x0 0xff110000 0x0 0x1000>;
 444                 clocks = <&cru SCLK_SPI3_PMU>, <&cru PCLK_SPI3_PMU>;
 445                 clock-names = "spiclk", "apb_pclk";
 446                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 449                 #address-cells = <1>;
 450                 #size-cells = <0>;
 451                 status = "disabled";
 452         };
 453
 454         uart4: serial@ff370000 {
 455                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 456                 reg = <0x0 0xff370000 0x0 0x100>;
 457                 clocks = <&cru SCLK_UART4_PMU>, <&cru PCLK_UART4_PMU>;
 458                 clock-names = "baudclk", "apb_pclk";
 459                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 460                 reg-shift = <2>;
 461                 reg-io-width = <4>;
 462                 status = "disabled";
 463         };
 464
 465         i2c4: i2c@ff3d0000 {
 466                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 467                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 468                 clocks = <&cru PCLK_I2C4_PMU>, <&cru SCLK_I2C4_PMU>;
 469                 clock-names = "i2c", "i2c_sclk";
 470                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 471                 pinctrl-names = "default";
 472                 pinctrl-0 = <&i2c4_xfer>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 status = "disabled";
 476         };
 477
 478         i2c8: i2c@ff3e0000 {
 479                 compatible = "rockchip,rk3399-i2c", "rockchip,rk3288-i2c";
 480                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 481                 clocks = <&cru PCLK_I2C8_PMU>, <&cru SCLK_I2C8_PMU>;
 482                 clock-names = "i2c", "i2c_sclk";
 483                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&i2c8_xfer>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 status = "disabled";
 489         };
 490
 491         pwm0: pwm@ff420000 {
 492                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 493                 reg = <0x0 0xff420000 0x0 0x10>;
 494                 #pwm-cells = <3>;
 495                 pinctrl-names = "default";
 496                 pinctrl-0 = <&pwm0_pin>;
 497                 clocks = <&cru PCLK_RKPWM_PMU>;
 498                 clock-names = "pwm";
 499                 status = "disabled";
 500         };
 501
 502         pwm1: pwm@ff420010 {
 503                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 504                 reg = <0x0 0xff420010 0x0 0x10>;
 505                 #pwm-cells = <3>;
 506                 pinctrl-names = "default";
 507                 pinctrl-0 = <&pwm1_pin>;
 508                 clocks = <&cru PCLK_RKPWM_PMU>;
 509                 clock-names = "pwm";
 510                 status = "disabled";
 511         };
 512
 513         pwm2: pwm@ff420020 {
 514                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 515                 reg = <0x0 0xff420020 0x0 0x10>;
 516                 #pwm-cells = <3>;
 517                 pinctrl-names = "default";
 518                 pinctrl-0 = <&pwm2_pin>;
 519                 clocks = <&cru PCLK_RKPWM_PMU>;
 520                 clock-names = "pwm";
 521                 status = "disabled";
 522         };
 523
 524         pwm3: pwm@ff420030 {
 525                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
 526                 reg = <0x0 0xff420030 0x0 0x10>;
 527                 #pwm-cells = <3>;
 528                 pinctrl-names = "default";
 529                 pinctrl-0 = <&pwm3a_pin>;
 530                 clocks = <&cru PCLK_RKPWM_PMU>;
 531                 clock-names = "pwm";
 532                 status = "disabled";
 533         };
 534
 535         pmucru: pmu-clock-controller@ff750000 {
 536                 compatible = "rockchip,rk3399-pmucru";
 537                 reg = <0x0 0xff750000 0x0 0x1000>;
 538                 rockchip,grf = <&pmugrf>;
 539                 #clock-cells = <1>;
 540                 #reset-cells = <1>;
 541         };
 542
 543         cru: clock-controller@ff760000 {
 544                 compatible = "rockchip,rk3399-cru";
 545                 reg = <0x0 0xff760000 0x0 0x1000>;
 546                 rockchip,grf = <&grf>;
 547                 #clock-cells = <1>;
 548                 #reset-cells = <1>;
 549         };
 550
 551         grf: syscon@ff770000 {
 552                 compatible = "rockchip,rk3399-grf", "syscon";
 553                 reg = <0x0 0xff770000 0x0 0x10000>;
 554         };
 555
 556         spdif: spdif@ff870000 {
 557                 compatible = "rockchip,rk3399-spdif";
 558                 reg = <0x0 0xff870000 0x0 0x1000>;
 559                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 560                 dmas = <&dmac_bus 7>;
 561                 dma-names = "tx";
 562                 clock-names = "hclk", "mclk";
 563                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&spdif_bus>;
 566                 status = "disabled";
 567         };
 568
 569         i2s0: i2s@ff880000 {
 570                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 571                 reg = <0x0 0xff880000 0x0 0x1000>;
 572                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 576                 dma-names = "tx", "rx";
 577                 clock-names = "i2s_hclk", "i2s_clk";
 578                 clocks = <&cru HCLK_I2S0_8CH>, <&cru SCLK_I2S0_8CH>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2s0_8ch_bus>;
 581                 status = "disabled";
 582         };
 583
 584         i2s1: i2s@ff890000 {
 585                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 586                 reg = <0x0 0xff890000 0x0 0x1000>;
 587                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
 591                 dma-names = "tx", "rx";
 592                 clock-names = "i2s_hclk", "i2s_clk";
 593                 clocks = <&cru HCLK_I2S1_8CH>, <&cru SCLK_I2S1_8CH>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&i2s1_2ch_bus>;
 596                 status = "disabled";
 597         };
 598
 599         i2s2: i2s@ff8a0000 {
 600                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
 601                 reg = <0x0 0xff8a0000 0x0 0x1000>;
 602                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 603                 #address-cells = <1>;
 604                 #size-cells = <0>;
 605                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
 606                 dma-names = "tx", "rx";
 607                 clock-names = "i2s_hclk", "i2s_clk";
 608                 clocks = <&cru HCLK_I2S2_8CH>, <&cru SCLK_I2S2_8CH>;
 609                 status = "disabled";
 610         };
 611
 612         pinctrl: pinctrl {
 613                 compatible = "rockchip,rk3399-pinctrl";
 614                 rockchip,grf = <&grf>;
 615                 rockchip,pmu = <&pmugrf>;
 616                 #address-cells = <0x2>;
 617                 #size-cells = <0x2>;
 618                 ranges;
 619
 620                 gpio0: gpio0@ff720000 {
 621                         compatible = "rockchip,gpio-bank";
 622                         reg = <0x0 0xff720000 0x0 0x100>;
 623                         clocks = <&xin24m>;
 624                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 625
 626                         gpio-controller;
 627                         #gpio-cells = <0x2>;
 628
 629                         interrupt-controller;
 630                         #interrupt-cells = <0x2>;
 631                 };
 632
 633                 gpio1: gpio1@ff730000 {
 634                         compatible = "rockchip,gpio-bank";
 635                         reg = <0x0 0xff730000 0x0 0x100>;
 636                         clocks = <&xin24m>;
 637                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 638
 639                         gpio-controller;
 640                         #gpio-cells = <0x2>;
 641
 642                         interrupt-controller;
 643                         #interrupt-cells = <0x2>;
 644                 };
 645
 646                 gpio2: gpio2@ff780000 {
 647                         compatible = "rockchip,gpio-bank";
 648                         reg = <0x0 0xff780000 0x0 0x100>;
 649                         clocks = <&xin24m>;
 650                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 651
 652                         gpio-controller;
 653                         #gpio-cells = <0x2>;
 654
 655                         interrupt-controller;
 656                         #interrupt-cells = <0x2>;
 657                 };
 658
 659                 gpio3: gpio3@ff788000 {
 660                         compatible = "rockchip,gpio-bank";
 661                         reg = <0x0 0xff788000 0x0 0x100>;
 662                         clocks = <&xin24m>;
 663                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 664
 665                         gpio-controller;
 666                         #gpio-cells = <0x2>;
 667
 668                         interrupt-controller;
 669                         #interrupt-cells = <0x2>;
 670                 };
 671
 672                 gpio4: gpio4@ff790000 {
 673                         compatible = "rockchip,gpio-bank";
 674                         reg = <0x0 0xff790000 0x0 0x100>;
 675                         clocks = <&xin24m>;
 676                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 677
 678                         gpio-controller;
 679                         #gpio-cells = <0x2>;
 680
 681                         interrupt-controller;
 682                         #interrupt-cells = <0x2>;
 683                 };
 684
 685                 pcfg_pull_up: pcfg-pull-up {
 686                         bias-pull-up;
 687                 };
 688
 689                 pcfg_pull_down: pcfg-pull-down {
 690                         bias-pull-down;
 691                 };
 692
 693                 pcfg_pull_none: pcfg-pull-none {
 694                         bias-disable;
 695                 };
 696
 697                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 698                         bias-disable;
 699                         drive-strength = <12>;
 700                 };
 701
 702                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 703                         bias-pull-up;
 704                         drive-strength = <8>;
 705                 };
 706
 707                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 708                         bias-pull-down;
 709                         drive-strength = <4>;
 710                 };
 711
 712                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 713                         bias-pull-up;
 714                         drive-strength = <2>;
 715                 };
 716
 717                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
 718                         bias-pull-down;
 719                         drive-strength = <12>;
 720                 };
 721
 722                 emmc {
 723                         emmc_pwr: emmc-pwr {
 724                                 rockchip,pins =
 725                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
 726                         };
 727                 };
 728
 729                 gmac {
 730                         rgmii_pins: rgmii-pins {
 731                                 rockchip,pins =
 732                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 733                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 734                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 735                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 736                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 737                                         <3 0 RK_FUNC_1 &pcfg_pull_none_12ma>,
 738                                         <3 1 RK_FUNC_1 &pcfg_pull_none_12ma>,
 739                                         <3 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
 740                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 741                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 742                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 743                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
 744                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
 745                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
 746                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 747                         };
 748
 749                         rmii_pins: rmii-pins {
 750                                 rockchip,pins =
 751                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
 752                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
 753                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
 754                                         <3 4 RK_FUNC_1 &pcfg_pull_none_12ma>,
 755                                         <3 5 RK_FUNC_1 &pcfg_pull_none_12ma>,
 756                                         <3 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
 757                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
 758                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
 759                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
 760                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 761                         };
 762                 };
 763
 764                 i2c0 {
 765                         i2c0_xfer: i2c0-xfer {
 766                                 rockchip,pins =
 767                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
 768                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
 769                         };
 770                 };
 771
 772                 i2c1 {
 773                         i2c1_xfer: i2c1-xfer {
 774                                 rockchip,pins =
 775                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
 776                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
 777                         };
 778                 };
 779
 780                 i2c2 {
 781                         i2c2_xfer: i2c2-xfer {
 782                                 rockchip,pins =
 783                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
 784                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
 785                         };
 786                 };
 787
 788                 i2c3 {
 789                         i2c3_xfer: i2c3-xfer {
 790                                 rockchip,pins =
 791                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 792                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
 793                         };
 794                 };
 795
 796                 i2c4 {
 797                         i2c4_xfer: i2c4-xfer {
 798                                 rockchip,pins =
 799                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
 800                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802                 };
 803
 804                 i2c5 {
 805                         i2c5_xfer: i2c5-xfer {
 806                                 rockchip,pins =
 807                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
 808                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
 809                         };
 810                 };
 811
 812                 i2c6 {
 813                         i2c6_xfer: i2c6-xfer {
 814                                 rockchip,pins =
 815                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
 816                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
 817                         };
 818                 };
 819
 820                 i2c7 {
 821                         i2c7_xfer: i2c7-xfer {
 822                                 rockchip,pins =
 823                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
 824                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
 825                         };
 826                 };
 827
 828                 i2c8 {
 829                         i2c8_xfer: i2c8-xfer {
 830                                 rockchip,pins =
 831                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
 832                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
 833                         };
 834                 };
 835
 836                 i2s0 {
 837                         i2s0_8ch_bus: i2s0-8ch-bus {
 838                                 rockchip,pins =
 839                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
 840                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
 841                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
 842                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
 843                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
 844                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
 845                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
 846                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
 847                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
 848                         };
 849                 };
 850
 851                 i2s1 {
 852                         i2s1_2ch_bus: i2s1-2ch-bus {
 853                                 rockchip,pins =
 854                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
 855                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
 856                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
 857                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
 858                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
 859                         };
 860                 };
 861
 862                 sdio0 {
 863                         sdio0_bus1: sdio0-bus1 {
 864                                 rockchip,pins =
 865                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
 866                         };
 867
 868                         sdio0_bus4: sdio0-bus4 {
 869                                 rockchip,pins =
 870                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
 871                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
 872                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
 873                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
 874                         };
 875
 876                         sdio0_cmd: sdio0-cmd {
 877                                 rockchip,pins =
 878                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
 879                         };
 880
 881                         sdio0_clk: sdio0-clk {
 882                                 rockchip,pins =
 883                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 884                         };
 885
 886                         sdio0_cd: sdio0-cd {
 887                                 rockchip,pins =
 888                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
 889                         };
 890
 891                         sdio0_pwr: sdio0-pwr {
 892                                 rockchip,pins =
 893                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
 894                         };
 895
 896                         sdio0_bkpwr: sdio0-bkpwr {
 897                                 rockchip,pins =
 898                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
 899                         };
 900
 901                         sdio0_wp: sdio0-wp {
 902                                 rockchip,pins =
 903                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
 904                         };
 905
 906                         sdio0_int: sdio0-int {
 907                                 rockchip,pins =
 908                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
 909                         };
 910                 };
 911
 912                 sdmmc {
 913                         sdmmc_bus1: sdmmc-bus1 {
 914                                 rockchip,pins =
 915                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
 916                         };
 917
 918                         sdmmc_bus4: sdmmc-bus4 {
 919                                 rockchip,pins =
 920                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
 921                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
 922                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
 923                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
 924                         };
 925
 926                         sdmmc_clk: sdmmc-clk {
 927                                 rockchip,pins =
 928                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930
 931                         sdmmc_cmd: sdmmc-cmd {
 932                                 rockchip,pins =
 933                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
 934                         };
 935
 936                         sdmmc_cd: sdmcc-cd {
 937                                 rockchip,pins =
 938                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940
 941                         sdmmc_wp: sdmmc-wp {
 942                                 rockchip,pins =
 943                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
 944                         };
 945                 };
 946
 947                 spdif {
 948                         spdif_bus: spdif-bus {
 949                                 rockchip,pins =
 950                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
 951                         };
 952                 };
 953
 954                 spi0 {
 955                         spi0_clk: spi0-clk {
 956                                 rockchip,pins =
 957                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
 958                         };
 959                         spi0_cs0: spi0-cs0 {
 960                                 rockchip,pins =
 961                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
 962                         };
 963                         spi0_cs1: spi0-cs1 {
 964                                 rockchip,pins =
 965                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
 966                         };
 967                         spi0_tx: spi0-tx {
 968                                 rockchip,pins =
 969                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
 970                         };
 971                         spi0_rx: spi0-rx {
 972                                 rockchip,pins =
 973                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
 974                         };
 975                 };
 976
 977                 spi1 {
 978                         spi1_clk: spi1-clk {
 979                                 rockchip,pins =
 980                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
 981                         };
 982                         spi1_cs0: spi1-cs0 {
 983                                 rockchip,pins =
 984                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
 985                         };
 986                         spi1_rx: spi1-rx {
 987                                 rockchip,pins =
 988                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
 989                         };
 990                         spi1_tx: spi1-tx {
 991                                 rockchip,pins =
 992                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
 993                         };
 994                 };
 995
 996                 spi2 {
 997                         spi2_clk: spi2-clk {
 998                                 rockchip,pins =
 999                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1000                         };
1001                         spi2_cs0: spi2-cs0 {
1002                                 rockchip,pins =
1003                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1004                         };
1005                         spi2_rx: spi2-rx {
1006                                 rockchip,pins =
1007                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1008                         };
1009                         spi2_tx: spi2-tx {
1010                                 rockchip,pins =
1011                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1012                         };
1013                 };
1014
1015                 spi3 {
1016                         spi3_clk: spi3-clk {
1017                                 rockchip,pins =
1018                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1019                         };
1020                         spi3_cs0: spi3-cs0 {
1021                                 rockchip,pins =
1022                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1023                         };
1024                         spi3_rx: spi3-rx {
1025                                 rockchip,pins =
1026                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1027                         };
1028                         spi3_tx: spi3-tx {
1029                                 rockchip,pins =
1030                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1031                         };
1032                 };
1033
1034                 spi4 {
1035                         spi4_clk: spi4-clk {
1036                                 rockchip,pins =
1037                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1038                         };
1039                         spi4_cs0: spi4-cs0 {
1040                                 rockchip,pins =
1041                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1042                         };
1043                         spi4_rx: spi4-rx {
1044                                 rockchip,pins =
1045                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1046                         };
1047                         spi4_tx: spi4-tx {
1048                                 rockchip,pins =
1049                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1050                         };
1051                 };
1052
1053                 spi5 {
1054                         spi5_clk: spi5-clk {
1055                                 rockchip,pins =
1056                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1057                         };
1058                         spi5_cs0: spi5-cs0 {
1059                                 rockchip,pins =
1060                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1061                         };
1062                         spi5_rx: spi5-rx {
1063                                 rockchip,pins =
1064                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1065                         };
1066                         spi5_tx: spi5-tx {
1067                                 rockchip,pins =
1068                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1069                         };
1070                 };
1071
1072                 tsadc {
1073                         otp_gpio: otp-gpio {
1074                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1075                         };
1076
1077                         otp_out: otp-out {
1078                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 uart0 {
1083                         uart0_xfer: uart0-xfer {
1084                                 rockchip,pins =
1085                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1086                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1087                         };
1088
1089                         uart0_cts: uart0-cts {
1090                                 rockchip,pins =
1091                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1092                         };
1093
1094                         uart0_rts: uart0-rts {
1095                                 rockchip,pins =
1096                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098                 };
1099
1100                 uart1 {
1101                         uart1_xfer: uart1-xfer {
1102                                 rockchip,pins =
1103                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1104                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1105                         };
1106                 };
1107
1108                 uart2a {
1109                         uart2a_xfer: uart2a-xfer {
1110                                 rockchip,pins =
1111                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1112                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1113                         };
1114                 };
1115
1116                 uart2b {
1117                         uart2b_xfer: uart2b-xfer {
1118                                 rockchip,pins =
1119                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1120                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1121                         };
1122                 };
1123
1124                 uart2c {
1125                         uart2c_xfer: uart2c-xfer {
1126                                 rockchip,pins =
1127                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1128                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1129                         };
1130                 };
1131
1132                 uart3 {
1133                         uart3_xfer: uart3-xfer {
1134                                 rockchip,pins =
1135                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1136                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1137                         };
1138
1139                         uart3_cts: uart3-cts {
1140                                 rockchip,pins =
1141                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1142                         };
1143
1144                         uart3_rts: uart3-rts {
1145                                 rockchip,pins =
1146                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1147                         };
1148                 };
1149
1150                 uart4 {
1151                         uart4_xfer: uart4-xfer {
1152                                 rockchip,pins =
1153                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1154                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 uarthdcp {
1159                         uarthdcp_xfer: uarthdcp-xfer {
1160                                 rockchip,pins =
1161                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1162                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1163                         };
1164                 };
1165
1166                 pwm0 {
1167                         pwm0_pin: pwm0-pin {
1168                                 rockchip,pins =
1169                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
1170                         };
1171
1172                         vop0_pwm_pin: vop0-pwm-pin {
1173                                 rockchip,pins =
1174                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
1175                         };
1176                 };
1177
1178                 pwm1 {
1179                         pwm1_pin: pwm1-pin {
1180                                 rockchip,pins =
1181                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
1182                         };
1183
1184                         vop1_pwm_pin: vop1-pwm-pin {
1185                                 rockchip,pins =
1186                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
1187                         };
1188                 };
1189
1190                 pwm2 {
1191                         pwm2_pin: pwm2-pin {
1192                                 rockchip,pins =
1193                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195                 };
1196
1197                 pwm3a {
1198                         pwm3a_pin: pwm3a-pin {
1199                                 rockchip,pins =
1200                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
1201                         };
1202                 };
1203
1204                 pwm3b {
1205                         pwm3b_pin: pwm3b-pin {
1206                                 rockchip,pins =
1207                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
1208                         };
1209                 };
1210         };
1211 };