arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         dynamic-power-coefficient = <121>;
 118                         clocks = <&cru ARMCLKL>;
 119                         cpu-idle-states = <&cpu_sleep>;
 120                         operating-points-v2 = <&cluster0_opp>;
 121                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 122                 };
 123
 124                 cpu_l1: cpu@1 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x1>;
 128                         enable-method = "psci";
 129                         clocks = <&cru ARMCLKL>;
 130                         cpu-idle-states = <&cpu_sleep>;
 131                         operating-points-v2 = <&cluster0_opp>;
 132                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 133                 };
 134
 135                 cpu_l2: cpu@2 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x2>;
 139                         enable-method = "psci";
 140                         clocks = <&cru ARMCLKL>;
 141                         cpu-idle-states = <&cpu_sleep>;
 142                         operating-points-v2 = <&cluster0_opp>;
 143                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 144                 };
 145
 146                 cpu_l3: cpu@3 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x3>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         cpu-idle-states = <&cpu_sleep>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a72", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         #cooling-cells = <2>; /* min followed by max */
 163                         dynamic-power-coefficient = <1068>;
 164                         clocks = <&cru ARMCLKB>;
 165                         cpu-idle-states = <&cpu_sleep>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 168                 };
 169
 170                 cpu_b1: cpu@101 {
 171                         device_type = "cpu";
 172                         compatible = "arm,cortex-a72", "arm,armv8";
 173                         reg = <0x0 0x101>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         cpu-idle-states = <&cpu_sleep>;
 177                         operating-points-v2 = <&cluster1_opp>;
 178                         sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
 179                 };
 180
 181                 idle-states {
 182                         entry-method = "psci";
 183                         cpu_sleep: cpu-sleep-0 {
 184                                 compatible = "arm,idle-state";
 185                                 local-timer-stop;
 186                                 arm,psci-suspend-param = <0x0010000>;
 187                                 entry-latency-us = <350>;
 188                                 exit-latency-us = <600>;
 189                                 min-residency-us = <1150>;
 190                         };
 191                 };
 192
 193                 /include/ "rk3399-sched-energy.dtsi"
 194
 195         };
 196
 197         cluster0_opp: opp_table0 {
 198                 compatible = "operating-points-v2";
 199                 opp-shared;
 200
 201                 opp00 {
 202                         opp-hz = /bits/ 64 <408000000>;
 203                         opp-microvolt = <800000>;
 204                         clock-latency-ns = <40000>;
 205                 };
 206                 opp01 {
 207                         opp-hz = /bits/ 64 <600000000>;
 208                         opp-microvolt = <800000>;
 209                 };
 210                 opp02 {
 211                         opp-hz = /bits/ 64 <816000000>;
 212                         opp-microvolt = <800000>;
 213                 };
 214                 opp03 {
 215                         opp-hz = /bits/ 64 <1008000000>;
 216                         opp-microvolt = <875000>;
 217                 };
 218                 opp04 {
 219                         opp-hz = /bits/ 64 <1200000000>;
 220                         opp-microvolt = <925000>;
 221                 };
 222                 opp05 {
 223                         opp-hz = /bits/ 64 <1416000000>;
 224                         opp-microvolt = <1025000>;
 225                 };
 226         };
 227
 228         cluster1_opp: opp_table1 {
 229                 compatible = "operating-points-v2";
 230                 opp-shared;
 231
 232                 opp00 {
 233                         opp-hz = /bits/ 64 <408000000>;
 234                         opp-microvolt = <800000>;
 235                         clock-latency-ns = <40000>;
 236                 };
 237                 opp01 {
 238                         opp-hz = /bits/ 64 <600000000>;
 239                         opp-microvolt = <800000>;
 240                 };
 241                 opp02 {
 242                         opp-hz = /bits/ 64 <816000000>;
 243                         opp-microvolt = <800000>;
 244                 };
 245                 opp03 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <850000>;
 248                 };
 249                 opp04 {
 250                         opp-hz = /bits/ 64 <1200000000>;
 251                         opp-microvolt = <925000>;
 252                 };
 253         };
 254
 255         timer {
 256                 compatible = "arm,armv8-timer";
 257                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 258                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 259                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 260                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 261         };
 262
 263         arm-pmu {
 264                 compatible = "arm,armv8-pmuv3";
 265                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 266         };
 267
 268         xin24m: xin24m {
 269                 compatible = "fixed-clock";
 270                 #clock-cells = <0>;
 271                 clock-frequency = <24000000>;
 272                 clock-output-names = "xin24m";
 273         };
 274
 275         amba {
 276                 compatible = "arm,amba-bus";
 277                 #address-cells = <2>;
 278                 #size-cells = <2>;
 279                 ranges;
 280
 281                 dmac_bus: dma-controller@ff6d0000 {
 282                         compatible = "arm,pl330", "arm,primecell";
 283                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 284                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 285                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 286                         #dma-cells = <1>;
 287                         clocks = <&cru ACLK_DMAC0_PERILP>;
 288                         clock-names = "apb_pclk";
 289                         peripherals-req-type-burst;
 290                 };
 291
 292                 dmac_peri: dma-controller@ff6e0000 {
 293                         compatible = "arm,pl330", "arm,primecell";
 294                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 295                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 296                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 297                         #dma-cells = <1>;
 298                         clocks = <&cru ACLK_DMAC1_PERILP>;
 299                         clock-names = "apb_pclk";
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         gmac: eth@fe300000 {
 305                 compatible = "rockchip,rk3399-gmac";
 306                 reg = <0x0 0xfe300000 0x0 0x10000>;
 307                 rockchip,grf = <&grf>;
 308                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 309                 interrupt-names = "macirq";
 310                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 311                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 312                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 313                          <&cru PCLK_GMAC>;
 314                 clock-names = "stmmaceth", "mac_clk_rx",
 315                               "mac_clk_tx", "clk_mac_ref",
 316                               "clk_mac_refout", "aclk_mac",
 317                               "pclk_mac";
 318                 resets = <&cru SRST_A_GMAC>;
 319                 reset-names = "stmmaceth";
 320                 status = "disabled";
 321         };
 322
 323         emmc_phy: phy {
 324                 compatible = "rockchip,rk3399-emmc-phy";
 325                 reg-offset = <0xf780>;
 326                 #phy-cells = <0>;
 327                 rockchip,grf = <&grf>;
 328                 ctrl-base = <0xfe330000>;
 329                 status = "disabled";
 330         };
 331
 332         sdio0: dwmmc@fe310000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe310000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 339                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdmmc: dwmmc@fe320000 {
 346                 compatible = "rockchip,rk3399-dw-mshc",
 347                              "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xfe320000 0x0 0x4000>;
 349                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 350                 clock-freq-min-max = <400000 150000000>;
 351                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 352                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 353                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 354                 fifo-depth = <0x100>;
 355                 status = "disabled";
 356         };
 357
 358         sdhci: sdhci@fe330000 {
 359                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 360                 reg = <0x0 0xfe330000 0x0 0x10000>;
 361                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 362                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 363                 clock-names = "clk_xin", "clk_ahb";
 364                 assigned-clocks = <&cru SCLK_EMMC>;
 365                 assigned-clock-parents = <&cru PLL_CPLL>;
 366                 assigned-clock-rates = <200000000>;
 367                 phys = <&emmc_phy>;
 368                 phy-names = "phy_arasan";
 369                 status = "disabled";
 370         };
 371
 372         usb2phy: usb2phy {
 373                 compatible = "rockchip,rk3399-usb-phy";
 374                 rockchip,grf = <&grf>;
 375                 #address-cells = <1>;
 376                 #size-cells = <0>;
 377
 378                 usb2phy0: usb2-phy0 {
 379                         #phy-cells = <0>;
 380                         #clock-cells = <0>;
 381                         reg = <0xe458>;
 382                 };
 383
 384                 usb2phy1: usb2-phy1 {
 385                         #phy-cells = <0>;
 386                         #clock-cells = <0>;
 387                         reg = <0xe468>;
 388                 };
 389         };
 390
 391         usb_host0_ehci: usb@fe380000 {
 392                 compatible = "generic-ehci";
 393                 reg = <0x0 0xfe380000 0x0 0x20000>;
 394                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 395                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 396                 clock-names = "hclk_host0", "hclk_host0_arb";
 397                 phys = <&usb2phy0>;
 398                 phy-names = "usb2_phy0";
 399                 status = "disabled";
 400         };
 401
 402         usb_host0_ohci: usb@fe3a0000 {
 403                 compatible = "generic-ohci";
 404                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 405                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 407                 clock-names = "hclk_host0", "hclk_host0_arb";
 408                 status = "disabled";
 409         };
 410
 411         usb_host1_ehci: usb@fe3c0000 {
 412                 compatible = "generic-ehci";
 413                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 414                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 415                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 416                 clock-names = "hclk_host1", "hclk_host1_arb";
 417                 phys = <&usb2phy1>;
 418                 phy-names = "usb2_phy1";
 419                 status = "disabled";
 420         };
 421
 422         usb_host1_ohci: usb@fe3e0000 {
 423                 compatible = "generic-ohci";
 424                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 425                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 426                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 427                 clock-names = "hclk_host1", "hclk_host1_arb";
 428                 status = "disabled";
 429         };
 430
 431         usbdrd3_0: usb@fe800000 {
 432                 compatible = "rockchip,dwc3";
 433                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 434                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 435                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 436                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 437                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 438                               "aclk_usb3", "aclk_usb3_grf";
 439                 #address-cells = <2>;
 440                 #size-cells = <2>;
 441                 ranges;
 442                 status = "disabled";
 443                 usbdrd_dwc3_0: dwc3@fe800000 {
 444                         compatible = "snps,dwc3";
 445                         reg = <0x0 0xfe800000 0x0 0x100000>;
 446                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 447                         dr_mode = "otg";
 448                         snps,dis_enblslpm_quirk;
 449                         snps,phyif_utmi_16_bits;
 450                         snps,dis_u2_freeclk_exists_quirk;
 451                         snps,dis_del_phy_power_chg_quirk;
 452                         snps,xhci_slow_suspend_quirk;
 453                         status = "disabled";
 454                 };
 455         };
 456
 457         usbdrd3_1: usb@fe900000 {
 458                 compatible = "rockchip,dwc3";
 459                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 460                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 461                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 462                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 463                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 464                               "aclk_usb3", "aclk_usb3_grf";
 465                 #address-cells = <2>;
 466                 #size-cells = <2>;
 467                 ranges;
 468                 status = "disabled";
 469                 usbdrd_dwc3_1: dwc3@fe900000 {
 470                         compatible = "snps,dwc3";
 471                         reg = <0x0 0xfe900000 0x0 0x100000>;
 472                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 473                         dr_mode = "otg";
 474                         snps,dis_enblslpm_quirk;
 475                         snps,phyif_utmi_16_bits;
 476                         snps,dis_u2_freeclk_exists_quirk;
 477                         snps,dis_del_phy_power_chg_quirk;
 478                         snps,xhci_slow_suspend_quirk;
 479                         status = "disabled";
 480                 };
 481         };
 482
 483         gic: interrupt-controller@fee00000 {
 484                 compatible = "arm,gic-v3";
 485                 #interrupt-cells = <3>;
 486                 #address-cells = <2>;
 487                 #size-cells = <2>;
 488                 ranges;
 489                 interrupt-controller;
 490
 491                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 492                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 493                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 494                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 495                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 496                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 497                 its: interrupt-controller@fee20000 {
 498                         compatible = "arm,gic-v3-its";
 499                         msi-controller;
 500                         reg = <0x0 0xfee20000 0x0 0x20000>;
 501                 };
 502         };
 503
 504         saradc: saradc@ff100000 {
 505                 compatible = "rockchip,rk3399-saradc";
 506                 reg = <0x0 0xff100000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 508                 #io-channel-cells = <1>;
 509                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 510                 clock-names = "saradc", "apb_pclk";
 511                 status = "disabled";
 512         };
 513
 514         i2c0: i2c@ff3c0000 {
 515                 compatible = "rockchip,rk3399-i2c";
 516                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 517                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 518                 clock-names = "i2c", "pclk";
 519                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 520                 pinctrl-names = "default";
 521                 pinctrl-0 = <&i2c0_xfer>;
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524                 status = "disabled";
 525         };
 526
 527         i2c1: i2c@ff110000 {
 528                 compatible = "rockchip,rk3399-i2c";
 529                 reg = <0x0 0xff110000 0x0 0x1000>;
 530                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 531                 clock-names = "i2c", "pclk";
 532                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 533                 pinctrl-names = "default";
 534                 pinctrl-0 = <&i2c1_xfer>;
 535                 #address-cells = <1>;
 536                 #size-cells = <0>;
 537                 status = "disabled";
 538         };
 539
 540         i2c2: i2c@ff120000 {
 541                 compatible = "rockchip,rk3399-i2c";
 542                 reg = <0x0 0xff120000 0x0 0x1000>;
 543                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 544                 clock-names = "i2c", "pclk";
 545                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 546                 pinctrl-names = "default";
 547                 pinctrl-0 = <&i2c2_xfer>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 status = "disabled";
 551         };
 552
 553         i2c3: i2c@ff130000 {
 554                 compatible = "rockchip,rk3399-i2c";
 555                 reg = <0x0 0xff130000 0x0 0x1000>;
 556                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 557                 clock-names = "i2c", "pclk";
 558                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c3_xfer>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 status = "disabled";
 564         };
 565
 566         i2c5: i2c@ff140000 {
 567                 compatible = "rockchip,rk3399-i2c";
 568                 reg = <0x0 0xff140000 0x0 0x1000>;
 569                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c5_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c6: i2c@ff150000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff150000 0x0 0x1000>;
 582                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 583                 clock-names = "i2c", "pclk";
 584                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&i2c6_xfer>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 status = "disabled";
 590         };
 591
 592         i2c7: i2c@ff160000 {
 593                 compatible = "rockchip,rk3399-i2c";
 594                 reg = <0x0 0xff160000 0x0 0x1000>;
 595                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 596                 clock-names = "i2c", "pclk";
 597                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 598                 pinctrl-names = "default";
 599                 pinctrl-0 = <&i2c7_xfer>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 status = "disabled";
 603         };
 604
 605         uart0: serial@ff180000 {
 606                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 607                 reg = <0x0 0xff180000 0x0 0x100>;
 608                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 609                 clock-names = "baudclk", "apb_pclk";
 610                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 611                 reg-shift = <2>;
 612                 reg-io-width = <4>;
 613                 pinctrl-names = "default";
 614                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 615                 status = "disabled";
 616         };
 617
 618         uart1: serial@ff190000 {
 619                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 620                 reg = <0x0 0xff190000 0x0 0x100>;
 621                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 622                 clock-names = "baudclk", "apb_pclk";
 623                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 624                 reg-shift = <2>;
 625                 reg-io-width = <4>;
 626                 pinctrl-names = "default";
 627                 pinctrl-0 = <&uart1_xfer>;
 628                 status = "disabled";
 629         };
 630
 631         uart2: serial@ff1a0000 {
 632                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 633                 reg = <0x0 0xff1a0000 0x0 0x100>;
 634                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 635                 clock-names = "baudclk", "apb_pclk";
 636                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 637                 reg-shift = <2>;
 638                 reg-io-width = <4>;
 639                 pinctrl-names = "default";
 640                 pinctrl-0 = <&uart2c_xfer>;
 641                 status = "disabled";
 642         };
 643
 644         uart3: serial@ff1b0000 {
 645                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1b0000 0x0 0x100>;
 647                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 648                 clock-names = "baudclk", "apb_pclk";
 649                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 650                 reg-shift = <2>;
 651                 reg-io-width = <4>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 654                 status = "disabled";
 655         };
 656
 657         spi0: spi@ff1c0000 {
 658                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 659                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 660                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 661                 clock-names = "spiclk", "apb_pclk";
 662                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 663                 pinctrl-names = "default";
 664                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 665                 #address-cells = <1>;
 666                 #size-cells = <0>;
 667                 status = "disabled";
 668         };
 669
 670         spi1: spi@ff1d0000 {
 671                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 672                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 673                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 674                 clock-names = "spiclk", "apb_pclk";
 675                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 676                 pinctrl-names = "default";
 677                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 678                 #address-cells = <1>;
 679                 #size-cells = <0>;
 680                 status = "disabled";
 681         };
 682
 683         spi2: spi@ff1e0000 {
 684                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 685                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 686                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 687                 clock-names = "spiclk", "apb_pclk";
 688                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 691                 #address-cells = <1>;
 692                 #size-cells = <0>;
 693                 status = "disabled";
 694         };
 695
 696         spi4: spi@ff1f0000 {
 697                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 698                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 699                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 700                 clock-names = "spiclk", "apb_pclk";
 701                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 702                 pinctrl-names = "default";
 703                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 704                 #address-cells = <1>;
 705                 #size-cells = <0>;
 706                 status = "disabled";
 707         };
 708
 709         spi5: spi@ff200000 {
 710                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 711                 reg = <0x0 0xff200000 0x0 0x1000>;
 712                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 713                 clock-names = "spiclk", "apb_pclk";
 714                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 717                 #address-cells = <1>;
 718                 #size-cells = <0>;
 719                 status = "disabled";
 720         };
 721
 722         thermal-zones {
 723                 soc_thermal: soc-thermal {
 724                         polling-delay-passive = <100>; /* milliseconds */
 725                         polling-delay = <1000>; /* milliseconds */
 726                         sustainable-power = <2600>; /* milliwatts */
 727
 728                         thermal-sensors = <&tsadc 0>;
 729
 730                         trips {
 731                                 threshold: trip-point@0 {
 732                                         temperature = <70000>; /* millicelsius */
 733                                         hysteresis = <2000>; /* millicelsius */
 734                                         type = "passive";
 735                                 };
 736                                 target: trip-point@1 {
 737                                         temperature = <85000>; /* millicelsius */
 738                                         hysteresis = <2000>; /* millicelsius */
 739                                         type = "passive";
 740                                 };
 741                                 soc_crit: soc-crit {
 742                                         temperature = <95000>; /* millicelsius */
 743                                         hysteresis = <2000>; /* millicelsius */
 744                                         type = "critical";
 745                                 };
 746                         };
 747
 748                         cooling-maps {
 749                                 map0 {
 750                                         trip = <&target>;
 751                                         cooling-device =
 752                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 753                                 };
 754                                 map1 {
 755                                         trip = <&target>;
 756                                         cooling-device =
 757                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 758                                 };
 759                                 map2 {
 760                                         trip = <&target>;
 761                                         cooling-device =
 762                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 763                                 };
 764                         };
 765                 };
 766
 767                 gpu_thermal: gpu-thermal {
 768                         polling-delay-passive = <100>; /* milliseconds */
 769                         polling-delay = <1000>; /* milliseconds */
 770
 771                         thermal-sensors = <&tsadc 1>;
 772                 };
 773         };
 774
 775         tsadc: tsadc@ff260000 {
 776                 compatible = "rockchip,rk3399-tsadc";
 777                 reg = <0x0 0xff260000 0x0 0x100>;
 778                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 779                 rockchip,grf = <&grf>;
 780                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 781                 clock-names = "tsadc", "apb_pclk";
 782                 assigned-clocks = <&cru SCLK_TSADC>;
 783                 assigned-clock-rates = <750000>;
 784                 resets = <&cru SRST_TSADC>;
 785                 reset-names = "tsadc-apb";
 786                 pinctrl-names = "init", "default", "sleep";
 787                 pinctrl-0 = <&otp_gpio>;
 788                 pinctrl-1 = <&otp_out>;
 789                 pinctrl-2 = <&otp_gpio>;
 790                 #thermal-sensor-cells = <1>;
 791                 rockchip,hw-tshut-temp = <95000>;
 792                 status = "disabled";
 793         };
 794
 795         qos_gpu: qos_gpu@0xffae0000 {
 796                 compatible ="syscon";
 797                 reg = <0x0 0xffae0000 0x0 0x20>;
 798         };
 799         qos_video_m0: qos_video_m0@0xffab8000 {
 800                 compatible ="syscon";
 801                 reg = <0x0 0xffab8000 0x0 0x20>;
 802         };
 803         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 804                 compatible ="syscon";
 805                 reg = <0x0 0xffac0000 0x0 0x20>;
 806         };
 807         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 808                 compatible ="syscon";
 809                 reg = <0x0 0xffac0080 0x0 0x20>;
 810         };
 811         qos_rga_r: qos_rga_r@0xffab0000 {
 812                 compatible ="syscon";
 813                 reg = <0x0 0xffab0000 0x0 0x20>;
 814         };
 815         qos_rga_w: qos_rga_w@0xffab0080 {
 816                 compatible ="syscon";
 817                 reg = <0x0 0xffab0000 0x0 0x20>;
 818         };
 819         qos_iep: qos_iep@0xffa98000 {
 820                 compatible ="syscon";
 821                 reg = <0x0 0xffa98000 0x0 0x20>;
 822         };
 823         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 824                 compatible ="syscon";
 825                 reg = <0x0 0xffac8000 0x0 0x20>;
 826         };
 827         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 828                 compatible ="syscon";
 829                 reg = <0x0 0xffac8080 0x0 0x20>;
 830         };
 831         qos_vop_little: qos_vop_little@0xffad0000 {
 832                 compatible ="syscon";
 833                 reg = <0x0 0xffad0000 0x0 0x20>;
 834         };
 835         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 836                 compatible ="syscon";
 837                 reg = <0x0 0xffaa0000 0x0 0x20>;
 838         };
 839         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 840                 compatible ="syscon";
 841                 reg = <0x0 0xffaa0080 0x0 0x20>;
 842         };
 843         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 844                 compatible ="syscon";
 845                 reg = <0x0 0xffaa8000 0x0 0x20>;
 846         };
 847         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 848                 compatible ="syscon";
 849                 reg = <0x0 0xffaa8080 0x0 0x20>;
 850         };
 851         qos_hdcp: qos_hdcp@0xffa90000 {
 852                 compatible ="syscon";
 853                 reg = <0x0 0xffa90000 0x0 0x20>;
 854         };
 855
 856         pmu: power-management@ff310000 {
 857                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 858                 reg = <0x0 0xff310000 0x0 0x1000>;
 859
 860                 power: power-controller {
 861                         status = "okay";
 862                         compatible = "rockchip,rk3399-power-controller";
 863                         #power-domain-cells = <1>;
 864                         #address-cells = <1>;
 865                         #size-cells = <0>;
 866
 867
 868                         pd_vdu {
 869                                 reg = <RK3399_PD_VDU>;
 870                                 clocks = <&cru ACLK_VDU>,
 871                                          <&cru HCLK_VDU>;
 872                                 pm_qos = <&qos_video_m1_r>,
 873                                          <&qos_video_m1_w>;
 874                         };
 875                         pd_vcodec {
 876                                 reg = <RK3399_PD_VCODEC>;
 877                                 clocks = <&cru ACLK_VCODEC>,
 878                                          <&cru HCLK_VCODEC>;
 879                                 pm_qos = <&qos_video_m0>;
 880                         };
 881                         pd_iep {
 882                                 reg = <RK3399_PD_IEP>;
 883                                 clocks = <&cru ACLK_IEP>,
 884                                          <&cru HCLK_IEP>;
 885                                 pm_qos = <&qos_iep>;
 886                         };
 887                         pd_rga {
 888                                 reg = <RK3399_PD_RGA>;
 889                                 clocks = <&cru ACLK_RGA>,
 890                                          <&cru HCLK_RGA>;
 891                                 pm_qos = <&qos_rga_r>,
 892                                          <&qos_rga_w>;
 893                         };
 894                         pd_vio {
 895                                 reg = <RK3399_PD_VIO>;
 896                                 #address-cells = <1>;
 897                                 #size-cells = <0>;
 898
 899                                 pd_isp0 {
 900                                         reg = <RK3399_PD_ISP0>;
 901                                         clocks = <&cru ACLK_ISP0>,
 902                                                  <&cru HCLK_ISP0>;
 903                                         pm_qos = <&qos_isp0_m0>,
 904                                                  <&qos_isp0_m1>;
 905                                 };
 906                                 pd_isp1 {
 907                                         reg = <RK3399_PD_ISP1>;
 908                                         clocks = <&cru ACLK_ISP1>,
 909                                                  <&cru HCLK_ISP1>;
 910                                         pm_qos = <&qos_isp1_m0>,
 911                                                  <&qos_isp1_m1>;
 912                                 };
 913                                 pd_hdcp {
 914                                         reg = <RK3399_PD_HDCP>;
 915                                         clocks = <&cru ACLK_HDCP>,
 916                                                  <&cru HCLK_HDCP>,
 917                                                  <&cru PCLK_HDCP>;
 918                                         pm_qos = <&qos_hdcp>;
 919                                 };
 920                                 pd_vo {
 921                                         reg = <RK3399_PD_VO>;
 922                                         #address-cells = <1>;
 923                                         #size-cells = <0>;
 924
 925                                         pd_vopb {
 926                                                 reg = <RK3399_PD_VOPB>;
 927                                                 clocks = <&cru ACLK_VOP0>,
 928                                                          <&cru HCLK_VOP0>;
 929                                                 pm_qos = <&qos_vop_big_r>,
 930                                                          <&qos_vop_big_w>;
 931                                         };
 932                                         pd_vopl {
 933                                                 reg = <RK3399_PD_VOPL>;
 934                                                 clocks = <&cru ACLK_VOP1>,
 935                                                          <&cru HCLK_VOP1>;
 936                                                 pm_qos = <&qos_vop_little>;
 937                                         };
 938                                 };
 939                         };
 940                         pd_gpu {
 941                                 reg = <RK3399_PD_GPU>;
 942                                 clocks = <&cru ACLK_GPU>;
 943                                 pm_qos = <&qos_gpu>;
 944                         };
 945                 };
 946         };
 947
 948         pmugrf: syscon@ff320000 {
 949                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 950                 reg = <0x0 0xff320000 0x0 0x1000>;
 951
 952                 reboot-mode {
 953                         compatible = "syscon-reboot-mode";
 954                         offset = <0x300>;
 955                         mode-normal = <BOOT_NORMAL>;
 956                         mode-recovery = <BOOT_RECOVERY>;
 957                         mode-bootloader = <BOOT_FASTBOOT>;
 958                         mode-loader = <BOOT_LOADER>;
 959                 };
 960         };
 961
 962         spi3: spi@ff350000 {
 963                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 964                 reg = <0x0 0xff350000 0x0 0x1000>;
 965                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 966                 clock-names = "spiclk", "apb_pclk";
 967                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 968                 pinctrl-names = "default";
 969                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 970                 #address-cells = <1>;
 971                 #size-cells = <0>;
 972                 status = "disabled";
 973         };
 974
 975         uart4: serial@ff370000 {
 976                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 977                 reg = <0x0 0xff370000 0x0 0x100>;
 978                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 979                 clock-names = "baudclk", "apb_pclk";
 980                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 981                 reg-shift = <2>;
 982                 reg-io-width = <4>;
 983                 pinctrl-names = "default";
 984                 pinctrl-0 = <&uart4_xfer>;
 985                 status = "disabled";
 986         };
 987
 988         i2c4: i2c@ff3d0000 {
 989                 compatible = "rockchip,rk3399-i2c";
 990                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 991                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 992                 clock-names = "i2c", "pclk";
 993                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 994                 pinctrl-names = "default";
 995                 pinctrl-0 = <&i2c4_xfer>;
 996                 #address-cells = <1>;
 997                 #size-cells = <0>;
 998                 status = "disabled";
 999         };
1000
1001         i2c8: i2c@ff3e0000 {
1002                 compatible = "rockchip,rk3399-i2c";
1003                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1004                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1005                 clock-names = "i2c", "pclk";
1006                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
1007                 pinctrl-names = "default";
1008                 pinctrl-0 = <&i2c8_xfer>;
1009                 #address-cells = <1>;
1010                 #size-cells = <0>;
1011                 status = "disabled";
1012         };
1013
1014         pcie0: pcie@f8000000 {
1015                 compatible = "rockchip,rk3399-pcie";
1016                 #address-cells = <3>;
1017                 #size-cells = <2>;
1018                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1019                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1020                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1021                               "hclk_pcie", "clk_pciephy_ref";
1022                 bus-range = <0x0 0x1>;
1023                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1024                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1025                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1026                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1027                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1028                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1029                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1030                       < 0x0 0xfd000000 0x0 0x1000000 >;
1031                 reg-name = "axi-base", "apb-base";
1032                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1033                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1034                          <&cru SRST_PCIE_PIPE>;
1035                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1036                               "mgmt-sticky-rst", "pipe-rst";
1037                 rockchip,grf = <&grf>;
1038                 pcie-conf = <0xe220>;
1039                 pcie-status = <0xe2a4>;
1040                 pcie-laneoff = <0xe214>;
1041                 msi-parent = <&its>;
1042                 #interrupt-cells = <1>;
1043                 interrupt-map-mask = <0 0 0 7>;
1044                 interrupt-map = <0 0 0 1 &pcie0 1>,
1045                                 <0 0 0 2 &pcie0 2>,
1046                                 <0 0 0 3 &pcie0 3>,
1047                                 <0 0 0 4 &pcie0 4>;
1048                 status = "disabled";
1049                 pcie_intc: interrupt-controller {
1050                         interrupt-controller;
1051                         #address-cells = <0>;
1052                         #interrupt-cells = <1>;
1053                 };
1054         };
1055
1056         pwm0: pwm@ff420000 {
1057                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1058                 reg = <0x0 0xff420000 0x0 0x10>;
1059                 #pwm-cells = <3>;
1060                 pinctrl-names = "default";
1061                 pinctrl-0 = <&pwm0_pin>;
1062                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1063                 clock-names = "pwm";
1064                 status = "disabled";
1065         };
1066
1067         pwm1: pwm@ff420010 {
1068                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1069                 reg = <0x0 0xff420010 0x0 0x10>;
1070                 #pwm-cells = <3>;
1071                 pinctrl-names = "default";
1072                 pinctrl-0 = <&pwm1_pin>;
1073                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1074                 clock-names = "pwm";
1075                 status = "disabled";
1076         };
1077
1078         pwm2: pwm@ff420020 {
1079                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1080                 reg = <0x0 0xff420020 0x0 0x10>;
1081                 #pwm-cells = <3>;
1082                 pinctrl-names = "default";
1083                 pinctrl-0 = <&pwm2_pin>;
1084                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1085                 clock-names = "pwm";
1086                 status = "disabled";
1087         };
1088
1089         pwm3: pwm@ff420030 {
1090                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1091                 reg = <0x0 0xff420030 0x0 0x10>;
1092                 #pwm-cells = <3>;
1093                 pinctrl-names = "default";
1094                 pinctrl-0 = <&pwm3a_pin>;
1095                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1096                 clock-names = "pwm";
1097                 status = "disabled";
1098         };
1099
1100         rga: rga@ff680000 {
1101                 compatible = "rockchip,rk3399-rga";
1102                 reg = <0x0 0xff680000 0x0 0x10000>;
1103                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1104                 interrupt-names = "rga";
1105                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1106                 clock-names = "aclk", "hclk", "sclk";
1107                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1108                 reset-names = "core", "axi", "ahb";
1109                 status = "disabled";
1110         };
1111
1112         pmucru: pmu-clock-controller@ff750000 {
1113                 compatible = "rockchip,rk3399-pmucru";
1114                 reg = <0x0 0xff750000 0x0 0x1000>;
1115                 #clock-cells = <1>;
1116                 #reset-cells = <1>;
1117                 assigned-clocks = <&pmucru PLL_PPLL>;
1118                 assigned-clock-rates = <676000000>;
1119         };
1120
1121         cru: clock-controller@ff760000 {
1122                 compatible = "rockchip,rk3399-cru";
1123                 reg = <0x0 0xff760000 0x0 0x1000>;
1124                 #clock-cells = <1>;
1125                 #reset-cells = <1>;
1126                 assigned-clocks =
1127                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1128                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1129                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1130                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1131                         <&cru PLL_NPLL>,
1132                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1133                         <&cru PCLK_PERIHP>,
1134                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1135                         <&cru PCLK_PERILP0>,
1136                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1137                 assigned-clock-rates =
1138                          <400000000>,  <200000000>,
1139                          <400000000>,  <200000000>,
1140                          <816000000>, <816000000>,
1141                          <594000000>,  <800000000>,
1142                         <1000000000>,
1143                          <150000000>,   <75000000>,
1144                           <37500000>,
1145                          <100000000>,  <100000000>,
1146                           <50000000>,
1147                          <100000000>,   <50000000>;
1148         };
1149
1150         grf: syscon@ff770000 {
1151                 compatible = "rockchip,rk3399-grf", "syscon";
1152                 reg = <0x0 0xff770000 0x0 0x10000>;
1153         };
1154
1155         watchdog@ff840000 {
1156                 compatible = "snps,dw-wdt";
1157                 reg = <0x0 0xff840000 0x0 0x100>;
1158                 clocks = <&cru PCLK_WDT>;
1159                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1160         };
1161
1162         rktimer: rktimer@ff850000 {
1163                 compatible = "rockchip,rk3399-timer";
1164                 reg = <0x0 0xff850000 0x0 0x1000>;
1165                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1166                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1167                 clock-names = "pclk", "timer";
1168         };
1169
1170         spdif: spdif@ff870000 {
1171                 compatible = "rockchip,rk3399-spdif";
1172                 reg = <0x0 0xff870000 0x0 0x1000>;
1173                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1174                 dmas = <&dmac_bus 7>;
1175                 dma-names = "tx";
1176                 clock-names = "mclk", "hclk";
1177                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1178                 pinctrl-names = "default";
1179                 pinctrl-0 = <&spdif_bus>;
1180                 status = "disabled";
1181         };
1182
1183         i2s0: i2s@ff880000 {
1184                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1185                 reg = <0x0 0xff880000 0x0 0x1000>;
1186                 rockchip,grf = <&grf>;
1187                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1188                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1189                 dma-names = "tx", "rx";
1190                 clock-names = "i2s_clk", "i2s_hclk";
1191                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1192                 pinctrl-names = "default";
1193                 pinctrl-0 = <&i2s0_8ch_bus>;
1194                 status = "disabled";
1195         };
1196
1197         i2s1: i2s@ff890000 {
1198                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1199                 reg = <0x0 0xff890000 0x0 0x1000>;
1200                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1201                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1202                 dma-names = "tx", "rx";
1203                 clock-names = "i2s_clk", "i2s_hclk";
1204                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1205                 pinctrl-names = "default";
1206                 pinctrl-0 = <&i2s1_2ch_bus>;
1207                 status = "disabled";
1208         };
1209
1210         i2s2: i2s@ff8a0000 {
1211                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1212                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1213                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1214                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1215                 dma-names = "tx", "rx";
1216                 clock-names = "i2s_clk", "i2s_hclk";
1217                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1218                 status = "disabled";
1219         };
1220
1221         gpu: gpu@ff9a0000 {
1222                 compatible = "arm,malit860",
1223                              "arm,malit86x",
1224                              "arm,malit8xx",
1225                              "arm,mali-midgard";
1226
1227                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1228
1229                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1230                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1231                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1232                 interrupt-names = "GPU", "JOB", "MMU";
1233
1234                 clocks = <&cru ACLK_GPU>;
1235                 clock-names = "clk_mali";
1236                 #cooling-cells = <2>; /* min followed by max */
1237                 operating-points-v2 = <&gpu_opp_table>;
1238                 power-domains = <&power RK3399_PD_GPU>;
1239                 power-off-delay-ms = <200>;
1240                 status = "disabled";
1241
1242                 power_model {
1243                         compatible = "arm,mali-simple-power-model";
1244                         voltage = <900>;
1245                         frequency = <500>;
1246                         static-power = <300>;
1247                         dynamic-power = <1780>;
1248                         ts = <32000 4700 (-80) 2>;
1249                         thermal-zone = "gpu-thermal";
1250                 };
1251         };
1252
1253         gpu_opp_table: gpu_opp_table {
1254                 compatible = "operating-points-v2";
1255                 opp-shared;
1256
1257                 opp00 {
1258                         opp-hz = /bits/ 64 <200000000>;
1259                         opp-microvolt = <900000>;
1260                 };
1261                 opp01 {
1262                         opp-hz = /bits/ 64 <300000000>;
1263                         opp-microvolt = <900000>;
1264                 };
1265                 opp02 {
1266                         opp-hz = /bits/ 64 <400000000>;
1267                         opp-microvolt = <900000>;
1268                 };
1269
1270         };
1271
1272         vopl: vop@ff8f0000 {
1273                 compatible = "rockchip,rk3399-vop-lit";
1274                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1275                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1276                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1277                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1278                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1279                 reset-names = "axi", "ahb", "dclk";
1280                 iommus = <&vopl_mmu>;
1281                 status = "disabled";
1282
1283                 vopl_out: port {
1284                         #address-cells = <1>;
1285                         #size-cells = <0>;
1286
1287                         vopl_out_mipi: endpoint@0 {
1288                                 reg = <0>;
1289                                 remote-endpoint = <&mipi_in_vopl>;
1290                         };
1291
1292                         vopl_out_edp: endpoint@1 {
1293                                 reg = <1>;
1294                                 remote-endpoint = <&edp_in_vopl>;
1295                         };
1296                 };
1297         };
1298
1299         vopl_mmu: iommu@ff8f3f00 {
1300                 compatible = "rockchip,iommu";
1301                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1302                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1303                 interrupt-names = "vopl_mmu";
1304                 #iommu-cells = <0>;
1305                 status = "disabled";
1306         };
1307
1308         vopb: vop@ff900000 {
1309                 compatible = "rockchip,rk3399-vop-big";
1310                 reg = <0x0 0xff900000 0x0 0x3efc>;
1311                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1312                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1313                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1314                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1315                 reset-names = "axi", "ahb", "dclk";
1316                 iommus = <&vopb_mmu>;
1317                 status = "disabled";
1318
1319                 vopb_out: port {
1320                         #address-cells = <1>;
1321                         #size-cells = <0>;
1322
1323                         vopb_out_edp: endpoint@0 {
1324                                 reg = <0>;
1325                                 remote-endpoint = <&edp_in_vopb>;
1326                         };
1327
1328                         vopb_out_mipi: endpoint@1 {
1329                                 reg = <1>;
1330                                 remote-endpoint = <&mipi_in_vopb>;
1331                         };
1332                 };
1333         };
1334
1335         vopb_mmu: iommu@ff903f00 {
1336                 compatible = "rockchip,iommu";
1337                 reg = <0x0 0xff903f00 0x0 0x100>;
1338                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1339                 interrupt-names = "vopb_mmu";
1340                 #iommu-cells = <0>;
1341                 status = "disabled";
1342         };
1343
1344         mipi_dsi: mipi@ff960000 {
1345                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1346                 reg = <0x0 0xff960000 0x0 0x8000>;
1347                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1348                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1349                          <&cru SCLK_DPHY_TX0_CFG>;
1350                 clock-names = "ref", "pclk", "phy_cfg";
1351                 rockchip,grf = <&grf>;
1352                 #address-cells = <1>;
1353                 #size-cells = <0>;
1354                 status = "disabled";
1355
1356                 ports {
1357                         #address-cells = <1>;
1358                         #size-cells = <0>;
1359                         reg = <1>;
1360
1361                         mipi_in: port {
1362                                 #address-cells = <1>;
1363                                 #size-cells = <0>;
1364
1365                                 mipi_in_vopb: endpoint@0 {
1366                                         reg = <0>;
1367                                         remote-endpoint = <&vopb_out_mipi>;
1368                                 };
1369                                 mipi_in_vopl: endpoint@1 {
1370                                         reg = <1>;
1371                                         remote-endpoint = <&vopl_out_mipi>;
1372                                 };
1373                         };
1374                 };
1375         };
1376
1377         edp: edp@ff970000 {
1378                 compatible = "rockchip,rk3399-edp";
1379                 reg = <0x0 0xff970000 0x0 0x8000>;
1380                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1381                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1382                 clock-names = "dp", "pclk";
1383                 resets = <&cru SRST_P_EDP_CTRL>;
1384                 reset-names = "dp";
1385                 rockchip,grf = <&grf>;
1386                 status = "disabled";
1387                 pinctrl-names = "default";
1388                 pinctrl-0 = <&edp_hpd>;
1389
1390                 ports {
1391                         #address-cells = <1>;
1392                         #size-cells = <0>;
1393
1394                         edp_in: port@0 {
1395                                 reg = <0>;
1396                                 #address-cells = <1>;
1397                                 #size-cells = <0>;
1398
1399                                 edp_in_vopb: endpoint@0 {
1400                                         reg = <0>;
1401                                         remote-endpoint = <&vopb_out_edp>;
1402                                 };
1403
1404                                 edp_in_vopl: endpoint@1 {
1405                                         reg = <1>;
1406                                         remote-endpoint = <&vopl_out_edp>;
1407                                 };
1408                         };
1409                 };
1410         };
1411
1412         display_subsystem: display-subsystem {
1413                 compatible = "rockchip,display-subsystem";
1414                 ports = <&vopl_out>, <&vopb_out>;
1415                 status = "disabled";
1416         };
1417
1418         pinctrl: pinctrl {
1419                 compatible = "rockchip,rk3399-pinctrl";
1420                 rockchip,grf = <&grf>;
1421                 rockchip,pmu = <&pmugrf>;
1422                 #address-cells = <0x2>;
1423                 #size-cells = <0x2>;
1424                 ranges;
1425
1426                 gpio0: gpio0@ff720000 {
1427                         compatible = "rockchip,gpio-bank";
1428                         reg = <0x0 0xff720000 0x0 0x100>;
1429                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1430                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1431
1432                         gpio-controller;
1433                         #gpio-cells = <0x2>;
1434
1435                         interrupt-controller;
1436                         #interrupt-cells = <0x2>;
1437                 };
1438
1439                 gpio1: gpio1@ff730000 {
1440                         compatible = "rockchip,gpio-bank";
1441                         reg = <0x0 0xff730000 0x0 0x100>;
1442                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1443                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1444
1445                         gpio-controller;
1446                         #gpio-cells = <0x2>;
1447
1448                         interrupt-controller;
1449                         #interrupt-cells = <0x2>;
1450                 };
1451
1452                 gpio2: gpio2@ff780000 {
1453                         compatible = "rockchip,gpio-bank";
1454                         reg = <0x0 0xff780000 0x0 0x100>;
1455                         clocks = <&cru PCLK_GPIO2>;
1456                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1457
1458                         gpio-controller;
1459                         #gpio-cells = <0x2>;
1460
1461                         interrupt-controller;
1462                         #interrupt-cells = <0x2>;
1463                 };
1464
1465                 gpio3: gpio3@ff788000 {
1466                         compatible = "rockchip,gpio-bank";
1467                         reg = <0x0 0xff788000 0x0 0x100>;
1468                         clocks = <&cru PCLK_GPIO3>;
1469                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1470
1471                         gpio-controller;
1472                         #gpio-cells = <0x2>;
1473
1474                         interrupt-controller;
1475                         #interrupt-cells = <0x2>;
1476                 };
1477
1478                 gpio4: gpio4@ff790000 {
1479                         compatible = "rockchip,gpio-bank";
1480                         reg = <0x0 0xff790000 0x0 0x100>;
1481                         clocks = <&cru PCLK_GPIO4>;
1482                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1483
1484                         gpio-controller;
1485                         #gpio-cells = <0x2>;
1486
1487                         interrupt-controller;
1488                         #interrupt-cells = <0x2>;
1489                 };
1490
1491                 pcfg_pull_up: pcfg-pull-up {
1492                         bias-pull-up;
1493                 };
1494
1495                 pcfg_pull_down: pcfg-pull-down {
1496                         bias-pull-down;
1497                 };
1498
1499                 pcfg_pull_none: pcfg-pull-none {
1500                         bias-disable;
1501                 };
1502
1503                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1504                         bias-disable;
1505                         drive-strength = <12>;
1506                 };
1507
1508                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1509                         bias-pull-up;
1510                         drive-strength = <8>;
1511                 };
1512
1513                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1514                         bias-pull-down;
1515                         drive-strength = <4>;
1516                 };
1517
1518                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1519                         bias-pull-up;
1520                         drive-strength = <2>;
1521                 };
1522
1523                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1524                         bias-pull-down;
1525                         drive-strength = <12>;
1526                 };
1527
1528                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1529                         bias-disable;
1530                         drive-strength = <13>;
1531                 };
1532
1533                 emmc {
1534                         emmc_pwr: emmc-pwr {
1535                                 rockchip,pins =
1536                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1537                         };
1538                 };
1539
1540                 gmac {
1541                         rgmii_pins: rgmii-pins {
1542                                 rockchip,pins =
1543                                         /* mac_txclk */
1544                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1545                                         /* mac_rxclk */
1546                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1547                                         /* mac_mdio */
1548                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1549                                         /* mac_txen */
1550                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1551                                         /* mac_clk */
1552                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1553                                         /* mac_rxdv */
1554                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1555                                         /* mac_mdc */
1556                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1557                                         /* mac_rxd1 */
1558                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxd0 */
1560                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_txd1 */
1562                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1563                                         /* mac_txd0 */
1564                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1565                                         /* mac_rxd3 */
1566                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1567                                         /* mac_rxd2 */
1568                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1569                                         /* mac_txd3 */
1570                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1571                                         /* mac_txd2 */
1572                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1573                         };
1574
1575                         rmii_pins: rmii-pins {
1576                                 rockchip,pins =
1577                                         /* mac_mdio */
1578                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1579                                         /* mac_txen */
1580                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1581                                         /* mac_clk */
1582                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1583                                         /* mac_rxer */
1584                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1585                                         /* mac_rxdv */
1586                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1587                                         /* mac_mdc */
1588                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1589                                         /* mac_rxd1 */
1590                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1591                                         /* mac_rxd0 */
1592                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1593                                         /* mac_txd1 */
1594                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1595                                         /* mac_txd0 */
1596                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1597                         };
1598                 };
1599
1600                 i2c0 {
1601                         i2c0_xfer: i2c0-xfer {
1602                                 rockchip,pins =
1603                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1604                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1605                         };
1606                 };
1607
1608                 i2c1 {
1609                         i2c1_xfer: i2c1-xfer {
1610                                 rockchip,pins =
1611                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1612                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1613                         };
1614                 };
1615
1616                 i2c2 {
1617                         i2c2_xfer: i2c2-xfer {
1618                                 rockchip,pins =
1619                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1620                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1621                         };
1622                 };
1623
1624                 i2c3 {
1625                         i2c3_xfer: i2c3-xfer {
1626                                 rockchip,pins =
1627                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1628                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1629                         };
1630
1631                         i2c3_gpio: i2c3_gpio {
1632                                 rockchip,pins =
1633                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1634                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1635                         };
1636
1637                 };
1638
1639                 i2c4 {
1640                         i2c4_xfer: i2c4-xfer {
1641                                 rockchip,pins =
1642                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1643                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1644                         };
1645                 };
1646
1647                 i2c5 {
1648                         i2c5_xfer: i2c5-xfer {
1649                                 rockchip,pins =
1650                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1651                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1652                         };
1653                 };
1654
1655                 i2c6 {
1656                         i2c6_xfer: i2c6-xfer {
1657                                 rockchip,pins =
1658                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1659                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1660                         };
1661                 };
1662
1663                 i2c7 {
1664                         i2c7_xfer: i2c7-xfer {
1665                                 rockchip,pins =
1666                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1667                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 i2c8 {
1672                         i2c8_xfer: i2c8-xfer {
1673                                 rockchip,pins =
1674                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1675                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1676                         };
1677                 };
1678
1679                 i2s0 {
1680                         i2s0_8ch_bus: i2s0-8ch-bus {
1681                                 rockchip,pins =
1682                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1683                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1684                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1685                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1686                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1687                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1688                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1689                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1690                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692                 };
1693
1694                 i2s1 {
1695                         i2s1_2ch_bus: i2s1-2ch-bus {
1696                                 rockchip,pins =
1697                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1698                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1699                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1700                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1701                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703                 };
1704
1705                 sdio0 {
1706                         sdio0_bus1: sdio0-bus1 {
1707                                 rockchip,pins =
1708                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1709                         };
1710
1711                         sdio0_bus4: sdio0-bus4 {
1712                                 rockchip,pins =
1713                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1714                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1715                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1716                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1717                         };
1718
1719                         sdio0_cmd: sdio0-cmd {
1720                                 rockchip,pins =
1721                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723
1724                         sdio0_clk: sdio0-clk {
1725                                 rockchip,pins =
1726                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1727                         };
1728
1729                         sdio0_cd: sdio0-cd {
1730                                 rockchip,pins =
1731                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1732                         };
1733
1734                         sdio0_pwr: sdio0-pwr {
1735                                 rockchip,pins =
1736                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1737                         };
1738
1739                         sdio0_bkpwr: sdio0-bkpwr {
1740                                 rockchip,pins =
1741                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1742                         };
1743
1744                         sdio0_wp: sdio0-wp {
1745                                 rockchip,pins =
1746                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1747                         };
1748
1749                         sdio0_int: sdio0-int {
1750                                 rockchip,pins =
1751                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1752                         };
1753                 };
1754
1755                 sdmmc {
1756                         sdmmc_bus1: sdmmc-bus1 {
1757                                 rockchip,pins =
1758                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1759                         };
1760
1761                         sdmmc_bus4: sdmmc-bus4 {
1762                                 rockchip,pins =
1763                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1764                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1765                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1766                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1767                         };
1768
1769                         sdmmc_clk: sdmmc-clk {
1770                                 rockchip,pins =
1771                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1772                         };
1773
1774                         sdmmc_cmd: sdmmc-cmd {
1775                                 rockchip,pins =
1776                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1777                         };
1778
1779                         sdmmc_cd: sdmcc-cd {
1780                                 rockchip,pins =
1781                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1782                         };
1783
1784                         sdmmc_wp: sdmmc-wp {
1785                                 rockchip,pins =
1786                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1787                         };
1788                 };
1789
1790                 spdif {
1791                         spdif_bus: spdif-bus {
1792                                 rockchip,pins =
1793                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1794                         };
1795                 };
1796
1797                 spi0 {
1798                         spi0_clk: spi0-clk {
1799                                 rockchip,pins =
1800                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1801                         };
1802                         spi0_cs0: spi0-cs0 {
1803                                 rockchip,pins =
1804                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1805                         };
1806                         spi0_cs1: spi0-cs1 {
1807                                 rockchip,pins =
1808                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1809                         };
1810                         spi0_tx: spi0-tx {
1811                                 rockchip,pins =
1812                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1813                         };
1814                         spi0_rx: spi0-rx {
1815                                 rockchip,pins =
1816                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1817                         };
1818                 };
1819
1820                 spi1 {
1821                         spi1_clk: spi1-clk {
1822                                 rockchip,pins =
1823                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1824                         };
1825                         spi1_cs0: spi1-cs0 {
1826                                 rockchip,pins =
1827                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1828                         };
1829                         spi1_rx: spi1-rx {
1830                                 rockchip,pins =
1831                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1832                         };
1833                         spi1_tx: spi1-tx {
1834                                 rockchip,pins =
1835                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1836                         };
1837                 };
1838
1839                 spi2 {
1840                         spi2_clk: spi2-clk {
1841                                 rockchip,pins =
1842                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1843                         };
1844                         spi2_cs0: spi2-cs0 {
1845                                 rockchip,pins =
1846                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1847                         };
1848                         spi2_rx: spi2-rx {
1849                                 rockchip,pins =
1850                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852                         spi2_tx: spi2-tx {
1853                                 rockchip,pins =
1854                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1855                         };
1856                 };
1857
1858                 spi3 {
1859                         spi3_clk: spi3-clk {
1860                                 rockchip,pins =
1861                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1862                         };
1863                         spi3_cs0: spi3-cs0 {
1864                                 rockchip,pins =
1865                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1866                         };
1867                         spi3_rx: spi3-rx {
1868                                 rockchip,pins =
1869                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1870                         };
1871                         spi3_tx: spi3-tx {
1872                                 rockchip,pins =
1873                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1874                         };
1875                 };
1876
1877                 spi4 {
1878                         spi4_clk: spi4-clk {
1879                                 rockchip,pins =
1880                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1881                         };
1882                         spi4_cs0: spi4-cs0 {
1883                                 rockchip,pins =
1884                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1885                         };
1886                         spi4_rx: spi4-rx {
1887                                 rockchip,pins =
1888                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1889                         };
1890                         spi4_tx: spi4-tx {
1891                                 rockchip,pins =
1892                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1893                         };
1894                 };
1895
1896                 spi5 {
1897                         spi5_clk: spi5-clk {
1898                                 rockchip,pins =
1899                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1900                         };
1901                         spi5_cs0: spi5-cs0 {
1902                                 rockchip,pins =
1903                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1904                         };
1905                         spi5_rx: spi5-rx {
1906                                 rockchip,pins =
1907                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1908                         };
1909                         spi5_tx: spi5-tx {
1910                                 rockchip,pins =
1911                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1912                         };
1913                 };
1914
1915                 tsadc {
1916                         otp_gpio: otp-gpio {
1917                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1918                         };
1919
1920                         otp_out: otp-out {
1921                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1922                         };
1923                 };
1924
1925                 uart0 {
1926                         uart0_xfer: uart0-xfer {
1927                                 rockchip,pins =
1928                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1929                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1930                         };
1931
1932                         uart0_cts: uart0-cts {
1933                                 rockchip,pins =
1934                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1935                         };
1936
1937                         uart0_rts: uart0-rts {
1938                                 rockchip,pins =
1939                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1940                         };
1941                 };
1942
1943                 uart1 {
1944                         uart1_xfer: uart1-xfer {
1945                                 rockchip,pins =
1946                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1947                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1948                         };
1949                 };
1950
1951                 uart2a {
1952                         uart2a_xfer: uart2a-xfer {
1953                                 rockchip,pins =
1954                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1955                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1956                         };
1957                 };
1958
1959                 uart2b {
1960                         uart2b_xfer: uart2b-xfer {
1961                                 rockchip,pins =
1962                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1963                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1964                         };
1965                 };
1966
1967                 uart2c {
1968                         uart2c_xfer: uart2c-xfer {
1969                                 rockchip,pins =
1970                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1971                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1972                         };
1973                 };
1974
1975                 uart3 {
1976                         uart3_xfer: uart3-xfer {
1977                                 rockchip,pins =
1978                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1979                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1980                         };
1981
1982                         uart3_cts: uart3-cts {
1983                                 rockchip,pins =
1984                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1985                         };
1986
1987                         uart3_rts: uart3-rts {
1988                                 rockchip,pins =
1989                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1990                         };
1991                 };
1992
1993                 uart4 {
1994                         uart4_xfer: uart4-xfer {
1995                                 rockchip,pins =
1996                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1997                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1998                         };
1999                 };
2000
2001                 uarthdcp {
2002                         uarthdcp_xfer: uarthdcp-xfer {
2003                                 rockchip,pins =
2004                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2005                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2006                         };
2007                 };
2008
2009                 pwm0 {
2010                         pwm0_pin: pwm0-pin {
2011                                 rockchip,pins =
2012                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2013                         };
2014
2015                         vop0_pwm_pin: vop0-pwm-pin {
2016                                 rockchip,pins =
2017                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2018                         };
2019                 };
2020
2021                 pwm1 {
2022                         pwm1_pin: pwm1-pin {
2023                                 rockchip,pins =
2024                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2025                         };
2026
2027                         vop1_pwm_pin: vop1-pwm-pin {
2028                                 rockchip,pins =
2029                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2030                         };
2031                 };
2032
2033                 pwm2 {
2034                         pwm2_pin: pwm2-pin {
2035                                 rockchip,pins =
2036                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2037                         };
2038                 };
2039
2040                 pwm3a {
2041                         pwm3a_pin: pwm3a-pin {
2042                                 rockchip,pins =
2043                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2044                         };
2045                 };
2046
2047                 pwm3b {
2048                         pwm3b_pin: pwm3b-pin {
2049                                 rockchip,pins =
2050                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2051                         };
2052                 };
2053
2054                 edp {
2055                         edp_hpd: edp-hpd {
2056                                 rockchip,pins =
2057                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2058                         };
2059                 };
2060
2061                 hdmi {
2062                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2063                                 rockchip,pins =
2064                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2065                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2066                         };
2067
2068                         hdmi_cec: hdmi-cec {
2069                                 rockchip,pins =
2070                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2071                         };
2072                 };
2073
2074                 pcie {
2075                         pcie_clkreqn: pci-clkreqn {
2076                                 rockchip,pins =
2077                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2078                         };
2079
2080                         pcie_clkreqnb: pci-clkreqnb {
2081                                 rockchip,pins =
2082                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2083                         };
2084                 };
2085         };
2086 };