arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip_boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3399";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 i2c6 = &i2c6;
  67                 i2c7 = &i2c7;
  68                 i2c8 = &i2c8;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74         };
  75
  76         psci {
  77                 compatible = "arm,psci-1.0";
  78                 method = "smc";
  79         };
  80
  81         cpus {
  82                 #address-cells = <2>;
  83                 #size-cells = <0>;
  84
  85                 cpu-map {
  86                         cluster0 {
  87                                 core0 {
  88                                         cpu = <&cpu_l0>;
  89                                 };
  90                                 core1 {
  91                                         cpu = <&cpu_l1>;
  92                                 };
  93                                 core2 {
  94                                         cpu = <&cpu_l2>;
  95                                 };
  96                                 core3 {
  97                                         cpu = <&cpu_l3>;
  98                                 };
  99                         };
 100
 101                         cluster1 {
 102                                 core0 {
 103                                         cpu = <&cpu_b0>;
 104                                 };
 105                                 core1 {
 106                                         cpu = <&cpu_b1>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116                         #cooling-cells = <2>; /* min followed by max */
 117                         clocks = <&cru ARMCLKL>;
 118                         cpu-idle-states = <&cpu_sleep>;
 119                         operating-points-v2 = <&cluster0_opp>;
 120                 };
 121
 122                 cpu_l1: cpu@1 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a53", "arm,armv8";
 125                         reg = <0x0 0x1>;
 126                         enable-method = "psci";
 127                         clocks = <&cru ARMCLKL>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         operating-points-v2 = <&cluster0_opp>;
 130                 };
 131
 132                 cpu_l2: cpu@2 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a53", "arm,armv8";
 135                         reg = <0x0 0x2>;
 136                         enable-method = "psci";
 137                         clocks = <&cru ARMCLKL>;
 138                         cpu-idle-states = <&cpu_sleep>;
 139                         operating-points-v2 = <&cluster0_opp>;
 140                 };
 141
 142                 cpu_l3: cpu@3 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a53", "arm,armv8";
 145                         reg = <0x0 0x3>;
 146                         enable-method = "psci";
 147                         clocks = <&cru ARMCLKL>;
 148                         cpu-idle-states = <&cpu_sleep>;
 149                         operating-points-v2 = <&cluster0_opp>;
 150                 };
 151
 152                 cpu_b0: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a72", "arm,armv8";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         #cooling-cells = <2>; /* min followed by max */
 158                         clocks = <&cru ARMCLKB>;
 159                         cpu-idle-states = <&cpu_sleep>;
 160                         operating-points-v2 = <&cluster1_opp>;
 161                 };
 162
 163                 cpu_b1: cpu@101 {
 164                         device_type = "cpu";
 165                         compatible = "arm,cortex-a72", "arm,armv8";
 166                         reg = <0x0 0x101>;
 167                         enable-method = "psci";
 168                         clocks = <&cru ARMCLKB>;
 169                         cpu-idle-states = <&cpu_sleep>;
 170                         operating-points-v2 = <&cluster1_opp>;
 171                 };
 172
 173                 idle-states {
 174                         entry-method = "psci";
 175                         cpu_sleep: cpu-sleep-0 {
 176                                 compatible = "arm,idle-state";
 177                                 local-timer-stop;
 178                                 arm,psci-suspend-param = <0x0010000>;
 179                                 entry-latency-us = <350>;
 180                                 exit-latency-us = <600>;
 181                                 min-residency-us = <1150>;
 182                         };
 183                 };
 184         };
 185
 186         cluster0_opp: opp_table0 {
 187                 compatible = "operating-points-v2";
 188                 opp-shared;
 189
 190                 opp00 {
 191                         opp-hz = /bits/ 64 <408000000>;
 192                         opp-microvolt = <800000>;
 193                         clock-latency-ns = <40000>;
 194                 };
 195                 opp01 {
 196                         opp-hz = /bits/ 64 <600000000>;
 197                         opp-microvolt = <800000>;
 198                 };
 199                 opp02 {
 200                         opp-hz = /bits/ 64 <816000000>;
 201                         opp-microvolt = <800000>;
 202                 };
 203                 opp03 {
 204                         opp-hz = /bits/ 64 <1008000000>;
 205                         opp-microvolt = <875000>;
 206                 };
 207                 opp04 {
 208                         opp-hz = /bits/ 64 <1200000000>;
 209                         opp-microvolt = <925000>;
 210                 };
 211                 opp05 {
 212                         opp-hz = /bits/ 64 <1416000000>;
 213                         opp-microvolt = <1025000>;
 214                 };
 215         };
 216
 217         cluster1_opp: opp_table1 {
 218                 compatible = "operating-points-v2";
 219                 opp-shared;
 220
 221                 opp00 {
 222                         opp-hz = /bits/ 64 <408000000>;
 223                         opp-microvolt = <800000>;
 224                         clock-latency-ns = <40000>;
 225                 };
 226                 opp01 {
 227                         opp-hz = /bits/ 64 <600000000>;
 228                         opp-microvolt = <800000>;
 229                 };
 230                 opp02 {
 231                         opp-hz = /bits/ 64 <816000000>;
 232                         opp-microvolt = <800000>;
 233                 };
 234                 opp03 {
 235                         opp-hz = /bits/ 64 <1008000000>;
 236                         opp-microvolt = <850000>;
 237                 };
 238                 opp04 {
 239                         opp-hz = /bits/ 64 <1200000000>;
 240                         opp-microvolt = <925000>;
 241                 };
 242         };
 243
 244         timer {
 245                 compatible = "arm,armv8-timer";
 246                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 250         };
 251
 252         arm-pmu {
 253                 compatible = "arm,armv8-pmuv3";
 254                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 255         };
 256
 257         xin24m: xin24m {
 258                 compatible = "fixed-clock";
 259                 #clock-cells = <0>;
 260                 clock-frequency = <24000000>;
 261                 clock-output-names = "xin24m";
 262         };
 263
 264         amba {
 265                 compatible = "arm,amba-bus";
 266                 #address-cells = <2>;
 267                 #size-cells = <2>;
 268                 ranges;
 269
 270                 dmac_bus: dma-controller@ff6d0000 {
 271                         compatible = "arm,pl330", "arm,primecell";
 272                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 273                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 274                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 275                         #dma-cells = <1>;
 276                         clocks = <&cru ACLK_DMAC0_PERILP>;
 277                         clock-names = "apb_pclk";
 278                 };
 279
 280                 dmac_peri: dma-controller@ff6e0000 {
 281                         compatible = "arm,pl330", "arm,primecell";
 282                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 283                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 284                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 285                         #dma-cells = <1>;
 286                         clocks = <&cru ACLK_DMAC1_PERILP>;
 287                         clock-names = "apb_pclk";
 288                 };
 289         };
 290
 291         gmac: eth@fe300000 {
 292                 compatible = "rockchip,rk3399-gmac";
 293                 reg = <0x0 0xfe300000 0x0 0x10000>;
 294                 rockchip,grf = <&grf>;
 295                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 296                 interrupt-names = "macirq";
 297                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 298                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 299                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 300                          <&cru PCLK_GMAC>;
 301                 clock-names = "stmmaceth", "mac_clk_rx",
 302                               "mac_clk_tx", "clk_mac_ref",
 303                               "clk_mac_refout", "aclk_mac",
 304                               "pclk_mac";
 305                 resets = <&cru SRST_A_GMAC>;
 306                 reset-names = "stmmaceth";
 307                 status = "disabled";
 308         };
 309
 310         emmc_phy: phy {
 311                 compatible = "rockchip,rk3399-emmc-phy";
 312                 reg-offset = <0xf780>;
 313                 #phy-cells = <0>;
 314                 rockchip,grf = <&grf>;
 315                 ctrl-base = <0xfe330000>;
 316                 status = "disabled";
 317         };
 318
 319         sdio0: dwmmc@fe310000 {
 320                 compatible = "rockchip,rk3399-dw-mshc",
 321                              "rockchip,rk3288-dw-mshc";
 322                 reg = <0x0 0xfe310000 0x0 0x4000>;
 323                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 324                 clock-freq-min-max = <400000 150000000>;
 325                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 326                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 327                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 328                 fifo-depth = <0x100>;
 329                 status = "disabled";
 330         };
 331
 332         sdmmc: dwmmc@fe320000 {
 333                 compatible = "rockchip,rk3399-dw-mshc",
 334                              "rockchip,rk3288-dw-mshc";
 335                 reg = <0x0 0xfe320000 0x0 0x4000>;
 336                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 339                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 status = "disabled";
 343         };
 344
 345         sdhci: sdhci@fe330000 {
 346                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 347                 reg = <0x0 0xfe330000 0x0 0x10000>;
 348                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 349                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 350                 clock-names = "clk_xin", "clk_ahb";
 351                 assigned-clocks = <&cru SCLK_EMMC>;
 352                 assigned-clock-parents = <&cru PLL_CPLL>;
 353                 assigned-clock-rates = <200000000>;
 354                 phys = <&emmc_phy>;
 355                 phy-names = "phy_arasan";
 356                 status = "disabled";
 357         };
 358
 359         usb2phy: usb2phy {
 360                 compatible = "rockchip,rk3399-usb-phy";
 361                 rockchip,grf = <&grf>;
 362                 #address-cells = <1>;
 363                 #size-cells = <0>;
 364
 365                 usb2phy0: usb2-phy0 {
 366                         #phy-cells = <0>;
 367                         #clock-cells = <0>;
 368                         reg = <0xe458>;
 369                 };
 370
 371                 usb2phy1: usb2-phy1 {
 372                         #phy-cells = <0>;
 373                         #clock-cells = <0>;
 374                         reg = <0xe468>;
 375                 };
 376         };
 377
 378         usb_host0_ehci: usb@fe380000 {
 379                 compatible = "generic-ehci";
 380                 reg = <0x0 0xfe380000 0x0 0x20000>;
 381                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 382                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 383                 clock-names = "hclk_host0", "hclk_host0_arb";
 384                 phys = <&usb2phy0>;
 385                 phy-names = "usb2_phy0";
 386                 status = "disabled";
 387         };
 388
 389         usb_host0_ohci: usb@fe3a0000 {
 390                 compatible = "generic-ohci";
 391                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 392                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 393                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
 394                 clock-names = "hclk_host0", "hclk_host0_arb";
 395                 status = "disabled";
 396         };
 397
 398         usb_host1_ehci: usb@fe3c0000 {
 399                 compatible = "generic-ehci";
 400                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 401                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 402                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 403                 clock-names = "hclk_host1", "hclk_host1_arb";
 404                 phys = <&usb2phy1>;
 405                 phy-names = "usb2_phy1";
 406                 status = "disabled";
 407         };
 408
 409         usb_host1_ohci: usb@fe3e0000 {
 410                 compatible = "generic-ohci";
 411                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 412                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 413                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
 414                 clock-names = "hclk_host1", "hclk_host1_arb";
 415                 status = "disabled";
 416         };
 417
 418         usbdrd3_0: usb@fe800000 {
 419                 compatible = "rockchip,dwc3";
 420                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 421                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 422                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 423                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
 424                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
 425                               "aclk_usb3", "aclk_usb3_grf";
 426                 #address-cells = <2>;
 427                 #size-cells = <2>;
 428                 ranges;
 429                 status = "disabled";
 430                 usbdrd_dwc3_0: dwc3 {
 431                         compatible = "snps,dwc3";
 432                         reg = <0x0 0xfe800000 0x0 0x100000>;
 433                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 434                         dr_mode = "otg";
 435                         tx-fifo-resize;
 436                         snps,dis_enblslpm_quirk;
 437                         snps,phyif_utmi_16_bits;
 438                         snps,dis_u2_freeclk_exists_quirk;
 439                         snps,dis_del_phy_power_chg_quirk;
 440                         snps,xhci_slow_suspend_quirk;
 441                         status = "disabled";
 442                 };
 443         };
 444
 445         usbdrd3_1: usb@fe900000 {
 446                 compatible = "rockchip,dwc3";
 447                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 448                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 449                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 450                 clock-names = "clk_usb3otg1_ref", "clk_usb3otg1_suspend",
 451                               "aclk_usb3otg1", "aclk_usb3_rksoc_axi_perf",
 452                               "aclk_usb3", "aclk_usb3_grf";
 453                 #address-cells = <2>;
 454                 #size-cells = <2>;
 455                 ranges;
 456                 status = "disabled";
 457                 usbdrd_dwc3_1: dwc3 {
 458                         compatible = "snps,dwc3";
 459                         reg = <0x0 0xfe900000 0x0 0x100000>;
 460                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 461                         dr_mode = "otg";
 462                         tx-fifo-resize;
 463                         snps,dis_enblslpm_quirk;
 464                         snps,phyif_utmi_16_bits;
 465                         snps,dis_u2_freeclk_exists_quirk;
 466                         snps,dis_del_phy_power_chg_quirk;
 467                         snps,xhci_slow_suspend_quirk;
 468                         status = "disabled";
 469                 };
 470         };
 471
 472         gic: interrupt-controller@fee00000 {
 473                 compatible = "arm,gic-v3";
 474                 #interrupt-cells = <3>;
 475                 #address-cells = <2>;
 476                 #size-cells = <2>;
 477                 ranges;
 478                 interrupt-controller;
 479
 480                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 481                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 482                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 483                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 484                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 485                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 486                 its: interrupt-controller@fee20000 {
 487                         compatible = "arm,gic-v3-its";
 488                         msi-controller;
 489                         reg = <0x0 0xfee20000 0x0 0x20000>;
 490                 };
 491         };
 492
 493         saradc: saradc@ff100000 {
 494                 compatible = "rockchip,rk3399-saradc";
 495                 reg = <0x0 0xff100000 0x0 0x100>;
 496                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 497                 #io-channel-cells = <1>;
 498                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 499                 clock-names = "saradc", "apb_pclk";
 500                 status = "disabled";
 501         };
 502
 503         i2c0: i2c@ff3c0000 {
 504                 compatible = "rockchip,rk3399-i2c";
 505                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 506                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 507                 clock-names = "i2c", "pclk";
 508                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&i2c0_xfer>;
 511                 #address-cells = <1>;
 512                 #size-cells = <0>;
 513                 status = "disabled";
 514         };
 515
 516         i2c1: i2c@ff110000 {
 517                 compatible = "rockchip,rk3399-i2c";
 518                 reg = <0x0 0xff110000 0x0 0x1000>;
 519                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 520                 clock-names = "i2c", "pclk";
 521                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 522                 pinctrl-names = "default";
 523                 pinctrl-0 = <&i2c1_xfer>;
 524                 #address-cells = <1>;
 525                 #size-cells = <0>;
 526                 status = "disabled";
 527         };
 528
 529         i2c2: i2c@ff120000 {
 530                 compatible = "rockchip,rk3399-i2c";
 531                 reg = <0x0 0xff120000 0x0 0x1000>;
 532                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 533                 clock-names = "i2c", "pclk";
 534                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 535                 pinctrl-names = "default";
 536                 pinctrl-0 = <&i2c2_xfer>;
 537                 #address-cells = <1>;
 538                 #size-cells = <0>;
 539                 status = "disabled";
 540         };
 541
 542         i2c3: i2c@ff130000 {
 543                 compatible = "rockchip,rk3399-i2c";
 544                 reg = <0x0 0xff130000 0x0 0x1000>;
 545                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 546                 clock-names = "i2c", "pclk";
 547                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 548                 pinctrl-names = "default";
 549                 pinctrl-0 = <&i2c3_xfer>;
 550                 #address-cells = <1>;
 551                 #size-cells = <0>;
 552                 status = "disabled";
 553         };
 554
 555         i2c5: i2c@ff140000 {
 556                 compatible = "rockchip,rk3399-i2c";
 557                 reg = <0x0 0xff140000 0x0 0x1000>;
 558                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 559                 clock-names = "i2c", "pclk";
 560                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c5_xfer>;
 563                 #address-cells = <1>;
 564                 #size-cells = <0>;
 565                 status = "disabled";
 566         };
 567
 568         i2c6: i2c@ff150000 {
 569                 compatible = "rockchip,rk3399-i2c";
 570                 reg = <0x0 0xff150000 0x0 0x1000>;
 571                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 572                 clock-names = "i2c", "pclk";
 573                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c6_xfer>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 status = "disabled";
 579         };
 580
 581         i2c7: i2c@ff160000 {
 582                 compatible = "rockchip,rk3399-i2c";
 583                 reg = <0x0 0xff160000 0x0 0x1000>;
 584                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c7_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         uart0: serial@ff180000 {
 595                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 596                 reg = <0x0 0xff180000 0x0 0x100>;
 597                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 598                 clock-names = "baudclk", "apb_pclk";
 599                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 600                 reg-shift = <2>;
 601                 reg-io-width = <4>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 604                 status = "disabled";
 605         };
 606
 607         uart1: serial@ff190000 {
 608                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 609                 reg = <0x0 0xff190000 0x0 0x100>;
 610                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 611                 clock-names = "baudclk", "apb_pclk";
 612                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 613                 reg-shift = <2>;
 614                 reg-io-width = <4>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart1_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         uart2: serial@ff1a0000 {
 621                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff1a0000 0x0 0x100>;
 623                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 624                 clock-names = "baudclk", "apb_pclk";
 625                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 626                 reg-shift = <2>;
 627                 reg-io-width = <4>;
 628                 pinctrl-names = "default";
 629                 pinctrl-0 = <&uart2c_xfer>;
 630                 status = "disabled";
 631         };
 632
 633         uart3: serial@ff1b0000 {
 634                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 635                 reg = <0x0 0xff1b0000 0x0 0x100>;
 636                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 pinctrl-names = "default";
 642                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 643                 status = "disabled";
 644         };
 645
 646         spi0: spi@ff1c0000 {
 647                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 648                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 649                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 650                 clock-names = "spiclk", "apb_pclk";
 651                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 652                 pinctrl-names = "default";
 653                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 654                 #address-cells = <1>;
 655                 #size-cells = <0>;
 656                 status = "disabled";
 657         };
 658
 659         spi1: spi@ff1d0000 {
 660                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 661                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 662                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 663                 clock-names = "spiclk", "apb_pclk";
 664                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 665                 pinctrl-names = "default";
 666                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 667                 #address-cells = <1>;
 668                 #size-cells = <0>;
 669                 status = "disabled";
 670         };
 671
 672         spi2: spi@ff1e0000 {
 673                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 674                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 675                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 676                 clock-names = "spiclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 678                 pinctrl-names = "default";
 679                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 status = "disabled";
 683         };
 684
 685         spi4: spi@ff1f0000 {
 686                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 687                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 688                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 689                 clock-names = "spiclk", "apb_pclk";
 690                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 691                 pinctrl-names = "default";
 692                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 693                 #address-cells = <1>;
 694                 #size-cells = <0>;
 695                 status = "disabled";
 696         };
 697
 698         spi5: spi@ff200000 {
 699                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 700                 reg = <0x0 0xff200000 0x0 0x1000>;
 701                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 702                 clock-names = "spiclk", "apb_pclk";
 703                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 706                 #address-cells = <1>;
 707                 #size-cells = <0>;
 708                 status = "disabled";
 709         };
 710
 711         thermal-zones {
 712                 cpu {
 713                         polling-delay-passive = <100>; /* milliseconds */
 714                         polling-delay = <1000>; /* milliseconds */
 715
 716                         thermal-sensors = <&tsadc 0>;
 717
 718                         trips {
 719                                 cpu_alert0: cpu_alert0 {
 720                                         temperature = <70000>; /* millicelsius */
 721                                         hysteresis = <2000>; /* millicelsius */
 722                                         type = "passive";
 723                                 };
 724                                 cpu_alert1: cpu_alert1 {
 725                                         temperature = <75000>; /* millicelsius */
 726                                         hysteresis = <2000>; /* millicelsius */
 727                                         type = "passive";
 728                                 };
 729                                 cpu_crit: cpu_crit {
 730                                         temperature = <95000>; /* millicelsius */
 731                                         hysteresis = <2000>; /* millicelsius */
 732                                         type = "critical";
 733                                 };
 734                         };
 735
 736                         cooling-maps {
 737                                 map0 {
 738                                         trip = <&cpu_alert0>;
 739                                         cooling-device =
 740                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 741                                 };
 742                                 map1 {
 743                                         trip = <&cpu_alert1>;
 744                                         cooling-device =
 745                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 746                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 747                                 };
 748                         };
 749                 };
 750
 751                 gpu {
 752                         polling-delay-passive = <100>; /* milliseconds */
 753                         polling-delay = <1000>; /* milliseconds */
 754
 755                         thermal-sensors = <&tsadc 1>;
 756
 757                         trips {
 758                                 gpu_alert0: gpu_alert0 {
 759                                         temperature = <75000>; /* millicelsius */
 760                                         hysteresis = <2000>; /* millicelsius */
 761                                         type = "passive";
 762                                 };
 763                                 gpu_crit: gpu_crit {
 764                                         temperature = <95000>; /* millicelsius */
 765                                         hysteresis = <2000>; /* millicelsius */
 766                                         type = "critical";
 767                                 };
 768                         };
 769
 770                         cooling-maps {
 771                                 map0 {
 772                                         trip = <&gpu_alert0>;
 773                                         cooling-device =
 774                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 775                                 };
 776                         };
 777                 };
 778         };
 779
 780         tsadc: tsadc@ff260000 {
 781                 compatible = "rockchip,rk3399-tsadc";
 782                 reg = <0x0 0xff260000 0x0 0x100>;
 783                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 784                 rockchip,grf = <&grf>;
 785                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 786                 clock-names = "tsadc", "apb_pclk";
 787                 assigned-clocks = <&cru SCLK_TSADC>;
 788                 assigned-clock-rates = <750000>;
 789                 resets = <&cru SRST_TSADC>;
 790                 reset-names = "tsadc-apb";
 791                 pinctrl-names = "init", "default", "sleep";
 792                 pinctrl-0 = <&otp_gpio>;
 793                 pinctrl-1 = <&otp_out>;
 794                 pinctrl-2 = <&otp_gpio>;
 795                 #thermal-sensor-cells = <1>;
 796                 rockchip,hw-tshut-temp = <95000>;
 797                 status = "disabled";
 798         };
 799
 800         qos_gpu: qos_gpu@0xffae0000 {
 801                 compatible ="syscon";
 802                 reg = <0x0 0xffae0000 0x0 0x20>;
 803         };
 804         qos_video_m0: qos_video_m0@0xffab8000 {
 805                 compatible ="syscon";
 806                 reg = <0x0 0xffab8000 0x0 0x20>;
 807         };
 808         qos_video_m1_r: qos_video_m1_r@0xffac0000 {
 809                 compatible ="syscon";
 810                 reg = <0x0 0xffac0000 0x0 0x20>;
 811         };
 812         qos_video_m1_w: qos_video_m1_w@0xffac0080 {
 813                 compatible ="syscon";
 814                 reg = <0x0 0xffac0080 0x0 0x20>;
 815         };
 816         qos_rga_r: qos_rga_r@0xffab0000 {
 817                 compatible ="syscon";
 818                 reg = <0x0 0xffab0000 0x0 0x20>;
 819         };
 820         qos_rga_w: qos_rga_w@0xffab0080 {
 821                 compatible ="syscon";
 822                 reg = <0x0 0xffab0000 0x0 0x20>;
 823         };
 824         qos_iep: qos_iep@0xffa98000 {
 825                 compatible ="syscon";
 826                 reg = <0x0 0xffa98000 0x0 0x20>;
 827         };
 828         qos_vop_big_r: qos_vop_big_r@0xffac8000 {
 829                 compatible ="syscon";
 830                 reg = <0x0 0xffac8000 0x0 0x20>;
 831         };
 832         qos_vop_big_w: qos_vop_big_w@0xffac8080 {
 833                 compatible ="syscon";
 834                 reg = <0x0 0xffac8080 0x0 0x20>;
 835         };
 836         qos_vop_little: qos_vop_little@0xffad0000 {
 837                 compatible ="syscon";
 838                 reg = <0x0 0xffad0000 0x0 0x20>;
 839         };
 840         qos_isp0_m0: qos_isp0_m0@0xffaa0000 {
 841                 compatible ="syscon";
 842                 reg = <0x0 0xffaa0000 0x0 0x20>;
 843         };
 844         qos_isp0_m1: qos_isp0_m1@0xffaa0080 {
 845                 compatible ="syscon";
 846                 reg = <0x0 0xffaa0080 0x0 0x20>;
 847         };
 848         qos_isp1_m0: qos_isp1_m0@0xffaa8000 {
 849                 compatible ="syscon";
 850                 reg = <0x0 0xffaa8000 0x0 0x20>;
 851         };
 852         qos_isp1_m1: qos_isp1_m1@0xffaa8080 {
 853                 compatible ="syscon";
 854                 reg = <0x0 0xffaa8080 0x0 0x20>;
 855         };
 856         qos_hdcp: qos_hdcp@0xffa90000 {
 857                 compatible ="syscon";
 858                 reg = <0x0 0xffa90000 0x0 0x20>;
 859         };
 860
 861         pmu: power-management@ff310000 {
 862                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 863                 reg = <0x0 0xff310000 0x0 0x1000>;
 864
 865                 power: power-controller {
 866                         status = "disabled";
 867                         compatible = "rockchip,rk3399-power-controller";
 868                         #power-domain-cells = <1>;
 869                         #address-cells = <1>;
 870                         #size-cells = <0>;
 871
 872                         pd_center {
 873                                 reg = <RK3399_PD_CENTER>;
 874                                 #address-cells = <1>;
 875                                 #size-cells = <0>;
 876
 877                                 pd_vdu {
 878                                         reg = <RK3399_PD_VDU>;
 879                                         pm_qos = <&qos_video_m1_r>,
 880                                                  <&qos_video_m1_w>;
 881                                 };
 882                                 pd_vcodec {
 883                                         reg = <RK3399_PD_VCODEC>;
 884                                         pm_qos = <&qos_video_m0>;
 885                                 };
 886                                 pd_iep {
 887                                         reg = <RK3399_PD_IEP>;
 888                                         pm_qos = <&qos_iep>;
 889                                 };
 890                                 pd_rga {
 891                                         reg = <RK3399_PD_RGA>;
 892                                         pm_qos = <&qos_rga_r>,
 893                                                  <&qos_rga_w>;
 894                                 };
 895                         };
 896                         pd_vio {
 897                                 reg = <RK3399_PD_VIO>;
 898                                 #address-cells = <1>;
 899                                 #size-cells = <0>;
 900
 901                                 pd_isp0 {
 902                                         reg = <RK3399_PD_ISP0>;
 903                                         pm_qos = <&qos_isp0_m0>,
 904                                                  <&qos_isp0_m1>;
 905                                 };
 906                                 pd_isp1 {
 907                                         reg = <RK3399_PD_ISP1>;
 908                                         pm_qos = <&qos_isp1_m0>,
 909                                                  <&qos_isp1_m1>;
 910                                 };
 911                                 pd_hdcp {
 912                                         reg = <RK3399_PD_HDCP>;
 913                                         pm_qos = <&qos_hdcp>;
 914                                 };
 915                                 pd_vo {
 916                                         reg = <RK3399_PD_VO>;
 917                                         #address-cells = <1>;
 918                                         #size-cells = <0>;
 919
 920                                         pd_vopb {
 921                                                 reg = <RK3399_PD_VOPB>;
 922                                                 pm_qos = <&qos_vop_big_r>,
 923                                                          <&qos_vop_big_w>;
 924                                         };
 925                                         pd_vopl {
 926                                                 reg = <RK3399_PD_VOPL>;
 927                                                 pm_qos = <&qos_vop_little>;
 928                                         };
 929                                 };
 930                         };
 931                         pd_gpu {
 932                                 reg = <RK3399_PD_GPU>;
 933                                 pm_qos = <&qos_gpu>;
 934                         };
 935                 };
 936         };
 937
 938         pmugrf: syscon@ff320000 {
 939                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 940                 reg = <0x0 0xff320000 0x0 0x1000>;
 941
 942                 reboot-mode {
 943                         compatible = "syscon-reboot-mode";
 944                         offset = <0x300>;
 945                         mode-normal = <BOOT_NORMAL>;
 946                         mode-recovery = <BOOT_RECOVERY>;
 947                         mode-bootloader = <BOOT_FASTBOOT>;
 948                         mode-loader = <BOOT_LOADER>;
 949                 };
 950         };
 951
 952         spi3: spi@ff350000 {
 953                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 954                 reg = <0x0 0xff350000 0x0 0x1000>;
 955                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
 956                 clock-names = "spiclk", "apb_pclk";
 957                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 958                 pinctrl-names = "default";
 959                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
 960                 #address-cells = <1>;
 961                 #size-cells = <0>;
 962                 status = "disabled";
 963         };
 964
 965         uart4: serial@ff370000 {
 966                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 967                 reg = <0x0 0xff370000 0x0 0x100>;
 968                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
 969                 clock-names = "baudclk", "apb_pclk";
 970                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 971                 reg-shift = <2>;
 972                 reg-io-width = <4>;
 973                 pinctrl-names = "default";
 974                 pinctrl-0 = <&uart4_xfer>;
 975                 status = "disabled";
 976         };
 977
 978         i2c4: i2c@ff3d0000 {
 979                 compatible = "rockchip,rk3399-i2c";
 980                 reg = <0x0 0xff3d0000 0x0 0x1000>;
 981                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
 982                 clock-names = "i2c", "pclk";
 983                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 984                 pinctrl-names = "default";
 985                 pinctrl-0 = <&i2c4_xfer>;
 986                 #address-cells = <1>;
 987                 #size-cells = <0>;
 988                 status = "disabled";
 989         };
 990
 991         i2c8: i2c@ff3e0000 {
 992                 compatible = "rockchip,rk3399-i2c";
 993                 reg = <0x0 0xff3e0000 0x0 0x1000>;
 994                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
 995                 clock-names = "i2c", "pclk";
 996                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 997                 pinctrl-names = "default";
 998                 pinctrl-0 = <&i2c8_xfer>;
 999                 #address-cells = <1>;
1000                 #size-cells = <0>;
1001                 status = "disabled";
1002         };
1003
1004         pcie0: pcie@f8000000 {
1005                 compatible = "rockchip,rk3399-pcie";
1006                 #address-cells = <3>;
1007                 #size-cells = <2>;
1008                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1009                          <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
1010                 clock-names = "aclk_pcie", "aclk_perf_pcie",
1011                               "hclk_pcie", "clk_pciephy_ref";
1012                 bus-range = <0x0 0x1>;
1013                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1014                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
1015                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1016                 interrupt-names = "pcie-sys", "pcie-legacy", "pcie-client";
1017                 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
1018                            0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
1019                 reg = < 0x0 0xf8000000 0x0 0x2000000 >,
1020                       < 0x0 0xfd000000 0x0 0x1000000 >;
1021                 reg-name = "axi-base", "apb-base";
1022                 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>,
1023                          <&cru SRST_PCIE_MGMT>, <&cru SRST_PCIE_MGMT_STICKY>,
1024                          <&cru SRST_PCIE_PIPE>;
1025                 reset-names = "phy-rst", "core-rst", "mgmt-rst",
1026                               "mgmt-sticky-rst", "pipe-rst";
1027                 rockchip,grf = <&grf>;
1028                 pcie-conf = <0xe220>;
1029                 pcie-status = <0xe2a4>;
1030                 pcie-laneoff = <0xe214>;
1031                 msi-parent = <&its>;
1032                 #interrupt-cells = <1>;
1033                 interrupt-map-mask = <0 0 0 7>;
1034                 interrupt-map = <0 0 0 1 &pcie0 1>,
1035                                 <0 0 0 2 &pcie0 2>,
1036                                 <0 0 0 3 &pcie0 3>,
1037                                 <0 0 0 4 &pcie0 4>;
1038                 status = "disabled";
1039                 pcie_intc: interrupt-controller {
1040                         interrupt-controller;
1041                         #address-cells = <0>;
1042                         #interrupt-cells = <1>;
1043                 };
1044         };
1045
1046         pwm0: pwm@ff420000 {
1047                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1048                 reg = <0x0 0xff420000 0x0 0x10>;
1049                 #pwm-cells = <3>;
1050                 pinctrl-names = "default";
1051                 pinctrl-0 = <&pwm0_pin>;
1052                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1053                 clock-names = "pwm";
1054                 status = "disabled";
1055         };
1056
1057         pwm1: pwm@ff420010 {
1058                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1059                 reg = <0x0 0xff420010 0x0 0x10>;
1060                 #pwm-cells = <3>;
1061                 pinctrl-names = "default";
1062                 pinctrl-0 = <&pwm1_pin>;
1063                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1064                 clock-names = "pwm";
1065                 status = "disabled";
1066         };
1067
1068         pwm2: pwm@ff420020 {
1069                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1070                 reg = <0x0 0xff420020 0x0 0x10>;
1071                 #pwm-cells = <3>;
1072                 pinctrl-names = "default";
1073                 pinctrl-0 = <&pwm2_pin>;
1074                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1075                 clock-names = "pwm";
1076                 status = "disabled";
1077         };
1078
1079         pwm3: pwm@ff420030 {
1080                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1081                 reg = <0x0 0xff420030 0x0 0x10>;
1082                 #pwm-cells = <3>;
1083                 pinctrl-names = "default";
1084                 pinctrl-0 = <&pwm3a_pin>;
1085                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1086                 clock-names = "pwm";
1087                 status = "disabled";
1088         };
1089
1090         rga: rga@ff680000 {
1091                 compatible = "rockchip,rk3399-rga";
1092                 reg = <0x0 0xff680000 0x0 0x10000>;
1093                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1094                 interrupt-names = "rga";
1095                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1096                 clock-names = "aclk", "hclk", "sclk";
1097                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1098                 reset-names = "core", "axi", "ahb";
1099                 status = "disabled";
1100         };
1101
1102         pmucru: pmu-clock-controller@ff750000 {
1103                 compatible = "rockchip,rk3399-pmucru";
1104                 reg = <0x0 0xff750000 0x0 0x1000>;
1105                 #clock-cells = <1>;
1106                 #reset-cells = <1>;
1107                 assigned-clocks = <&pmucru PLL_PPLL>;
1108                 assigned-clock-rates = <676000000>;
1109         };
1110
1111         cru: clock-controller@ff760000 {
1112                 compatible = "rockchip,rk3399-cru";
1113                 reg = <0x0 0xff760000 0x0 0x1000>;
1114                 #clock-cells = <1>;
1115                 #reset-cells = <1>;
1116                 assigned-clocks =
1117                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1118                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1119                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1120                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1121                         <&cru PLL_NPLL>,
1122                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1123                         <&cru PCLK_PERIHP>,
1124                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1125                         <&cru PCLK_PERILP0>,
1126                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1127                 assigned-clock-rates =
1128                          <400000000>,  <200000000>,
1129                          <400000000>,  <200000000>,
1130                          <816000000>, <816000000>,
1131                          <594000000>,  <800000000>,
1132                         <1000000000>,
1133                          <150000000>,   <75000000>,
1134                           <37500000>,
1135                          <100000000>,  <100000000>,
1136                           <50000000>,
1137                          <100000000>,   <50000000>;
1138         };
1139
1140         grf: syscon@ff770000 {
1141                 compatible = "rockchip,rk3399-grf", "syscon";
1142                 reg = <0x0 0xff770000 0x0 0x10000>;
1143         };
1144
1145         watchdog@ff840000 {
1146                 compatible = "snps,dw-wdt";
1147                 reg = <0x0 0xff840000 0x0 0x100>;
1148                 clocks = <&cru PCLK_WDT>;
1149                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1150         };
1151
1152         rktimer: rktimer@ff850000 {
1153                 compatible = "rockchip,rk3399-timer";
1154                 reg = <0x0 0xff850000 0x0 0x1000>;
1155                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1156                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1157                 clock-names = "pclk", "timer";
1158         };
1159
1160         spdif: spdif@ff870000 {
1161                 compatible = "rockchip,rk3399-spdif";
1162                 reg = <0x0 0xff870000 0x0 0x1000>;
1163                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1164                 dmas = <&dmac_bus 7>;
1165                 dma-names = "tx";
1166                 clock-names = "mclk", "hclk";
1167                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1168                 pinctrl-names = "default";
1169                 pinctrl-0 = <&spdif_bus>;
1170                 status = "disabled";
1171         };
1172
1173         i2s0: i2s@ff880000 {
1174                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1175                 reg = <0x0 0xff880000 0x0 0x1000>;
1176                 rockchip,grf = <&grf>;
1177                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1178                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1179                 dma-names = "tx", "rx";
1180                 clock-names = "i2s_clk", "i2s_hclk";
1181                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1182                 pinctrl-names = "default";
1183                 pinctrl-0 = <&i2s0_8ch_bus>;
1184                 status = "disabled";
1185         };
1186
1187         i2s1: i2s@ff890000 {
1188                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1189                 reg = <0x0 0xff890000 0x0 0x1000>;
1190                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1191                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1192                 dma-names = "tx", "rx";
1193                 clock-names = "i2s_clk", "i2s_hclk";
1194                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1195                 pinctrl-names = "default";
1196                 pinctrl-0 = <&i2s1_2ch_bus>;
1197                 status = "disabled";
1198         };
1199
1200         i2s2: i2s@ff8a0000 {
1201                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1202                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1203                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1204                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1205                 dma-names = "tx", "rx";
1206                 clock-names = "i2s_clk", "i2s_hclk";
1207                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1208                 status = "disabled";
1209         };
1210
1211         gpu: gpu@ff9a0000 {
1212                 compatible = "arm,malit860",
1213                              "arm,malit86x",
1214                              "arm,malit8xx",
1215                              "arm,mali-midgard";
1216
1217                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1218
1219                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
1220                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
1221                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1222                 interrupt-names = "GPU", "JOB", "MMU";
1223
1224                 clocks = <&cru ACLK_GPU>;
1225                 clock-names = "clk_mali";
1226                 #cooling-cells = <2>; /* min followed by max */
1227                 operating-points-v2 = <&gpu_opp_table>;
1228
1229                 status = "disabled";
1230
1231                 power_model {
1232                         compatible = "arm,mali-simple-power-model";
1233                         voltage = <900>;
1234                         frequency = <500>;
1235                         static-power = <500>;
1236                         dynamic-power = <1500>;
1237                         ts = <20000 2000 (-20) 2>;
1238                         thermal-zone = "gpu";
1239                 };
1240         };
1241
1242         gpu_opp_table: gpu_opp_table {
1243                 compatible = "operating-points-v2";
1244                 opp-shared;
1245
1246                 opp00 {
1247                         opp-hz = /bits/ 64 <200000000>;
1248                         opp-microvolt = <900000>;
1249                 };
1250                 opp01 {
1251                         opp-hz = /bits/ 64 <300000000>;
1252                         opp-microvolt = <900000>;
1253                 };
1254                 opp02 {
1255                         opp-hz = /bits/ 64 <400000000>;
1256                         opp-microvolt = <900000>;
1257                 };
1258
1259         };
1260
1261         vopl: vop@ff8f0000 {
1262                 compatible = "rockchip,rk3399-vop-lit";
1263                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1264                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1265                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1266                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1267                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1268                 reset-names = "axi", "ahb", "dclk";
1269                 iommus = <&vopl_mmu>;
1270                 status = "disabled";
1271
1272                 vopl_out: port {
1273                         #address-cells = <1>;
1274                         #size-cells = <0>;
1275
1276                         vopl_out_mipi: endpoint@0 {
1277                                 reg = <0>;
1278                                 remote-endpoint = <&mipi_in_vopl>;
1279                         };
1280
1281                         vopl_out_edp: endpoint@1 {
1282                                 reg = <1>;
1283                                 remote-endpoint = <&edp_in_vopl>;
1284                         };
1285                 };
1286         };
1287
1288         vopl_mmu: iommu@ff8f3f00 {
1289                 compatible = "rockchip,iommu";
1290                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1291                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1292                 interrupt-names = "vopl_mmu";
1293                 #iommu-cells = <0>;
1294                 status = "disabled";
1295         };
1296
1297         vopb: vop@ff900000 {
1298                 compatible = "rockchip,rk3399-vop-big";
1299                 reg = <0x0 0xff900000 0x0 0x3efc>;
1300                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1301                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1302                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1303                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1304                 reset-names = "axi", "ahb", "dclk";
1305                 iommus = <&vopb_mmu>;
1306                 status = "disabled";
1307
1308                 vopb_out: port {
1309                         #address-cells = <1>;
1310                         #size-cells = <0>;
1311
1312                         vopb_out_edp: endpoint@0 {
1313                                 reg = <0>;
1314                                 remote-endpoint = <&edp_in_vopb>;
1315                         };
1316
1317                         vopb_out_mipi: endpoint@1 {
1318                                 reg = <1>;
1319                                 remote-endpoint = <&mipi_in_vopb>;
1320                         };
1321                 };
1322         };
1323
1324         vopb_mmu: iommu@ff903f00 {
1325                 compatible = "rockchip,iommu";
1326                 reg = <0x0 0xff903f00 0x0 0x100>;
1327                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1328                 interrupt-names = "vopb_mmu";
1329                 #iommu-cells = <0>;
1330                 status = "disabled";
1331         };
1332
1333         mipi_dsi: mipi@ff960000 {
1334                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1335                 reg = <0x0 0xff960000 0x0 0x8000>;
1336                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1337                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1338                          <&cru SCLK_DPHY_TX0_CFG>;
1339                 clock-names = "ref", "pclk", "phy_cfg";
1340                 rockchip,grf = <&grf>;
1341                 #address-cells = <1>;
1342                 #size-cells = <0>;
1343                 status = "disabled";
1344
1345                 ports {
1346                         #address-cells = <1>;
1347                         #size-cells = <0>;
1348                         reg = <1>;
1349
1350                         mipi_in: port {
1351                                 #address-cells = <1>;
1352                                 #size-cells = <0>;
1353
1354                                 mipi_in_vopb: endpoint@0 {
1355                                         reg = <0>;
1356                                         remote-endpoint = <&vopb_out_mipi>;
1357                                 };
1358                                 mipi_in_vopl: endpoint@1 {
1359                                         reg = <1>;
1360                                         remote-endpoint = <&vopl_out_mipi>;
1361                                 };
1362                         };
1363                 };
1364         };
1365
1366         edp: edp@ff970000 {
1367                 compatible = "rockchip,rk3399-edp";
1368                 reg = <0x0 0xff970000 0x0 0x8000>;
1369                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1370                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1371                 clock-names = "dp", "pclk";
1372                 resets = <&cru SRST_P_EDP_CTRL>;
1373                 reset-names = "dp";
1374                 rockchip,grf = <&grf>;
1375                 status = "disabled";
1376                 pinctrl-names = "default";
1377                 pinctrl-0 = <&edp_hpd>;
1378
1379                 ports {
1380                         #address-cells = <1>;
1381                         #size-cells = <0>;
1382
1383                         edp_in: port@0 {
1384                                 reg = <0>;
1385                                 #address-cells = <1>;
1386                                 #size-cells = <0>;
1387
1388                                 edp_in_vopb: endpoint@0 {
1389                                         reg = <0>;
1390                                         remote-endpoint = <&vopb_out_edp>;
1391                                 };
1392
1393                                 edp_in_vopl: endpoint@1 {
1394                                         reg = <1>;
1395                                         remote-endpoint = <&vopl_out_edp>;
1396                                 };
1397                         };
1398                 };
1399         };
1400
1401         display_subsystem: display-subsystem {
1402                 compatible = "rockchip,display-subsystem";
1403                 ports = <&vopl_out>, <&vopb_out>;
1404                 status = "disabled";
1405         };
1406
1407         pinctrl: pinctrl {
1408                 compatible = "rockchip,rk3399-pinctrl";
1409                 rockchip,grf = <&grf>;
1410                 rockchip,pmu = <&pmugrf>;
1411                 #address-cells = <0x2>;
1412                 #size-cells = <0x2>;
1413                 ranges;
1414
1415                 gpio0: gpio0@ff720000 {
1416                         compatible = "rockchip,gpio-bank";
1417                         reg = <0x0 0xff720000 0x0 0x100>;
1418                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1419                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1420
1421                         gpio-controller;
1422                         #gpio-cells = <0x2>;
1423
1424                         interrupt-controller;
1425                         #interrupt-cells = <0x2>;
1426                 };
1427
1428                 gpio1: gpio1@ff730000 {
1429                         compatible = "rockchip,gpio-bank";
1430                         reg = <0x0 0xff730000 0x0 0x100>;
1431                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1432                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1433
1434                         gpio-controller;
1435                         #gpio-cells = <0x2>;
1436
1437                         interrupt-controller;
1438                         #interrupt-cells = <0x2>;
1439                 };
1440
1441                 gpio2: gpio2@ff780000 {
1442                         compatible = "rockchip,gpio-bank";
1443                         reg = <0x0 0xff780000 0x0 0x100>;
1444                         clocks = <&cru PCLK_GPIO2>;
1445                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1446
1447                         gpio-controller;
1448                         #gpio-cells = <0x2>;
1449
1450                         interrupt-controller;
1451                         #interrupt-cells = <0x2>;
1452                 };
1453
1454                 gpio3: gpio3@ff788000 {
1455                         compatible = "rockchip,gpio-bank";
1456                         reg = <0x0 0xff788000 0x0 0x100>;
1457                         clocks = <&cru PCLK_GPIO3>;
1458                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1459
1460                         gpio-controller;
1461                         #gpio-cells = <0x2>;
1462
1463                         interrupt-controller;
1464                         #interrupt-cells = <0x2>;
1465                 };
1466
1467                 gpio4: gpio4@ff790000 {
1468                         compatible = "rockchip,gpio-bank";
1469                         reg = <0x0 0xff790000 0x0 0x100>;
1470                         clocks = <&cru PCLK_GPIO4>;
1471                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1472
1473                         gpio-controller;
1474                         #gpio-cells = <0x2>;
1475
1476                         interrupt-controller;
1477                         #interrupt-cells = <0x2>;
1478                 };
1479
1480                 pcfg_pull_up: pcfg-pull-up {
1481                         bias-pull-up;
1482                 };
1483
1484                 pcfg_pull_down: pcfg-pull-down {
1485                         bias-pull-down;
1486                 };
1487
1488                 pcfg_pull_none: pcfg-pull-none {
1489                         bias-disable;
1490                 };
1491
1492                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1493                         bias-disable;
1494                         drive-strength = <12>;
1495                 };
1496
1497                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1498                         bias-pull-up;
1499                         drive-strength = <8>;
1500                 };
1501
1502                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1503                         bias-pull-down;
1504                         drive-strength = <4>;
1505                 };
1506
1507                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1508                         bias-pull-up;
1509                         drive-strength = <2>;
1510                 };
1511
1512                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1513                         bias-pull-down;
1514                         drive-strength = <12>;
1515                 };
1516
1517                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1518                         bias-disable;
1519                         drive-strength = <13>;
1520                 };
1521
1522                 emmc {
1523                         emmc_pwr: emmc-pwr {
1524                                 rockchip,pins =
1525                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
1526                         };
1527                 };
1528
1529                 gmac {
1530                         rgmii_pins: rgmii-pins {
1531                                 rockchip,pins =
1532                                         /* mac_txclk */
1533                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
1534                                         /* mac_rxclk */
1535                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
1536                                         /* mac_mdio */
1537                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1538                                         /* mac_txen */
1539                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1540                                         /* mac_clk */
1541                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1542                                         /* mac_rxdv */
1543                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1544                                         /* mac_mdc */
1545                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1546                                         /* mac_rxd1 */
1547                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1548                                         /* mac_rxd0 */
1549                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1550                                         /* mac_txd1 */
1551                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1552                                         /* mac_txd0 */
1553                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
1554                                         /* mac_rxd3 */
1555                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
1556                                         /* mac_rxd2 */
1557                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
1558                                         /* mac_txd3 */
1559                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
1560                                         /* mac_txd2 */
1561                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
1562                         };
1563
1564                         rmii_pins: rmii-pins {
1565                                 rockchip,pins =
1566                                         /* mac_mdio */
1567                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_txen */
1569                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
1570                                         /* mac_clk */
1571                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
1572                                         /* mac_rxer */
1573                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
1574                                         /* mac_rxdv */
1575                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
1576                                         /* mac_mdc */
1577                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
1578                                         /* mac_rxd1 */
1579                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
1580                                         /* mac_rxd0 */
1581                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
1582                                         /* mac_txd1 */
1583                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
1584                                         /* mac_txd0 */
1585                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
1586                         };
1587                 };
1588
1589                 i2c0 {
1590                         i2c0_xfer: i2c0-xfer {
1591                                 rockchip,pins =
1592                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
1593                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 i2c1 {
1598                         i2c1_xfer: i2c1-xfer {
1599                                 rockchip,pins =
1600                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
1601                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
1602                         };
1603                 };
1604
1605                 i2c2 {
1606                         i2c2_xfer: i2c2-xfer {
1607                                 rockchip,pins =
1608                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1609                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
1610                         };
1611                 };
1612
1613                 i2c3 {
1614                         i2c3_xfer: i2c3-xfer {
1615                                 rockchip,pins =
1616                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1617                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
1618                         };
1619
1620                         i2c3_gpio: i2c3_gpio {
1621                                 rockchip,pins =
1622                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
1623                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
1624                         };
1625
1626                 };
1627
1628                 i2c4 {
1629                         i2c4_xfer: i2c4-xfer {
1630                                 rockchip,pins =
1631                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
1632                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 i2c5 {
1637                         i2c5_xfer: i2c5-xfer {
1638                                 rockchip,pins =
1639                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1640                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
1641                         };
1642                 };
1643
1644                 i2c6 {
1645                         i2c6_xfer: i2c6-xfer {
1646                                 rockchip,pins =
1647                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
1648                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
1649                         };
1650                 };
1651
1652                 i2c7 {
1653                         i2c7_xfer: i2c7-xfer {
1654                                 rockchip,pins =
1655                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
1656                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
1657                         };
1658                 };
1659
1660                 i2c8 {
1661                         i2c8_xfer: i2c8-xfer {
1662                                 rockchip,pins =
1663                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
1664                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
1665                         };
1666                 };
1667
1668                 i2s0 {
1669                         i2s0_8ch_bus: i2s0-8ch-bus {
1670                                 rockchip,pins =
1671                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
1672                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
1673                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
1674                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
1675                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
1676                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
1677                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
1678                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
1679                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
1680                         };
1681                 };
1682
1683                 i2s1 {
1684                         i2s1_2ch_bus: i2s1-2ch-bus {
1685                                 rockchip,pins =
1686                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
1687                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
1688                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
1689                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
1690                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
1691                         };
1692                 };
1693
1694                 sdio0 {
1695                         sdio0_bus1: sdio0-bus1 {
1696                                 rockchip,pins =
1697                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
1698                         };
1699
1700                         sdio0_bus4: sdio0-bus4 {
1701                                 rockchip,pins =
1702                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
1703                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
1704                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
1705                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
1706                         };
1707
1708                         sdio0_cmd: sdio0-cmd {
1709                                 rockchip,pins =
1710                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
1711                         };
1712
1713                         sdio0_clk: sdio0-clk {
1714                                 rockchip,pins =
1715                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717
1718                         sdio0_cd: sdio0-cd {
1719                                 rockchip,pins =
1720                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
1721                         };
1722
1723                         sdio0_pwr: sdio0-pwr {
1724                                 rockchip,pins =
1725                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
1726                         };
1727
1728                         sdio0_bkpwr: sdio0-bkpwr {
1729                                 rockchip,pins =
1730                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
1731                         };
1732
1733                         sdio0_wp: sdio0-wp {
1734                                 rockchip,pins =
1735                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
1736                         };
1737
1738                         sdio0_int: sdio0-int {
1739                                 rockchip,pins =
1740                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
1741                         };
1742                 };
1743
1744                 sdmmc {
1745                         sdmmc_bus1: sdmmc-bus1 {
1746                                 rockchip,pins =
1747                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
1748                         };
1749
1750                         sdmmc_bus4: sdmmc-bus4 {
1751                                 rockchip,pins =
1752                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
1753                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
1754                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
1755                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
1756                         };
1757
1758                         sdmmc_clk: sdmmc-clk {
1759                                 rockchip,pins =
1760                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762
1763                         sdmmc_cmd: sdmmc-cmd {
1764                                 rockchip,pins =
1765                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
1766                         };
1767
1768                         sdmmc_cd: sdmcc-cd {
1769                                 rockchip,pins =
1770                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
1771                         };
1772
1773                         sdmmc_wp: sdmmc-wp {
1774                                 rockchip,pins =
1775                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
1776                         };
1777                 };
1778
1779                 spdif {
1780                         spdif_bus: spdif-bus {
1781                                 rockchip,pins =
1782                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
1783                         };
1784                 };
1785
1786                 spi0 {
1787                         spi0_clk: spi0-clk {
1788                                 rockchip,pins =
1789                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
1790                         };
1791                         spi0_cs0: spi0-cs0 {
1792                                 rockchip,pins =
1793                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
1794                         };
1795                         spi0_cs1: spi0-cs1 {
1796                                 rockchip,pins =
1797                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
1798                         };
1799                         spi0_tx: spi0-tx {
1800                                 rockchip,pins =
1801                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
1802                         };
1803                         spi0_rx: spi0-rx {
1804                                 rockchip,pins =
1805                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
1806                         };
1807                 };
1808
1809                 spi1 {
1810                         spi1_clk: spi1-clk {
1811                                 rockchip,pins =
1812                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
1813                         };
1814                         spi1_cs0: spi1-cs0 {
1815                                 rockchip,pins =
1816                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
1817                         };
1818                         spi1_rx: spi1-rx {
1819                                 rockchip,pins =
1820                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
1821                         };
1822                         spi1_tx: spi1-tx {
1823                                 rockchip,pins =
1824                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
1825                         };
1826                 };
1827
1828                 spi2 {
1829                         spi2_clk: spi2-clk {
1830                                 rockchip,pins =
1831                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
1832                         };
1833                         spi2_cs0: spi2-cs0 {
1834                                 rockchip,pins =
1835                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837                         spi2_rx: spi2-rx {
1838                                 rockchip,pins =
1839                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841                         spi2_tx: spi2-tx {
1842                                 rockchip,pins =
1843                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1844                         };
1845                 };
1846
1847                 spi3 {
1848                         spi3_clk: spi3-clk {
1849                                 rockchip,pins =
1850                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
1851                         };
1852                         spi3_cs0: spi3-cs0 {
1853                                 rockchip,pins =
1854                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
1855                         };
1856                         spi3_rx: spi3-rx {
1857                                 rockchip,pins =
1858                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
1859                         };
1860                         spi3_tx: spi3-tx {
1861                                 rockchip,pins =
1862                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
1863                         };
1864                 };
1865
1866                 spi4 {
1867                         spi4_clk: spi4-clk {
1868                                 rockchip,pins =
1869                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
1870                         };
1871                         spi4_cs0: spi4-cs0 {
1872                                 rockchip,pins =
1873                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
1874                         };
1875                         spi4_rx: spi4-rx {
1876                                 rockchip,pins =
1877                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
1878                         };
1879                         spi4_tx: spi4-tx {
1880                                 rockchip,pins =
1881                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
1882                         };
1883                 };
1884
1885                 spi5 {
1886                         spi5_clk: spi5-clk {
1887                                 rockchip,pins =
1888                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
1889                         };
1890                         spi5_cs0: spi5-cs0 {
1891                                 rockchip,pins =
1892                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
1893                         };
1894                         spi5_rx: spi5-rx {
1895                                 rockchip,pins =
1896                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
1897                         };
1898                         spi5_tx: spi5-tx {
1899                                 rockchip,pins =
1900                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1901                         };
1902                 };
1903
1904                 tsadc {
1905                         otp_gpio: otp-gpio {
1906                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
1907                         };
1908
1909                         otp_out: otp-out {
1910                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
1911                         };
1912                 };
1913
1914                 uart0 {
1915                         uart0_xfer: uart0-xfer {
1916                                 rockchip,pins =
1917                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
1918                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1919                         };
1920
1921                         uart0_cts: uart0-cts {
1922                                 rockchip,pins =
1923                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1924                         };
1925
1926                         uart0_rts: uart0-rts {
1927                                 rockchip,pins =
1928                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1929                         };
1930                 };
1931
1932                 uart1 {
1933                         uart1_xfer: uart1-xfer {
1934                                 rockchip,pins =
1935                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
1936                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
1937                         };
1938                 };
1939
1940                 uart2a {
1941                         uart2a_xfer: uart2a-xfer {
1942                                 rockchip,pins =
1943                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
1944                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
1945                         };
1946                 };
1947
1948                 uart2b {
1949                         uart2b_xfer: uart2b-xfer {
1950                                 rockchip,pins =
1951                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
1952                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
1953                         };
1954                 };
1955
1956                 uart2c {
1957                         uart2c_xfer: uart2c-xfer {
1958                                 rockchip,pins =
1959                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
1960                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
1961                         };
1962                 };
1963
1964                 uart3 {
1965                         uart3_xfer: uart3-xfer {
1966                                 rockchip,pins =
1967                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
1968                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
1969                         };
1970
1971                         uart3_cts: uart3-cts {
1972                                 rockchip,pins =
1973                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
1974                         };
1975
1976                         uart3_rts: uart3-rts {
1977                                 rockchip,pins =
1978                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
1979                         };
1980                 };
1981
1982                 uart4 {
1983                         uart4_xfer: uart4-xfer {
1984                                 rockchip,pins =
1985                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
1986                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
1987                         };
1988                 };
1989
1990                 uarthdcp {
1991                         uarthdcp_xfer: uarthdcp-xfer {
1992                                 rockchip,pins =
1993                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
1994                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
1995                         };
1996                 };
1997
1998                 pwm0 {
1999                         pwm0_pin: pwm0-pin {
2000                                 rockchip,pins =
2001                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2002                         };
2003
2004                         vop0_pwm_pin: vop0-pwm-pin {
2005                                 rockchip,pins =
2006                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2007                         };
2008                 };
2009
2010                 pwm1 {
2011                         pwm1_pin: pwm1-pin {
2012                                 rockchip,pins =
2013                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2014                         };
2015
2016                         vop1_pwm_pin: vop1-pwm-pin {
2017                                 rockchip,pins =
2018                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2019                         };
2020                 };
2021
2022                 pwm2 {
2023                         pwm2_pin: pwm2-pin {
2024                                 rockchip,pins =
2025                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2026                         };
2027                 };
2028
2029                 pwm3a {
2030                         pwm3a_pin: pwm3a-pin {
2031                                 rockchip,pins =
2032                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2033                         };
2034                 };
2035
2036                 pwm3b {
2037                         pwm3b_pin: pwm3b-pin {
2038                                 rockchip,pins =
2039                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2040                         };
2041                 };
2042
2043                 edp {
2044                         edp_hpd: edp-hpd {
2045                                 rockchip,pins =
2046                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2047                         };
2048                 };
2049
2050                 hdmi {
2051                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2052                                 rockchip,pins =
2053                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2054                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2055                         };
2056
2057                         hdmi_cec: hdmi-cec {
2058                                 rockchip,pins =
2059                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2060                         };
2061                 };
2062
2063                 pcie {
2064                         pcie_clkreqn: pci-clkreqn {
2065                                 rockchip,pins =
2066                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2067                         };
2068
2069                         pcie_clkreqnb: pci-clkreqnb {
2070                                 rockchip,pins =
2071                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2072                         };
2073                 };
2074         };
2075 };