2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/suspend/rockchip-rk3399.h>
51 #include <dt-bindings/thermal/thermal.h>
53 #include "rk3399-dram-default-timing.dtsi"
56 compatible = "rockchip,rk3399";
58 interrupt-parent = <&gic>;
111 compatible = "arm,cortex-a53", "arm,armv8";
113 enable-method = "psci";
114 #cooling-cells = <2>; /* min followed by max */
115 dynamic-power-coefficient = <100>;
116 clocks = <&cru ARMCLKL>;
117 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 compatible = "arm,cortex-a53", "arm,armv8";
124 enable-method = "psci";
125 clocks = <&cru ARMCLKL>;
126 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
131 compatible = "arm,cortex-a53", "arm,armv8";
133 enable-method = "psci";
134 clocks = <&cru ARMCLKL>;
135 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
140 compatible = "arm,cortex-a53", "arm,armv8";
142 enable-method = "psci";
143 clocks = <&cru ARMCLKL>;
144 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
149 compatible = "arm,cortex-a72", "arm,armv8";
151 enable-method = "psci";
152 #cooling-cells = <2>; /* min followed by max */
153 dynamic-power-coefficient = <436>;
154 clocks = <&cru ARMCLKB>;
155 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
160 compatible = "arm,cortex-a72", "arm,armv8";
162 enable-method = "psci";
163 clocks = <&cru ARMCLKB>;
164 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
168 entry-method = "psci";
170 CPU_SLEEP: cpu-sleep {
171 compatible = "arm,idle-state";
173 arm,psci-suspend-param = <0x0010000>;
174 entry-latency-us = <120>;
175 exit-latency-us = <250>;
176 min-residency-us = <900>;
179 CLUSTER_SLEEP: cluster-sleep {
180 compatible = "arm,idle-state";
182 arm,psci-suspend-param = <0x1010000>;
183 entry-latency-us = <400>;
184 exit-latency-us = <500>;
185 min-residency-us = <2000>;
193 min-volt = <800000>; /* uV */
194 min-freq = <408000>; /* KHz */
195 leakage-adjust-volt = <
199 nvmem-cells = <&cpul_leakage>;
200 nvmem-cell-names = "cpu_leakage";
204 min-volt = <800000>; /* uV */
205 min-freq = <408000>; /* KHz */
206 leakage-adjust-volt = <
210 nvmem-cells = <&cpub_leakage>;
211 nvmem-cell-names = "cpu_leakage";
216 compatible = "arm,cortex-a53-pmu";
217 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
221 compatible = "arm,cortex-a72-pmu";
222 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
226 compatible = "arm,psci-1.0";
231 compatible = "arm,armv8-timer";
232 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
233 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
234 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
235 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
239 compatible = "fixed-clock";
240 clock-frequency = <24000000>;
241 clock-output-names = "xin24m";
245 dummy_cpll: dummy_cpll {
246 compatible = "fixed-clock";
247 clock-frequency = <0>;
248 clock-output-names = "dummy_cpll";
252 dummy_vpll: dummy_vpll {
253 compatible = "fixed-clock";
254 clock-frequency = <0>;
255 clock-output-names = "dummy_vpll";
260 compatible = "arm,amba-bus";
261 #address-cells = <2>;
265 dmac_bus: dma-controller@ff6d0000 {
266 compatible = "arm,pl330", "arm,primecell";
267 reg = <0x0 0xff6d0000 0x0 0x4000>;
268 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
269 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
271 clocks = <&cru ACLK_DMAC0_PERILP>;
272 clock-names = "apb_pclk";
273 peripherals-req-type-burst;
276 dmac_peri: dma-controller@ff6e0000 {
277 compatible = "arm,pl330", "arm,primecell";
278 reg = <0x0 0xff6e0000 0x0 0x4000>;
279 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
280 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
282 clocks = <&cru ACLK_DMAC1_PERILP>;
283 clock-names = "apb_pclk";
284 peripherals-req-type-burst;
288 gmac: ethernet@fe300000 {
289 compatible = "rockchip,rk3399-gmac";
290 reg = <0x0 0xfe300000 0x0 0x10000>;
291 rockchip,grf = <&grf>;
292 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
293 interrupt-names = "macirq";
294 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
295 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
296 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
298 clock-names = "stmmaceth", "mac_clk_rx",
299 "mac_clk_tx", "clk_mac_ref",
300 "clk_mac_refout", "aclk_mac",
302 resets = <&cru SRST_A_GMAC>;
303 reset-names = "stmmaceth";
304 power-domains = <&power RK3399_PD_GMAC>;
308 sdio0: dwmmc@fe310000 {
309 compatible = "rockchip,rk3399-dw-mshc",
310 "rockchip,rk3288-dw-mshc";
311 reg = <0x0 0xfe310000 0x0 0x4000>;
312 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
313 clock-freq-min-max = <400000 150000000>;
314 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
315 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
316 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
317 fifo-depth = <0x100>;
318 power-domains = <&power RK3399_PD_SDIOAUDIO>;
322 sdmmc: dwmmc@fe320000 {
323 compatible = "rockchip,rk3399-dw-mshc",
324 "rockchip,rk3288-dw-mshc";
325 reg = <0x0 0xfe320000 0x0 0x4000>;
326 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
327 clock-freq-min-max = <400000 150000000>;
328 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
329 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
330 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
331 fifo-depth = <0x100>;
332 power-domains = <&power RK3399_PD_SD>;
336 sdhci: sdhci@fe330000 {
337 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
338 reg = <0x0 0xfe330000 0x0 0x10000>;
339 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
340 arasan,soc-ctl-syscon = <&grf>;
341 assigned-clocks = <&cru SCLK_EMMC>;
342 assigned-clock-rates = <200000000>;
343 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
344 clock-names = "clk_xin", "clk_ahb";
345 clock-output-names = "emmc_cardclock";
348 phy-names = "phy_arasan";
349 power-domains = <&power RK3399_PD_EMMC>;
353 usb_host0_ehci: usb@fe380000 {
354 compatible = "generic-ehci";
355 reg = <0x0 0xfe380000 0x0 0x20000>;
356 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
357 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
358 <&cru SCLK_USBPHY0_480M_SRC>;
359 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
360 phys = <&u2phy0_host>;
362 power-domains = <&power RK3399_PD_PERIHP>;
366 usb_host0_ohci: usb@fe3a0000 {
367 compatible = "generic-ohci";
368 reg = <0x0 0xfe3a0000 0x0 0x20000>;
369 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
370 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
371 <&cru SCLK_USBPHY0_480M_SRC>;
372 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
373 phys = <&u2phy0_host>;
375 power-domains = <&power RK3399_PD_PERIHP>;
379 usb_host1_ehci: usb@fe3c0000 {
380 compatible = "generic-ehci";
381 reg = <0x0 0xfe3c0000 0x0 0x20000>;
382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
384 <&cru SCLK_USBPHY1_480M_SRC>;
385 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
386 phys = <&u2phy1_host>;
388 power-domains = <&power RK3399_PD_PERIHP>;
392 usb_host1_ohci: usb@fe3e0000 {
393 compatible = "generic-ohci";
394 reg = <0x0 0xfe3e0000 0x0 0x20000>;
395 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
396 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
397 <&cru SCLK_USBPHY1_480M_SRC>;
398 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
399 phys = <&u2phy1_host>;
401 power-domains = <&power RK3399_PD_PERIHP>;
405 usbdrd3_0: usb@fe800000 {
406 compatible = "rockchip,rk3399-dwc3";
407 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
408 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
409 clock-names = "ref_clk", "suspend_clk",
410 "bus_clk", "grf_clk";
411 power-domains = <&power RK3399_PD_USB3>;
412 resets = <&cru SRST_A_USB3_OTG0>;
413 reset-names = "usb3-otg";
414 #address-cells = <2>;
418 usbdrd_dwc3_0: dwc3@fe800000 {
419 compatible = "snps,dwc3";
420 reg = <0x0 0xfe800000 0x0 0x100000>;
421 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
423 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
424 phy-names = "usb2-phy", "usb3-phy";
425 phy_type = "utmi_wide";
426 snps,dis_enblslpm_quirk;
427 snps,dis-u2-freeclk-exists-quirk;
428 snps,dis_u2_susphy_quirk;
429 snps,dis-del-phy-power-chg-quirk;
430 snps,xhci-slow-suspend-quirk;
435 usbdrd3_1: usb@fe900000 {
436 compatible = "rockchip,rk3399-dwc3";
437 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
438 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
439 clock-names = "ref_clk", "suspend_clk",
440 "bus_clk", "grf_clk";
441 power-domains = <&power RK3399_PD_USB3>;
442 resets = <&cru SRST_A_USB3_OTG1>;
443 reset-names = "usb3-otg";
444 #address-cells = <2>;
448 usbdrd_dwc3_1: dwc3@fe900000 {
449 compatible = "snps,dwc3";
450 reg = <0x0 0xfe900000 0x0 0x100000>;
451 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
453 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
454 phy-names = "usb2-phy", "usb3-phy";
455 phy_type = "utmi_wide";
456 snps,dis_enblslpm_quirk;
457 snps,dis-u2-freeclk-exists-quirk;
458 snps,dis_u2_susphy_quirk;
459 snps,dis-del-phy-power-chg-quirk;
460 snps,xhci-slow-suspend-quirk;
465 cdn_dp: dp@fec00000 {
466 compatible = "rockchip,rk3399-cdn-dp";
467 reg = <0x0 0xfec00000 0x0 0x100000>;
468 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
470 <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
471 clock-names = "core-clk", "pclk", "spdif", "grf";
472 assigned-clocks = <&cru SCLK_DP_CORE>;
473 assigned-clock-rates = <100000000>;
474 power-domains = <&power RK3399_PD_HDCP>;
475 phys = <&tcphy0_dp>, <&tcphy1_dp>;
476 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
477 <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
478 reset-names = "spdif", "dptx", "apb", "core";
479 rockchip,grf = <&grf>;
480 #address-cells = <1>;
482 #sound-dai-cells = <1>;
486 #address-cells = <1>;
490 #address-cells = <1>;
492 dp_in_vopb: endpoint@0 {
494 remote-endpoint = <&vopb_out_dp>;
497 dp_in_vopl: endpoint@1 {
499 remote-endpoint = <&vopl_out_dp>;
505 gic: interrupt-controller@fee00000 {
506 compatible = "arm,gic-v3";
507 #interrupt-cells = <4>;
508 #address-cells = <2>;
511 interrupt-controller;
513 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
514 <0x0 0xfef00000 0 0xc0000>, /* GICR */
515 <0x0 0xfff00000 0 0x10000>, /* GICC */
516 <0x0 0xfff10000 0 0x10000>, /* GICH */
517 <0x0 0xfff20000 0 0x10000>; /* GICV */
518 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
519 its: interrupt-controller@fee20000 {
520 compatible = "arm,gic-v3-its";
522 reg = <0x0 0xfee20000 0x0 0x20000>;
526 ppi_cluster0: interrupt-partition-0 {
527 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
530 ppi_cluster1: interrupt-partition-1 {
531 affinity = <&cpu_b0 &cpu_b1>;
536 saradc: saradc@ff100000 {
537 compatible = "rockchip,rk3399-saradc";
538 reg = <0x0 0xff100000 0x0 0x100>;
539 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
540 #io-channel-cells = <1>;
541 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
542 clock-names = "saradc", "apb_pclk";
543 resets = <&cru SRST_P_SARADC>;
544 reset-names = "saradc-apb";
549 compatible = "rockchip,rk3399-i2c";
550 reg = <0x0 0xff3c0000 0x0 0x1000>;
551 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
552 clock-names = "i2c", "pclk";
553 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&i2c0_xfer>;
556 #address-cells = <1>;
562 compatible = "rockchip,rk3399-i2c";
563 reg = <0x0 0xff110000 0x0 0x1000>;
564 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
565 clock-names = "i2c", "pclk";
566 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
567 pinctrl-names = "default";
568 pinctrl-0 = <&i2c1_xfer>;
569 #address-cells = <1>;
575 compatible = "rockchip,rk3399-i2c";
576 reg = <0x0 0xff120000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c2_xfer>;
582 #address-cells = <1>;
588 compatible = "rockchip,rk3399-i2c";
589 reg = <0x0 0xff130000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c3_xfer>;
595 #address-cells = <1>;
601 compatible = "rockchip,rk3399-i2c";
602 reg = <0x0 0xff140000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
604 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c5_xfer>;
608 #address-cells = <1>;
614 compatible = "rockchip,rk3399-i2c";
615 reg = <0x0 0xff150000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
617 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c6_xfer>;
621 #address-cells = <1>;
627 compatible = "rockchip,rk3399-i2c";
628 reg = <0x0 0xff160000 0x0 0x1000>;
629 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
630 clock-names = "i2c", "pclk";
631 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
632 pinctrl-names = "default";
633 pinctrl-0 = <&i2c7_xfer>;
634 #address-cells = <1>;
639 uart0: serial@ff180000 {
640 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
641 reg = <0x0 0xff180000 0x0 0x100>;
642 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
643 clock-names = "baudclk", "apb_pclk";
644 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
652 uart1: serial@ff190000 {
653 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff190000 0x0 0x100>;
655 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
656 clock-names = "baudclk", "apb_pclk";
657 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&uart1_xfer>;
665 uart2: serial@ff1a0000 {
666 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
667 reg = <0x0 0xff1a0000 0x0 0x100>;
668 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
669 clock-names = "baudclk", "apb_pclk";
670 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
673 pinctrl-names = "default";
674 pinctrl-0 = <&uart2c_xfer>;
678 uart3: serial@ff1b0000 {
679 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
680 reg = <0x0 0xff1b0000 0x0 0x100>;
681 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
682 clock-names = "baudclk", "apb_pclk";
683 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
686 pinctrl-names = "default";
687 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
692 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
693 reg = <0x0 0xff1c0000 0x0 0x1000>;
694 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
695 clock-names = "spiclk", "apb_pclk";
696 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
697 pinctrl-names = "default";
698 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
699 #address-cells = <1>;
705 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
706 reg = <0x0 0xff1d0000 0x0 0x1000>;
707 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
708 clock-names = "spiclk", "apb_pclk";
709 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
710 pinctrl-names = "default";
711 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
712 #address-cells = <1>;
718 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
719 reg = <0x0 0xff1e0000 0x0 0x1000>;
720 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
721 clock-names = "spiclk", "apb_pclk";
722 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
723 pinctrl-names = "default";
724 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
725 #address-cells = <1>;
731 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
732 reg = <0x0 0xff1f0000 0x0 0x1000>;
733 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
734 clock-names = "spiclk", "apb_pclk";
735 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
736 pinctrl-names = "default";
737 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
738 #address-cells = <1>;
744 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
745 reg = <0x0 0xff200000 0x0 0x1000>;
746 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
747 clock-names = "spiclk", "apb_pclk";
748 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
749 pinctrl-names = "default";
750 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
751 #address-cells = <1>;
756 thermal_zones: thermal-zones {
757 soc_thermal: soc-thermal {
758 polling-delay-passive = <20>; /* milliseconds */
759 polling-delay = <1000>; /* milliseconds */
760 sustainable-power = <1000>; /* milliwatts */
762 thermal-sensors = <&tsadc 0>;
765 threshold: trip-point@0 {
766 temperature = <70000>; /* millicelsius */
767 hysteresis = <2000>; /* millicelsius */
770 target: trip-point@1 {
771 temperature = <85000>; /* millicelsius */
772 hysteresis = <2000>; /* millicelsius */
776 temperature = <95000>; /* millicelsius */
777 hysteresis = <2000>; /* millicelsius */
786 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
787 contribution = <4096>;
792 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
793 contribution = <1024>;
798 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
799 contribution = <4096>;
804 gpu_thermal: gpu-thermal {
805 polling-delay-passive = <100>; /* milliseconds */
806 polling-delay = <1000>; /* milliseconds */
808 thermal-sensors = <&tsadc 1>;
812 tsadc: tsadc@ff260000 {
813 compatible = "rockchip,rk3399-tsadc";
814 reg = <0x0 0xff260000 0x0 0x100>;
815 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
816 rockchip,grf = <&grf>;
817 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
818 clock-names = "tsadc", "apb_pclk";
819 assigned-clocks = <&cru SCLK_TSADC>;
820 assigned-clock-rates = <750000>;
821 resets = <&cru SRST_TSADC>;
822 reset-names = "tsadc-apb";
823 pinctrl-names = "init", "default", "sleep";
824 pinctrl-0 = <&otp_gpio>;
825 pinctrl-1 = <&otp_out>;
826 pinctrl-2 = <&otp_gpio>;
827 #thermal-sensor-cells = <1>;
828 rockchip,hw-tshut-temp = <95000>;
832 qos_emmc: qos@ffa58000 {
833 compatible = "syscon";
834 reg = <0x0 0xffa58000 0x0 0x20>;
837 qos_gmac: qos@ffa5c000 {
838 compatible = "syscon";
839 reg = <0x0 0xffa5c000 0x0 0x20>;
842 qos_pcie: qos@ffa60080 {
843 compatible = "syscon";
844 reg = <0x0 0xffa60080 0x0 0x20>;
847 qos_usb_host0: qos@ffa60100 {
848 compatible = "syscon";
849 reg = <0x0 0xffa60100 0x0 0x20>;
852 qos_usb_host1: qos@ffa60180 {
853 compatible = "syscon";
854 reg = <0x0 0xffa60180 0x0 0x20>;
857 qos_usb_otg0: qos@ffa70000 {
858 compatible = "syscon";
859 reg = <0x0 0xffa70000 0x0 0x20>;
862 qos_usb_otg1: qos@ffa70080 {
863 compatible = "syscon";
864 reg = <0x0 0xffa70080 0x0 0x20>;
867 qos_sd: qos@ffa74000 {
868 compatible = "syscon";
869 reg = <0x0 0xffa74000 0x0 0x20>;
872 qos_sdioaudio: qos@ffa76000 {
873 compatible = "syscon";
874 reg = <0x0 0xffa76000 0x0 0x20>;
877 qos_hdcp: qos@ffa90000 {
878 compatible = "syscon";
879 reg = <0x0 0xffa90000 0x0 0x20>;
882 qos_iep: qos@ffa98000 {
883 compatible = "syscon";
884 reg = <0x0 0xffa98000 0x0 0x20>;
887 qos_isp0_m0: qos@ffaa0000 {
888 compatible = "syscon";
889 reg = <0x0 0xffaa0000 0x0 0x20>;
892 qos_isp0_m1: qos@ffaa0080 {
893 compatible = "syscon";
894 reg = <0x0 0xffaa0080 0x0 0x20>;
897 qos_isp1_m0: qos@ffaa8000 {
898 compatible = "syscon";
899 reg = <0x0 0xffaa8000 0x0 0x20>;
902 qos_isp1_m1: qos@ffaa8080 {
903 compatible = "syscon";
904 reg = <0x0 0xffaa8080 0x0 0x20>;
907 qos_rga_r: qos@ffab0000 {
908 compatible = "syscon";
909 reg = <0x0 0xffab0000 0x0 0x20>;
912 qos_rga_w: qos@ffab0080 {
913 compatible = "syscon";
914 reg = <0x0 0xffab0080 0x0 0x20>;
917 qos_video_m0: qos@ffab8000 {
918 compatible = "syscon";
919 reg = <0x0 0xffab8000 0x0 0x20>;
922 qos_video_m1_r: qos@ffac0000 {
923 compatible = "syscon";
924 reg = <0x0 0xffac0000 0x0 0x20>;
927 qos_video_m1_w: qos@ffac0080 {
928 compatible = "syscon";
929 reg = <0x0 0xffac0080 0x0 0x20>;
932 qos_vop_big_r: qos@ffac8000 {
933 compatible = "syscon";
934 reg = <0x0 0xffac8000 0x0 0x20>;
937 qos_vop_big_w: qos@ffac8080 {
938 compatible = "syscon";
939 reg = <0x0 0xffac8080 0x0 0x20>;
942 qos_vop_little: qos@ffad0000 {
943 compatible = "syscon";
944 reg = <0x0 0xffad0000 0x0 0x20>;
947 qos_perihp: qos@ffad8080 {
948 compatible = "syscon";
949 reg = <0x0 0xffad8080 0x0 0x20>;
952 qos_gpu: qos@ffae0000 {
953 compatible = "syscon";
954 reg = <0x0 0xffae0000 0x0 0x20>;
957 pmu: power-management@ff310000 {
958 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
959 reg = <0x0 0xff310000 0x0 0x1000>;
962 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
963 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
964 * Some of the power domains are grouped together for every
966 * The detail contents as below.
968 power: power-controller {
969 compatible = "rockchip,rk3399-power-controller";
970 #power-domain-cells = <1>;
971 #address-cells = <1>;
974 /* These power domains are grouped by VD_CENTER */
975 pd_iep@RK3399_PD_IEP {
976 reg = <RK3399_PD_IEP>;
977 clocks = <&cru ACLK_IEP>,
981 pd_rga@RK3399_PD_RGA {
982 reg = <RK3399_PD_RGA>;
983 clocks = <&cru ACLK_RGA>,
985 pm_qos = <&qos_rga_r>,
988 pd_vcodec@RK3399_PD_VCODEC {
989 reg = <RK3399_PD_VCODEC>;
990 clocks = <&cru ACLK_VCODEC>,
992 pm_qos = <&qos_video_m0>;
994 pd_vdu@RK3399_PD_VDU {
995 reg = <RK3399_PD_VDU>;
996 clocks = <&cru ACLK_VDU>,
998 pm_qos = <&qos_video_m1_r>,
1002 /* These power domains are grouped by VD_GPU */
1003 pd_gpu@RK3399_PD_GPU {
1004 reg = <RK3399_PD_GPU>;
1005 clocks = <&cru ACLK_GPU>;
1006 pm_qos = <&qos_gpu>;
1009 /* These power domains are grouped by VD_LOGIC */
1010 pd_edp@RK3399_PD_EDP {
1011 reg = <RK3399_PD_EDP>;
1012 clocks = <&cru PCLK_EDP_CTRL>;
1014 pd_emmc@RK3399_PD_EMMC {
1015 reg = <RK3399_PD_EMMC>;
1016 clocks = <&cru ACLK_EMMC>;
1017 pm_qos = <&qos_emmc>;
1019 pd_gmac@RK3399_PD_GMAC {
1020 reg = <RK3399_PD_GMAC>;
1021 clocks = <&cru ACLK_GMAC>,
1023 pm_qos = <&qos_gmac>;
1025 pd_perihp@RK3399_PD_PERIHP {
1026 reg = <RK3399_PD_PERIHP>;
1027 #address-cells = <1>;
1029 clocks = <&cru ACLK_PERIHP>;
1030 pm_qos = <&qos_perihp>,
1035 pd_sd@RK3399_PD_SD {
1036 reg = <RK3399_PD_SD>;
1037 clocks = <&cru HCLK_SDMMC>,
1042 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1043 reg = <RK3399_PD_SDIOAUDIO>;
1044 clocks = <&cru HCLK_SDIO>;
1045 pm_qos = <&qos_sdioaudio>;
1047 pd_usb3@RK3399_PD_USB3 {
1048 reg = <RK3399_PD_USB3>;
1049 clocks = <&cru ACLK_USB3>;
1050 pm_qos = <&qos_usb_otg0>,
1053 pd_vio@RK3399_PD_VIO {
1054 reg = <RK3399_PD_VIO>;
1055 #address-cells = <1>;
1058 pd_hdcp@RK3399_PD_HDCP {
1059 reg = <RK3399_PD_HDCP>;
1060 clocks = <&cru ACLK_HDCP>,
1063 pm_qos = <&qos_hdcp>;
1065 pd_isp0@RK3399_PD_ISP0 {
1066 reg = <RK3399_PD_ISP0>;
1067 clocks = <&cru ACLK_ISP0>,
1069 pm_qos = <&qos_isp0_m0>,
1072 pd_isp1@RK3399_PD_ISP1 {
1073 reg = <RK3399_PD_ISP1>;
1074 clocks = <&cru ACLK_ISP1>,
1076 pm_qos = <&qos_isp1_m0>,
1079 pd_tcpc0@RK3399_PD_TCPC0 {
1080 reg = <RK3399_PD_TCPD0>;
1081 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1082 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1084 pd_tcpc1@RK3399_PD_TCPC1 {
1085 reg = <RK3399_PD_TCPD1>;
1086 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1087 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1089 pd_vo@RK3399_PD_VO {
1090 reg = <RK3399_PD_VO>;
1091 #address-cells = <1>;
1094 pd_vopb@RK3399_PD_VOPB {
1095 reg = <RK3399_PD_VOPB>;
1096 clocks = <&cru ACLK_VOP0>,
1098 pm_qos = <&qos_vop_big_r>,
1101 pd_vopl@RK3399_PD_VOPL {
1102 reg = <RK3399_PD_VOPL>;
1103 clocks = <&cru ACLK_VOP1>,
1105 pm_qos = <&qos_vop_little>;
1112 pmugrf: syscon@ff320000 {
1113 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1114 reg = <0x0 0xff320000 0x0 0x1000>;
1115 #address-cells = <1>;
1118 pmu_io_domains: io-domains {
1119 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1120 status = "disabled";
1124 compatible = "syscon-reboot-mode";
1126 mode-bootloader = <BOOT_BL_DOWNLOAD>;
1127 mode-charge = <BOOT_CHARGING>;
1128 mode-fastboot = <BOOT_FASTBOOT>;
1129 mode-loader = <BOOT_BL_DOWNLOAD>;
1130 mode-normal = <BOOT_NORMAL>;
1131 mode-recovery = <BOOT_RECOVERY>;
1132 mode-ums = <BOOT_UMS>;
1135 pmu_pvtm: pmu-pvtm {
1136 compatible = "rockchip,rk3399-pmu-pvtm";
1137 clocks = <&pmucru SCLK_PVTM_PMU>;
1138 clock-names = "pmu";
1139 status = "disabled";
1143 spi3: spi@ff350000 {
1144 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1145 reg = <0x0 0xff350000 0x0 0x1000>;
1146 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1147 clock-names = "spiclk", "apb_pclk";
1148 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1151 #address-cells = <1>;
1153 status = "disabled";
1156 uart4: serial@ff370000 {
1157 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1158 reg = <0x0 0xff370000 0x0 0x100>;
1159 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1160 clock-names = "baudclk", "apb_pclk";
1161 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1164 pinctrl-names = "default";
1165 pinctrl-0 = <&uart4_xfer>;
1166 status = "disabled";
1169 i2c4: i2c@ff3d0000 {
1170 compatible = "rockchip,rk3399-i2c";
1171 reg = <0x0 0xff3d0000 0x0 0x1000>;
1172 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1173 clock-names = "i2c", "pclk";
1174 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&i2c4_xfer>;
1177 #address-cells = <1>;
1179 status = "disabled";
1182 i2c8: i2c@ff3e0000 {
1183 compatible = "rockchip,rk3399-i2c";
1184 reg = <0x0 0xff3e0000 0x0 0x1000>;
1185 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1186 clock-names = "i2c", "pclk";
1187 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1188 pinctrl-names = "default";
1189 pinctrl-0 = <&i2c8_xfer>;
1190 #address-cells = <1>;
1192 status = "disabled";
1195 pcie_phy: phy@e220 {
1196 compatible = "rockchip,rk3399-pcie-phy";
1198 rockchip,grf = <&grf>;
1199 clocks = <&cru SCLK_PCIEPHY_REF>;
1200 clock-names = "refclk";
1201 resets = <&cru SRST_PCIEPHY>;
1202 reset-names = "phy";
1203 status = "disabled";
1206 pcie0: pcie@f8000000 {
1207 compatible = "rockchip,rk3399-pcie";
1208 #address-cells = <3>;
1211 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1212 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1213 clock-names = "aclk", "aclk-perf",
1215 bus-range = <0x0 0x1>;
1216 max-link-speed = <1>;
1217 linux,pci-domain = <0>;
1218 msi-map = <0x0 &its 0x0 0x1000>;
1219 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1220 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1221 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1222 interrupt-names = "sys", "legacy", "client";
1223 #interrupt-cells = <1>;
1224 interrupt-map-mask = <0 0 0 7>;
1225 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1226 <0 0 0 2 &pcie0_intc 1>,
1227 <0 0 0 3 &pcie0_intc 2>,
1228 <0 0 0 4 &pcie0_intc 3>;
1230 phy-names = "pcie-phy";
1231 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1232 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1233 reg = <0x0 0xf8000000 0x0 0x2000000>,
1234 <0x0 0xfd000000 0x0 0x1000000>;
1235 reg-names = "axi-base", "apb-base";
1236 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1237 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1238 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1240 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1241 "pm", "pclk", "aclk";
1242 status = "disabled";
1243 pcie0_intc: interrupt-controller {
1244 interrupt-controller;
1245 #address-cells = <0>;
1246 #interrupt-cells = <1>;
1250 pwm0: pwm@ff420000 {
1251 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1252 reg = <0x0 0xff420000 0x0 0x10>;
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&pwm0_pin>;
1256 clocks = <&pmucru PCLK_RKPWM_PMU>;
1257 clock-names = "pwm";
1258 status = "disabled";
1261 pwm1: pwm@ff420010 {
1262 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1263 reg = <0x0 0xff420010 0x0 0x10>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&pwm1_pin>;
1267 clocks = <&pmucru PCLK_RKPWM_PMU>;
1268 clock-names = "pwm";
1269 status = "disabled";
1272 pwm2: pwm@ff420020 {
1273 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1274 reg = <0x0 0xff420020 0x0 0x10>;
1276 pinctrl-names = "default";
1277 pinctrl-0 = <&pwm2_pin>;
1278 clocks = <&pmucru PCLK_RKPWM_PMU>;
1279 clock-names = "pwm";
1280 status = "disabled";
1283 pwm3: pwm@ff420030 {
1284 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1285 reg = <0x0 0xff420030 0x0 0x10>;
1287 pinctrl-names = "default";
1288 pinctrl-0 = <&pwm3a_pin>;
1289 clocks = <&pmucru PCLK_RKPWM_PMU>;
1290 clock-names = "pwm";
1291 status = "disabled";
1295 reg = <0x00 0xff630000 0x00 0x4000>;
1296 compatible = "rockchip,rk3399-dfi";
1297 rockchip,pmu = <&pmugrf>;
1298 clocks = <&cru PCLK_DDR_MON>;
1299 clock-names = "pclk_ddr_mon";
1300 status = "disabled";
1304 compatible = "rockchip,rk3399-dmc";
1305 devfreq-events = <&dfi>;
1306 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1307 clocks = <&cru SCLK_DDRCLK>;
1308 clock-names = "dmc_clk";
1309 ddr_timing = <&ddr_timing>;
1310 status = "disabled";
1313 vpu: vpu_service@ff650000 {
1314 compatible = "rockchip,vpu_service";
1315 rockchip,grf = <&grf>;
1316 iommus = <&vpu_mmu>;
1317 iommu_enabled = <1>;
1318 reg = <0x0 0xff650000 0x0 0x800>;
1319 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1320 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1321 interrupt-names = "irq_dec", "irq_enc";
1322 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1323 clock-names = "aclk_vcodec", "hclk_vcodec";
1324 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1325 reset-names = "video_h", "video_a";
1326 power-domains = <&power RK3399_PD_VCODEC>;
1327 name = "vpu_service";
1329 /* 0 means ion, 1 means drm */
1331 status = "disabled";
1334 vpu_mmu: iommu@ff650800 {
1335 compatible = "rockchip,iommu";
1336 reg = <0x0 0xff650800 0x0 0x40>;
1337 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1338 interrupt-names = "vpu_mmu";
1339 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1340 clock-names = "aclk", "hclk";
1341 power-domains = <&power RK3399_PD_VCODEC>;
1345 rkvdec: rkvdec@ff660000 {
1346 compatible = "rockchip,rkvdec";
1347 rockchip,grf = <&grf>;
1348 iommus = <&vdec_mmu>;
1349 iommu_enabled = <1>;
1350 reg = <0x0 0xff660000 0x0 0x400>;
1351 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1352 interrupt-names = "irq_dec";
1353 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1354 <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1355 clock-names = "aclk_vcodec", "hclk_vcodec",
1356 "clk_cabac", "clk_core";
1357 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1358 reset-names = "video_h", "video_a";
1359 power-domains = <&power RK3399_PD_VDU>;
1362 /* 0 means ion, 1 means drm */
1364 status = "disabled";
1367 vdec_mmu: iommu@ff660480 {
1368 compatible = "rockchip,iommu";
1369 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1370 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1371 interrupt-names = "vdec_mmu";
1372 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1373 clock-names = "aclk", "hclk";
1374 power-domains = <&power RK3399_PD_VDU>;
1379 compatible = "rockchip,iep";
1380 iommu_enabled = <1>;
1381 iommus = <&iep_mmu>;
1382 reg = <0x0 0xff670000 0x0 0x800>;
1383 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1384 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1385 clock-names = "aclk_iep", "hclk_iep";
1386 power-domains = <&power RK3399_PD_IEP>;
1389 status = "disabled";
1392 iep_mmu: iommu@ff670800 {
1393 compatible = "rockchip,iommu";
1394 reg = <0x0 0xff670800 0x0 0x40>;
1395 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1396 interrupt-names = "iep_mmu";
1398 status = "disabled";
1402 compatible = "rockchip,rk3399-rga";
1403 reg = <0x0 0xff680000 0x0 0x10000>;
1404 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1405 interrupt-names = "rga";
1406 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1407 clock-names = "aclk", "hclk", "sclk";
1408 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1409 reset-names = "core", "axi", "ahb";
1410 power-domains = <&power RK3399_PD_RGA>;
1411 status = "disabled";
1414 efuse0: efuse@ff690000 {
1415 compatible = "rockchip,rk3399-efuse";
1416 reg = <0x0 0xff690000 0x0 0x80>;
1417 #address-cells = <1>;
1419 clocks = <&cru PCLK_EFUSE1024NS>;
1420 clock-names = "pclk_efuse";
1426 cpul_leakage: cpul-leakage {
1429 cpub_leakage: cpub-leakage {
1432 gpu_leakage: gpu-leakage {
1435 center_leakage: center-leakage {
1438 logic_leakage: logic-leakage {
1441 wafer_info: wafer-info {
1446 pmucru: pmu-clock-controller@ff750000 {
1447 compatible = "rockchip,rk3399-pmucru";
1448 reg = <0x0 0xff750000 0x0 0x1000>;
1451 assigned-clocks = <&pmucru PLL_PPLL>;
1452 assigned-clock-rates = <676000000>;
1455 cru: clock-controller@ff760000 {
1456 compatible = "rockchip,rk3399-cru";
1457 reg = <0x0 0xff760000 0x0 0x1000>;
1461 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1462 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1463 <&cru ARMCLKL>, <&cru ARMCLKB>,
1464 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1465 <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1466 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1468 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1469 <&cru PCLK_PERILP0>,
1470 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1471 assigned-clock-rates =
1472 <400000000>, <200000000>,
1473 <400000000>, <200000000>,
1474 <816000000>, <816000000>,
1475 <594000000>, <800000000>,
1476 <200000000>, <1000000000>,
1477 <150000000>, <75000000>,
1479 <100000000>, <100000000>,
1481 <100000000>, <50000000>;
1484 grf: syscon@ff770000 {
1485 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1486 reg = <0x0 0xff770000 0x0 0x10000>;
1487 #address-cells = <1>;
1490 io_domains: io-domains {
1491 compatible = "rockchip,rk3399-io-voltage-domain";
1492 status = "disabled";
1495 emmc_phy: phy@f780 {
1496 compatible = "rockchip,rk3399-emmc-phy";
1497 reg = <0xf780 0x24>;
1499 clock-names = "emmcclk";
1501 status = "disabled";
1504 u2phy0: usb2-phy@e450 {
1505 compatible = "rockchip,rk3399-usb2phy";
1506 reg = <0xe450 0x10>;
1507 clocks = <&cru SCLK_USB2PHY0_REF>;
1508 clock-names = "phyclk";
1510 clock-output-names = "clk_usbphy0_480m";
1511 status = "disabled";
1513 u2phy0_otg: otg-port {
1515 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1516 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1517 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1518 interrupt-names = "otg-bvalid", "otg-id",
1520 status = "disabled";
1523 u2phy0_host: host-port {
1525 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1526 interrupt-names = "linestate";
1527 status = "disabled";
1531 u2phy1: usb2-phy@e460 {
1532 compatible = "rockchip,rk3399-usb2phy";
1533 reg = <0xe460 0x10>;
1534 clocks = <&cru SCLK_USB2PHY1_REF>;
1535 clock-names = "phyclk";
1537 clock-output-names = "clk_usbphy1_480m";
1538 status = "disabled";
1540 u2phy1_otg: otg-port {
1542 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1543 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1544 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1545 interrupt-names = "otg-bvalid", "otg-id",
1547 status = "disabled";
1550 u2phy1_host: host-port {
1552 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1553 interrupt-names = "linestate";
1554 status = "disabled";
1559 compatible = "rockchip,rk3399-pvtm";
1560 clocks = <&cru SCLK_PVTM_CORE_L>,
1561 <&cru SCLK_PVTM_CORE_B>,
1562 <&cru SCLK_PVTM_GPU>,
1563 <&cru SCLK_PVTM_DDR>;
1564 clock-names = "core_l", "core_b", "gpu", "ddr";
1565 status = "disabled";
1569 tcphy0: phy@ff7c0000 {
1570 compatible = "rockchip,rk3399-typec-phy";
1571 reg = <0x0 0xff7c0000 0x0 0x40000>;
1572 rockchip,grf = <&grf>;
1574 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1575 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1576 clock-names = "tcpdcore", "tcpdphy-ref";
1577 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1578 assigned-clock-rates = <50000000>;
1579 power-domains = <&power RK3399_PD_TCPD0>;
1580 resets = <&cru SRST_UPHY0>,
1581 <&cru SRST_UPHY0_PIPE_L00>,
1582 <&cru SRST_P_UPHY0_TCPHY>;
1583 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1584 rockchip,typec-conn-dir = <0xe580 0 16>;
1585 rockchip,usb3tousb2-en = <0xe580 3 19>;
1586 rockchip,usb3-host-disable = <0x2434 0 16>;
1587 rockchip,usb3-host-port = <0x2434 12 28>;
1588 rockchip,external-psm = <0xe588 14 30>;
1589 rockchip,pipe-status = <0xe5c0 0 0>;
1590 rockchip,uphy-dp-sel = <0x6268 19 19>;
1591 status = "disabled";
1593 tcphy0_dp: dp-port {
1597 tcphy0_usb3: usb3-port {
1602 tcphy1: phy@ff800000 {
1603 compatible = "rockchip,rk3399-typec-phy";
1604 reg = <0x0 0xff800000 0x0 0x40000>;
1605 rockchip,grf = <&grf>;
1607 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1608 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1609 clock-names = "tcpdcore", "tcpdphy-ref";
1610 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1611 assigned-clock-rates = <50000000>;
1612 power-domains = <&power RK3399_PD_TCPD1>;
1613 resets = <&cru SRST_UPHY1>,
1614 <&cru SRST_UPHY1_PIPE_L00>,
1615 <&cru SRST_P_UPHY1_TCPHY>;
1616 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1617 rockchip,typec-conn-dir = <0xe58c 0 16>;
1618 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1619 rockchip,usb3-host-disable = <0x2444 0 16>;
1620 rockchip,usb3-host-port = <0x2444 12 28>;
1621 rockchip,external-psm = <0xe594 14 30>;
1622 rockchip,pipe-status = <0xe5c0 16 16>;
1623 rockchip,uphy-dp-sel = <0x6268 3 19>;
1624 status = "disabled";
1626 tcphy1_dp: dp-port {
1630 tcphy1_usb3: usb3-port {
1636 compatible = "snps,dw-wdt";
1637 reg = <0x0 0xff848000 0x0 0x100>;
1638 clocks = <&cru PCLK_WDT>;
1639 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1642 rktimer: rktimer@ff850000 {
1643 compatible = "rockchip,rk3399-timer";
1644 reg = <0x0 0xff850000 0x0 0x1000>;
1645 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1646 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1647 clock-names = "pclk", "timer";
1650 spdif: spdif@ff870000 {
1651 compatible = "rockchip,rk3399-spdif";
1652 reg = <0x0 0xff870000 0x0 0x1000>;
1653 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1654 dmas = <&dmac_bus 7>;
1656 clock-names = "mclk", "hclk";
1657 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1658 pinctrl-names = "default";
1659 pinctrl-0 = <&spdif_bus>;
1660 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1661 status = "disabled";
1664 i2s0: i2s@ff880000 {
1665 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1666 reg = <0x0 0xff880000 0x0 0x1000>;
1667 rockchip,grf = <&grf>;
1668 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1669 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1670 dma-names = "tx", "rx";
1671 clock-names = "i2s_clk", "i2s_hclk";
1672 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1673 pinctrl-names = "default";
1674 pinctrl-0 = <&i2s0_8ch_bus>;
1675 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1676 status = "disabled";
1679 i2s1: i2s@ff890000 {
1680 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1681 reg = <0x0 0xff890000 0x0 0x1000>;
1682 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1683 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1684 dma-names = "tx", "rx";
1685 clock-names = "i2s_clk", "i2s_hclk";
1686 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1687 pinctrl-names = "default";
1688 pinctrl-0 = <&i2s1_2ch_bus>;
1689 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1690 status = "disabled";
1693 i2s2: i2s@ff8a0000 {
1694 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1695 reg = <0x0 0xff8a0000 0x0 0x1000>;
1696 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1697 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1698 dma-names = "tx", "rx";
1699 clock-names = "i2s_clk", "i2s_hclk";
1700 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1701 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1702 status = "disabled";
1706 compatible = "arm,malit860",
1711 reg = <0x0 0xff9a0000 0x0 0x10000>;
1713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1714 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1715 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1716 interrupt-names = "GPU", "JOB", "MMU";
1718 clocks = <&cru ACLK_GPU>;
1719 clock-names = "clk_mali";
1720 #cooling-cells = <2>; /* min followed by max */
1721 power-domains = <&power RK3399_PD_GPU>;
1722 power-off-delay-ms = <200>;
1723 status = "disabled";
1725 gpu_power_model: power_model {
1726 compatible = "arm,mali-simple-power-model";
1729 static-power = <300>;
1730 dynamic-power = <396>;
1731 ts = <32000 4700 (-80) 2>;
1732 thermal-zone = "gpu-thermal";
1736 vopl: vop@ff8f0000 {
1737 compatible = "rockchip,rk3399-vop-lit";
1738 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1739 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1740 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1741 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1742 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1743 reset-names = "axi", "ahb", "dclk";
1744 power-domains = <&power RK3399_PD_VOPL>;
1745 iommus = <&vopl_mmu>;
1746 status = "disabled";
1749 #address-cells = <1>;
1752 vopl_out_mipi: endpoint@0 {
1754 remote-endpoint = <&mipi_in_vopl>;
1757 vopl_out_edp: endpoint@1 {
1759 remote-endpoint = <&edp_in_vopl>;
1762 vopl_out_hdmi: endpoint@2 {
1764 remote-endpoint = <&hdmi_in_vopl>;
1767 vopl_out_dp: endpoint@3 {
1769 remote-endpoint = <&dp_in_vopl>;
1774 vop1_pwm: voppwm@ff8f01a0 {
1775 compatible = "rockchip,vop-pwm";
1776 reg = <0x0 0xff8f01a0 0x0 0x10>;
1778 pinctrl-names = "default";
1779 pinctrl-0 = <&vop1_pwm_pin>;
1780 clocks = <&cru SCLK_VOP1_PWM>;
1781 clock-names = "pwm";
1782 status = "disabled";
1785 vopl_mmu: iommu@ff8f3f00 {
1786 compatible = "rockchip,iommu";
1787 reg = <0x0 0xff8f3f00 0x0 0x100>;
1788 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1789 interrupt-names = "vopl_mmu";
1790 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1791 clock-names = "aclk", "hclk";
1792 power-domains = <&power RK3399_PD_VOPL>;
1794 status = "disabled";
1797 vopb: vop@ff900000 {
1798 compatible = "rockchip,rk3399-vop-big";
1799 reg = <0x0 0xff900000 0x0 0x3efc>;
1800 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1801 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1802 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1803 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1804 reset-names = "axi", "ahb", "dclk";
1805 power-domains = <&power RK3399_PD_VOPB>;
1806 iommus = <&vopb_mmu>;
1807 status = "disabled";
1810 #address-cells = <1>;
1813 vopb_out_edp: endpoint@0 {
1815 remote-endpoint = <&edp_in_vopb>;
1818 vopb_out_mipi: endpoint@1 {
1820 remote-endpoint = <&mipi_in_vopb>;
1823 vopb_out_hdmi: endpoint@2 {
1825 remote-endpoint = <&hdmi_in_vopb>;
1828 vopb_out_dp: endpoint@3 {
1830 remote-endpoint = <&dp_in_vopb>;
1835 vop0_pwm: voppwm@ff9001a0 {
1836 compatible = "rockchip,vop-pwm";
1837 reg = <0x0 0xff9001a0 0x0 0x10>;
1839 pinctrl-names = "default";
1840 pinctrl-0 = <&vop0_pwm_pin>;
1841 clocks = <&cru SCLK_VOP0_PWM>;
1842 clock-names = "pwm";
1843 status = "disabled";
1846 vopb_mmu: iommu@ff903f00 {
1847 compatible = "rockchip,iommu";
1848 reg = <0x0 0xff903f00 0x0 0x100>;
1849 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1850 interrupt-names = "vopb_mmu";
1851 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1852 clock-names = "aclk", "hclk";
1853 power-domains = <&power RK3399_PD_VOPB>;
1855 status = "disabled";
1858 isp0_mmu: iommu@ff914000 {
1859 compatible = "rockchip,iommu";
1860 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1861 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1862 interrupt-names = "isp0_mmu";
1864 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1865 clock-names = "aclk", "hclk";
1866 power-domains = <&power RK3399_PD_ISP0>;
1867 rk_iommu,disable_reset_quirk;
1868 status = "disabled";
1871 isp1_mmu: iommu@ff924000 {
1872 compatible = "rockchip,iommu";
1873 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1874 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1875 interrupt-names = "isp1_mmu";
1877 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1878 clock-names = "aclk", "hclk";
1879 power-domains = <&power RK3399_PD_ISP1>;
1880 rk_iommu,disable_reset_quirk;
1881 status = "disabled";
1884 hdmi: hdmi@ff940000 {
1885 compatible = "rockchip,rk3399-dw-hdmi";
1886 reg = <0x0 0xff940000 0x0 0x20000>;
1888 rockchip,grf = <&grf>;
1889 pinctrl-names = "default";
1890 pinctrl-0 = <&hdmi_i2c_xfer>;
1891 power-domains = <&power RK3399_PD_HDCP>;
1892 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1893 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1894 clock-names = "iahb", "isfr", "vpll", "grf";
1895 status = "disabled";
1899 #address-cells = <1>;
1901 hdmi_in_vopb: endpoint@0 {
1903 remote-endpoint = <&vopb_out_hdmi>;
1905 hdmi_in_vopl: endpoint@1 {
1907 remote-endpoint = <&vopl_out_hdmi>;
1913 mipi_dsi: mipi@ff960000 {
1914 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1915 reg = <0x0 0xff960000 0x0 0x8000>;
1916 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1917 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1918 <&cru SCLK_DPHY_TX0_CFG>;
1919 clock-names = "ref", "pclk", "phy_cfg";
1920 power-domains = <&power RK3399_PD_VIO>;
1921 rockchip,grf = <&grf>;
1922 #address-cells = <1>;
1924 status = "disabled";
1927 #address-cells = <1>;
1932 #address-cells = <1>;
1935 mipi_in_vopb: endpoint@0 {
1937 remote-endpoint = <&vopb_out_mipi>;
1939 mipi_in_vopl: endpoint@1 {
1941 remote-endpoint = <&vopl_out_mipi>;
1948 compatible = "rockchip,rk3399-edp";
1949 reg = <0x0 0xff970000 0x0 0x8000>;
1950 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1951 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1952 clock-names = "dp", "pclk";
1953 power-domains = <&power RK3399_PD_EDP>;
1954 resets = <&cru SRST_P_EDP_CTRL>;
1956 rockchip,grf = <&grf>;
1957 status = "disabled";
1958 pinctrl-names = "default";
1959 pinctrl-0 = <&edp_hpd>;
1962 #address-cells = <1>;
1967 #address-cells = <1>;
1970 edp_in_vopb: endpoint@0 {
1972 remote-endpoint = <&vopb_out_edp>;
1975 edp_in_vopl: endpoint@1 {
1977 remote-endpoint = <&vopl_out_edp>;
1983 display_subsystem: display-subsystem {
1984 compatible = "rockchip,display-subsystem";
1985 ports = <&vopl_out>, <&vopb_out>;
1986 status = "disabled";
1990 compatible = "rockchip,rk3399-pinctrl";
1991 rockchip,grf = <&grf>;
1992 rockchip,pmu = <&pmugrf>;
1993 #address-cells = <0x2>;
1994 #size-cells = <0x2>;
1997 gpio0: gpio0@ff720000 {
1998 compatible = "rockchip,gpio-bank";
1999 reg = <0x0 0xff720000 0x0 0x100>;
2000 clocks = <&pmucru PCLK_GPIO0_PMU>;
2001 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2004 #gpio-cells = <0x2>;
2006 interrupt-controller;
2007 #interrupt-cells = <0x2>;
2010 gpio1: gpio1@ff730000 {
2011 compatible = "rockchip,gpio-bank";
2012 reg = <0x0 0xff730000 0x0 0x100>;
2013 clocks = <&pmucru PCLK_GPIO1_PMU>;
2014 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2017 #gpio-cells = <0x2>;
2019 interrupt-controller;
2020 #interrupt-cells = <0x2>;
2023 gpio2: gpio2@ff780000 {
2024 compatible = "rockchip,gpio-bank";
2025 reg = <0x0 0xff780000 0x0 0x100>;
2026 clocks = <&cru PCLK_GPIO2>;
2027 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2030 #gpio-cells = <0x2>;
2032 interrupt-controller;
2033 #interrupt-cells = <0x2>;
2036 gpio3: gpio3@ff788000 {
2037 compatible = "rockchip,gpio-bank";
2038 reg = <0x0 0xff788000 0x0 0x100>;
2039 clocks = <&cru PCLK_GPIO3>;
2040 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2043 #gpio-cells = <0x2>;
2045 interrupt-controller;
2046 #interrupt-cells = <0x2>;
2049 gpio4: gpio4@ff790000 {
2050 compatible = "rockchip,gpio-bank";
2051 reg = <0x0 0xff790000 0x0 0x100>;
2052 clocks = <&cru PCLK_GPIO4>;
2053 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2056 #gpio-cells = <0x2>;
2058 interrupt-controller;
2059 #interrupt-cells = <0x2>;
2062 pcfg_pull_up: pcfg-pull-up {
2066 pcfg_pull_down: pcfg-pull-down {
2070 pcfg_pull_none: pcfg-pull-none {
2074 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2076 drive-strength = <20>;
2079 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2081 drive-strength = <20>;
2084 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2086 drive-strength = <18>;
2089 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2091 drive-strength = <12>;
2094 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2096 drive-strength = <8>;
2099 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2101 drive-strength = <4>;
2104 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2106 drive-strength = <2>;
2109 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2111 drive-strength = <12>;
2114 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2116 drive-strength = <13>;
2119 pcfg_output_high: pcfg-output-high {
2123 pcfg_output_low: pcfg-output-low {
2127 pcfg_input: pcfg-input {
2132 emmc_pwr: emmc-pwr {
2134 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2139 rgmii_pins: rgmii-pins {
2142 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2144 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2146 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2148 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2150 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2152 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2154 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2156 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2158 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2160 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2162 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2164 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2166 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2168 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2170 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2173 rmii_pins: rmii-pins {
2176 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2178 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2180 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2182 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2184 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2186 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2188 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2190 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2192 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2194 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2199 i2c0_xfer: i2c0-xfer {
2201 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2202 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2207 i2c1_xfer: i2c1-xfer {
2209 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2210 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2215 i2c2_xfer: i2c2-xfer {
2217 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2218 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2223 i2c3_xfer: i2c3-xfer {
2225 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2226 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2229 i2c3_gpio: i2c3_gpio {
2231 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2232 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2238 i2c4_xfer: i2c4-xfer {
2240 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2241 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2246 i2c5_xfer: i2c5-xfer {
2248 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2249 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2254 i2c6_xfer: i2c6-xfer {
2256 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2257 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2262 i2c7_xfer: i2c7-xfer {
2264 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2265 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2270 i2c8_xfer: i2c8-xfer {
2272 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2273 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2278 i2s0_8ch_bus: i2s0-8ch-bus {
2280 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2281 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2282 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2283 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2284 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2285 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2286 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2287 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2288 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2293 i2s1_2ch_bus: i2s1-2ch-bus {
2295 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2296 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2297 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2298 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2299 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2304 sdio0_bus1: sdio0-bus1 {
2306 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2309 sdio0_bus4: sdio0-bus4 {
2311 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2312 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2313 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2314 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2317 sdio0_cmd: sdio0-cmd {
2319 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2322 sdio0_clk: sdio0-clk {
2324 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2327 sdio0_cd: sdio0-cd {
2329 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2332 sdio0_pwr: sdio0-pwr {
2334 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2337 sdio0_bkpwr: sdio0-bkpwr {
2339 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2342 sdio0_wp: sdio0-wp {
2344 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2347 sdio0_int: sdio0-int {
2349 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2354 sdmmc_bus1: sdmmc-bus1 {
2356 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2359 sdmmc_bus4: sdmmc-bus4 {
2361 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2362 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2363 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2364 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2367 sdmmc_clk: sdmmc-clk {
2369 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2372 sdmmc_cmd: sdmmc-cmd {
2374 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2377 sdmmc_cd: sdmcc-cd {
2379 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2382 sdmmc_wp: sdmmc-wp {
2384 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2389 spdif_bus: spdif-bus {
2391 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2394 spdif_bus_1: spdif-bus-1 {
2396 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2401 spi0_clk: spi0-clk {
2403 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2405 spi0_cs0: spi0-cs0 {
2407 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2409 spi0_cs1: spi0-cs1 {
2411 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2415 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2419 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2424 spi1_clk: spi1-clk {
2426 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2428 spi1_cs0: spi1-cs0 {
2430 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2434 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2438 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2443 spi2_clk: spi2-clk {
2445 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2447 spi2_cs0: spi2-cs0 {
2449 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2453 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2457 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2462 spi3_clk: spi3-clk {
2464 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2466 spi3_cs0: spi3-cs0 {
2468 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2472 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2476 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2481 spi4_clk: spi4-clk {
2483 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2485 spi4_cs0: spi4-cs0 {
2487 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2491 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2495 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2500 spi5_clk: spi5-clk {
2502 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2504 spi5_cs0: spi5-cs0 {
2506 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2510 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2514 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2519 otp_gpio: otp-gpio {
2520 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2524 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2529 uart0_xfer: uart0-xfer {
2531 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2532 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2535 uart0_cts: uart0-cts {
2537 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2540 uart0_rts: uart0-rts {
2542 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2547 uart1_xfer: uart1-xfer {
2549 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2550 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2555 uart2a_xfer: uart2a-xfer {
2557 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2558 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2563 uart2b_xfer: uart2b-xfer {
2565 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2566 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2571 uart2c_xfer: uart2c-xfer {
2573 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2574 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2579 uart3_xfer: uart3-xfer {
2581 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2582 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2585 uart3_cts: uart3-cts {
2587 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2590 uart3_rts: uart3-rts {
2592 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2597 uart4_xfer: uart4-xfer {
2599 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2600 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2605 uarthdcp_xfer: uarthdcp-xfer {
2607 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2608 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2613 pwm0_pin: pwm0-pin {
2615 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2618 vop0_pwm_pin: vop0-pwm-pin {
2620 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2625 pwm1_pin: pwm1-pin {
2627 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2630 vop1_pwm_pin: vop1-pwm-pin {
2632 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2637 pwm2_pin: pwm2-pin {
2639 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2644 pwm3a_pin: pwm3a-pin {
2646 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2651 pwm3b_pin: pwm3b-pin {
2653 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2660 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2665 hdmi_i2c_xfer: hdmi-i2c-xfer {
2667 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2668 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2671 hdmi_cec: hdmi-cec {
2673 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2678 pcie_clkreqn: pci-clkreqn {
2680 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2683 pcie_clkreqnb: pci-clkreqnb {
2685 <4 24 RK_FUNC_1 &pcfg_pull_none>;
2688 pcie_clkreqn_cpm: pci-clkreqn-cpm {
2690 * Since our pcie doesn't support
2691 * ClockPM(CPM), we want to hack this as
2692 * gpio, so the EP could be able to
2693 * de-assert it along and make ClockPM(CPM)
2697 <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2700 pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2702 <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2707 rockchip_suspend: rockchip-suspend {
2708 compatible = "rockchip,pm-rk3399";
2709 status = "disabled";
2710 rockchip,sleep-debug-en = <0>;
2711 rockchip,virtual-poweroff = <0>;
2712 rockchip,sleep-mode-config = <
2719 | RKPM_SLP_CENTER_PD
2720 | RKPM_SLP_AP_PWROFF
2723 rockchip,wakeup-config = <