arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         dynamic-power-coefficient = <100>;
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                         clocks = <&cru ARMCLKL>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu_l2: cpu@2 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x2>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 136                 };
 137
 138                 cpu_l3: cpu@3 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53", "arm,armv8";
 141                         reg = <0x0 0x3>;
 142                         enable-method = "psci";
 143                         clocks = <&cru ARMCLKL>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu_b0: cpu@100 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x100>;
 151                         enable-method = "psci";
 152                         #cooling-cells = <2>; /* min followed by max */
 153                         dynamic-power-coefficient = <436>;
 154                         clocks = <&cru ARMCLKB>;
 155                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 156                 };
 157
 158                 cpu_b1: cpu@101 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a72", "arm,armv8";
 161                         reg = <0x0 0x101>;
 162                         enable-method = "psci";
 163                         clocks = <&cru ARMCLKB>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 idle-states {
 168                         entry-method = "psci";
 169
 170                         CPU_SLEEP: cpu-sleep {
 171                                 compatible = "arm,idle-state";
 172                                 local-timer-stop;
 173                                 arm,psci-suspend-param = <0x0010000>;
 174                                 entry-latency-us = <120>;
 175                                 exit-latency-us = <250>;
 176                                 min-residency-us = <900>;
 177                         };
 178
 179                         CLUSTER_SLEEP: cluster-sleep {
 180                                 compatible = "arm,idle-state";
 181                                 local-timer-stop;
 182                                 arm,psci-suspend-param = <0x1010000>;
 183                                 entry-latency-us = <400>;
 184                                 exit-latency-us = <500>;
 185                                 min-residency-us = <2000>;
 186                         };
 187                 };
 188         };
 189
 190         cpu_avs: cpu-avs {
 191                 cluster0-avs {
 192                         cluster-id = <0>;
 193                         min-volt = <800000>; /* uV */
 194                         min-freq = <408000>; /* KHz */
 195                         leakage-adjust-volt = <
 196                         /*  mA        mA         uV */
 197                             0         254        0
 198                         >;
 199                         nvmem-cells = <&cpul_leakage>;
 200                         nvmem-cell-names = "cpu_leakage";
 201                 };
 202                 cluster1-avs {
 203                         cluster-id = <1>;
 204                         min-volt = <800000>; /* uV */
 205                         min-freq = <408000>; /* KHz */
 206                         leakage-adjust-volt = <
 207                         /*  mA        mA         uV */
 208                             0         254        0
 209                         >;
 210                         nvmem-cells = <&cpub_leakage>;
 211                         nvmem-cell-names = "cpu_leakage";
 212                 };
 213         };
 214
 215         pmu_a53 {
 216                 compatible = "arm,cortex-a53-pmu";
 217                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 218         };
 219
 220         pmu_a72 {
 221                 compatible = "arm,cortex-a72-pmu";
 222                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 223         };
 224
 225         psci {
 226                 compatible = "arm,psci-1.0";
 227                 method = "smc";
 228         };
 229
 230         cpuinfo {
 231                 compatible = "rockchip,cpuinfo";
 232                 nvmem-cells = <&efuse_id>;
 233                 nvmem-cell-names = "id";
 234         };
 235
 236         timer {
 237                 compatible = "arm,armv8-timer";
 238                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 239                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 240                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 241                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 242         };
 243
 244         xin24m: xin24m {
 245                 compatible = "fixed-clock";
 246                 clock-frequency = <24000000>;
 247                 clock-output-names = "xin24m";
 248                 #clock-cells = <0>;
 249         };
 250
 251         dummy_cpll: dummy_cpll {
 252                 compatible = "fixed-clock";
 253                 clock-frequency = <0>;
 254                 clock-output-names = "dummy_cpll";
 255                 #clock-cells = <0>;
 256         };
 257
 258         dummy_vpll: dummy_vpll {
 259                 compatible = "fixed-clock";
 260                 clock-frequency = <0>;
 261                 clock-output-names = "dummy_vpll";
 262                 #clock-cells = <0>;
 263         };
 264
 265         amba {
 266                 compatible = "arm,amba-bus";
 267                 #address-cells = <2>;
 268                 #size-cells = <2>;
 269                 ranges;
 270
 271                 dmac_bus: dma-controller@ff6d0000 {
 272                         compatible = "arm,pl330", "arm,primecell";
 273                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 274                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 275                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 276                         #dma-cells = <1>;
 277                         clocks = <&cru ACLK_DMAC0_PERILP>;
 278                         clock-names = "apb_pclk";
 279                         peripherals-req-type-burst;
 280                 };
 281
 282                 dmac_peri: dma-controller@ff6e0000 {
 283                         compatible = "arm,pl330", "arm,primecell";
 284                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 285                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 286                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 287                         #dma-cells = <1>;
 288                         clocks = <&cru ACLK_DMAC1_PERILP>;
 289                         clock-names = "apb_pclk";
 290                         peripherals-req-type-burst;
 291                 };
 292         };
 293
 294         gmac: ethernet@fe300000 {
 295                 compatible = "rockchip,rk3399-gmac";
 296                 reg = <0x0 0xfe300000 0x0 0x10000>;
 297                 rockchip,grf = <&grf>;
 298                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 299                 interrupt-names = "macirq";
 300                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 301                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 302                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 303                          <&cru PCLK_GMAC>;
 304                 clock-names = "stmmaceth", "mac_clk_rx",
 305                               "mac_clk_tx", "clk_mac_ref",
 306                               "clk_mac_refout", "aclk_mac",
 307                               "pclk_mac";
 308                 resets = <&cru SRST_A_GMAC>;
 309                 reset-names = "stmmaceth";
 310                 power-domains = <&power RK3399_PD_GMAC>;
 311                 status = "disabled";
 312         };
 313
 314         sdio0: dwmmc@fe310000 {
 315                 compatible = "rockchip,rk3399-dw-mshc",
 316                              "rockchip,rk3288-dw-mshc";
 317                 reg = <0x0 0xfe310000 0x0 0x4000>;
 318                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 319                 clock-freq-min-max = <400000 150000000>;
 320                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 321                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 322                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 323                 fifo-depth = <0x100>;
 324                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 325                 status = "disabled";
 326         };
 327
 328         sdmmc: dwmmc@fe320000 {
 329                 compatible = "rockchip,rk3399-dw-mshc",
 330                              "rockchip,rk3288-dw-mshc";
 331                 reg = <0x0 0xfe320000 0x0 0x4000>;
 332                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 333                 clock-freq-min-max = <400000 150000000>;
 334                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 335                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 336                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 337                 fifo-depth = <0x100>;
 338                 power-domains = <&power RK3399_PD_SD>;
 339                 status = "disabled";
 340         };
 341
 342         sdhci: sdhci@fe330000 {
 343                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 344                 reg = <0x0 0xfe330000 0x0 0x10000>;
 345                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 346                 arasan,soc-ctl-syscon = <&grf>;
 347                 assigned-clocks = <&cru SCLK_EMMC>;
 348                 assigned-clock-rates = <200000000>;
 349                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 350                 clock-names = "clk_xin", "clk_ahb";
 351                 clock-output-names = "emmc_cardclock";
 352                 #clock-cells = <0>;
 353                 phys = <&emmc_phy>;
 354                 phy-names = "phy_arasan";
 355                 power-domains = <&power RK3399_PD_EMMC>;
 356                 status = "disabled";
 357         };
 358
 359         usb_host0_ehci: usb@fe380000 {
 360                 compatible = "generic-ehci";
 361                 reg = <0x0 0xfe380000 0x0 0x20000>;
 362                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 363                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 364                          <&cru SCLK_USBPHY0_480M_SRC>;
 365                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 366                 phys = <&u2phy0_host>;
 367                 phy-names = "usb";
 368                 power-domains = <&power RK3399_PD_PERIHP>;
 369                 status = "disabled";
 370         };
 371
 372         usb_host0_ohci: usb@fe3a0000 {
 373                 compatible = "generic-ohci";
 374                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 375                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 376                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 377                          <&cru SCLK_USBPHY0_480M_SRC>;
 378                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 379                 phys = <&u2phy0_host>;
 380                 phy-names = "usb";
 381                 power-domains = <&power RK3399_PD_PERIHP>;
 382                 status = "disabled";
 383         };
 384
 385         usb_host1_ehci: usb@fe3c0000 {
 386                 compatible = "generic-ehci";
 387                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 388                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 389                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 390                          <&cru SCLK_USBPHY1_480M_SRC>;
 391                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 392                 phys = <&u2phy1_host>;
 393                 phy-names = "usb";
 394                 power-domains = <&power RK3399_PD_PERIHP>;
 395                 status = "disabled";
 396         };
 397
 398         usb_host1_ohci: usb@fe3e0000 {
 399                 compatible = "generic-ohci";
 400                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 401                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 402                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 403                          <&cru SCLK_USBPHY1_480M_SRC>;
 404                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 405                 phys = <&u2phy1_host>;
 406                 phy-names = "usb";
 407                 power-domains = <&power RK3399_PD_PERIHP>;
 408                 status = "disabled";
 409         };
 410
 411         usbdrd3_0: usb@fe800000 {
 412                 compatible = "rockchip,rk3399-dwc3";
 413                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 414                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 415                 clock-names = "ref_clk", "suspend_clk",
 416                               "bus_clk", "grf_clk";
 417                 power-domains = <&power RK3399_PD_USB3>;
 418                 resets = <&cru SRST_A_USB3_OTG0>;
 419                 reset-names = "usb3-otg";
 420                 #address-cells = <2>;
 421                 #size-cells = <2>;
 422                 ranges;
 423                 status = "disabled";
 424                 usbdrd_dwc3_0: dwc3@fe800000 {
 425                         compatible = "snps,dwc3";
 426                         reg = <0x0 0xfe800000 0x0 0x100000>;
 427                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 428                         dr_mode = "otg";
 429                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 430                         phy-names = "usb2-phy", "usb3-phy";
 431                         phy_type = "utmi_wide";
 432                         snps,dis_enblslpm_quirk;
 433                         snps,dis-u2-freeclk-exists-quirk;
 434                         snps,dis_u2_susphy_quirk;
 435                         snps,dis-del-phy-power-chg-quirk;
 436                         snps,xhci-slow-suspend-quirk;
 437                         status = "disabled";
 438                 };
 439         };
 440
 441         usbdrd3_1: usb@fe900000 {
 442                 compatible = "rockchip,rk3399-dwc3";
 443                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 444                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 445                 clock-names = "ref_clk", "suspend_clk",
 446                               "bus_clk", "grf_clk";
 447                 power-domains = <&power RK3399_PD_USB3>;
 448                 resets = <&cru SRST_A_USB3_OTG1>;
 449                 reset-names = "usb3-otg";
 450                 #address-cells = <2>;
 451                 #size-cells = <2>;
 452                 ranges;
 453                 status = "disabled";
 454                 usbdrd_dwc3_1: dwc3@fe900000 {
 455                         compatible = "snps,dwc3";
 456                         reg = <0x0 0xfe900000 0x0 0x100000>;
 457                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 458                         dr_mode = "host";
 459                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 460                         phy-names = "usb2-phy", "usb3-phy";
 461                         phy_type = "utmi_wide";
 462                         snps,dis_enblslpm_quirk;
 463                         snps,dis-u2-freeclk-exists-quirk;
 464                         snps,dis_u2_susphy_quirk;
 465                         snps,dis-del-phy-power-chg-quirk;
 466                         snps,xhci-slow-suspend-quirk;
 467                         status = "disabled";
 468                 };
 469         };
 470
 471         cdn_dp: dp@fec00000 {
 472                 compatible = "rockchip,rk3399-cdn-dp";
 473                 reg = <0x0 0xfec00000 0x0 0x100000>;
 474                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 475                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 476                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 477                 clock-names = "core-clk", "pclk", "spdif", "grf";
 478                 assigned-clocks = <&cru SCLK_DP_CORE>;
 479                 assigned-clock-rates = <100000000>;
 480                 power-domains = <&power RK3399_PD_HDCP>;
 481                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 482                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 483                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 484                 reset-names = "spdif", "dptx", "apb", "core";
 485                 rockchip,grf = <&grf>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 #sound-dai-cells = <1>;
 489                 status = "disabled";
 490
 491                 ports {
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494
 495                         dp_in: port {
 496                                 #address-cells = <1>;
 497                                 #size-cells = <0>;
 498                                 dp_in_vopb: endpoint@0 {
 499                                         reg = <0>;
 500                                         remote-endpoint = <&vopb_out_dp>;
 501                                 };
 502
 503                                 dp_in_vopl: endpoint@1 {
 504                                         reg = <1>;
 505                                         remote-endpoint = <&vopl_out_dp>;
 506                                 };
 507                         };
 508                 };
 509         };
 510
 511         gic: interrupt-controller@fee00000 {
 512                 compatible = "arm,gic-v3";
 513                 #interrupt-cells = <4>;
 514                 #address-cells = <2>;
 515                 #size-cells = <2>;
 516                 ranges;
 517                 interrupt-controller;
 518
 519                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 520                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 521                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 522                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 523                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 524                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 525                 its: interrupt-controller@fee20000 {
 526                         compatible = "arm,gic-v3-its";
 527                         msi-controller;
 528                         reg = <0x0 0xfee20000 0x0 0x20000>;
 529                 };
 530
 531                 ppi-partitions {
 532                         ppi_cluster0: interrupt-partition-0 {
 533                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 534                         };
 535
 536                         ppi_cluster1: interrupt-partition-1 {
 537                                 affinity = <&cpu_b0 &cpu_b1>;
 538                         };
 539                 };
 540         };
 541
 542         saradc: saradc@ff100000 {
 543                 compatible = "rockchip,rk3399-saradc";
 544                 reg = <0x0 0xff100000 0x0 0x100>;
 545                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 546                 #io-channel-cells = <1>;
 547                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 548                 clock-names = "saradc", "apb_pclk";
 549                 resets = <&cru SRST_P_SARADC>;
 550                 reset-names = "saradc-apb";
 551                 status = "disabled";
 552         };
 553
 554         i2c0: i2c@ff3c0000 {
 555                 compatible = "rockchip,rk3399-i2c";
 556                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 557                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 558                 clock-names = "i2c", "pclk";
 559                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c0_xfer>;
 562                 #address-cells = <1>;
 563                 #size-cells = <0>;
 564                 status = "disabled";
 565         };
 566
 567         i2c1: i2c@ff110000 {
 568                 compatible = "rockchip,rk3399-i2c";
 569                 reg = <0x0 0xff110000 0x0 0x1000>;
 570                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 571                 clock-names = "i2c", "pclk";
 572                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c1_xfer>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 status = "disabled";
 578         };
 579
 580         i2c2: i2c@ff120000 {
 581                 compatible = "rockchip,rk3399-i2c";
 582                 reg = <0x0 0xff120000 0x0 0x1000>;
 583                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 584                 clock-names = "i2c", "pclk";
 585                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 586                 pinctrl-names = "default";
 587                 pinctrl-0 = <&i2c2_xfer>;
 588                 #address-cells = <1>;
 589                 #size-cells = <0>;
 590                 status = "disabled";
 591         };
 592
 593         i2c3: i2c@ff130000 {
 594                 compatible = "rockchip,rk3399-i2c";
 595                 reg = <0x0 0xff130000 0x0 0x1000>;
 596                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 597                 clock-names = "i2c", "pclk";
 598                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&i2c3_xfer>;
 601                 #address-cells = <1>;
 602                 #size-cells = <0>;
 603                 status = "disabled";
 604         };
 605
 606         i2c5: i2c@ff140000 {
 607                 compatible = "rockchip,rk3399-i2c";
 608                 reg = <0x0 0xff140000 0x0 0x1000>;
 609                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 610                 clock-names = "i2c", "pclk";
 611                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 612                 pinctrl-names = "default";
 613                 pinctrl-0 = <&i2c5_xfer>;
 614                 #address-cells = <1>;
 615                 #size-cells = <0>;
 616                 status = "disabled";
 617         };
 618
 619         i2c6: i2c@ff150000 {
 620                 compatible = "rockchip,rk3399-i2c";
 621                 reg = <0x0 0xff150000 0x0 0x1000>;
 622                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 623                 clock-names = "i2c", "pclk";
 624                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 625                 pinctrl-names = "default";
 626                 pinctrl-0 = <&i2c6_xfer>;
 627                 #address-cells = <1>;
 628                 #size-cells = <0>;
 629                 status = "disabled";
 630         };
 631
 632         i2c7: i2c@ff160000 {
 633                 compatible = "rockchip,rk3399-i2c";
 634                 reg = <0x0 0xff160000 0x0 0x1000>;
 635                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 636                 clock-names = "i2c", "pclk";
 637                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 638                 pinctrl-names = "default";
 639                 pinctrl-0 = <&i2c7_xfer>;
 640                 #address-cells = <1>;
 641                 #size-cells = <0>;
 642                 status = "disabled";
 643         };
 644
 645         uart0: serial@ff180000 {
 646                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 647                 reg = <0x0 0xff180000 0x0 0x100>;
 648                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 649                 clock-names = "baudclk", "apb_pclk";
 650                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 651                 reg-shift = <2>;
 652                 reg-io-width = <4>;
 653                 pinctrl-names = "default";
 654                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 655                 status = "disabled";
 656         };
 657
 658         uart1: serial@ff190000 {
 659                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 660                 reg = <0x0 0xff190000 0x0 0x100>;
 661                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 662                 clock-names = "baudclk", "apb_pclk";
 663                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 664                 reg-shift = <2>;
 665                 reg-io-width = <4>;
 666                 pinctrl-names = "default";
 667                 pinctrl-0 = <&uart1_xfer>;
 668                 status = "disabled";
 669         };
 670
 671         uart2: serial@ff1a0000 {
 672                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 673                 reg = <0x0 0xff1a0000 0x0 0x100>;
 674                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 675                 clock-names = "baudclk", "apb_pclk";
 676                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 677                 reg-shift = <2>;
 678                 reg-io-width = <4>;
 679                 pinctrl-names = "default";
 680                 pinctrl-0 = <&uart2c_xfer>;
 681                 status = "disabled";
 682         };
 683
 684         uart3: serial@ff1b0000 {
 685                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 686                 reg = <0x0 0xff1b0000 0x0 0x100>;
 687                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 688                 clock-names = "baudclk", "apb_pclk";
 689                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 690                 reg-shift = <2>;
 691                 reg-io-width = <4>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 694                 status = "disabled";
 695         };
 696
 697         spi0: spi@ff1c0000 {
 698                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 699                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 700                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 701                 clock-names = "spiclk", "apb_pclk";
 702                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 705                 #address-cells = <1>;
 706                 #size-cells = <0>;
 707                 status = "disabled";
 708         };
 709
 710         spi1: spi@ff1d0000 {
 711                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 712                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 713                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 714                 clock-names = "spiclk", "apb_pclk";
 715                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 716                 pinctrl-names = "default";
 717                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 718                 #address-cells = <1>;
 719                 #size-cells = <0>;
 720                 status = "disabled";
 721         };
 722
 723         spi2: spi@ff1e0000 {
 724                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 725                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 726                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 727                 clock-names = "spiclk", "apb_pclk";
 728                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 731                 #address-cells = <1>;
 732                 #size-cells = <0>;
 733                 status = "disabled";
 734         };
 735
 736         spi4: spi@ff1f0000 {
 737                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 738                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 739                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 740                 clock-names = "spiclk", "apb_pclk";
 741                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 742                 pinctrl-names = "default";
 743                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 744                 #address-cells = <1>;
 745                 #size-cells = <0>;
 746                 status = "disabled";
 747         };
 748
 749         spi5: spi@ff200000 {
 750                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 751                 reg = <0x0 0xff200000 0x0 0x1000>;
 752                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 753                 clock-names = "spiclk", "apb_pclk";
 754                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 755                 pinctrl-names = "default";
 756                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 757                 #address-cells = <1>;
 758                 #size-cells = <0>;
 759                 status = "disabled";
 760         };
 761
 762         thermal_zones: thermal-zones {
 763                 soc_thermal: soc-thermal {
 764                         polling-delay-passive = <20>; /* milliseconds */
 765                         polling-delay = <1000>; /* milliseconds */
 766                         sustainable-power = <1000>; /* milliwatts */
 767
 768                         thermal-sensors = <&tsadc 0>;
 769
 770                         trips {
 771                                 threshold: trip-point@0 {
 772                                         temperature = <70000>; /* millicelsius */
 773                                         hysteresis = <2000>; /* millicelsius */
 774                                         type = "passive";
 775                                 };
 776                                 target: trip-point@1 {
 777                                         temperature = <85000>; /* millicelsius */
 778                                         hysteresis = <2000>; /* millicelsius */
 779                                         type = "passive";
 780                                 };
 781                                 soc_crit: soc-crit {
 782                                         temperature = <95000>; /* millicelsius */
 783                                         hysteresis = <2000>; /* millicelsius */
 784                                         type = "critical";
 785                                 };
 786                         };
 787
 788                         cooling-maps {
 789                                 map0 {
 790                                         trip = <&target>;
 791                                         cooling-device =
 792                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 793                                         contribution = <4096>;
 794                                 };
 795                                 map1 {
 796                                         trip = <&target>;
 797                                         cooling-device =
 798                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 799                                         contribution = <1024>;
 800                                 };
 801                                 map2 {
 802                                         trip = <&target>;
 803                                         cooling-device =
 804                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 805                                         contribution = <4096>;
 806                                 };
 807                         };
 808                 };
 809
 810                 gpu_thermal: gpu-thermal {
 811                         polling-delay-passive = <100>; /* milliseconds */
 812                         polling-delay = <1000>; /* milliseconds */
 813
 814                         thermal-sensors = <&tsadc 1>;
 815                 };
 816         };
 817
 818         tsadc: tsadc@ff260000 {
 819                 compatible = "rockchip,rk3399-tsadc";
 820                 reg = <0x0 0xff260000 0x0 0x100>;
 821                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 822                 rockchip,grf = <&grf>;
 823                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 824                 clock-names = "tsadc", "apb_pclk";
 825                 assigned-clocks = <&cru SCLK_TSADC>;
 826                 assigned-clock-rates = <750000>;
 827                 resets = <&cru SRST_TSADC>;
 828                 reset-names = "tsadc-apb";
 829                 pinctrl-names = "init", "default", "sleep";
 830                 pinctrl-0 = <&otp_gpio>;
 831                 pinctrl-1 = <&otp_out>;
 832                 pinctrl-2 = <&otp_gpio>;
 833                 #thermal-sensor-cells = <1>;
 834                 rockchip,hw-tshut-temp = <95000>;
 835                 status = "disabled";
 836         };
 837
 838         qos_emmc: qos@ffa58000 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa58000 0x0 0x20>;
 841         };
 842
 843         qos_gmac: qos@ffa5c000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa5c000 0x0 0x20>;
 846         };
 847
 848         qos_pcie: qos@ffa60080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa60080 0x0 0x20>;
 851         };
 852
 853         qos_usb_host0: qos@ffa60100 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa60100 0x0 0x20>;
 856         };
 857
 858         qos_usb_host1: qos@ffa60180 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa60180 0x0 0x20>;
 861         };
 862
 863         qos_usb_otg0: qos@ffa70000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa70000 0x0 0x20>;
 866         };
 867
 868         qos_usb_otg1: qos@ffa70080 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa70080 0x0 0x20>;
 871         };
 872
 873         qos_sd: qos@ffa74000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffa74000 0x0 0x20>;
 876         };
 877
 878         qos_sdioaudio: qos@ffa76000 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffa76000 0x0 0x20>;
 881         };
 882
 883         qos_hdcp: qos@ffa90000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffa90000 0x0 0x20>;
 886         };
 887
 888         qos_iep: qos@ffa98000 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffa98000 0x0 0x20>;
 891         };
 892
 893         qos_isp0_m0: qos@ffaa0000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffaa0000 0x0 0x20>;
 896         };
 897
 898         qos_isp0_m1: qos@ffaa0080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffaa0080 0x0 0x20>;
 901         };
 902
 903         qos_isp1_m0: qos@ffaa8000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffaa8000 0x0 0x20>;
 906         };
 907
 908         qos_isp1_m1: qos@ffaa8080 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffaa8080 0x0 0x20>;
 911         };
 912
 913         qos_rga_r: qos@ffab0000 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffab0000 0x0 0x20>;
 916         };
 917
 918         qos_rga_w: qos@ffab0080 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffab0080 0x0 0x20>;
 921         };
 922
 923         qos_video_m0: qos@ffab8000 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffab8000 0x0 0x20>;
 926         };
 927
 928         qos_video_m1_r: qos@ffac0000 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffac0000 0x0 0x20>;
 931         };
 932
 933         qos_video_m1_w: qos@ffac0080 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffac0080 0x0 0x20>;
 936         };
 937
 938         qos_vop_big_r: qos@ffac8000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffac8000 0x0 0x20>;
 941         };
 942
 943         qos_vop_big_w: qos@ffac8080 {
 944                 compatible = "syscon";
 945                 reg = <0x0 0xffac8080 0x0 0x20>;
 946         };
 947
 948         qos_vop_little: qos@ffad0000 {
 949                 compatible = "syscon";
 950                 reg = <0x0 0xffad0000 0x0 0x20>;
 951         };
 952
 953         qos_perihp: qos@ffad8080 {
 954                 compatible = "syscon";
 955                 reg = <0x0 0xffad8080 0x0 0x20>;
 956         };
 957
 958         qos_gpu: qos@ffae0000 {
 959                 compatible = "syscon";
 960                 reg = <0x0 0xffae0000 0x0 0x20>;
 961         };
 962
 963         pmu: power-management@ff310000 {
 964                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 965                 reg = <0x0 0xff310000 0x0 0x1000>;
 966
 967                 /*
 968                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 969                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 970                  * Some of the power domains are grouped together for every
 971                  * voltage domain.
 972                  * The detail contents as below.
 973                  */
 974                 power: power-controller {
 975                         compatible = "rockchip,rk3399-power-controller";
 976                         #power-domain-cells = <1>;
 977                         #address-cells = <1>;
 978                         #size-cells = <0>;
 979
 980                         /* These power domains are grouped by VD_CENTER */
 981                         pd_iep@RK3399_PD_IEP {
 982                                 reg = <RK3399_PD_IEP>;
 983                                 clocks = <&cru ACLK_IEP>,
 984                                          <&cru HCLK_IEP>;
 985                                 pm_qos = <&qos_iep>;
 986                         };
 987                         pd_rga@RK3399_PD_RGA {
 988                                 reg = <RK3399_PD_RGA>;
 989                                 clocks = <&cru ACLK_RGA>,
 990                                          <&cru HCLK_RGA>;
 991                                 pm_qos = <&qos_rga_r>,
 992                                          <&qos_rga_w>;
 993                         };
 994                         pd_vcodec@RK3399_PD_VCODEC {
 995                                 reg = <RK3399_PD_VCODEC>;
 996                                 clocks = <&cru ACLK_VCODEC>,
 997                                          <&cru HCLK_VCODEC>;
 998                                 pm_qos = <&qos_video_m0>;
 999                         };
1000                         pd_vdu@RK3399_PD_VDU {
1001                                 reg = <RK3399_PD_VDU>;
1002                                 clocks = <&cru ACLK_VDU>,
1003                                          <&cru HCLK_VDU>;
1004                                 pm_qos = <&qos_video_m1_r>,
1005                                          <&qos_video_m1_w>;
1006                         };
1007
1008                         /* These power domains are grouped by VD_GPU */
1009                         pd_gpu@RK3399_PD_GPU {
1010                                 reg = <RK3399_PD_GPU>;
1011                                 clocks = <&cru ACLK_GPU>;
1012                                 pm_qos = <&qos_gpu>;
1013                         };
1014
1015                         /* These power domains are grouped by VD_LOGIC */
1016                         pd_edp@RK3399_PD_EDP {
1017                                 reg = <RK3399_PD_EDP>;
1018                                 clocks = <&cru PCLK_EDP_CTRL>;
1019                         };
1020                         pd_emmc@RK3399_PD_EMMC {
1021                                 reg = <RK3399_PD_EMMC>;
1022                                 clocks = <&cru ACLK_EMMC>;
1023                                 pm_qos = <&qos_emmc>;
1024                         };
1025                         pd_gmac@RK3399_PD_GMAC {
1026                                 reg = <RK3399_PD_GMAC>;
1027                                 clocks = <&cru ACLK_GMAC>,
1028                                          <&cru PCLK_GMAC>;
1029                                 pm_qos = <&qos_gmac>;
1030                         };
1031                         pd_perihp@RK3399_PD_PERIHP {
1032                                 reg = <RK3399_PD_PERIHP>;
1033                                 #address-cells = <1>;
1034                                 #size-cells = <0>;
1035                                 clocks = <&cru ACLK_PERIHP>;
1036                                 pm_qos = <&qos_perihp>,
1037                                          <&qos_pcie>,
1038                                          <&qos_usb_host0>,
1039                                          <&qos_usb_host1>;
1040
1041                                 pd_sd@RK3399_PD_SD {
1042                                         reg = <RK3399_PD_SD>;
1043                                         clocks = <&cru HCLK_SDMMC>,
1044                                                  <&cru SCLK_SDMMC>;
1045                                         pm_qos = <&qos_sd>;
1046                                 };
1047                         };
1048                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1049                                 reg = <RK3399_PD_SDIOAUDIO>;
1050                                 clocks = <&cru HCLK_SDIO>;
1051                                 pm_qos = <&qos_sdioaudio>;
1052                         };
1053                         pd_usb3@RK3399_PD_USB3 {
1054                                 reg = <RK3399_PD_USB3>;
1055                                 clocks = <&cru ACLK_USB3>;
1056                                 pm_qos = <&qos_usb_otg0>,
1057                                          <&qos_usb_otg1>;
1058                         };
1059                         pd_vio@RK3399_PD_VIO {
1060                                 reg = <RK3399_PD_VIO>;
1061                                 #address-cells = <1>;
1062                                 #size-cells = <0>;
1063
1064                                 pd_hdcp@RK3399_PD_HDCP {
1065                                         reg = <RK3399_PD_HDCP>;
1066                                         clocks = <&cru ACLK_HDCP>,
1067                                                  <&cru HCLK_HDCP>,
1068                                                  <&cru PCLK_HDCP>;
1069                                         pm_qos = <&qos_hdcp>;
1070                                 };
1071                                 pd_isp0@RK3399_PD_ISP0 {
1072                                         reg = <RK3399_PD_ISP0>;
1073                                         clocks = <&cru ACLK_ISP0>,
1074                                                  <&cru HCLK_ISP0>;
1075                                         pm_qos = <&qos_isp0_m0>,
1076                                                  <&qos_isp0_m1>;
1077                                 };
1078                                 pd_isp1@RK3399_PD_ISP1 {
1079                                         reg = <RK3399_PD_ISP1>;
1080                                         clocks = <&cru ACLK_ISP1>,
1081                                                  <&cru HCLK_ISP1>;
1082                                         pm_qos = <&qos_isp1_m0>,
1083                                                  <&qos_isp1_m1>;
1084                                 };
1085                                 pd_tcpc0@RK3399_PD_TCPC0 {
1086                                         reg = <RK3399_PD_TCPD0>;
1087                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1088                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1089                                 };
1090                                 pd_tcpc1@RK3399_PD_TCPC1 {
1091                                         reg = <RK3399_PD_TCPD1>;
1092                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1093                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1094                                 };
1095                                 pd_vo@RK3399_PD_VO {
1096                                         reg = <RK3399_PD_VO>;
1097                                         #address-cells = <1>;
1098                                         #size-cells = <0>;
1099
1100                                         pd_vopb@RK3399_PD_VOPB {
1101                                                 reg = <RK3399_PD_VOPB>;
1102                                                 clocks = <&cru ACLK_VOP0>,
1103                                                          <&cru HCLK_VOP0>;
1104                                                 pm_qos = <&qos_vop_big_r>,
1105                                                          <&qos_vop_big_w>;
1106                                         };
1107                                         pd_vopl@RK3399_PD_VOPL {
1108                                                 reg = <RK3399_PD_VOPL>;
1109                                                 clocks = <&cru ACLK_VOP1>,
1110                                                          <&cru HCLK_VOP1>;
1111                                                 pm_qos = <&qos_vop_little>;
1112                                         };
1113                                 };
1114                         };
1115                 };
1116         };
1117
1118         pmugrf: syscon@ff320000 {
1119                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1120                 reg = <0x0 0xff320000 0x0 0x1000>;
1121                 #address-cells = <1>;
1122                 #size-cells = <1>;
1123
1124                 pmu_io_domains: io-domains {
1125                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1126                         status = "disabled";
1127                 };
1128
1129                 reboot-mode {
1130                         compatible = "syscon-reboot-mode";
1131                         offset = <0x300>;
1132                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1133                         mode-charge = <BOOT_CHARGING>;
1134                         mode-fastboot = <BOOT_FASTBOOT>;
1135                         mode-loader = <BOOT_BL_DOWNLOAD>;
1136                         mode-normal = <BOOT_NORMAL>;
1137                         mode-recovery = <BOOT_RECOVERY>;
1138                         mode-ums = <BOOT_UMS>;
1139                 };
1140
1141                 pmu_pvtm: pmu-pvtm {
1142                         compatible = "rockchip,rk3399-pmu-pvtm";
1143                         clocks = <&pmucru SCLK_PVTM_PMU>;
1144                         clock-names = "pmu";
1145                         status = "disabled";
1146                 };
1147         };
1148
1149         spi3: spi@ff350000 {
1150                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1151                 reg = <0x0 0xff350000 0x0 0x1000>;
1152                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1153                 clock-names = "spiclk", "apb_pclk";
1154                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1155                 pinctrl-names = "default";
1156                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1157                 #address-cells = <1>;
1158                 #size-cells = <0>;
1159                 status = "disabled";
1160         };
1161
1162         uart4: serial@ff370000 {
1163                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1164                 reg = <0x0 0xff370000 0x0 0x100>;
1165                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1166                 clock-names = "baudclk", "apb_pclk";
1167                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1168                 reg-shift = <2>;
1169                 reg-io-width = <4>;
1170                 pinctrl-names = "default";
1171                 pinctrl-0 = <&uart4_xfer>;
1172                 status = "disabled";
1173         };
1174
1175         i2c4: i2c@ff3d0000 {
1176                 compatible = "rockchip,rk3399-i2c";
1177                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1178                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1179                 clock-names = "i2c", "pclk";
1180                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1181                 pinctrl-names = "default";
1182                 pinctrl-0 = <&i2c4_xfer>;
1183                 #address-cells = <1>;
1184                 #size-cells = <0>;
1185                 status = "disabled";
1186         };
1187
1188         i2c8: i2c@ff3e0000 {
1189                 compatible = "rockchip,rk3399-i2c";
1190                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1191                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1192                 clock-names = "i2c", "pclk";
1193                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1194                 pinctrl-names = "default";
1195                 pinctrl-0 = <&i2c8_xfer>;
1196                 #address-cells = <1>;
1197                 #size-cells = <0>;
1198                 status = "disabled";
1199         };
1200
1201         pcie_phy: phy@e220 {
1202                 compatible = "rockchip,rk3399-pcie-phy";
1203                 #phy-cells = <0>;
1204                 rockchip,grf = <&grf>;
1205                 clocks = <&cru SCLK_PCIEPHY_REF>;
1206                 clock-names = "refclk";
1207                 resets = <&cru SRST_PCIEPHY>;
1208                 reset-names = "phy";
1209                 status = "disabled";
1210         };
1211
1212         pcie0: pcie@f8000000 {
1213                 compatible = "rockchip,rk3399-pcie";
1214                 #address-cells = <3>;
1215                 #size-cells = <2>;
1216                 aspm-no-l0s;
1217                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1218                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1219                 clock-names = "aclk", "aclk-perf",
1220                               "hclk", "pm";
1221                 bus-range = <0x0 0x1>;
1222                 max-link-speed = <1>;
1223                 linux,pci-domain = <0>;
1224                 msi-map = <0x0 &its 0x0 0x1000>;
1225                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1226                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1227                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1228                 interrupt-names = "sys", "legacy", "client";
1229                 #interrupt-cells = <1>;
1230                 interrupt-map-mask = <0 0 0 7>;
1231                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1232                                 <0 0 0 2 &pcie0_intc 1>,
1233                                 <0 0 0 3 &pcie0_intc 2>,
1234                                 <0 0 0 4 &pcie0_intc 3>;
1235                 phys = <&pcie_phy>;
1236                 phy-names = "pcie-phy";
1237                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1238                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1239                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1240                       <0x0 0xfd000000 0x0 0x1000000>;
1241                 reg-names = "axi-base", "apb-base";
1242                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1243                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1244                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1245                          <&cru SRST_A_PCIE>;
1246                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1247                               "pm", "pclk", "aclk";
1248                 status = "disabled";
1249                 pcie0_intc: interrupt-controller {
1250                         interrupt-controller;
1251                         #address-cells = <0>;
1252                         #interrupt-cells = <1>;
1253                 };
1254         };
1255
1256         pwm0: pwm@ff420000 {
1257                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1258                 reg = <0x0 0xff420000 0x0 0x10>;
1259                 #pwm-cells = <3>;
1260                 pinctrl-names = "default";
1261                 pinctrl-0 = <&pwm0_pin>;
1262                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1263                 clock-names = "pwm";
1264                 status = "disabled";
1265         };
1266
1267         pwm1: pwm@ff420010 {
1268                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1269                 reg = <0x0 0xff420010 0x0 0x10>;
1270                 #pwm-cells = <3>;
1271                 pinctrl-names = "default";
1272                 pinctrl-0 = <&pwm1_pin>;
1273                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1274                 clock-names = "pwm";
1275                 status = "disabled";
1276         };
1277
1278         pwm2: pwm@ff420020 {
1279                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1280                 reg = <0x0 0xff420020 0x0 0x10>;
1281                 #pwm-cells = <3>;
1282                 pinctrl-names = "default";
1283                 pinctrl-0 = <&pwm2_pin>;
1284                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1285                 clock-names = "pwm";
1286                 status = "disabled";
1287         };
1288
1289         pwm3: pwm@ff420030 {
1290                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1291                 reg = <0x0 0xff420030 0x0 0x10>;
1292                 #pwm-cells = <3>;
1293                 pinctrl-names = "default";
1294                 pinctrl-0 = <&pwm3a_pin>;
1295                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1296                 clock-names = "pwm";
1297                 status = "disabled";
1298         };
1299
1300         dfi: dfi@ff630000 {
1301                 reg = <0x00 0xff630000 0x00 0x4000>;
1302                 compatible = "rockchip,rk3399-dfi";
1303                 rockchip,pmu = <&pmugrf>;
1304                 clocks = <&cru PCLK_DDR_MON>;
1305                 clock-names = "pclk_ddr_mon";
1306                 status = "disabled";
1307         };
1308
1309         dmc: dmc {
1310                 compatible = "rockchip,rk3399-dmc";
1311                 devfreq-events = <&dfi>;
1312                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1313                 clocks = <&cru SCLK_DDRCLK>;
1314                 clock-names = "dmc_clk";
1315                 ddr_timing = <&ddr_timing>;
1316                 status = "disabled";
1317         };
1318
1319         vpu: vpu_service@ff650000 {
1320                 compatible = "rockchip,vpu_service";
1321                 rockchip,grf = <&grf>;
1322                 iommus = <&vpu_mmu>;
1323                 iommu_enabled = <1>;
1324                 reg = <0x0 0xff650000 0x0 0x800>;
1325                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1326                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1327                 interrupt-names = "irq_dec", "irq_enc";
1328                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1329                 clock-names = "aclk_vcodec", "hclk_vcodec";
1330                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1331                 reset-names = "video_h", "video_a";
1332                 power-domains = <&power RK3399_PD_VCODEC>;
1333                 name = "vpu_service";
1334                 dev_mode = <0>;
1335                 /* 0 means ion, 1 means drm */
1336                 allocator = <1>;
1337                 status = "disabled";
1338         };
1339
1340         vpu_mmu: iommu@ff650800 {
1341                 compatible = "rockchip,iommu";
1342                 reg = <0x0 0xff650800 0x0 0x40>;
1343                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1344                 interrupt-names = "vpu_mmu";
1345                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1346                 clock-names = "aclk", "hclk";
1347                 power-domains = <&power RK3399_PD_VCODEC>;
1348                 #iommu-cells = <0>;
1349         };
1350
1351         rkvdec: rkvdec@ff660000 {
1352                 compatible = "rockchip,rkvdec";
1353                 rockchip,grf = <&grf>;
1354                 iommus = <&vdec_mmu>;
1355                 iommu_enabled = <1>;
1356                 reg = <0x0 0xff660000 0x0 0x400>;
1357                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1358                 interrupt-names = "irq_dec";
1359                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1360                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1361                 clock-names = "aclk_vcodec", "hclk_vcodec",
1362                               "clk_cabac", "clk_core";
1363                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1364                 reset-names = "video_h", "video_a";
1365                 power-domains = <&power RK3399_PD_VDU>;
1366                 dev_mode = <2>;
1367                 name = "rkvdec";
1368                 /* 0 means ion, 1 means drm */
1369                 allocator = <1>;
1370                 status = "disabled";
1371         };
1372
1373         vdec_mmu: iommu@ff660480 {
1374                 compatible = "rockchip,iommu";
1375                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1376                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1377                 interrupt-names = "vdec_mmu";
1378                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1379                 clock-names = "aclk", "hclk";
1380                 power-domains = <&power RK3399_PD_VDU>;
1381                 #iommu-cells = <0>;
1382         };
1383
1384         iep: iep@ff670000 {
1385                 compatible = "rockchip,iep";
1386                 iommu_enabled = <1>;
1387                 iommus = <&iep_mmu>;
1388                 reg = <0x0 0xff670000 0x0 0x800>;
1389                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1390                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1391                 clock-names = "aclk_iep", "hclk_iep";
1392                 power-domains = <&power RK3399_PD_IEP>;
1393                 allocator = <1>;
1394                 version = <2>;
1395                 status = "disabled";
1396         };
1397
1398         iep_mmu: iommu@ff670800 {
1399                 compatible = "rockchip,iommu";
1400                 reg = <0x0 0xff670800 0x0 0x40>;
1401                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1402                 interrupt-names = "iep_mmu";
1403                 #iommu-cells = <0>;
1404                 status = "disabled";
1405         };
1406
1407         rga: rga@ff680000 {
1408                 compatible = "rockchip,rk3399-rga";
1409                 reg = <0x0 0xff680000 0x0 0x10000>;
1410                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1411                 interrupt-names = "rga";
1412                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1413                 clock-names = "aclk", "hclk", "sclk";
1414                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1415                 reset-names = "core", "axi", "ahb";
1416                 power-domains = <&power RK3399_PD_RGA>;
1417                 status = "disabled";
1418         };
1419
1420         efuse0: efuse@ff690000 {
1421                 compatible = "rockchip,rk3399-efuse";
1422                 reg = <0x0 0xff690000 0x0 0x80>;
1423                 #address-cells = <1>;
1424                 #size-cells = <1>;
1425                 clocks = <&cru PCLK_EFUSE1024NS>;
1426                 clock-names = "pclk_efuse";
1427
1428                 /* Data cells */
1429                 efuse_id: id {
1430                         reg = <0x07 0x10>;
1431                 };
1432                 cpul_leakage: cpul-leakage {
1433                         reg = <0x1a 0x1>;
1434                 };
1435                 cpub_leakage: cpub-leakage {
1436                         reg = <0x17 0x1>;
1437                 };
1438                 gpu_leakage: gpu-leakage {
1439                         reg = <0x18 0x1>;
1440                 };
1441                 center_leakage: center-leakage {
1442                         reg = <0x19 0x1>;
1443                 };
1444                 logic_leakage: logic-leakage {
1445                         reg = <0x1b 0x1>;
1446                 };
1447                 wafer_info: wafer-info {
1448                         reg = <0x1c 0x1>;
1449                 };
1450         };
1451
1452         pmucru: pmu-clock-controller@ff750000 {
1453                 compatible = "rockchip,rk3399-pmucru";
1454                 reg = <0x0 0xff750000 0x0 0x1000>;
1455                 #clock-cells = <1>;
1456                 #reset-cells = <1>;
1457                 assigned-clocks = <&pmucru PLL_PPLL>;
1458                 assigned-clock-rates = <676000000>;
1459         };
1460
1461         cru: clock-controller@ff760000 {
1462                 compatible = "rockchip,rk3399-cru";
1463                 reg = <0x0 0xff760000 0x0 0x1000>;
1464                 #clock-cells = <1>;
1465                 #reset-cells = <1>;
1466                 assigned-clocks =
1467                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1468                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1469                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1470                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1471                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1472                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1473                         <&cru PCLK_PERIHP>,
1474                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1475                         <&cru PCLK_PERILP0>,
1476                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1477                 assigned-clock-rates =
1478                          <400000000>,  <200000000>,
1479                          <400000000>,  <200000000>,
1480                          <816000000>, <816000000>,
1481                          <594000000>,  <800000000>,
1482                          <200000000>, <1000000000>,
1483                          <150000000>,   <75000000>,
1484                           <37500000>,
1485                          <100000000>,  <100000000>,
1486                           <50000000>,
1487                          <100000000>,   <50000000>;
1488         };
1489
1490         grf: syscon@ff770000 {
1491                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1492                 reg = <0x0 0xff770000 0x0 0x10000>;
1493                 #address-cells = <1>;
1494                 #size-cells = <1>;
1495
1496                 io_domains: io-domains {
1497                         compatible = "rockchip,rk3399-io-voltage-domain";
1498                         status = "disabled";
1499                 };
1500
1501                 emmc_phy: phy@f780 {
1502                         compatible = "rockchip,rk3399-emmc-phy";
1503                         reg = <0xf780 0x24>;
1504                         clocks = <&sdhci>;
1505                         clock-names = "emmcclk";
1506                         #phy-cells = <0>;
1507                         status = "disabled";
1508                 };
1509
1510                 u2phy0: usb2-phy@e450 {
1511                         compatible = "rockchip,rk3399-usb2phy";
1512                         reg = <0xe450 0x10>;
1513                         clocks = <&cru SCLK_USB2PHY0_REF>;
1514                         clock-names = "phyclk";
1515                         #clock-cells = <0>;
1516                         clock-output-names = "clk_usbphy0_480m";
1517                         status = "disabled";
1518
1519                         u2phy0_otg: otg-port {
1520                                 #phy-cells = <0>;
1521                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1522                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1523                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1524                                 interrupt-names = "otg-bvalid", "otg-id",
1525                                                   "linestate";
1526                                 status = "disabled";
1527                         };
1528
1529                         u2phy0_host: host-port {
1530                                 #phy-cells = <0>;
1531                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1532                                 interrupt-names = "linestate";
1533                                 status = "disabled";
1534                         };
1535                 };
1536
1537                 u2phy1: usb2-phy@e460 {
1538                         compatible = "rockchip,rk3399-usb2phy";
1539                         reg = <0xe460 0x10>;
1540                         clocks = <&cru SCLK_USB2PHY1_REF>;
1541                         clock-names = "phyclk";
1542                         #clock-cells = <0>;
1543                         clock-output-names = "clk_usbphy1_480m";
1544                         status = "disabled";
1545
1546                         u2phy1_otg: otg-port {
1547                                 #phy-cells = <0>;
1548                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1549                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1550                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1551                                 interrupt-names = "otg-bvalid", "otg-id",
1552                                                   "linestate";
1553                                 status = "disabled";
1554                         };
1555
1556                         u2phy1_host: host-port {
1557                                 #phy-cells = <0>;
1558                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1559                                 interrupt-names = "linestate";
1560                                 status = "disabled";
1561                         };
1562                 };
1563
1564                 pvtm: pvtm {
1565                         compatible = "rockchip,rk3399-pvtm";
1566                         clocks = <&cru SCLK_PVTM_CORE_L>,
1567                                  <&cru SCLK_PVTM_CORE_B>,
1568                                  <&cru SCLK_PVTM_GPU>,
1569                                  <&cru SCLK_PVTM_DDR>;
1570                         clock-names = "core_l", "core_b", "gpu", "ddr";
1571                         status = "disabled";
1572                 };
1573         };
1574
1575         tcphy0: phy@ff7c0000 {
1576                 compatible = "rockchip,rk3399-typec-phy";
1577                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1578                 rockchip,grf = <&grf>;
1579                 #phy-cells = <1>;
1580                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1581                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1582                 clock-names = "tcpdcore", "tcpdphy-ref";
1583                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1584                 assigned-clock-rates = <50000000>;
1585                 power-domains = <&power RK3399_PD_TCPD0>;
1586                 resets = <&cru SRST_UPHY0>,
1587                          <&cru SRST_UPHY0_PIPE_L00>,
1588                          <&cru SRST_P_UPHY0_TCPHY>;
1589                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1590                 rockchip,typec-conn-dir = <0xe580 0 16>;
1591                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1592                 rockchip,usb3-host-disable = <0x2434 0 16>;
1593                 rockchip,usb3-host-port = <0x2434 12 28>;
1594                 rockchip,external-psm = <0xe588 14 30>;
1595                 rockchip,pipe-status = <0xe5c0 0 0>;
1596                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1597                 status = "disabled";
1598
1599                 tcphy0_dp: dp-port {
1600                         #phy-cells = <0>;
1601                 };
1602
1603                 tcphy0_usb3: usb3-port {
1604                         #phy-cells = <0>;
1605                 };
1606         };
1607
1608         tcphy1: phy@ff800000 {
1609                 compatible = "rockchip,rk3399-typec-phy";
1610                 reg = <0x0 0xff800000 0x0 0x40000>;
1611                 rockchip,grf = <&grf>;
1612                 #phy-cells = <1>;
1613                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1614                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1615                 clock-names = "tcpdcore", "tcpdphy-ref";
1616                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1617                 assigned-clock-rates = <50000000>;
1618                 power-domains = <&power RK3399_PD_TCPD1>;
1619                 resets = <&cru SRST_UPHY1>,
1620                          <&cru SRST_UPHY1_PIPE_L00>,
1621                          <&cru SRST_P_UPHY1_TCPHY>;
1622                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1623                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1624                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1625                 rockchip,usb3-host-disable = <0x2444 0 16>;
1626                 rockchip,usb3-host-port = <0x2444 12 28>;
1627                 rockchip,external-psm = <0xe594 14 30>;
1628                 rockchip,pipe-status = <0xe5c0 16 16>;
1629                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1630                 status = "disabled";
1631
1632                 tcphy1_dp: dp-port {
1633                         #phy-cells = <0>;
1634                 };
1635
1636                 tcphy1_usb3: usb3-port {
1637                         #phy-cells = <0>;
1638                 };
1639         };
1640
1641         watchdog@ff848000 {
1642                 compatible = "snps,dw-wdt";
1643                 reg = <0x0 0xff848000 0x0 0x100>;
1644                 clocks = <&cru PCLK_WDT>;
1645                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1646         };
1647
1648         rktimer: rktimer@ff850000 {
1649                 compatible = "rockchip,rk3399-timer";
1650                 reg = <0x0 0xff850000 0x0 0x1000>;
1651                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1652                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1653                 clock-names = "pclk", "timer";
1654         };
1655
1656         spdif: spdif@ff870000 {
1657                 compatible = "rockchip,rk3399-spdif";
1658                 reg = <0x0 0xff870000 0x0 0x1000>;
1659                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1660                 dmas = <&dmac_bus 7>;
1661                 dma-names = "tx";
1662                 clock-names = "mclk", "hclk";
1663                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1664                 pinctrl-names = "default";
1665                 pinctrl-0 = <&spdif_bus>;
1666                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1667                 status = "disabled";
1668         };
1669
1670         i2s0: i2s@ff880000 {
1671                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1672                 reg = <0x0 0xff880000 0x0 0x1000>;
1673                 rockchip,grf = <&grf>;
1674                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1675                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1676                 dma-names = "tx", "rx";
1677                 clock-names = "i2s_clk", "i2s_hclk";
1678                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1679                 pinctrl-names = "default";
1680                 pinctrl-0 = <&i2s0_8ch_bus>;
1681                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1682                 status = "disabled";
1683         };
1684
1685         i2s1: i2s@ff890000 {
1686                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1687                 reg = <0x0 0xff890000 0x0 0x1000>;
1688                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1689                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1690                 dma-names = "tx", "rx";
1691                 clock-names = "i2s_clk", "i2s_hclk";
1692                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1693                 pinctrl-names = "default";
1694                 pinctrl-0 = <&i2s1_2ch_bus>;
1695                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1696                 status = "disabled";
1697         };
1698
1699         i2s2: i2s@ff8a0000 {
1700                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1701                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1702                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1703                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1704                 dma-names = "tx", "rx";
1705                 clock-names = "i2s_clk", "i2s_hclk";
1706                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1707                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1708                 status = "disabled";
1709         };
1710
1711         gpu: gpu@ff9a0000 {
1712                 compatible = "arm,malit860",
1713                              "arm,malit86x",
1714                              "arm,malit8xx",
1715                              "arm,mali-midgard";
1716
1717                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1718
1719                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1720                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1721                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1722                 interrupt-names = "GPU", "JOB", "MMU";
1723
1724                 clocks = <&cru ACLK_GPU>;
1725                 clock-names = "clk_mali";
1726                 #cooling-cells = <2>; /* min followed by max */
1727                 power-domains = <&power RK3399_PD_GPU>;
1728                 power-off-delay-ms = <200>;
1729                 status = "disabled";
1730
1731                 gpu_power_model: power_model {
1732                         compatible = "arm,mali-simple-power-model";
1733                         voltage = <900>;
1734                         frequency = <500>;
1735                         static-power = <300>;
1736                         dynamic-power = <396>;
1737                         ts = <32000 4700 (-80) 2>;
1738                         thermal-zone = "gpu-thermal";
1739                 };
1740         };
1741
1742         vopl: vop@ff8f0000 {
1743                 compatible = "rockchip,rk3399-vop-lit";
1744                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1745                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1746                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1747                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1748                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1749                 reset-names = "axi", "ahb", "dclk";
1750                 power-domains = <&power RK3399_PD_VOPL>;
1751                 iommus = <&vopl_mmu>;
1752                 status = "disabled";
1753
1754                 vopl_out: port {
1755                         #address-cells = <1>;
1756                         #size-cells = <0>;
1757
1758                         vopl_out_mipi: endpoint@0 {
1759                                 reg = <0>;
1760                                 remote-endpoint = <&mipi_in_vopl>;
1761                         };
1762
1763                         vopl_out_edp: endpoint@1 {
1764                                 reg = <1>;
1765                                 remote-endpoint = <&edp_in_vopl>;
1766                         };
1767
1768                         vopl_out_hdmi: endpoint@2 {
1769                                 reg = <2>;
1770                                 remote-endpoint = <&hdmi_in_vopl>;
1771                         };
1772
1773                         vopl_out_dp: endpoint@3 {
1774                                 reg = <3>;
1775                                 remote-endpoint = <&dp_in_vopl>;
1776                         };
1777                 };
1778         };
1779
1780         vop1_pwm: voppwm@ff8f01a0 {
1781                 compatible = "rockchip,vop-pwm";
1782                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1783                 #pwm-cells = <3>;
1784                 pinctrl-names = "default";
1785                 pinctrl-0 = <&vop1_pwm_pin>;
1786                 clocks = <&cru SCLK_VOP1_PWM>;
1787                 clock-names = "pwm";
1788                 status = "disabled";
1789         };
1790
1791         vopl_mmu: iommu@ff8f3f00 {
1792                 compatible = "rockchip,iommu";
1793                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1794                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1795                 interrupt-names = "vopl_mmu";
1796                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1797                 clock-names = "aclk", "hclk";
1798                 power-domains = <&power RK3399_PD_VOPL>;
1799                 #iommu-cells = <0>;
1800                 status = "disabled";
1801         };
1802
1803         vopb: vop@ff900000 {
1804                 compatible = "rockchip,rk3399-vop-big";
1805                 reg = <0x0 0xff900000 0x0 0x3efc>;
1806                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1807                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1808                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1809                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1810                 reset-names = "axi", "ahb", "dclk";
1811                 power-domains = <&power RK3399_PD_VOPB>;
1812                 iommus = <&vopb_mmu>;
1813                 status = "disabled";
1814
1815                 vopb_out: port {
1816                         #address-cells = <1>;
1817                         #size-cells = <0>;
1818
1819                         vopb_out_edp: endpoint@0 {
1820                                 reg = <0>;
1821                                 remote-endpoint = <&edp_in_vopb>;
1822                         };
1823
1824                         vopb_out_mipi: endpoint@1 {
1825                                 reg = <1>;
1826                                 remote-endpoint = <&mipi_in_vopb>;
1827                         };
1828
1829                         vopb_out_hdmi: endpoint@2 {
1830                                 reg = <2>;
1831                                 remote-endpoint = <&hdmi_in_vopb>;
1832                         };
1833
1834                         vopb_out_dp: endpoint@3 {
1835                                 reg = <3>;
1836                                 remote-endpoint = <&dp_in_vopb>;
1837                         };
1838                 };
1839         };
1840
1841         vop0_pwm: voppwm@ff9001a0 {
1842                 compatible = "rockchip,vop-pwm";
1843                 reg = <0x0 0xff9001a0 0x0 0x10>;
1844                 #pwm-cells = <3>;
1845                 pinctrl-names = "default";
1846                 pinctrl-0 = <&vop0_pwm_pin>;
1847                 clocks = <&cru SCLK_VOP0_PWM>;
1848                 clock-names = "pwm";
1849                 status = "disabled";
1850         };
1851
1852         vopb_mmu: iommu@ff903f00 {
1853                 compatible = "rockchip,iommu";
1854                 reg = <0x0 0xff903f00 0x0 0x100>;
1855                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1856                 interrupt-names = "vopb_mmu";
1857                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1858                 clock-names = "aclk", "hclk";
1859                 power-domains = <&power RK3399_PD_VOPB>;
1860                 #iommu-cells = <0>;
1861                 status = "disabled";
1862         };
1863
1864         isp0_mmu: iommu@ff914000 {
1865                 compatible = "rockchip,iommu";
1866                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1867                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1868                 interrupt-names = "isp0_mmu";
1869                 #iommu-cells = <0>;
1870                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1871                 clock-names = "aclk", "hclk";
1872                 power-domains = <&power RK3399_PD_ISP0>;
1873                 rk_iommu,disable_reset_quirk;
1874                 status = "disabled";
1875         };
1876
1877         isp1_mmu: iommu@ff924000 {
1878                 compatible = "rockchip,iommu";
1879                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1880                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1881                 interrupt-names = "isp1_mmu";
1882                 #iommu-cells = <0>;
1883                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1884                 clock-names = "aclk", "hclk";
1885                 power-domains = <&power RK3399_PD_ISP1>;
1886                 rk_iommu,disable_reset_quirk;
1887                 status = "disabled";
1888         };
1889
1890         hdmi: hdmi@ff940000 {
1891                 compatible = "rockchip,rk3399-dw-hdmi";
1892                 reg = <0x0 0xff940000 0x0 0x20000>;
1893                 reg-io-width = <4>;
1894                 rockchip,grf = <&grf>;
1895                 pinctrl-names = "default";
1896                 pinctrl-0 = <&hdmi_i2c_xfer>;
1897                 power-domains = <&power RK3399_PD_HDCP>;
1898                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1899                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1900                 clock-names = "iahb", "isfr", "vpll", "grf";
1901                 status = "disabled";
1902
1903                 ports {
1904                         hdmi_in: port {
1905                                 #address-cells = <1>;
1906                                 #size-cells = <0>;
1907                                 hdmi_in_vopb: endpoint@0 {
1908                                         reg = <0>;
1909                                         remote-endpoint = <&vopb_out_hdmi>;
1910                                 };
1911                                 hdmi_in_vopl: endpoint@1 {
1912                                         reg = <1>;
1913                                         remote-endpoint = <&vopl_out_hdmi>;
1914                                 };
1915                         };
1916                 };
1917         };
1918
1919         mipi_dsi: mipi@ff960000 {
1920                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1921                 reg = <0x0 0xff960000 0x0 0x8000>;
1922                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1923                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1924                          <&cru SCLK_DPHY_TX0_CFG>;
1925                 clock-names = "ref", "pclk", "phy_cfg";
1926                 power-domains = <&power RK3399_PD_VIO>;
1927                 rockchip,grf = <&grf>;
1928                 #address-cells = <1>;
1929                 #size-cells = <0>;
1930                 status = "disabled";
1931
1932                 ports {
1933                         #address-cells = <1>;
1934                         #size-cells = <0>;
1935                         reg = <1>;
1936
1937                         mipi_in: port {
1938                                 #address-cells = <1>;
1939                                 #size-cells = <0>;
1940
1941                                 mipi_in_vopb: endpoint@0 {
1942                                         reg = <0>;
1943                                         remote-endpoint = <&vopb_out_mipi>;
1944                                 };
1945                                 mipi_in_vopl: endpoint@1 {
1946                                         reg = <1>;
1947                                         remote-endpoint = <&vopl_out_mipi>;
1948                                 };
1949                         };
1950                 };
1951         };
1952
1953         edp: edp@ff970000 {
1954                 compatible = "rockchip,rk3399-edp";
1955                 reg = <0x0 0xff970000 0x0 0x8000>;
1956                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1957                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1958                 clock-names = "dp", "pclk";
1959                 power-domains = <&power RK3399_PD_EDP>;
1960                 resets = <&cru SRST_P_EDP_CTRL>;
1961                 reset-names = "dp";
1962                 rockchip,grf = <&grf>;
1963                 status = "disabled";
1964                 pinctrl-names = "default";
1965                 pinctrl-0 = <&edp_hpd>;
1966
1967                 ports {
1968                         #address-cells = <1>;
1969                         #size-cells = <0>;
1970
1971                         edp_in: port@0 {
1972                                 reg = <0>;
1973                                 #address-cells = <1>;
1974                                 #size-cells = <0>;
1975
1976                                 edp_in_vopb: endpoint@0 {
1977                                         reg = <0>;
1978                                         remote-endpoint = <&vopb_out_edp>;
1979                                 };
1980
1981                                 edp_in_vopl: endpoint@1 {
1982                                         reg = <1>;
1983                                         remote-endpoint = <&vopl_out_edp>;
1984                                 };
1985                         };
1986                 };
1987         };
1988
1989         display_subsystem: display-subsystem {
1990                 compatible = "rockchip,display-subsystem";
1991                 ports = <&vopl_out>, <&vopb_out>;
1992                 status = "disabled";
1993         };
1994
1995         pinctrl: pinctrl {
1996                 compatible = "rockchip,rk3399-pinctrl";
1997                 rockchip,grf = <&grf>;
1998                 rockchip,pmu = <&pmugrf>;
1999                 #address-cells = <0x2>;
2000                 #size-cells = <0x2>;
2001                 ranges;
2002
2003                 gpio0: gpio0@ff720000 {
2004                         compatible = "rockchip,gpio-bank";
2005                         reg = <0x0 0xff720000 0x0 0x100>;
2006                         clocks = <&pmucru PCLK_GPIO0_PMU>;
2007                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
2008
2009                         gpio-controller;
2010                         #gpio-cells = <0x2>;
2011
2012                         interrupt-controller;
2013                         #interrupt-cells = <0x2>;
2014                 };
2015
2016                 gpio1: gpio1@ff730000 {
2017                         compatible = "rockchip,gpio-bank";
2018                         reg = <0x0 0xff730000 0x0 0x100>;
2019                         clocks = <&pmucru PCLK_GPIO1_PMU>;
2020                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
2021
2022                         gpio-controller;
2023                         #gpio-cells = <0x2>;
2024
2025                         interrupt-controller;
2026                         #interrupt-cells = <0x2>;
2027                 };
2028
2029                 gpio2: gpio2@ff780000 {
2030                         compatible = "rockchip,gpio-bank";
2031                         reg = <0x0 0xff780000 0x0 0x100>;
2032                         clocks = <&cru PCLK_GPIO2>;
2033                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2034
2035                         gpio-controller;
2036                         #gpio-cells = <0x2>;
2037
2038                         interrupt-controller;
2039                         #interrupt-cells = <0x2>;
2040                 };
2041
2042                 gpio3: gpio3@ff788000 {
2043                         compatible = "rockchip,gpio-bank";
2044                         reg = <0x0 0xff788000 0x0 0x100>;
2045                         clocks = <&cru PCLK_GPIO3>;
2046                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2047
2048                         gpio-controller;
2049                         #gpio-cells = <0x2>;
2050
2051                         interrupt-controller;
2052                         #interrupt-cells = <0x2>;
2053                 };
2054
2055                 gpio4: gpio4@ff790000 {
2056                         compatible = "rockchip,gpio-bank";
2057                         reg = <0x0 0xff790000 0x0 0x100>;
2058                         clocks = <&cru PCLK_GPIO4>;
2059                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2060
2061                         gpio-controller;
2062                         #gpio-cells = <0x2>;
2063
2064                         interrupt-controller;
2065                         #interrupt-cells = <0x2>;
2066                 };
2067
2068                 pcfg_pull_up: pcfg-pull-up {
2069                         bias-pull-up;
2070                 };
2071
2072                 pcfg_pull_down: pcfg-pull-down {
2073                         bias-pull-down;
2074                 };
2075
2076                 pcfg_pull_none: pcfg-pull-none {
2077                         bias-disable;
2078                 };
2079
2080                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2081                         bias-pull-up;
2082                         drive-strength = <20>;
2083                 };
2084
2085                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2086                         bias-disable;
2087                         drive-strength = <20>;
2088                 };
2089
2090                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2091                         bias-disable;
2092                         drive-strength = <18>;
2093                 };
2094
2095                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2096                         bias-disable;
2097                         drive-strength = <12>;
2098                 };
2099
2100                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2101                         bias-pull-up;
2102                         drive-strength = <8>;
2103                 };
2104
2105                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2106                         bias-pull-down;
2107                         drive-strength = <4>;
2108                 };
2109
2110                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2111                         bias-pull-up;
2112                         drive-strength = <2>;
2113                 };
2114
2115                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2116                         bias-pull-down;
2117                         drive-strength = <12>;
2118                 };
2119
2120                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2121                         bias-disable;
2122                         drive-strength = <13>;
2123                 };
2124
2125                 pcfg_output_high: pcfg-output-high {
2126                         output-high;
2127                 };
2128
2129                 pcfg_output_low: pcfg-output-low {
2130                         output-low;
2131                 };
2132
2133                 pcfg_input: pcfg-input {
2134                         input-enable;
2135                 };
2136
2137                 emmc {
2138                         emmc_pwr: emmc-pwr {
2139                                 rockchip,pins =
2140                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2141                         };
2142                 };
2143
2144                 gmac {
2145                         rgmii_pins: rgmii-pins {
2146                                 rockchip,pins =
2147                                         /* mac_txclk */
2148                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2149                                         /* mac_rxclk */
2150                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2151                                         /* mac_mdio */
2152                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2153                                         /* mac_txen */
2154                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2155                                         /* mac_clk */
2156                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2157                                         /* mac_rxdv */
2158                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2159                                         /* mac_mdc */
2160                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2161                                         /* mac_rxd1 */
2162                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2163                                         /* mac_rxd0 */
2164                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2165                                         /* mac_txd1 */
2166                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2167                                         /* mac_txd0 */
2168                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2169                                         /* mac_rxd3 */
2170                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2171                                         /* mac_rxd2 */
2172                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2173                                         /* mac_txd3 */
2174                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2175                                         /* mac_txd2 */
2176                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2177                         };
2178
2179                         rmii_pins: rmii-pins {
2180                                 rockchip,pins =
2181                                         /* mac_mdio */
2182                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2183                                         /* mac_txen */
2184                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2185                                         /* mac_clk */
2186                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2187                                         /* mac_rxer */
2188                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2189                                         /* mac_rxdv */
2190                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2191                                         /* mac_mdc */
2192                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2193                                         /* mac_rxd1 */
2194                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2195                                         /* mac_rxd0 */
2196                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2197                                         /* mac_txd1 */
2198                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2199                                         /* mac_txd0 */
2200                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2201                         };
2202                 };
2203
2204                 i2c0 {
2205                         i2c0_xfer: i2c0-xfer {
2206                                 rockchip,pins =
2207                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2208                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2209                         };
2210                 };
2211
2212                 i2c1 {
2213                         i2c1_xfer: i2c1-xfer {
2214                                 rockchip,pins =
2215                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2216                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2217                         };
2218                 };
2219
2220                 i2c2 {
2221                         i2c2_xfer: i2c2-xfer {
2222                                 rockchip,pins =
2223                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2224                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2225                         };
2226                 };
2227
2228                 i2c3 {
2229                         i2c3_xfer: i2c3-xfer {
2230                                 rockchip,pins =
2231                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2232                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2233                         };
2234
2235                         i2c3_gpio: i2c3_gpio {
2236                                 rockchip,pins =
2237                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2238                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2239                         };
2240
2241                 };
2242
2243                 i2c4 {
2244                         i2c4_xfer: i2c4-xfer {
2245                                 rockchip,pins =
2246                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2247                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2248                         };
2249                 };
2250
2251                 i2c5 {
2252                         i2c5_xfer: i2c5-xfer {
2253                                 rockchip,pins =
2254                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2255                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2256                         };
2257                 };
2258
2259                 i2c6 {
2260                         i2c6_xfer: i2c6-xfer {
2261                                 rockchip,pins =
2262                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2263                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2264                         };
2265                 };
2266
2267                 i2c7 {
2268                         i2c7_xfer: i2c7-xfer {
2269                                 rockchip,pins =
2270                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2271                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2272                         };
2273                 };
2274
2275                 i2c8 {
2276                         i2c8_xfer: i2c8-xfer {
2277                                 rockchip,pins =
2278                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2279                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2280                         };
2281                 };
2282
2283                 i2s0 {
2284                         i2s0_8ch_bus: i2s0-8ch-bus {
2285                                 rockchip,pins =
2286                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2287                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2288                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2289                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2290                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2291                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2292                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2293                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2294                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2295                         };
2296                 };
2297
2298                 i2s1 {
2299                         i2s1_2ch_bus: i2s1-2ch-bus {
2300                                 rockchip,pins =
2301                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2302                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2303                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2304                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2305                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2306                         };
2307                 };
2308
2309                 sdio0 {
2310                         sdio0_bus1: sdio0-bus1 {
2311                                 rockchip,pins =
2312                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2313                         };
2314
2315                         sdio0_bus4: sdio0-bus4 {
2316                                 rockchip,pins =
2317                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2318                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2319                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2320                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2321                         };
2322
2323                         sdio0_cmd: sdio0-cmd {
2324                                 rockchip,pins =
2325                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2326                         };
2327
2328                         sdio0_clk: sdio0-clk {
2329                                 rockchip,pins =
2330                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2331                         };
2332
2333                         sdio0_cd: sdio0-cd {
2334                                 rockchip,pins =
2335                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2336                         };
2337
2338                         sdio0_pwr: sdio0-pwr {
2339                                 rockchip,pins =
2340                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2341                         };
2342
2343                         sdio0_bkpwr: sdio0-bkpwr {
2344                                 rockchip,pins =
2345                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2346                         };
2347
2348                         sdio0_wp: sdio0-wp {
2349                                 rockchip,pins =
2350                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2351                         };
2352
2353                         sdio0_int: sdio0-int {
2354                                 rockchip,pins =
2355                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2356                         };
2357                 };
2358
2359                 sdmmc {
2360                         sdmmc_bus1: sdmmc-bus1 {
2361                                 rockchip,pins =
2362                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2363                         };
2364
2365                         sdmmc_bus4: sdmmc-bus4 {
2366                                 rockchip,pins =
2367                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2368                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2369                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2370                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2371                         };
2372
2373                         sdmmc_clk: sdmmc-clk {
2374                                 rockchip,pins =
2375                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2376                         };
2377
2378                         sdmmc_cmd: sdmmc-cmd {
2379                                 rockchip,pins =
2380                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2381                         };
2382
2383                         sdmmc_cd: sdmcc-cd {
2384                                 rockchip,pins =
2385                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2386                         };
2387
2388                         sdmmc_wp: sdmmc-wp {
2389                                 rockchip,pins =
2390                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2391                         };
2392                 };
2393
2394                 spdif {
2395                         spdif_bus: spdif-bus {
2396                                 rockchip,pins =
2397                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2398                         };
2399
2400                         spdif_bus_1: spdif-bus-1 {
2401                                 rockchip,pins =
2402                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2403                         };
2404                 };
2405
2406                 spi0 {
2407                         spi0_clk: spi0-clk {
2408                                 rockchip,pins =
2409                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2410                         };
2411                         spi0_cs0: spi0-cs0 {
2412                                 rockchip,pins =
2413                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2414                         };
2415                         spi0_cs1: spi0-cs1 {
2416                                 rockchip,pins =
2417                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2418                         };
2419                         spi0_tx: spi0-tx {
2420                                 rockchip,pins =
2421                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2422                         };
2423                         spi0_rx: spi0-rx {
2424                                 rockchip,pins =
2425                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2426                         };
2427                 };
2428
2429                 spi1 {
2430                         spi1_clk: spi1-clk {
2431                                 rockchip,pins =
2432                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2433                         };
2434                         spi1_cs0: spi1-cs0 {
2435                                 rockchip,pins =
2436                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2437                         };
2438                         spi1_rx: spi1-rx {
2439                                 rockchip,pins =
2440                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2441                         };
2442                         spi1_tx: spi1-tx {
2443                                 rockchip,pins =
2444                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2445                         };
2446                 };
2447
2448                 spi2 {
2449                         spi2_clk: spi2-clk {
2450                                 rockchip,pins =
2451                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2452                         };
2453                         spi2_cs0: spi2-cs0 {
2454                                 rockchip,pins =
2455                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2456                         };
2457                         spi2_rx: spi2-rx {
2458                                 rockchip,pins =
2459                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2460                         };
2461                         spi2_tx: spi2-tx {
2462                                 rockchip,pins =
2463                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2464                         };
2465                 };
2466
2467                 spi3 {
2468                         spi3_clk: spi3-clk {
2469                                 rockchip,pins =
2470                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2471                         };
2472                         spi3_cs0: spi3-cs0 {
2473                                 rockchip,pins =
2474                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2475                         };
2476                         spi3_rx: spi3-rx {
2477                                 rockchip,pins =
2478                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2479                         };
2480                         spi3_tx: spi3-tx {
2481                                 rockchip,pins =
2482                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2483                         };
2484                 };
2485
2486                 spi4 {
2487                         spi4_clk: spi4-clk {
2488                                 rockchip,pins =
2489                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2490                         };
2491                         spi4_cs0: spi4-cs0 {
2492                                 rockchip,pins =
2493                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2494                         };
2495                         spi4_rx: spi4-rx {
2496                                 rockchip,pins =
2497                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2498                         };
2499                         spi4_tx: spi4-tx {
2500                                 rockchip,pins =
2501                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2502                         };
2503                 };
2504
2505                 spi5 {
2506                         spi5_clk: spi5-clk {
2507                                 rockchip,pins =
2508                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2509                         };
2510                         spi5_cs0: spi5-cs0 {
2511                                 rockchip,pins =
2512                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2513                         };
2514                         spi5_rx: spi5-rx {
2515                                 rockchip,pins =
2516                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2517                         };
2518                         spi5_tx: spi5-tx {
2519                                 rockchip,pins =
2520                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2521                         };
2522                 };
2523
2524                 tsadc {
2525                         otp_gpio: otp-gpio {
2526                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2527                         };
2528
2529                         otp_out: otp-out {
2530                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2531                         };
2532                 };
2533
2534                 uart0 {
2535                         uart0_xfer: uart0-xfer {
2536                                 rockchip,pins =
2537                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2538                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2539                         };
2540
2541                         uart0_cts: uart0-cts {
2542                                 rockchip,pins =
2543                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2544                         };
2545
2546                         uart0_rts: uart0-rts {
2547                                 rockchip,pins =
2548                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2549                         };
2550                 };
2551
2552                 uart1 {
2553                         uart1_xfer: uart1-xfer {
2554                                 rockchip,pins =
2555                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2556                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2557                         };
2558                 };
2559
2560                 uart2a {
2561                         uart2a_xfer: uart2a-xfer {
2562                                 rockchip,pins =
2563                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2564                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2565                         };
2566                 };
2567
2568                 uart2b {
2569                         uart2b_xfer: uart2b-xfer {
2570                                 rockchip,pins =
2571                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2572                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2573                         };
2574                 };
2575
2576                 uart2c {
2577                         uart2c_xfer: uart2c-xfer {
2578                                 rockchip,pins =
2579                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2580                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2581                         };
2582                 };
2583
2584                 uart3 {
2585                         uart3_xfer: uart3-xfer {
2586                                 rockchip,pins =
2587                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2588                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2589                         };
2590
2591                         uart3_cts: uart3-cts {
2592                                 rockchip,pins =
2593                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2594                         };
2595
2596                         uart3_rts: uart3-rts {
2597                                 rockchip,pins =
2598                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2599                         };
2600                 };
2601
2602                 uart4 {
2603                         uart4_xfer: uart4-xfer {
2604                                 rockchip,pins =
2605                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2606                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2607                         };
2608                 };
2609
2610                 uarthdcp {
2611                         uarthdcp_xfer: uarthdcp-xfer {
2612                                 rockchip,pins =
2613                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2614                                         <4 22 RK_FUNC_2 &pcfg_pull_none>;
2615                         };
2616                 };
2617
2618                 pwm0 {
2619                         pwm0_pin: pwm0-pin {
2620                                 rockchip,pins =
2621                                         <4 18 RK_FUNC_1 &pcfg_pull_none>;
2622                         };
2623
2624                         vop0_pwm_pin: vop0-pwm-pin {
2625                                 rockchip,pins =
2626                                         <4 18 RK_FUNC_2 &pcfg_pull_none>;
2627                         };
2628                 };
2629
2630                 pwm1 {
2631                         pwm1_pin: pwm1-pin {
2632                                 rockchip,pins =
2633                                         <4 22 RK_FUNC_1 &pcfg_pull_none>;
2634                         };
2635
2636                         vop1_pwm_pin: vop1-pwm-pin {
2637                                 rockchip,pins =
2638                                         <4 18 RK_FUNC_3 &pcfg_pull_none>;
2639                         };
2640                 };
2641
2642                 pwm2 {
2643                         pwm2_pin: pwm2-pin {
2644                                 rockchip,pins =
2645                                         <1 19 RK_FUNC_1 &pcfg_pull_none>;
2646                         };
2647                 };
2648
2649                 pwm3a {
2650                         pwm3a_pin: pwm3a-pin {
2651                                 rockchip,pins =
2652                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
2653                         };
2654                 };
2655
2656                 pwm3b {
2657                         pwm3b_pin: pwm3b-pin {
2658                                 rockchip,pins =
2659                                         <1 14 RK_FUNC_1 &pcfg_pull_none>;
2660                         };
2661                 };
2662
2663                 edp {
2664                         edp_hpd: edp-hpd {
2665                                 rockchip,pins =
2666                                         <4 23 RK_FUNC_2 &pcfg_pull_none>;
2667                         };
2668                 };
2669
2670                 hdmi {
2671                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2672                                 rockchip,pins =
2673                                         <4 17 RK_FUNC_3 &pcfg_pull_none>,
2674                                         <4 16 RK_FUNC_3 &pcfg_pull_none>;
2675                         };
2676
2677                         hdmi_cec: hdmi-cec {
2678                                 rockchip,pins =
2679                                         <4 23 RK_FUNC_1 &pcfg_pull_none>;
2680                         };
2681                 };
2682
2683                 pcie {
2684                         pcie_clkreqn: pci-clkreqn {
2685                                 rockchip,pins =
2686                                         <2 26 RK_FUNC_2 &pcfg_pull_none>;
2687                         };
2688
2689                         pcie_clkreqnb: pci-clkreqnb {
2690                                 rockchip,pins =
2691                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
2692                         };
2693
2694                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2695                                 /*
2696                                  * Since our pcie doesn't support
2697                                  * ClockPM(CPM), we want to hack this as
2698                                  * gpio, so the EP could be able to
2699                                  * de-assert it along and make ClockPM(CPM)
2700                                  * work.
2701                                  */
2702                                 rockchip,pins =
2703                                         <2 26 RK_FUNC_GPIO &pcfg_pull_none>;
2704                         };
2705
2706                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2707                                 rockchip,pins =
2708                                         <4 24 RK_FUNC_GPIO &pcfg_pull_none>;
2709                         };
2710                 };
2711         };
2712
2713         rockchip_suspend: rockchip-suspend {
2714                 compatible = "rockchip,pm-rk3399";
2715                 status = "disabled";
2716                 rockchip,sleep-debug-en = <0>;
2717                 rockchip,virtual-poweroff = <0>;
2718                 rockchip,sleep-mode-config = <
2719                         (0
2720                         | RKPM_SLP_ARMPD
2721                         | RKPM_SLP_PERILPPD
2722                         | RKPM_SLP_DDR_RET
2723                         | RKPM_SLP_PLLPD
2724                         | RKPM_SLP_OSC_DIS
2725                         | RKPM_SLP_CENTER_PD
2726                         | RKPM_SLP_AP_PWROFF
2727                         )
2728                 >;
2729                 rockchip,wakeup-config = <
2730                         (0
2731                         | RKPM_GPIO_WKUP_EN
2732                         )
2733                 >;
2734         };
2735 };