2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3399-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3399-power.h>
49 #include <dt-bindings/soc/rockchip_boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
52 #include "rk3399-dram-default-timing.dtsi"
55 compatible = "rockchip,rk3399";
57 interrupt-parent = <&gic>;
79 compatible = "arm,psci-1.0";
115 compatible = "arm,cortex-a53", "arm,armv8";
117 enable-method = "psci";
118 #cooling-cells = <2>; /* min followed by max */
119 dynamic-power-coefficient = <100>;
120 clocks = <&cru ARMCLKL>;
121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
122 operating-points-v2 = <&cluster0_opp>;
123 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
128 compatible = "arm,cortex-a53", "arm,armv8";
130 enable-method = "psci";
131 clocks = <&cru ARMCLKL>;
132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
133 operating-points-v2 = <&cluster0_opp>;
134 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
144 operating-points-v2 = <&cluster0_opp>;
145 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
150 compatible = "arm,cortex-a53", "arm,armv8";
152 enable-method = "psci";
153 clocks = <&cru ARMCLKL>;
154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
155 operating-points-v2 = <&cluster0_opp>;
156 sched-energy-costs = <&CPU_COST_A53 &CLUSTER_COST_A53>;
161 compatible = "arm,cortex-a72", "arm,armv8";
163 enable-method = "psci";
164 #cooling-cells = <2>; /* min followed by max */
165 dynamic-power-coefficient = <436>;
166 clocks = <&cru ARMCLKB>;
167 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
168 operating-points-v2 = <&cluster1_opp>;
169 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
174 compatible = "arm,cortex-a72", "arm,armv8";
176 enable-method = "psci";
177 clocks = <&cru ARMCLKB>;
178 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
179 operating-points-v2 = <&cluster1_opp>;
180 sched-energy-costs = <&CPU_COST_A72 &CLUSTER_COST_A72>;
184 entry-method = "psci";
186 CPU_SLEEP: cpu-sleep {
187 compatible = "arm,idle-state";
189 arm,psci-suspend-param = <0x0010000>;
190 entry-latency-us = <120>;
191 exit-latency-us = <250>;
192 min-residency-us = <900>;
195 CLUSTER_SLEEP: cluster-sleep {
196 compatible = "arm,idle-state";
198 arm,psci-suspend-param = <0x1010000>;
199 entry-latency-us = <400>;
200 exit-latency-us = <500>;
201 min-residency-us = <2000>;
205 /include/ "rk3399-sched-energy.dtsi"
209 cluster0_opp: opp_table0 {
210 compatible = "operating-points-v2";
214 opp-hz = /bits/ 64 <408000000>;
215 opp-microvolt = <800000>;
216 clock-latency-ns = <40000>;
219 opp-hz = /bits/ 64 <600000000>;
220 opp-microvolt = <800000>;
223 opp-hz = /bits/ 64 <816000000>;
224 opp-microvolt = <800000>;
227 opp-hz = /bits/ 64 <1008000000>;
228 opp-microvolt = <875000>;
231 opp-hz = /bits/ 64 <1200000000>;
232 opp-microvolt = <925000>;
235 opp-hz = /bits/ 64 <1416000000>;
236 opp-microvolt = <1025000>;
240 cluster1_opp: opp_table1 {
241 compatible = "operating-points-v2";
245 opp-hz = /bits/ 64 <408000000>;
246 opp-microvolt = <800000>;
247 clock-latency-ns = <40000>;
250 opp-hz = /bits/ 64 <600000000>;
251 opp-microvolt = <800000>;
254 opp-hz = /bits/ 64 <816000000>;
255 opp-microvolt = <800000>;
258 opp-hz = /bits/ 64 <1008000000>;
259 opp-microvolt = <850000>;
262 opp-hz = /bits/ 64 <1200000000>;
263 opp-microvolt = <925000>;
270 min-volt = <800000>; /* uV */
271 min-freq = <408000>; /* KHz */
272 leakage-adjust-volt = <
276 nvmem-cells = <&cpul_leakage>;
277 nvmem-cell-names = "cpu_leakage";
281 min-volt = <800000>; /* uV */
282 min-freq = <408000>; /* KHz */
283 leakage-adjust-volt = <
287 nvmem-cells = <&cpub_leakage>;
288 nvmem-cell-names = "cpu_leakage";
293 compatible = "arm,armv8-timer";
294 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
295 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
296 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
297 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
301 compatible = "arm,cortex-a53-pmu";
302 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part0>;
306 compatible = "arm,cortex-a72-pmu";
307 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &part1>;
311 compatible = "fixed-clock";
313 clock-frequency = <24000000>;
314 clock-output-names = "xin24m";
318 compatible = "arm,amba-bus";
319 #address-cells = <2>;
323 dmac_bus: dma-controller@ff6d0000 {
324 compatible = "arm,pl330", "arm,primecell";
325 reg = <0x0 0xff6d0000 0x0 0x4000>;
326 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
327 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
329 clocks = <&cru ACLK_DMAC0_PERILP>;
330 clock-names = "apb_pclk";
331 peripherals-req-type-burst;
334 dmac_peri: dma-controller@ff6e0000 {
335 compatible = "arm,pl330", "arm,primecell";
336 reg = <0x0 0xff6e0000 0x0 0x4000>;
337 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
338 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
340 clocks = <&cru ACLK_DMAC1_PERILP>;
341 clock-names = "apb_pclk";
342 peripherals-req-type-burst;
347 compatible = "rockchip,rk3399-gmac";
348 reg = <0x0 0xfe300000 0x0 0x10000>;
349 rockchip,grf = <&grf>;
350 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
351 interrupt-names = "macirq";
352 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
353 <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
354 <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
356 clock-names = "stmmaceth", "mac_clk_rx",
357 "mac_clk_tx", "clk_mac_ref",
358 "clk_mac_refout", "aclk_mac",
360 resets = <&cru SRST_A_GMAC>;
361 reset-names = "stmmaceth";
362 power-domains = <&power RK3399_PD_GMAC>;
366 sdio0: dwmmc@fe310000 {
367 compatible = "rockchip,rk3399-dw-mshc",
368 "rockchip,rk3288-dw-mshc";
369 reg = <0x0 0xfe310000 0x0 0x4000>;
370 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
371 clock-freq-min-max = <400000 150000000>;
372 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
373 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
374 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
375 fifo-depth = <0x100>;
376 power-domains = <&power RK3399_PD_SDIOAUDIO>;
380 sdmmc: dwmmc@fe320000 {
381 compatible = "rockchip,rk3399-dw-mshc",
382 "rockchip,rk3288-dw-mshc";
383 reg = <0x0 0xfe320000 0x0 0x4000>;
384 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
385 clock-freq-min-max = <400000 150000000>;
386 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
387 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
388 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
389 fifo-depth = <0x100>;
390 power-domains = <&power RK3399_PD_SD>;
394 sdhci: sdhci@fe330000 {
395 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
396 reg = <0x0 0xfe330000 0x0 0x10000>;
397 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
398 arasan,soc-ctl-syscon = <&grf>;
399 assigned-clocks = <&cru SCLK_EMMC>;
400 assigned-clock-rates = <200000000>;
401 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
402 clock-names = "clk_xin", "clk_ahb";
403 clock-output-names = "emmc_cardclock";
406 phy-names = "phy_arasan";
407 power-domains = <&power RK3399_PD_EMMC>;
411 usb_host0_ehci: usb@fe380000 {
412 compatible = "generic-ehci";
413 reg = <0x0 0xfe380000 0x0 0x20000>;
414 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
415 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
416 <&cru SCLK_USBPHY0_480M_SRC>;
417 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
418 phys = <&u2phy0_host>;
420 power-domains = <&power RK3399_PD_PERIHP>;
424 usb_host0_ohci: usb@fe3a0000 {
425 compatible = "generic-ohci";
426 reg = <0x0 0xfe3a0000 0x0 0x20000>;
427 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
428 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
429 <&cru SCLK_USBPHY0_480M_SRC>;
430 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
431 phys = <&u2phy0_host>;
433 power-domains = <&power RK3399_PD_PERIHP>;
437 usb_host1_ehci: usb@fe3c0000 {
438 compatible = "generic-ehci";
439 reg = <0x0 0xfe3c0000 0x0 0x20000>;
440 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
441 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
442 <&cru SCLK_USBPHY1_480M_SRC>;
443 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
444 phys = <&u2phy1_host>;
446 power-domains = <&power RK3399_PD_PERIHP>;
450 usb_host1_ohci: usb@fe3e0000 {
451 compatible = "generic-ohci";
452 reg = <0x0 0xfe3e0000 0x0 0x20000>;
453 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
454 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
455 <&cru SCLK_USBPHY1_480M_SRC>;
456 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
457 phys = <&u2phy1_host>;
459 power-domains = <&power RK3399_PD_PERIHP>;
463 usbdrd3_0: usb@fe800000 {
464 compatible = "rockchip,rk3399-dwc3";
465 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
466 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
467 clock-names = "ref_clk", "suspend_clk",
468 "bus_clk", "grf_clk";
469 power-domains = <&power RK3399_PD_USB3>;
470 resets = <&cru SRST_A_USB3_OTG0>;
471 reset-names = "usb3-otg";
472 #address-cells = <2>;
476 usbdrd_dwc3_0: dwc3@fe800000 {
477 compatible = "snps,dwc3";
478 reg = <0x0 0xfe800000 0x0 0x100000>;
479 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
481 phys = <&u2phy0_otg>, <&tcphy0_usb3>;
482 phy-names = "usb2-phy", "usb3-phy";
483 phy_type = "utmi_wide";
484 snps,dis_enblslpm_quirk;
485 snps,dis-u2-freeclk-exists-quirk;
486 snps,dis_u2_susphy_quirk;
487 snps,dis-del-phy-power-chg-quirk;
488 snps,xhci-slow-suspend-quirk;
493 usbdrd3_1: usb@fe900000 {
494 compatible = "rockchip,rk3399-dwc3";
495 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
496 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
497 clock-names = "ref_clk", "suspend_clk",
498 "bus_clk", "grf_clk";
499 power-domains = <&power RK3399_PD_USB3>;
500 resets = <&cru SRST_A_USB3_OTG1>;
501 reset-names = "usb3-otg";
502 #address-cells = <2>;
506 usbdrd_dwc3_1: dwc3@fe900000 {
507 compatible = "snps,dwc3";
508 reg = <0x0 0xfe900000 0x0 0x100000>;
509 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
511 phys = <&u2phy1_otg>, <&tcphy1_usb3>;
512 phy-names = "usb2-phy", "usb3-phy";
513 phy_type = "utmi_wide";
514 snps,dis_enblslpm_quirk;
515 snps,dis-u2-freeclk-exists-quirk;
516 snps,dis_u2_susphy_quirk;
517 snps,dis-del-phy-power-chg-quirk;
518 snps,xhci-slow-suspend-quirk;
523 gic: interrupt-controller@fee00000 {
524 compatible = "arm,gic-v3";
525 #interrupt-cells = <4>;
526 #address-cells = <2>;
529 interrupt-controller;
531 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
532 <0x0 0xfef00000 0 0xc0000>, /* GICR */
533 <0x0 0xfff00000 0 0x10000>, /* GICC */
534 <0x0 0xfff10000 0 0x10000>, /* GICH */
535 <0x0 0xfff20000 0 0x10000>; /* GICV */
536 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
537 its: interrupt-controller@fee20000 {
538 compatible = "arm,gic-v3-its";
540 reg = <0x0 0xfee20000 0x0 0x20000>;
544 part0: interrupt-partition-0 {
545 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
548 part1: interrupt-partition-1 {
549 affinity = <&cpu_b0 &cpu_b1>;
554 saradc: saradc@ff100000 {
555 compatible = "rockchip,rk3399-saradc";
556 reg = <0x0 0xff100000 0x0 0x100>;
557 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
558 #io-channel-cells = <1>;
559 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
560 clock-names = "saradc", "apb_pclk";
565 compatible = "rockchip,rk3399-i2c";
566 reg = <0x0 0xff3c0000 0x0 0x1000>;
567 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
568 clock-names = "i2c", "pclk";
569 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
570 pinctrl-names = "default";
571 pinctrl-0 = <&i2c0_xfer>;
572 #address-cells = <1>;
578 compatible = "rockchip,rk3399-i2c";
579 reg = <0x0 0xff110000 0x0 0x1000>;
580 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
581 clock-names = "i2c", "pclk";
582 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
583 pinctrl-names = "default";
584 pinctrl-0 = <&i2c1_xfer>;
585 #address-cells = <1>;
591 compatible = "rockchip,rk3399-i2c";
592 reg = <0x0 0xff120000 0x0 0x1000>;
593 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
594 clock-names = "i2c", "pclk";
595 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&i2c2_xfer>;
598 #address-cells = <1>;
604 compatible = "rockchip,rk3399-i2c";
605 reg = <0x0 0xff130000 0x0 0x1000>;
606 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
607 clock-names = "i2c", "pclk";
608 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&i2c3_xfer>;
611 #address-cells = <1>;
617 compatible = "rockchip,rk3399-i2c";
618 reg = <0x0 0xff140000 0x0 0x1000>;
619 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
620 clock-names = "i2c", "pclk";
621 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
622 pinctrl-names = "default";
623 pinctrl-0 = <&i2c5_xfer>;
624 #address-cells = <1>;
630 compatible = "rockchip,rk3399-i2c";
631 reg = <0x0 0xff150000 0x0 0x1000>;
632 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
633 clock-names = "i2c", "pclk";
634 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&i2c6_xfer>;
637 #address-cells = <1>;
643 compatible = "rockchip,rk3399-i2c";
644 reg = <0x0 0xff160000 0x0 0x1000>;
645 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
646 clock-names = "i2c", "pclk";
647 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
648 pinctrl-names = "default";
649 pinctrl-0 = <&i2c7_xfer>;
650 #address-cells = <1>;
655 uart0: serial@ff180000 {
656 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
657 reg = <0x0 0xff180000 0x0 0x100>;
658 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
659 clock-names = "baudclk", "apb_pclk";
660 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
663 pinctrl-names = "default";
664 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
668 uart1: serial@ff190000 {
669 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
670 reg = <0x0 0xff190000 0x0 0x100>;
671 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
672 clock-names = "baudclk", "apb_pclk";
673 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
676 pinctrl-names = "default";
677 pinctrl-0 = <&uart1_xfer>;
681 uart2: serial@ff1a0000 {
682 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
683 reg = <0x0 0xff1a0000 0x0 0x100>;
684 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
685 clock-names = "baudclk", "apb_pclk";
686 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&uart2c_xfer>;
694 uart3: serial@ff1b0000 {
695 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
696 reg = <0x0 0xff1b0000 0x0 0x100>;
697 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
698 clock-names = "baudclk", "apb_pclk";
699 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
708 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
709 reg = <0x0 0xff1c0000 0x0 0x1000>;
710 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
711 clock-names = "spiclk", "apb_pclk";
712 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
715 #address-cells = <1>;
721 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
722 reg = <0x0 0xff1d0000 0x0 0x1000>;
723 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
724 clock-names = "spiclk", "apb_pclk";
725 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
726 pinctrl-names = "default";
727 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
728 #address-cells = <1>;
734 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
735 reg = <0x0 0xff1e0000 0x0 0x1000>;
736 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
737 clock-names = "spiclk", "apb_pclk";
738 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
739 pinctrl-names = "default";
740 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
741 #address-cells = <1>;
747 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
748 reg = <0x0 0xff1f0000 0x0 0x1000>;
749 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
750 clock-names = "spiclk", "apb_pclk";
751 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
752 pinctrl-names = "default";
753 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
754 #address-cells = <1>;
760 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
761 reg = <0x0 0xff200000 0x0 0x1000>;
762 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
763 clock-names = "spiclk", "apb_pclk";
764 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
765 pinctrl-names = "default";
766 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
767 #address-cells = <1>;
773 soc_thermal: soc-thermal {
774 polling-delay-passive = <20>; /* milliseconds */
775 polling-delay = <1000>; /* milliseconds */
776 sustainable-power = <1000>; /* milliwatts */
778 thermal-sensors = <&tsadc 0>;
781 threshold: trip-point@0 {
782 temperature = <70000>; /* millicelsius */
783 hysteresis = <2000>; /* millicelsius */
786 target: trip-point@1 {
787 temperature = <85000>; /* millicelsius */
788 hysteresis = <2000>; /* millicelsius */
792 temperature = <95000>; /* millicelsius */
793 hysteresis = <2000>; /* millicelsius */
802 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
803 contribution = <4096>;
808 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
809 contribution = <1024>;
814 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
815 contribution = <4096>;
820 gpu_thermal: gpu-thermal {
821 polling-delay-passive = <100>; /* milliseconds */
822 polling-delay = <1000>; /* milliseconds */
824 thermal-sensors = <&tsadc 1>;
828 tsadc: tsadc@ff260000 {
829 compatible = "rockchip,rk3399-tsadc";
830 reg = <0x0 0xff260000 0x0 0x100>;
831 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
832 rockchip,grf = <&grf>;
833 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
834 clock-names = "tsadc", "apb_pclk";
835 assigned-clocks = <&cru SCLK_TSADC>;
836 assigned-clock-rates = <750000>;
837 resets = <&cru SRST_TSADC>;
838 reset-names = "tsadc-apb";
839 pinctrl-names = "init", "default", "sleep";
840 pinctrl-0 = <&otp_gpio>;
841 pinctrl-1 = <&otp_out>;
842 pinctrl-2 = <&otp_gpio>;
843 #thermal-sensor-cells = <1>;
844 rockchip,hw-tshut-temp = <95000>;
848 qos_emmc: qos@ffa58000 {
849 compatible = "syscon";
850 reg = <0x0 0xffa58000 0x0 0x20>;
853 qos_gmac: qos@ffa5c000 {
854 compatible = "syscon";
855 reg = <0x0 0xffa5c000 0x0 0x20>;
858 qos_pcie: qos@ffa60080 {
859 compatible = "syscon";
860 reg = <0x0 0xffa60080 0x0 0x20>;
863 qos_usb_host0: qos@ffa60100 {
864 compatible = "syscon";
865 reg = <0x0 0xffa60100 0x0 0x20>;
868 qos_usb_host1: qos@ffa60180 {
869 compatible = "syscon";
870 reg = <0x0 0xffa60180 0x0 0x20>;
873 qos_usb_otg0: qos@ffa70000 {
874 compatible = "syscon";
875 reg = <0x0 0xffa70000 0x0 0x20>;
878 qos_usb_otg1: qos@ffa70080 {
879 compatible = "syscon";
880 reg = <0x0 0xffa70080 0x0 0x20>;
883 qos_sd: qos@ffa74000 {
884 compatible = "syscon";
885 reg = <0x0 0xffa74000 0x0 0x20>;
888 qos_sdioaudio: qos@ffa76000 {
889 compatible = "syscon";
890 reg = <0x0 0xffa76000 0x0 0x20>;
893 qos_hdcp: qos@ffa90000 {
894 compatible = "syscon";
895 reg = <0x0 0xffa90000 0x0 0x20>;
898 qos_iep: qos@ffa98000 {
899 compatible = "syscon";
900 reg = <0x0 0xffa98000 0x0 0x20>;
903 qos_isp0_m0: qos@ffaa0000 {
904 compatible = "syscon";
905 reg = <0x0 0xffaa0000 0x0 0x20>;
908 qos_isp0_m1: qos@ffaa0080 {
909 compatible = "syscon";
910 reg = <0x0 0xffaa0080 0x0 0x20>;
913 qos_isp1_m0: qos@ffaa8000 {
914 compatible = "syscon";
915 reg = <0x0 0xffaa8000 0x0 0x20>;
918 qos_isp1_m1: qos@ffaa8080 {
919 compatible = "syscon";
920 reg = <0x0 0xffaa8080 0x0 0x20>;
923 qos_rga_r: qos@ffab0000 {
924 compatible = "syscon";
925 reg = <0x0 0xffab0000 0x0 0x20>;
928 qos_rga_w: qos@ffab0080 {
929 compatible = "syscon";
930 reg = <0x0 0xffab0080 0x0 0x20>;
933 qos_video_m0: qos@ffab8000 {
934 compatible = "syscon";
935 reg = <0x0 0xffab8000 0x0 0x20>;
938 qos_video_m1_r: qos@ffac0000 {
939 compatible = "syscon";
940 reg = <0x0 0xffac0000 0x0 0x20>;
943 qos_video_m1_w: qos@ffac0080 {
944 compatible = "syscon";
945 reg = <0x0 0xffac0080 0x0 0x20>;
948 qos_vop_big_r: qos@ffac8000 {
949 compatible = "syscon";
950 reg = <0x0 0xffac8000 0x0 0x20>;
953 qos_vop_big_w: qos@ffac8080 {
954 compatible = "syscon";
955 reg = <0x0 0xffac8080 0x0 0x20>;
958 qos_vop_little: qos@ffad0000 {
959 compatible = "syscon";
960 reg = <0x0 0xffad0000 0x0 0x20>;
963 qos_perihp: qos@ffad8080 {
964 compatible = "syscon";
965 reg = <0x0 0xffad8080 0x0 0x20>;
968 qos_gpu: qos@ffae0000 {
969 compatible = "syscon";
970 reg = <0x0 0xffae0000 0x0 0x20>;
973 pmu: power-management@ff310000 {
974 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
975 reg = <0x0 0xff310000 0x0 0x1000>;
978 * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
979 * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
980 * Some of the power domains are grouped together for every
982 * The detail contents as below.
984 power: power-controller {
985 compatible = "rockchip,rk3399-power-controller";
986 #power-domain-cells = <1>;
987 #address-cells = <1>;
990 /* These power domains are grouped by VD_CENTER */
991 pd_iep@RK3399_PD_IEP {
992 reg = <RK3399_PD_IEP>;
993 clocks = <&cru ACLK_IEP>,
997 pd_rga@RK3399_PD_RGA {
998 reg = <RK3399_PD_RGA>;
999 clocks = <&cru ACLK_RGA>,
1001 pm_qos = <&qos_rga_r>,
1004 pd_vcodec@RK3399_PD_VCODEC {
1005 reg = <RK3399_PD_VCODEC>;
1006 clocks = <&cru ACLK_VCODEC>,
1008 pm_qos = <&qos_video_m0>;
1010 pd_vdu@RK3399_PD_VDU {
1011 reg = <RK3399_PD_VDU>;
1012 clocks = <&cru ACLK_VDU>,
1014 pm_qos = <&qos_video_m1_r>,
1018 /* These power domains are grouped by VD_GPU */
1019 pd_gpu@RK3399_PD_GPU {
1020 reg = <RK3399_PD_GPU>;
1021 clocks = <&cru ACLK_GPU>;
1022 pm_qos = <&qos_gpu>;
1025 /* These power domains are grouped by VD_LOGIC */
1026 pd_edp@RK3399_PD_EDP {
1027 reg = <RK3399_PD_EDP>;
1028 clocks = <&cru PCLK_EDP_CTRL>;
1030 pd_emmc@RK3399_PD_EMMC {
1031 reg = <RK3399_PD_EMMC>;
1032 clocks = <&cru ACLK_EMMC>;
1033 pm_qos = <&qos_emmc>;
1035 pd_gmac@RK3399_PD_GMAC {
1036 reg = <RK3399_PD_GMAC>;
1037 clocks = <&cru ACLK_GMAC>;
1038 pm_qos = <&qos_gmac>;
1040 pd_perihp@RK3399_PD_PERIHP {
1041 reg = <RK3399_PD_PERIHP>;
1042 #address-cells = <1>;
1044 clocks = <&cru ACLK_PERIHP>;
1045 pm_qos = <&qos_perihp>,
1050 pd_sd@RK3399_PD_SD {
1051 reg = <RK3399_PD_SD>;
1052 clocks = <&cru HCLK_SDMMC>,
1057 pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1058 reg = <RK3399_PD_SDIOAUDIO>;
1059 clocks = <&cru HCLK_SDIO>;
1060 pm_qos = <&qos_sdioaudio>;
1062 pd_usb3@RK3399_PD_USB3 {
1063 reg = <RK3399_PD_USB3>;
1064 clocks = <&cru ACLK_USB3>;
1065 pm_qos = <&qos_usb_otg0>,
1068 pd_vio@RK3399_PD_VIO {
1069 reg = <RK3399_PD_VIO>;
1070 #address-cells = <1>;
1073 pd_hdcp@RK3399_PD_HDCP {
1074 reg = <RK3399_PD_HDCP>;
1075 clocks = <&cru ACLK_HDCP>,
1078 pm_qos = <&qos_hdcp>;
1080 pd_isp0@RK3399_PD_ISP0 {
1081 reg = <RK3399_PD_ISP0>;
1082 clocks = <&cru ACLK_ISP0>,
1084 pm_qos = <&qos_isp0_m0>,
1087 pd_isp1@RK3399_PD_ISP1 {
1088 reg = <RK3399_PD_ISP1>;
1089 clocks = <&cru ACLK_ISP1>,
1091 pm_qos = <&qos_isp1_m0>,
1094 pd_vo@RK3399_PD_VO {
1095 reg = <RK3399_PD_VO>;
1096 #address-cells = <1>;
1099 pd_vopb@RK3399_PD_VOPB {
1100 reg = <RK3399_PD_VOPB>;
1101 clocks = <&cru ACLK_VOP0>,
1103 pm_qos = <&qos_vop_big_r>,
1106 pd_vopl@RK3399_PD_VOPL {
1107 reg = <RK3399_PD_VOPL>;
1108 clocks = <&cru ACLK_VOP1>,
1110 pm_qos = <&qos_vop_little>;
1117 pmugrf: syscon@ff320000 {
1118 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1119 reg = <0x0 0xff320000 0x0 0x1000>;
1122 compatible = "syscon-reboot-mode";
1124 mode-bootloader = <BOOT_LOADER>;
1125 mode-charge = <BOOT_CHARGING>;
1126 mode-fastboot = <BOOT_FASTBOOT>;
1127 mode-loader = <BOOT_LOADER>;
1128 mode-normal = <BOOT_NORMAL>;
1129 mode-recovery = <BOOT_RECOVERY>;
1130 mode-ums = <BOOT_UMS>;
1134 spi3: spi@ff350000 {
1135 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1136 reg = <0x0 0xff350000 0x0 0x1000>;
1137 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1138 clock-names = "spiclk", "apb_pclk";
1139 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1140 pinctrl-names = "default";
1141 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1142 #address-cells = <1>;
1144 status = "disabled";
1147 uart4: serial@ff370000 {
1148 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1149 reg = <0x0 0xff370000 0x0 0x100>;
1150 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1151 clock-names = "baudclk", "apb_pclk";
1152 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1155 pinctrl-names = "default";
1156 pinctrl-0 = <&uart4_xfer>;
1157 status = "disabled";
1160 i2c4: i2c@ff3d0000 {
1161 compatible = "rockchip,rk3399-i2c";
1162 reg = <0x0 0xff3d0000 0x0 0x1000>;
1163 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1164 clock-names = "i2c", "pclk";
1165 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1166 pinctrl-names = "default";
1167 pinctrl-0 = <&i2c4_xfer>;
1168 #address-cells = <1>;
1170 status = "disabled";
1173 i2c8: i2c@ff3e0000 {
1174 compatible = "rockchip,rk3399-i2c";
1175 reg = <0x0 0xff3e0000 0x0 0x1000>;
1176 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1177 clock-names = "i2c", "pclk";
1178 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&i2c8_xfer>;
1181 #address-cells = <1>;
1183 status = "disabled";
1186 pcie_phy: phy@e220 {
1187 compatible = "rockchip,rk3399-pcie-phy";
1189 rockchip,grf = <&grf>;
1190 clocks = <&cru SCLK_PCIEPHY_REF>;
1191 clock-names = "refclk";
1192 resets = <&cru SRST_PCIEPHY>;
1193 reset-names = "phy";
1194 status = "disabled";
1197 pcie0: pcie@f8000000 {
1198 compatible = "rockchip,rk3399-pcie";
1199 #address-cells = <3>;
1201 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1202 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1203 clock-names = "aclk", "aclk-perf",
1205 bus-range = <0x0 0x1>;
1206 msi-map = <0x0 &its 0x0 0x1000>;
1207 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1208 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1209 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1210 interrupt-names = "sys", "legacy", "client";
1211 #interrupt-cells = <1>;
1212 interrupt-map-mask = <0 0 0 7>;
1213 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1214 <0 0 0 2 &pcie0_intc 1>,
1215 <0 0 0 3 &pcie0_intc 2>,
1216 <0 0 0 4 &pcie0_intc 3>;
1218 phy-names = "pcie-phy";
1219 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1220 0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1221 reg = <0x0 0xf8000000 0x0 0x2000000>,
1222 <0x0 0xfd000000 0x0 0x1000000>;
1223 reg-names = "axi-base", "apb-base";
1224 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1225 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
1226 reset-names = "core", "mgmt", "mgmt-sticky", "pipe";
1227 status = "disabled";
1228 pcie0_intc: interrupt-controller {
1229 interrupt-controller;
1230 #address-cells = <0>;
1231 #interrupt-cells = <1>;
1235 pwm0: pwm@ff420000 {
1236 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1237 reg = <0x0 0xff420000 0x0 0x10>;
1239 pinctrl-names = "default";
1240 pinctrl-0 = <&pwm0_pin>;
1241 clocks = <&pmucru PCLK_RKPWM_PMU>;
1242 clock-names = "pwm";
1243 status = "disabled";
1246 pwm1: pwm@ff420010 {
1247 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1248 reg = <0x0 0xff420010 0x0 0x10>;
1250 pinctrl-names = "default";
1251 pinctrl-0 = <&pwm1_pin>;
1252 clocks = <&pmucru PCLK_RKPWM_PMU>;
1253 clock-names = "pwm";
1254 status = "disabled";
1257 pwm2: pwm@ff420020 {
1258 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1259 reg = <0x0 0xff420020 0x0 0x10>;
1261 pinctrl-names = "default";
1262 pinctrl-0 = <&pwm2_pin>;
1263 clocks = <&pmucru PCLK_RKPWM_PMU>;
1264 clock-names = "pwm";
1265 status = "disabled";
1268 pwm3: pwm@ff420030 {
1269 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1270 reg = <0x0 0xff420030 0x0 0x10>;
1272 pinctrl-names = "default";
1273 pinctrl-0 = <&pwm3a_pin>;
1274 clocks = <&pmucru PCLK_RKPWM_PMU>;
1275 clock-names = "pwm";
1276 status = "disabled";
1280 reg = <0x00 0xff630000 0x00 0x4000>;
1281 compatible = "rockchip,rk3399-dfi";
1282 rockchip,pmu = <&pmugrf>;
1283 clocks = <&cru PCLK_DDR_MON>;
1284 clock-names = "pclk_ddr_mon";
1285 status = "disabled";
1289 compatible = "rockchip,rk3399-dmc";
1290 devfreq-events = <&dfi>;
1291 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1292 clocks = <&cru SCLK_DDRCLK>;
1293 clock-names = "dmc_clk";
1294 ddr_timing = <&ddr_timing>;
1295 operating-points-v2 = <&dmc_opp_table>;
1296 status = "disabled";
1299 dmc_opp_table: dmc_opp_table {
1300 compatible = "operating-points-v2";
1303 opp-hz = /bits/ 64 <666000000>;
1304 opp-microvolt = <900000>;
1309 compatible = "rockchip,rk3399-rga";
1310 reg = <0x0 0xff680000 0x0 0x10000>;
1311 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1312 interrupt-names = "rga";
1313 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1314 clock-names = "aclk", "hclk", "sclk";
1315 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1316 reset-names = "core", "axi", "ahb";
1317 power-domains = <&power RK3399_PD_RGA>;
1318 status = "disabled";
1321 efuse0: efuse@ff690000 {
1322 compatible = "rockchip,rk3399-efuse";
1323 reg = <0x0 0xff690000 0x0 0x80>;
1324 #address-cells = <1>;
1326 clocks = <&cru PCLK_EFUSE1024NS>;
1327 clock-names = "pclk_efuse";
1330 cpul_leakage: cpul-leakage {
1333 cpub_leakage: cpub-leakage {
1336 gpu_leakage: gpu-leakage {
1339 center_leakage: center-leakage {
1342 logic_leakage: logic-leakage {
1345 wafer_info: wafer-info {
1350 pmucru: pmu-clock-controller@ff750000 {
1351 compatible = "rockchip,rk3399-pmucru";
1352 reg = <0x0 0xff750000 0x0 0x1000>;
1355 assigned-clocks = <&pmucru PLL_PPLL>;
1356 assigned-clock-rates = <676000000>;
1359 cru: clock-controller@ff760000 {
1360 compatible = "rockchip,rk3399-cru";
1361 reg = <0x0 0xff760000 0x0 0x1000>;
1365 <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1366 <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1367 <&cru ARMCLKL>, <&cru ARMCLKB>,
1368 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1370 <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1372 <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1373 <&cru PCLK_PERILP0>,
1374 <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1375 assigned-clock-rates =
1376 <400000000>, <200000000>,
1377 <400000000>, <200000000>,
1378 <816000000>, <816000000>,
1379 <594000000>, <800000000>,
1381 <150000000>, <75000000>,
1383 <100000000>, <100000000>,
1385 <100000000>, <50000000>;
1388 grf: syscon@ff770000 {
1389 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1390 reg = <0x0 0xff770000 0x0 0x10000>;
1391 #address-cells = <1>;
1394 emmc_phy: phy@f780 {
1395 compatible = "rockchip,rk3399-emmc-phy";
1396 reg = <0xf780 0x24>;
1398 clock-names = "emmcclk";
1400 status = "disabled";
1403 u2phy0: usb2-phy@e450 {
1404 compatible = "rockchip,rk3399-usb2phy";
1405 reg = <0xe450 0x10>;
1406 clocks = <&cru SCLK_USB2PHY0_REF>;
1407 clock-names = "phyclk";
1409 clock-output-names = "clk_usbphy0_480m";
1410 status = "disabled";
1412 u2phy0_otg: otg-port {
1414 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1415 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1416 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1417 interrupt-names = "otg-bvalid", "otg-id",
1419 status = "disabled";
1422 u2phy0_host: host-port {
1424 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1425 interrupt-names = "linestate";
1426 status = "disabled";
1430 u2phy1: usb2-phy@e460 {
1431 compatible = "rockchip,rk3399-usb2phy";
1432 reg = <0xe460 0x10>;
1433 clocks = <&cru SCLK_USB2PHY1_REF>;
1434 clock-names = "phyclk";
1436 clock-output-names = "clk_usbphy1_480m";
1437 status = "disabled";
1439 u2phy1_otg: otg-port {
1441 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1442 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1443 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1444 interrupt-names = "otg-bvalid", "otg-id",
1446 status = "disabled";
1449 u2phy1_host: host-port {
1451 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1452 interrupt-names = "linestate";
1453 status = "disabled";
1458 tcphy0: phy@ff7c0000 {
1459 compatible = "rockchip,rk3399-typec-phy";
1460 reg = <0x0 0xff7c0000 0x0 0x40000>;
1461 rockchip,grf = <&grf>;
1463 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1464 <&cru SCLK_UPHY0_TCPDPHY_REF>;
1465 clock-names = "tcpdcore", "tcpdphy-ref";
1466 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1467 assigned-clock-rates = <50000000>;
1468 resets = <&cru SRST_UPHY0>,
1469 <&cru SRST_UPHY0_PIPE_L00>,
1470 <&cru SRST_P_UPHY0_TCPHY>;
1471 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1472 rockchip,typec-conn-dir = <0xe580 0 16>;
1473 rockchip,usb3tousb2-en = <0xe580 3 19>;
1474 rockchip,usb3-host-disable = <0x2434 0 16>;
1475 rockchip,usb3-host-port = <0x2434 12 28>;
1476 rockchip,external-psm = <0xe588 14 30>;
1477 rockchip,pipe-status = <0xe5c0 0 0>;
1478 rockchip,uphy-dp-sel = <0x6268 19 19>;
1479 status = "disabled";
1481 tcphy0_dp: dp-port {
1485 tcphy0_usb3: usb3-port {
1490 tcphy1: phy@ff800000 {
1491 compatible = "rockchip,rk3399-typec-phy";
1492 reg = <0x0 0xff800000 0x0 0x40000>;
1493 rockchip,grf = <&grf>;
1495 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1496 <&cru SCLK_UPHY1_TCPDPHY_REF>;
1497 clock-names = "tcpdcore", "tcpdphy-ref";
1498 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1499 assigned-clock-rates = <50000000>;
1500 resets = <&cru SRST_UPHY1>,
1501 <&cru SRST_UPHY1_PIPE_L00>,
1502 <&cru SRST_P_UPHY1_TCPHY>;
1503 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1504 rockchip,typec-conn-dir = <0xe58c 0 16>;
1505 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1506 rockchip,usb3-host-disable = <0x2444 0 16>;
1507 rockchip,usb3-host-port = <0x2444 12 28>;
1508 rockchip,external-psm = <0xe594 14 30>;
1509 rockchip,pipe-status = <0xe5c0 16 16>;
1510 rockchip,uphy-dp-sel = <0x6268 3 19>;
1511 status = "disabled";
1513 tcphy1_dp: dp-port {
1517 tcphy1_usb3: usb3-port {
1523 compatible = "snps,dw-wdt";
1524 reg = <0x0 0xff848000 0x0 0x100>;
1525 clocks = <&cru PCLK_WDT>;
1526 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1529 rktimer: rktimer@ff850000 {
1530 compatible = "rockchip,rk3399-timer";
1531 reg = <0x0 0xff850000 0x0 0x1000>;
1532 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1533 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1534 clock-names = "pclk", "timer";
1537 spdif: spdif@ff870000 {
1538 compatible = "rockchip,rk3399-spdif";
1539 reg = <0x0 0xff870000 0x0 0x1000>;
1540 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1541 dmas = <&dmac_bus 7>;
1543 clock-names = "mclk", "hclk";
1544 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&spdif_bus>;
1547 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1548 status = "disabled";
1551 i2s0: i2s@ff880000 {
1552 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1553 reg = <0x0 0xff880000 0x0 0x1000>;
1554 rockchip,grf = <&grf>;
1555 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1556 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1557 dma-names = "tx", "rx";
1558 clock-names = "i2s_clk", "i2s_hclk";
1559 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1560 pinctrl-names = "default";
1561 pinctrl-0 = <&i2s0_8ch_bus>;
1562 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1563 status = "disabled";
1566 i2s1: i2s@ff890000 {
1567 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1568 reg = <0x0 0xff890000 0x0 0x1000>;
1569 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1570 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1571 dma-names = "tx", "rx";
1572 clock-names = "i2s_clk", "i2s_hclk";
1573 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1574 pinctrl-names = "default";
1575 pinctrl-0 = <&i2s1_2ch_bus>;
1576 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1577 status = "disabled";
1580 i2s2: i2s@ff8a0000 {
1581 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1582 reg = <0x0 0xff8a0000 0x0 0x1000>;
1583 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1584 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1585 dma-names = "tx", "rx";
1586 clock-names = "i2s_clk", "i2s_hclk";
1587 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1588 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1589 status = "disabled";
1593 compatible = "arm,malit860",
1598 reg = <0x0 0xff9a0000 0x0 0x10000>;
1600 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1601 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1602 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1603 interrupt-names = "GPU", "JOB", "MMU";
1605 clocks = <&cru ACLK_GPU>;
1606 clock-names = "clk_mali";
1607 #cooling-cells = <2>; /* min followed by max */
1608 operating-points-v2 = <&gpu_opp_table>;
1609 power-domains = <&power RK3399_PD_GPU>;
1610 power-off-delay-ms = <200>;
1611 status = "disabled";
1613 gpu_power_model: power_model {
1614 compatible = "arm,mali-simple-power-model";
1617 static-power = <300>;
1618 dynamic-power = <396>;
1619 ts = <32000 4700 (-80) 2>;
1620 thermal-zone = "gpu-thermal";
1624 gpu_opp_table: gpu_opp_table {
1625 compatible = "operating-points-v2";
1629 opp-hz = /bits/ 64 <200000000>;
1630 opp-microvolt = <900000>;
1633 opp-hz = /bits/ 64 <300000000>;
1634 opp-microvolt = <900000>;
1637 opp-hz = /bits/ 64 <400000000>;
1638 opp-microvolt = <900000>;
1643 vopl: vop@ff8f0000 {
1644 compatible = "rockchip,rk3399-vop-lit";
1645 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1646 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1647 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1648 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1649 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1650 reset-names = "axi", "ahb", "dclk";
1651 power-domains = <&power RK3399_PD_VOPL>;
1652 iommus = <&vopl_mmu>;
1653 status = "disabled";
1656 #address-cells = <1>;
1659 vopl_out_mipi: endpoint@0 {
1661 remote-endpoint = <&mipi_in_vopl>;
1664 vopl_out_edp: endpoint@1 {
1666 remote-endpoint = <&edp_in_vopl>;
1669 vopl_out_hdmi: endpoint@2 {
1671 remote-endpoint = <&hdmi_in_vopl>;
1676 vop1_pwm: voppwm@ff8f01a0 {
1677 compatible = "rockchip,vop-pwm";
1678 reg = <0x0 0xff8f01a0 0x0 0x10>;
1680 pinctrl-names = "default";
1681 pinctrl-0 = <&vop1_pwm_pin>;
1682 clocks = <&cru SCLK_VOP1_PWM>;
1683 clock-names = "pwm";
1684 status = "disabled";
1687 vopl_mmu: iommu@ff8f3f00 {
1688 compatible = "rockchip,iommu";
1689 reg = <0x0 0xff8f3f00 0x0 0x100>;
1690 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1691 interrupt-names = "vopl_mmu";
1693 status = "disabled";
1696 vopb: vop@ff900000 {
1697 compatible = "rockchip,rk3399-vop-big";
1698 reg = <0x0 0xff900000 0x0 0x3efc>;
1699 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1700 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1701 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1702 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1703 reset-names = "axi", "ahb", "dclk";
1704 power-domains = <&power RK3399_PD_VOPB>;
1705 iommus = <&vopb_mmu>;
1706 status = "disabled";
1709 #address-cells = <1>;
1712 vopb_out_edp: endpoint@0 {
1714 remote-endpoint = <&edp_in_vopb>;
1717 vopb_out_mipi: endpoint@1 {
1719 remote-endpoint = <&mipi_in_vopb>;
1722 vopb_out_hdmi: endpoint@2 {
1724 remote-endpoint = <&hdmi_in_vopb>;
1729 vop0_pwm: voppwm@ff9001a0 {
1730 compatible = "rockchip,vop-pwm";
1731 reg = <0x0 0xff9001a0 0x0 0x10>;
1733 pinctrl-names = "default";
1734 pinctrl-0 = <&vop0_pwm_pin>;
1735 clocks = <&cru SCLK_VOP0_PWM>;
1736 clock-names = "pwm";
1737 status = "disabled";
1740 vopb_mmu: iommu@ff903f00 {
1741 compatible = "rockchip,iommu";
1742 reg = <0x0 0xff903f00 0x0 0x100>;
1743 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1744 interrupt-names = "vopb_mmu";
1746 status = "disabled";
1749 hdmi: hdmi@ff940000 {
1750 compatible = "rockchip,rk3399-dw-hdmi";
1751 reg = <0x0 0xff940000 0x0 0x20000>;
1753 rockchip,grf = <&grf>;
1754 power-domains = <&power RK3399_PD_HDCP>;
1755 pinctrl-names = "default";
1756 pinctrl-0 = <&hdmi_i2c_xfer>;
1757 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1758 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru SCLK_HDMI_SFR>, <&cru PCLK_EDP_CTRL>;
1759 clock-names = "iahb", "isfr", "vpll", "grf";
1760 status = "disabled";
1764 #address-cells = <1>;
1766 hdmi_in_vopb: endpoint@0 {
1768 remote-endpoint = <&vopb_out_hdmi>;
1770 hdmi_in_vopl: endpoint@1 {
1772 remote-endpoint = <&vopl_out_hdmi>;
1778 mipi_dsi: mipi@ff960000 {
1779 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1780 reg = <0x0 0xff960000 0x0 0x8000>;
1781 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1782 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1783 <&cru SCLK_DPHY_TX0_CFG>;
1784 clock-names = "ref", "pclk", "phy_cfg";
1785 power-domains = <&power RK3399_PD_VIO>;
1786 rockchip,grf = <&grf>;
1787 #address-cells = <1>;
1789 status = "disabled";
1792 #address-cells = <1>;
1797 #address-cells = <1>;
1800 mipi_in_vopb: endpoint@0 {
1802 remote-endpoint = <&vopb_out_mipi>;
1804 mipi_in_vopl: endpoint@1 {
1806 remote-endpoint = <&vopl_out_mipi>;
1813 compatible = "rockchip,rk3399-edp";
1814 reg = <0x0 0xff970000 0x0 0x8000>;
1815 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1816 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1817 clock-names = "dp", "pclk";
1818 power-domains = <&power RK3399_PD_EDP>;
1819 resets = <&cru SRST_P_EDP_CTRL>;
1821 rockchip,grf = <&grf>;
1822 status = "disabled";
1823 pinctrl-names = "default";
1824 pinctrl-0 = <&edp_hpd>;
1827 #address-cells = <1>;
1832 #address-cells = <1>;
1835 edp_in_vopb: endpoint@0 {
1837 remote-endpoint = <&vopb_out_edp>;
1840 edp_in_vopl: endpoint@1 {
1842 remote-endpoint = <&vopl_out_edp>;
1848 display_subsystem: display-subsystem {
1849 compatible = "rockchip,display-subsystem";
1850 ports = <&vopl_out>, <&vopb_out>;
1851 status = "disabled";
1855 compatible = "rockchip,rk3399-pinctrl";
1856 rockchip,grf = <&grf>;
1857 rockchip,pmu = <&pmugrf>;
1858 #address-cells = <0x2>;
1859 #size-cells = <0x2>;
1862 gpio0: gpio0@ff720000 {
1863 compatible = "rockchip,gpio-bank";
1864 reg = <0x0 0xff720000 0x0 0x100>;
1865 clocks = <&pmucru PCLK_GPIO0_PMU>;
1866 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1869 #gpio-cells = <0x2>;
1871 interrupt-controller;
1872 #interrupt-cells = <0x2>;
1875 gpio1: gpio1@ff730000 {
1876 compatible = "rockchip,gpio-bank";
1877 reg = <0x0 0xff730000 0x0 0x100>;
1878 clocks = <&pmucru PCLK_GPIO1_PMU>;
1879 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1882 #gpio-cells = <0x2>;
1884 interrupt-controller;
1885 #interrupt-cells = <0x2>;
1888 gpio2: gpio2@ff780000 {
1889 compatible = "rockchip,gpio-bank";
1890 reg = <0x0 0xff780000 0x0 0x100>;
1891 clocks = <&cru PCLK_GPIO2>;
1892 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1895 #gpio-cells = <0x2>;
1897 interrupt-controller;
1898 #interrupt-cells = <0x2>;
1901 gpio3: gpio3@ff788000 {
1902 compatible = "rockchip,gpio-bank";
1903 reg = <0x0 0xff788000 0x0 0x100>;
1904 clocks = <&cru PCLK_GPIO3>;
1905 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1908 #gpio-cells = <0x2>;
1910 interrupt-controller;
1911 #interrupt-cells = <0x2>;
1914 gpio4: gpio4@ff790000 {
1915 compatible = "rockchip,gpio-bank";
1916 reg = <0x0 0xff790000 0x0 0x100>;
1917 clocks = <&cru PCLK_GPIO4>;
1918 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
1921 #gpio-cells = <0x2>;
1923 interrupt-controller;
1924 #interrupt-cells = <0x2>;
1927 pcfg_pull_up: pcfg-pull-up {
1931 pcfg_pull_down: pcfg-pull-down {
1935 pcfg_pull_none: pcfg-pull-none {
1939 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
1941 drive-strength = <20>;
1944 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
1946 drive-strength = <20>;
1949 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
1951 drive-strength = <18>;
1954 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1956 drive-strength = <12>;
1959 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1961 drive-strength = <8>;
1964 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1966 drive-strength = <4>;
1969 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1971 drive-strength = <2>;
1974 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
1976 drive-strength = <12>;
1979 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
1981 drive-strength = <13>;
1984 pcfg_output_high: pcfg-output-high {
1988 pcfg_output_low: pcfg-output-low {
1992 pcfg_input: pcfg-input {
1997 emmc_pwr: emmc-pwr {
1999 <0 5 RK_FUNC_1 &pcfg_pull_up>;
2004 rgmii_pins: rgmii-pins {
2007 <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2009 <3 14 RK_FUNC_1 &pcfg_pull_none>,
2011 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2013 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2015 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2017 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2019 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2021 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2023 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2025 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2027 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2029 <3 3 RK_FUNC_1 &pcfg_pull_none>,
2031 <3 2 RK_FUNC_1 &pcfg_pull_none>,
2033 <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2035 <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2038 rmii_pins: rmii-pins {
2041 <3 13 RK_FUNC_1 &pcfg_pull_none>,
2043 <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2045 <3 11 RK_FUNC_1 &pcfg_pull_none>,
2047 <3 10 RK_FUNC_1 &pcfg_pull_none>,
2049 <3 9 RK_FUNC_1 &pcfg_pull_none>,
2051 <3 8 RK_FUNC_1 &pcfg_pull_none>,
2053 <3 7 RK_FUNC_1 &pcfg_pull_none>,
2055 <3 6 RK_FUNC_1 &pcfg_pull_none>,
2057 <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2059 <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2064 i2c0_xfer: i2c0-xfer {
2066 <1 15 RK_FUNC_2 &pcfg_pull_none>,
2067 <1 16 RK_FUNC_2 &pcfg_pull_none>;
2072 i2c1_xfer: i2c1-xfer {
2074 <4 2 RK_FUNC_1 &pcfg_pull_none>,
2075 <4 1 RK_FUNC_1 &pcfg_pull_none>;
2080 i2c2_xfer: i2c2-xfer {
2082 <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2083 <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2088 i2c3_xfer: i2c3-xfer {
2090 <4 17 RK_FUNC_1 &pcfg_pull_none>,
2091 <4 16 RK_FUNC_1 &pcfg_pull_none>;
2094 i2c3_gpio: i2c3_gpio {
2096 <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2097 <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2103 i2c4_xfer: i2c4-xfer {
2105 <1 12 RK_FUNC_1 &pcfg_pull_none>,
2106 <1 11 RK_FUNC_1 &pcfg_pull_none>;
2111 i2c5_xfer: i2c5-xfer {
2113 <3 11 RK_FUNC_2 &pcfg_pull_none>,
2114 <3 10 RK_FUNC_2 &pcfg_pull_none>;
2119 i2c6_xfer: i2c6-xfer {
2121 <2 10 RK_FUNC_2 &pcfg_pull_none>,
2122 <2 9 RK_FUNC_2 &pcfg_pull_none>;
2127 i2c7_xfer: i2c7-xfer {
2129 <2 8 RK_FUNC_2 &pcfg_pull_none>,
2130 <2 7 RK_FUNC_2 &pcfg_pull_none>;
2135 i2c8_xfer: i2c8-xfer {
2137 <1 21 RK_FUNC_1 &pcfg_pull_none>,
2138 <1 20 RK_FUNC_1 &pcfg_pull_none>;
2143 i2s0_8ch_bus: i2s0-8ch-bus {
2145 <3 24 RK_FUNC_1 &pcfg_pull_none>,
2146 <3 25 RK_FUNC_1 &pcfg_pull_none>,
2147 <3 26 RK_FUNC_1 &pcfg_pull_none>,
2148 <3 27 RK_FUNC_1 &pcfg_pull_none>,
2149 <3 28 RK_FUNC_1 &pcfg_pull_none>,
2150 <3 29 RK_FUNC_1 &pcfg_pull_none>,
2151 <3 30 RK_FUNC_1 &pcfg_pull_none>,
2152 <3 31 RK_FUNC_1 &pcfg_pull_none>,
2153 <4 0 RK_FUNC_1 &pcfg_pull_none>;
2158 i2s1_2ch_bus: i2s1-2ch-bus {
2160 <4 3 RK_FUNC_1 &pcfg_pull_none>,
2161 <4 4 RK_FUNC_1 &pcfg_pull_none>,
2162 <4 5 RK_FUNC_1 &pcfg_pull_none>,
2163 <4 6 RK_FUNC_1 &pcfg_pull_none>,
2164 <4 7 RK_FUNC_1 &pcfg_pull_none>;
2169 sdio0_bus1: sdio0-bus1 {
2171 <2 20 RK_FUNC_1 &pcfg_pull_up>;
2174 sdio0_bus4: sdio0-bus4 {
2176 <2 20 RK_FUNC_1 &pcfg_pull_up>,
2177 <2 21 RK_FUNC_1 &pcfg_pull_up>,
2178 <2 22 RK_FUNC_1 &pcfg_pull_up>,
2179 <2 23 RK_FUNC_1 &pcfg_pull_up>;
2182 sdio0_cmd: sdio0-cmd {
2184 <2 24 RK_FUNC_1 &pcfg_pull_up>;
2187 sdio0_clk: sdio0-clk {
2189 <2 25 RK_FUNC_1 &pcfg_pull_none>;
2192 sdio0_cd: sdio0-cd {
2194 <2 26 RK_FUNC_1 &pcfg_pull_up>;
2197 sdio0_pwr: sdio0-pwr {
2199 <2 27 RK_FUNC_1 &pcfg_pull_up>;
2202 sdio0_bkpwr: sdio0-bkpwr {
2204 <2 28 RK_FUNC_1 &pcfg_pull_up>;
2207 sdio0_wp: sdio0-wp {
2209 <0 3 RK_FUNC_1 &pcfg_pull_up>;
2212 sdio0_int: sdio0-int {
2214 <0 4 RK_FUNC_1 &pcfg_pull_up>;
2219 sdmmc_bus1: sdmmc-bus1 {
2221 <4 8 RK_FUNC_1 &pcfg_pull_up>;
2224 sdmmc_bus4: sdmmc-bus4 {
2226 <4 8 RK_FUNC_1 &pcfg_pull_up>,
2227 <4 9 RK_FUNC_1 &pcfg_pull_up>,
2228 <4 10 RK_FUNC_1 &pcfg_pull_up>,
2229 <4 11 RK_FUNC_1 &pcfg_pull_up>;
2232 sdmmc_clk: sdmmc-clk {
2234 <4 12 RK_FUNC_1 &pcfg_pull_none>;
2237 sdmmc_cmd: sdmmc-cmd {
2239 <4 13 RK_FUNC_1 &pcfg_pull_up>;
2242 sdmmc_cd: sdmcc-cd {
2244 <0 7 RK_FUNC_1 &pcfg_pull_up>;
2247 sdmmc_wp: sdmmc-wp {
2249 <0 8 RK_FUNC_1 &pcfg_pull_up>;
2254 spdif_bus: spdif-bus {
2256 <4 21 RK_FUNC_1 &pcfg_pull_none>;
2259 spdif_bus_1: spdif-bus-1 {
2261 <3 16 RK_FUNC_3 &pcfg_pull_none>;
2266 spi0_clk: spi0-clk {
2268 <3 6 RK_FUNC_2 &pcfg_pull_up>;
2270 spi0_cs0: spi0-cs0 {
2272 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2274 spi0_cs1: spi0-cs1 {
2276 <3 8 RK_FUNC_2 &pcfg_pull_up>;
2280 <3 5 RK_FUNC_2 &pcfg_pull_up>;
2284 <3 4 RK_FUNC_2 &pcfg_pull_up>;
2289 spi1_clk: spi1-clk {
2291 <1 9 RK_FUNC_2 &pcfg_pull_up>;
2293 spi1_cs0: spi1-cs0 {
2295 <1 10 RK_FUNC_2 &pcfg_pull_up>;
2299 <1 7 RK_FUNC_2 &pcfg_pull_up>;
2303 <1 8 RK_FUNC_2 &pcfg_pull_up>;
2308 spi2_clk: spi2-clk {
2310 <2 11 RK_FUNC_1 &pcfg_pull_up>;
2312 spi2_cs0: spi2-cs0 {
2314 <2 12 RK_FUNC_1 &pcfg_pull_up>;
2318 <2 9 RK_FUNC_1 &pcfg_pull_up>;
2322 <2 10 RK_FUNC_1 &pcfg_pull_up>;
2327 spi3_clk: spi3-clk {
2329 <1 17 RK_FUNC_1 &pcfg_pull_up>;
2331 spi3_cs0: spi3-cs0 {
2333 <1 18 RK_FUNC_1 &pcfg_pull_up>;
2337 <1 15 RK_FUNC_1 &pcfg_pull_up>;
2341 <1 16 RK_FUNC_1 &pcfg_pull_up>;
2346 spi4_clk: spi4-clk {
2348 <3 2 RK_FUNC_2 &pcfg_pull_up>;
2350 spi4_cs0: spi4-cs0 {
2352 <3 3 RK_FUNC_2 &pcfg_pull_up>;
2356 <3 0 RK_FUNC_2 &pcfg_pull_up>;
2360 <3 1 RK_FUNC_2 &pcfg_pull_up>;
2365 spi5_clk: spi5-clk {
2367 <2 22 RK_FUNC_2 &pcfg_pull_up>;
2369 spi5_cs0: spi5-cs0 {
2371 <2 23 RK_FUNC_2 &pcfg_pull_up>;
2375 <2 20 RK_FUNC_2 &pcfg_pull_up>;
2379 <2 21 RK_FUNC_2 &pcfg_pull_up>;
2384 otp_gpio: otp-gpio {
2385 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2389 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2394 uart0_xfer: uart0-xfer {
2396 <2 16 RK_FUNC_1 &pcfg_pull_up>,
2397 <2 17 RK_FUNC_1 &pcfg_pull_none>;
2400 uart0_cts: uart0-cts {
2402 <2 18 RK_FUNC_1 &pcfg_pull_none>;
2405 uart0_rts: uart0-rts {
2407 <2 19 RK_FUNC_1 &pcfg_pull_none>;
2412 uart1_xfer: uart1-xfer {
2414 <3 12 RK_FUNC_2 &pcfg_pull_up>,
2415 <3 13 RK_FUNC_2 &pcfg_pull_none>;
2420 uart2a_xfer: uart2a-xfer {
2422 <4 8 RK_FUNC_2 &pcfg_pull_up>,
2423 <4 9 RK_FUNC_2 &pcfg_pull_none>;
2428 uart2b_xfer: uart2b-xfer {
2430 <4 16 RK_FUNC_2 &pcfg_pull_up>,
2431 <4 17 RK_FUNC_2 &pcfg_pull_none>;
2436 uart2c_xfer: uart2c-xfer {
2438 <4 19 RK_FUNC_1 &pcfg_pull_up>,
2439 <4 20 RK_FUNC_1 &pcfg_pull_none>;
2444 uart3_xfer: uart3-xfer {
2446 <3 14 RK_FUNC_2 &pcfg_pull_up>,
2447 <3 15 RK_FUNC_2 &pcfg_pull_none>;
2450 uart3_cts: uart3-cts {
2452 <3 18 RK_FUNC_2 &pcfg_pull_none>;
2455 uart3_rts: uart3-rts {
2457 <3 19 RK_FUNC_2 &pcfg_pull_none>;
2462 uart4_xfer: uart4-xfer {
2464 <1 7 RK_FUNC_1 &pcfg_pull_up>,
2465 <1 8 RK_FUNC_1 &pcfg_pull_none>;
2470 uarthdcp_xfer: uarthdcp-xfer {
2472 <4 21 RK_FUNC_2 &pcfg_pull_up>,
2473 <4 22 RK_FUNC_2 &pcfg_pull_none>;
2478 pwm0_pin: pwm0-pin {
2480 <4 18 RK_FUNC_1 &pcfg_pull_none>;
2483 vop0_pwm_pin: vop0-pwm-pin {
2485 <4 18 RK_FUNC_2 &pcfg_pull_none>;
2490 pwm1_pin: pwm1-pin {
2492 <4 22 RK_FUNC_1 &pcfg_pull_none>;
2495 vop1_pwm_pin: vop1-pwm-pin {
2497 <4 18 RK_FUNC_3 &pcfg_pull_none>;
2502 pwm2_pin: pwm2-pin {
2504 <1 19 RK_FUNC_1 &pcfg_pull_none>;
2509 pwm3a_pin: pwm3a-pin {
2511 <0 6 RK_FUNC_1 &pcfg_pull_none>;
2516 pwm3b_pin: pwm3b-pin {
2518 <1 14 RK_FUNC_1 &pcfg_pull_none>;
2525 <4 23 RK_FUNC_2 &pcfg_pull_none>;
2530 hdmi_i2c_xfer: hdmi-i2c-xfer {
2532 <4 17 RK_FUNC_3 &pcfg_pull_none>,
2533 <4 16 RK_FUNC_3 &pcfg_pull_none>;
2536 hdmi_cec: hdmi-cec {
2538 <4 23 RK_FUNC_1 &pcfg_pull_none>;
2543 pcie_clkreqn: pci-clkreqn {
2545 <2 26 RK_FUNC_2 &pcfg_pull_none>;
2548 pcie_clkreqnb: pci-clkreqnb {
2550 <4 24 RK_FUNC_1 &pcfg_pull_none>;