arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3399-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3399-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/suspend/rockchip-rk3399.h>
  51 #include <dt-bindings/thermal/thermal.h>
  52
  53 #include "rk3399-dram-default-timing.dtsi"
  54
  55 / {
  56         compatible = "rockchip,rk3399";
  57
  58         interrupt-parent = <&gic>;
  59         #address-cells = <2>;
  60         #size-cells = <2>;
  61
  62         aliases {
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 i2c6 = &i2c6;
  70                 i2c7 = &i2c7;
  71                 i2c8 = &i2c8;
  72                 serial0 = &uart0;
  73                 serial1 = &uart1;
  74                 serial2 = &uart2;
  75                 serial3 = &uart3;
  76                 serial4 = &uart4;
  77         };
  78
  79         cpus {
  80                 #address-cells = <2>;
  81                 #size-cells = <0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                         };
 107                 };
 108
 109                 cpu_l0: cpu@0 {
 110                         device_type = "cpu";
 111                         compatible = "arm,cortex-a53", "arm,armv8";
 112                         reg = <0x0 0x0>;
 113                         enable-method = "psci";
 114                         #cooling-cells = <2>; /* min followed by max */
 115                         dynamic-power-coefficient = <100>;
 116                         clocks = <&cru ARMCLKL>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                         clocks = <&cru ARMCLKL>;
 126                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 127                 };
 128
 129                 cpu_l2: cpu@2 {
 130                         device_type = "cpu";
 131                         compatible = "arm,cortex-a53", "arm,armv8";
 132                         reg = <0x0 0x2>;
 133                         enable-method = "psci";
 134                         clocks = <&cru ARMCLKL>;
 135                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 136                 };
 137
 138                 cpu_l3: cpu@3 {
 139                         device_type = "cpu";
 140                         compatible = "arm,cortex-a53", "arm,armv8";
 141                         reg = <0x0 0x3>;
 142                         enable-method = "psci";
 143                         clocks = <&cru ARMCLKL>;
 144                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 145                 };
 146
 147                 cpu_b0: cpu@100 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a72", "arm,armv8";
 150                         reg = <0x0 0x100>;
 151                         enable-method = "psci";
 152                         #cooling-cells = <2>; /* min followed by max */
 153                         dynamic-power-coefficient = <436>;
 154                         clocks = <&cru ARMCLKB>;
 155                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 156                 };
 157
 158                 cpu_b1: cpu@101 {
 159                         device_type = "cpu";
 160                         compatible = "arm,cortex-a72", "arm,armv8";
 161                         reg = <0x0 0x101>;
 162                         enable-method = "psci";
 163                         clocks = <&cru ARMCLKB>;
 164                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 165                 };
 166
 167                 idle-states {
 168                         entry-method = "psci";
 169
 170                         CPU_SLEEP: cpu-sleep {
 171                                 compatible = "arm,idle-state";
 172                                 local-timer-stop;
 173                                 arm,psci-suspend-param = <0x0010000>;
 174                                 entry-latency-us = <120>;
 175                                 exit-latency-us = <250>;
 176                                 min-residency-us = <900>;
 177                         };
 178
 179                         CLUSTER_SLEEP: cluster-sleep {
 180                                 compatible = "arm,idle-state";
 181                                 local-timer-stop;
 182                                 arm,psci-suspend-param = <0x1010000>;
 183                                 entry-latency-us = <400>;
 184                                 exit-latency-us = <500>;
 185                                 min-residency-us = <2000>;
 186                         };
 187                 };
 188         };
 189
 190         cpu_avs: cpu-avs {
 191                 cluster0-avs {
 192                         cluster-id = <0>;
 193                         min-volt = <800000>; /* uV */
 194                         min-freq = <408000>; /* KHz */
 195                         leakage-adjust-volt = <
 196                         /*  mA        mA         uV */
 197                             0         254        0
 198                         >;
 199                         nvmem-cells = <&cpul_leakage>;
 200                         nvmem-cell-names = "cpu_leakage";
 201                 };
 202                 cluster1-avs {
 203                         cluster-id = <1>;
 204                         min-volt = <800000>; /* uV */
 205                         min-freq = <408000>; /* KHz */
 206                         leakage-adjust-volt = <
 207                         /*  mA        mA         uV */
 208                             0         254        0
 209                         >;
 210                         nvmem-cells = <&cpub_leakage>;
 211                         nvmem-cell-names = "cpu_leakage";
 212                 };
 213         };
 214
 215         pmu_a53 {
 216                 compatible = "arm,cortex-a53-pmu";
 217                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 218         };
 219
 220         pmu_a72 {
 221                 compatible = "arm,cortex-a72-pmu";
 222                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 223         };
 224
 225         psci {
 226                 compatible = "arm,psci-1.0";
 227                 method = "smc";
 228         };
 229
 230         timer {
 231                 compatible = "arm,armv8-timer";
 232                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 233                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 234                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 235                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 236         };
 237
 238         xin24m: xin24m {
 239                 compatible = "fixed-clock";
 240                 clock-frequency = <24000000>;
 241                 clock-output-names = "xin24m";
 242                 #clock-cells = <0>;
 243         };
 244
 245         amba {
 246                 compatible = "arm,amba-bus";
 247                 #address-cells = <2>;
 248                 #size-cells = <2>;
 249                 ranges;
 250
 251                 dmac_bus: dma-controller@ff6d0000 {
 252                         compatible = "arm,pl330", "arm,primecell";
 253                         reg = <0x0 0xff6d0000 0x0 0x4000>;
 254                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
 255                                      <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
 256                         #dma-cells = <1>;
 257                         clocks = <&cru ACLK_DMAC0_PERILP>;
 258                         clock-names = "apb_pclk";
 259                         peripherals-req-type-burst;
 260                 };
 261
 262                 dmac_peri: dma-controller@ff6e0000 {
 263                         compatible = "arm,pl330", "arm,primecell";
 264                         reg = <0x0 0xff6e0000 0x0 0x4000>;
 265                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
 266                                      <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
 267                         #dma-cells = <1>;
 268                         clocks = <&cru ACLK_DMAC1_PERILP>;
 269                         clock-names = "apb_pclk";
 270                         peripherals-req-type-burst;
 271                 };
 272         };
 273
 274         gmac: ethernet@fe300000 {
 275                 compatible = "rockchip,rk3399-gmac";
 276                 reg = <0x0 0xfe300000 0x0 0x10000>;
 277                 rockchip,grf = <&grf>;
 278                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 279                 interrupt-names = "macirq";
 280                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 281                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 282                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 283                          <&cru PCLK_GMAC>;
 284                 clock-names = "stmmaceth", "mac_clk_rx",
 285                               "mac_clk_tx", "clk_mac_ref",
 286                               "clk_mac_refout", "aclk_mac",
 287                               "pclk_mac";
 288                 resets = <&cru SRST_A_GMAC>;
 289                 reset-names = "stmmaceth";
 290                 power-domains = <&power RK3399_PD_GMAC>;
 291                 status = "disabled";
 292         };
 293
 294         sdio0: dwmmc@fe310000 {
 295                 compatible = "rockchip,rk3399-dw-mshc",
 296                              "rockchip,rk3288-dw-mshc";
 297                 reg = <0x0 0xfe310000 0x0 0x4000>;
 298                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 299                 clock-freq-min-max = <400000 150000000>;
 300                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 301                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 302                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 303                 fifo-depth = <0x100>;
 304                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 305                 status = "disabled";
 306         };
 307
 308         sdmmc: dwmmc@fe320000 {
 309                 compatible = "rockchip,rk3399-dw-mshc",
 310                              "rockchip,rk3288-dw-mshc";
 311                 reg = <0x0 0xfe320000 0x0 0x4000>;
 312                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 313                 clock-freq-min-max = <400000 150000000>;
 314                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 315                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 316                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 317                 fifo-depth = <0x100>;
 318                 power-domains = <&power RK3399_PD_SD>;
 319                 status = "disabled";
 320         };
 321
 322         sdhci: sdhci@fe330000 {
 323                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 324                 reg = <0x0 0xfe330000 0x0 0x10000>;
 325                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 326                 arasan,soc-ctl-syscon = <&grf>;
 327                 assigned-clocks = <&cru SCLK_EMMC>;
 328                 assigned-clock-rates = <200000000>;
 329                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 330                 clock-names = "clk_xin", "clk_ahb";
 331                 clock-output-names = "emmc_cardclock";
 332                 #clock-cells = <0>;
 333                 phys = <&emmc_phy>;
 334                 phy-names = "phy_arasan";
 335                 power-domains = <&power RK3399_PD_EMMC>;
 336                 status = "disabled";
 337         };
 338
 339         usb_host0_ehci: usb@fe380000 {
 340                 compatible = "generic-ehci";
 341                 reg = <0x0 0xfe380000 0x0 0x20000>;
 342                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 343                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 344                          <&cru SCLK_USBPHY0_480M_SRC>;
 345                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 346                 phys = <&u2phy0_host>;
 347                 phy-names = "usb";
 348                 power-domains = <&power RK3399_PD_PERIHP>;
 349                 status = "disabled";
 350         };
 351
 352         usb_host0_ohci: usb@fe3a0000 {
 353                 compatible = "generic-ohci";
 354                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 355                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 356                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 357                          <&cru SCLK_USBPHY0_480M_SRC>;
 358                 clock-names = "hclk_host0", "hclk_host0_arb", "usbphy0_480m";
 359                 phys = <&u2phy0_host>;
 360                 phy-names = "usb";
 361                 power-domains = <&power RK3399_PD_PERIHP>;
 362                 status = "disabled";
 363         };
 364
 365         usb_host1_ehci: usb@fe3c0000 {
 366                 compatible = "generic-ehci";
 367                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 368                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 369                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 370                          <&cru SCLK_USBPHY1_480M_SRC>;
 371                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 372                 phys = <&u2phy1_host>;
 373                 phy-names = "usb";
 374                 power-domains = <&power RK3399_PD_PERIHP>;
 375                 status = "disabled";
 376         };
 377
 378         usb_host1_ohci: usb@fe3e0000 {
 379                 compatible = "generic-ohci";
 380                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 381                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 382                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 383                          <&cru SCLK_USBPHY1_480M_SRC>;
 384                 clock-names = "hclk_host1", "hclk_host1_arb", "usbphy1_480m";
 385                 phys = <&u2phy1_host>;
 386                 phy-names = "usb";
 387                 power-domains = <&power RK3399_PD_PERIHP>;
 388                 status = "disabled";
 389         };
 390
 391         usbdrd3_0: usb@fe800000 {
 392                 compatible = "rockchip,rk3399-dwc3";
 393                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 394                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
 395                 clock-names = "ref_clk", "suspend_clk",
 396                               "bus_clk", "grf_clk";
 397                 power-domains = <&power RK3399_PD_USB3>;
 398                 resets = <&cru SRST_A_USB3_OTG0>;
 399                 reset-names = "usb3-otg";
 400                 #address-cells = <2>;
 401                 #size-cells = <2>;
 402                 ranges;
 403                 status = "disabled";
 404                 usbdrd_dwc3_0: dwc3@fe800000 {
 405                         compatible = "snps,dwc3";
 406                         reg = <0x0 0xfe800000 0x0 0x100000>;
 407                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 408                         dr_mode = "otg";
 409                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 410                         phy-names = "usb2-phy", "usb3-phy";
 411                         phy_type = "utmi_wide";
 412                         snps,dis_enblslpm_quirk;
 413                         snps,dis-u2-freeclk-exists-quirk;
 414                         snps,dis_u2_susphy_quirk;
 415                         snps,dis-del-phy-power-chg-quirk;
 416                         snps,xhci-slow-suspend-quirk;
 417                         status = "disabled";
 418                 };
 419         };
 420
 421         usbdrd3_1: usb@fe900000 {
 422                 compatible = "rockchip,rk3399-dwc3";
 423                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 424                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
 425                 clock-names = "ref_clk", "suspend_clk",
 426                               "bus_clk", "grf_clk";
 427                 power-domains = <&power RK3399_PD_USB3>;
 428                 resets = <&cru SRST_A_USB3_OTG1>;
 429                 reset-names = "usb3-otg";
 430                 #address-cells = <2>;
 431                 #size-cells = <2>;
 432                 ranges;
 433                 status = "disabled";
 434                 usbdrd_dwc3_1: dwc3@fe900000 {
 435                         compatible = "snps,dwc3";
 436                         reg = <0x0 0xfe900000 0x0 0x100000>;
 437                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 438                         dr_mode = "host";
 439                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 440                         phy-names = "usb2-phy", "usb3-phy";
 441                         phy_type = "utmi_wide";
 442                         snps,dis_enblslpm_quirk;
 443                         snps,dis-u2-freeclk-exists-quirk;
 444                         snps,dis_u2_susphy_quirk;
 445                         snps,dis-del-phy-power-chg-quirk;
 446                         snps,xhci-slow-suspend-quirk;
 447                         status = "disabled";
 448                 };
 449         };
 450
 451         cdn_dp: dp@fec00000 {
 452                 compatible = "rockchip,rk3399-cdn-dp";
 453                 reg = <0x0 0xfec00000 0x0 0x100000>;
 454                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 455                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 456                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 457                 clock-names = "core-clk", "pclk", "spdif", "grf";
 458                 assigned-clocks = <&cru SCLK_DP_CORE>;
 459                 assigned-clock-rates = <100000000>;
 460                 power-domains = <&power RK3399_PD_HDCP>;
 461                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 462                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 463                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 464                 reset-names = "spdif", "dptx", "apb", "core";
 465                 rockchip,grf = <&grf>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 #sound-dai-cells = <1>;
 469                 status = "disabled";
 470
 471                 ports {
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474
 475                         dp_in: port {
 476                                 #address-cells = <1>;
 477                                 #size-cells = <0>;
 478                                 dp_in_vopb: endpoint@0 {
 479                                         reg = <0>;
 480                                         remote-endpoint = <&vopb_out_dp>;
 481                                 };
 482
 483                                 dp_in_vopl: endpoint@1 {
 484                                         reg = <1>;
 485                                         remote-endpoint = <&vopl_out_dp>;
 486                                 };
 487                         };
 488                 };
 489         };
 490
 491         gic: interrupt-controller@fee00000 {
 492                 compatible = "arm,gic-v3";
 493                 #interrupt-cells = <4>;
 494                 #address-cells = <2>;
 495                 #size-cells = <2>;
 496                 ranges;
 497                 interrupt-controller;
 498
 499                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 500                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 501                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 502                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 503                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 504                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 505                 its: interrupt-controller@fee20000 {
 506                         compatible = "arm,gic-v3-its";
 507                         msi-controller;
 508                         reg = <0x0 0xfee20000 0x0 0x20000>;
 509                 };
 510
 511                 ppi-partitions {
 512                         ppi_cluster0: interrupt-partition-0 {
 513                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 514                         };
 515
 516                         ppi_cluster1: interrupt-partition-1 {
 517                                 affinity = <&cpu_b0 &cpu_b1>;
 518                         };
 519                 };
 520         };
 521
 522         saradc: saradc@ff100000 {
 523                 compatible = "rockchip,rk3399-saradc";
 524                 reg = <0x0 0xff100000 0x0 0x100>;
 525                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 526                 #io-channel-cells = <1>;
 527                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 528                 clock-names = "saradc", "apb_pclk";
 529                 resets = <&cru SRST_P_SARADC>;
 530                 reset-names = "saradc-apb";
 531                 status = "disabled";
 532         };
 533
 534         i2c0: i2c@ff3c0000 {
 535                 compatible = "rockchip,rk3399-i2c";
 536                 reg = <0x0 0xff3c0000 0x0 0x1000>;
 537                 clocks =  <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
 538                 clock-names = "i2c", "pclk";
 539                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c0_xfer>;
 542                 #address-cells = <1>;
 543                 #size-cells = <0>;
 544                 status = "disabled";
 545         };
 546
 547         i2c1: i2c@ff110000 {
 548                 compatible = "rockchip,rk3399-i2c";
 549                 reg = <0x0 0xff110000 0x0 0x1000>;
 550                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 551                 clock-names = "i2c", "pclk";
 552                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 553                 pinctrl-names = "default";
 554                 pinctrl-0 = <&i2c1_xfer>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 status = "disabled";
 558         };
 559
 560         i2c2: i2c@ff120000 {
 561                 compatible = "rockchip,rk3399-i2c";
 562                 reg = <0x0 0xff120000 0x0 0x1000>;
 563                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 564                 clock-names = "i2c", "pclk";
 565                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 566                 pinctrl-names = "default";
 567                 pinctrl-0 = <&i2c2_xfer>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 status = "disabled";
 571         };
 572
 573         i2c3: i2c@ff130000 {
 574                 compatible = "rockchip,rk3399-i2c";
 575                 reg = <0x0 0xff130000 0x0 0x1000>;
 576                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 577                 clock-names = "i2c", "pclk";
 578                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c3_xfer>;
 581                 #address-cells = <1>;
 582                 #size-cells = <0>;
 583                 status = "disabled";
 584         };
 585
 586         i2c5: i2c@ff140000 {
 587                 compatible = "rockchip,rk3399-i2c";
 588                 reg = <0x0 0xff140000 0x0 0x1000>;
 589                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 590                 clock-names = "i2c", "pclk";
 591                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&i2c5_xfer>;
 594                 #address-cells = <1>;
 595                 #size-cells = <0>;
 596                 status = "disabled";
 597         };
 598
 599         i2c6: i2c@ff150000 {
 600                 compatible = "rockchip,rk3399-i2c";
 601                 reg = <0x0 0xff150000 0x0 0x1000>;
 602                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 603                 clock-names = "i2c", "pclk";
 604                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&i2c6_xfer>;
 607                 #address-cells = <1>;
 608                 #size-cells = <0>;
 609                 status = "disabled";
 610         };
 611
 612         i2c7: i2c@ff160000 {
 613                 compatible = "rockchip,rk3399-i2c";
 614                 reg = <0x0 0xff160000 0x0 0x1000>;
 615                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 616                 clock-names = "i2c", "pclk";
 617                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 618                 pinctrl-names = "default";
 619                 pinctrl-0 = <&i2c7_xfer>;
 620                 #address-cells = <1>;
 621                 #size-cells = <0>;
 622                 status = "disabled";
 623         };
 624
 625         uart0: serial@ff180000 {
 626                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 627                 reg = <0x0 0xff180000 0x0 0x100>;
 628                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 pinctrl-names = "default";
 634                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 635                 status = "disabled";
 636         };
 637
 638         uart1: serial@ff190000 {
 639                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 640                 reg = <0x0 0xff190000 0x0 0x100>;
 641                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 642                 clock-names = "baudclk", "apb_pclk";
 643                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 644                 reg-shift = <2>;
 645                 reg-io-width = <4>;
 646                 pinctrl-names = "default";
 647                 pinctrl-0 = <&uart1_xfer>;
 648                 status = "disabled";
 649         };
 650
 651         uart2: serial@ff1a0000 {
 652                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 653                 reg = <0x0 0xff1a0000 0x0 0x100>;
 654                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 655                 clock-names = "baudclk", "apb_pclk";
 656                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 657                 reg-shift = <2>;
 658                 reg-io-width = <4>;
 659                 pinctrl-names = "default";
 660                 pinctrl-0 = <&uart2c_xfer>;
 661                 status = "disabled";
 662         };
 663
 664         uart3: serial@ff1b0000 {
 665                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 666                 reg = <0x0 0xff1b0000 0x0 0x100>;
 667                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 668                 clock-names = "baudclk", "apb_pclk";
 669                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 670                 reg-shift = <2>;
 671                 reg-io-width = <4>;
 672                 pinctrl-names = "default";
 673                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 674                 status = "disabled";
 675         };
 676
 677         spi0: spi@ff1c0000 {
 678                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 679                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 680                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 681                 clock-names = "spiclk", "apb_pclk";
 682                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 685                 #address-cells = <1>;
 686                 #size-cells = <0>;
 687                 status = "disabled";
 688         };
 689
 690         spi1: spi@ff1d0000 {
 691                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 692                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 693                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 694                 clock-names = "spiclk", "apb_pclk";
 695                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 698                 #address-cells = <1>;
 699                 #size-cells = <0>;
 700                 status = "disabled";
 701         };
 702
 703         spi2: spi@ff1e0000 {
 704                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 705                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 706                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 707                 clock-names = "spiclk", "apb_pclk";
 708                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 709                 pinctrl-names = "default";
 710                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 711                 #address-cells = <1>;
 712                 #size-cells = <0>;
 713                 status = "disabled";
 714         };
 715
 716         spi4: spi@ff1f0000 {
 717                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 718                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 719                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 720                 clock-names = "spiclk", "apb_pclk";
 721                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 724                 #address-cells = <1>;
 725                 #size-cells = <0>;
 726                 status = "disabled";
 727         };
 728
 729         spi5: spi@ff200000 {
 730                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 731                 reg = <0x0 0xff200000 0x0 0x1000>;
 732                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 733                 clock-names = "spiclk", "apb_pclk";
 734                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 737                 #address-cells = <1>;
 738                 #size-cells = <0>;
 739                 status = "disabled";
 740         };
 741
 742         thermal_zones: thermal-zones {
 743                 soc_thermal: soc-thermal {
 744                         polling-delay-passive = <20>; /* milliseconds */
 745                         polling-delay = <1000>; /* milliseconds */
 746                         sustainable-power = <1000>; /* milliwatts */
 747
 748                         thermal-sensors = <&tsadc 0>;
 749
 750                         trips {
 751                                 threshold: trip-point@0 {
 752                                         temperature = <70000>; /* millicelsius */
 753                                         hysteresis = <2000>; /* millicelsius */
 754                                         type = "passive";
 755                                 };
 756                                 target: trip-point@1 {
 757                                         temperature = <85000>; /* millicelsius */
 758                                         hysteresis = <2000>; /* millicelsius */
 759                                         type = "passive";
 760                                 };
 761                                 soc_crit: soc-crit {
 762                                         temperature = <95000>; /* millicelsius */
 763                                         hysteresis = <2000>; /* millicelsius */
 764                                         type = "critical";
 765                                 };
 766                         };
 767
 768                         cooling-maps {
 769                                 map0 {
 770                                         trip = <&target>;
 771                                         cooling-device =
 772                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 773                                         contribution = <4096>;
 774                                 };
 775                                 map1 {
 776                                         trip = <&target>;
 777                                         cooling-device =
 778                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 779                                         contribution = <1024>;
 780                                 };
 781                                 map2 {
 782                                         trip = <&target>;
 783                                         cooling-device =
 784                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 785                                         contribution = <4096>;
 786                                 };
 787                         };
 788                 };
 789
 790                 gpu_thermal: gpu-thermal {
 791                         polling-delay-passive = <100>; /* milliseconds */
 792                         polling-delay = <1000>; /* milliseconds */
 793
 794                         thermal-sensors = <&tsadc 1>;
 795                 };
 796         };
 797
 798         tsadc: tsadc@ff260000 {
 799                 compatible = "rockchip,rk3399-tsadc";
 800                 reg = <0x0 0xff260000 0x0 0x100>;
 801                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 802                 rockchip,grf = <&grf>;
 803                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 804                 clock-names = "tsadc", "apb_pclk";
 805                 assigned-clocks = <&cru SCLK_TSADC>;
 806                 assigned-clock-rates = <750000>;
 807                 resets = <&cru SRST_TSADC>;
 808                 reset-names = "tsadc-apb";
 809                 pinctrl-names = "init", "default", "sleep";
 810                 pinctrl-0 = <&otp_gpio>;
 811                 pinctrl-1 = <&otp_out>;
 812                 pinctrl-2 = <&otp_gpio>;
 813                 #thermal-sensor-cells = <1>;
 814                 rockchip,hw-tshut-temp = <95000>;
 815                 status = "disabled";
 816         };
 817
 818         qos_emmc: qos@ffa58000 {
 819                 compatible = "syscon";
 820                 reg = <0x0 0xffa58000 0x0 0x20>;
 821         };
 822
 823         qos_gmac: qos@ffa5c000 {
 824                 compatible = "syscon";
 825                 reg = <0x0 0xffa5c000 0x0 0x20>;
 826         };
 827
 828         qos_pcie: qos@ffa60080 {
 829                 compatible = "syscon";
 830                 reg = <0x0 0xffa60080 0x0 0x20>;
 831         };
 832
 833         qos_usb_host0: qos@ffa60100 {
 834                 compatible = "syscon";
 835                 reg = <0x0 0xffa60100 0x0 0x20>;
 836         };
 837
 838         qos_usb_host1: qos@ffa60180 {
 839                 compatible = "syscon";
 840                 reg = <0x0 0xffa60180 0x0 0x20>;
 841         };
 842
 843         qos_usb_otg0: qos@ffa70000 {
 844                 compatible = "syscon";
 845                 reg = <0x0 0xffa70000 0x0 0x20>;
 846         };
 847
 848         qos_usb_otg1: qos@ffa70080 {
 849                 compatible = "syscon";
 850                 reg = <0x0 0xffa70080 0x0 0x20>;
 851         };
 852
 853         qos_sd: qos@ffa74000 {
 854                 compatible = "syscon";
 855                 reg = <0x0 0xffa74000 0x0 0x20>;
 856         };
 857
 858         qos_sdioaudio: qos@ffa76000 {
 859                 compatible = "syscon";
 860                 reg = <0x0 0xffa76000 0x0 0x20>;
 861         };
 862
 863         qos_hdcp: qos@ffa90000 {
 864                 compatible = "syscon";
 865                 reg = <0x0 0xffa90000 0x0 0x20>;
 866         };
 867
 868         qos_iep: qos@ffa98000 {
 869                 compatible = "syscon";
 870                 reg = <0x0 0xffa98000 0x0 0x20>;
 871         };
 872
 873         qos_isp0_m0: qos@ffaa0000 {
 874                 compatible = "syscon";
 875                 reg = <0x0 0xffaa0000 0x0 0x20>;
 876         };
 877
 878         qos_isp0_m1: qos@ffaa0080 {
 879                 compatible = "syscon";
 880                 reg = <0x0 0xffaa0080 0x0 0x20>;
 881         };
 882
 883         qos_isp1_m0: qos@ffaa8000 {
 884                 compatible = "syscon";
 885                 reg = <0x0 0xffaa8000 0x0 0x20>;
 886         };
 887
 888         qos_isp1_m1: qos@ffaa8080 {
 889                 compatible = "syscon";
 890                 reg = <0x0 0xffaa8080 0x0 0x20>;
 891         };
 892
 893         qos_rga_r: qos@ffab0000 {
 894                 compatible = "syscon";
 895                 reg = <0x0 0xffab0000 0x0 0x20>;
 896         };
 897
 898         qos_rga_w: qos@ffab0080 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffab0080 0x0 0x20>;
 901         };
 902
 903         qos_video_m0: qos@ffab8000 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffab8000 0x0 0x20>;
 906         };
 907
 908         qos_video_m1_r: qos@ffac0000 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffac0000 0x0 0x20>;
 911         };
 912
 913         qos_video_m1_w: qos@ffac0080 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffac0080 0x0 0x20>;
 916         };
 917
 918         qos_vop_big_r: qos@ffac8000 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffac8000 0x0 0x20>;
 921         };
 922
 923         qos_vop_big_w: qos@ffac8080 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffac8080 0x0 0x20>;
 926         };
 927
 928         qos_vop_little: qos@ffad0000 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad0000 0x0 0x20>;
 931         };
 932
 933         qos_perihp: qos@ffad8080 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffad8080 0x0 0x20>;
 936         };
 937
 938         qos_gpu: qos@ffae0000 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffae0000 0x0 0x20>;
 941         };
 942
 943         pmu: power-management@ff310000 {
 944                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 945                 reg = <0x0 0xff310000 0x0 0x1000>;
 946
 947                 /*
 948                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 949                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 950                  * Some of the power domains are grouped together for every
 951                  * voltage domain.
 952                  * The detail contents as below.
 953                  */
 954                 power: power-controller {
 955                         compatible = "rockchip,rk3399-power-controller";
 956                         #power-domain-cells = <1>;
 957                         #address-cells = <1>;
 958                         #size-cells = <0>;
 959
 960                         /* These power domains are grouped by VD_CENTER */
 961                         pd_iep@RK3399_PD_IEP {
 962                                 reg = <RK3399_PD_IEP>;
 963                                 clocks = <&cru ACLK_IEP>,
 964                                          <&cru HCLK_IEP>;
 965                                 pm_qos = <&qos_iep>;
 966                         };
 967                         pd_rga@RK3399_PD_RGA {
 968                                 reg = <RK3399_PD_RGA>;
 969                                 clocks = <&cru ACLK_RGA>,
 970                                          <&cru HCLK_RGA>;
 971                                 pm_qos = <&qos_rga_r>,
 972                                          <&qos_rga_w>;
 973                         };
 974                         pd_vcodec@RK3399_PD_VCODEC {
 975                                 reg = <RK3399_PD_VCODEC>;
 976                                 clocks = <&cru ACLK_VCODEC>,
 977                                          <&cru HCLK_VCODEC>;
 978                                 pm_qos = <&qos_video_m0>;
 979                         };
 980                         pd_vdu@RK3399_PD_VDU {
 981                                 reg = <RK3399_PD_VDU>;
 982                                 clocks = <&cru ACLK_VDU>,
 983                                          <&cru HCLK_VDU>;
 984                                 pm_qos = <&qos_video_m1_r>,
 985                                          <&qos_video_m1_w>;
 986                         };
 987
 988                         /* These power domains are grouped by VD_GPU */
 989                         pd_gpu@RK3399_PD_GPU {
 990                                 reg = <RK3399_PD_GPU>;
 991                                 clocks = <&cru ACLK_GPU>;
 992                                 pm_qos = <&qos_gpu>;
 993                         };
 994
 995                         /* These power domains are grouped by VD_LOGIC */
 996                         pd_edp@RK3399_PD_EDP {
 997                                 reg = <RK3399_PD_EDP>;
 998                                 clocks = <&cru PCLK_EDP_CTRL>;
 999                         };
1000                         pd_emmc@RK3399_PD_EMMC {
1001                                 reg = <RK3399_PD_EMMC>;
1002                                 clocks = <&cru ACLK_EMMC>;
1003                                 pm_qos = <&qos_emmc>;
1004                         };
1005                         pd_gmac@RK3399_PD_GMAC {
1006                                 reg = <RK3399_PD_GMAC>;
1007                                 clocks = <&cru ACLK_GMAC>,
1008                                          <&cru PCLK_GMAC>;
1009                                 pm_qos = <&qos_gmac>;
1010                         };
1011                         pd_perihp@RK3399_PD_PERIHP {
1012                                 reg = <RK3399_PD_PERIHP>;
1013                                 #address-cells = <1>;
1014                                 #size-cells = <0>;
1015                                 clocks = <&cru ACLK_PERIHP>;
1016                                 pm_qos = <&qos_perihp>,
1017                                          <&qos_pcie>,
1018                                          <&qos_usb_host0>,
1019                                          <&qos_usb_host1>;
1020
1021                                 pd_sd@RK3399_PD_SD {
1022                                         reg = <RK3399_PD_SD>;
1023                                         clocks = <&cru HCLK_SDMMC>,
1024                                                  <&cru SCLK_SDMMC>;
1025                                         pm_qos = <&qos_sd>;
1026                                 };
1027                         };
1028                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1029                                 reg = <RK3399_PD_SDIOAUDIO>;
1030                                 clocks = <&cru HCLK_SDIO>;
1031                                 pm_qos = <&qos_sdioaudio>;
1032                         };
1033                         pd_usb3@RK3399_PD_USB3 {
1034                                 reg = <RK3399_PD_USB3>;
1035                                 clocks = <&cru ACLK_USB3>;
1036                                 pm_qos = <&qos_usb_otg0>,
1037                                          <&qos_usb_otg1>;
1038                         };
1039                         pd_vio@RK3399_PD_VIO {
1040                                 reg = <RK3399_PD_VIO>;
1041                                 #address-cells = <1>;
1042                                 #size-cells = <0>;
1043
1044                                 pd_hdcp@RK3399_PD_HDCP {
1045                                         reg = <RK3399_PD_HDCP>;
1046                                         clocks = <&cru ACLK_HDCP>,
1047                                                  <&cru HCLK_HDCP>,
1048                                                  <&cru PCLK_HDCP>;
1049                                         pm_qos = <&qos_hdcp>;
1050                                 };
1051                                 pd_isp0@RK3399_PD_ISP0 {
1052                                         reg = <RK3399_PD_ISP0>;
1053                                         clocks = <&cru ACLK_ISP0>,
1054                                                  <&cru HCLK_ISP0>;
1055                                         pm_qos = <&qos_isp0_m0>,
1056                                                  <&qos_isp0_m1>;
1057                                 };
1058                                 pd_isp1@RK3399_PD_ISP1 {
1059                                         reg = <RK3399_PD_ISP1>;
1060                                         clocks = <&cru ACLK_ISP1>,
1061                                                  <&cru HCLK_ISP1>;
1062                                         pm_qos = <&qos_isp1_m0>,
1063                                                  <&qos_isp1_m1>;
1064                                 };
1065                                 pd_tcpc0@RK3399_PD_TCPC0 {
1066                                         reg = <RK3399_PD_TCPD0>;
1067                                         clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1068                                                  <&cru SCLK_UPHY0_TCPDPHY_REF>;
1069                                 };
1070                                 pd_tcpc1@RK3399_PD_TCPC1 {
1071                                         reg = <RK3399_PD_TCPD1>;
1072                                         clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1073                                                  <&cru SCLK_UPHY1_TCPDPHY_REF>;
1074                                 };
1075                                 pd_vo@RK3399_PD_VO {
1076                                         reg = <RK3399_PD_VO>;
1077                                         #address-cells = <1>;
1078                                         #size-cells = <0>;
1079
1080                                         pd_vopb@RK3399_PD_VOPB {
1081                                                 reg = <RK3399_PD_VOPB>;
1082                                                 clocks = <&cru ACLK_VOP0>,
1083                                                          <&cru HCLK_VOP0>;
1084                                                 pm_qos = <&qos_vop_big_r>,
1085                                                          <&qos_vop_big_w>;
1086                                         };
1087                                         pd_vopl@RK3399_PD_VOPL {
1088                                                 reg = <RK3399_PD_VOPL>;
1089                                                 clocks = <&cru ACLK_VOP1>,
1090                                                          <&cru HCLK_VOP1>;
1091                                                 pm_qos = <&qos_vop_little>;
1092                                         };
1093                                 };
1094                         };
1095                 };
1096         };
1097
1098         pmugrf: syscon@ff320000 {
1099                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1100                 reg = <0x0 0xff320000 0x0 0x1000>;
1101                 #address-cells = <1>;
1102                 #size-cells = <1>;
1103
1104                 pmu_io_domains: io-domains {
1105                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1106                         status = "disabled";
1107                 };
1108
1109                 reboot-mode {
1110                         compatible = "syscon-reboot-mode";
1111                         offset = <0x300>;
1112                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
1113                         mode-charge = <BOOT_CHARGING>;
1114                         mode-fastboot = <BOOT_FASTBOOT>;
1115                         mode-loader = <BOOT_BL_DOWNLOAD>;
1116                         mode-normal = <BOOT_NORMAL>;
1117                         mode-recovery = <BOOT_RECOVERY>;
1118                         mode-ums = <BOOT_UMS>;
1119                 };
1120
1121                 pmu_pvtm: pmu-pvtm {
1122                         compatible = "rockchip,rk3399-pmu-pvtm";
1123                         clocks = <&pmucru SCLK_PVTM_PMU>;
1124                         clock-names = "pmu";
1125                         status = "disabled";
1126                 };
1127         };
1128
1129         spi3: spi@ff350000 {
1130                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1131                 reg = <0x0 0xff350000 0x0 0x1000>;
1132                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1133                 clock-names = "spiclk", "apb_pclk";
1134                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1135                 pinctrl-names = "default";
1136                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1137                 #address-cells = <1>;
1138                 #size-cells = <0>;
1139                 status = "disabled";
1140         };
1141
1142         uart4: serial@ff370000 {
1143                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1144                 reg = <0x0 0xff370000 0x0 0x100>;
1145                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1146                 clock-names = "baudclk", "apb_pclk";
1147                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1148                 reg-shift = <2>;
1149                 reg-io-width = <4>;
1150                 pinctrl-names = "default";
1151                 pinctrl-0 = <&uart4_xfer>;
1152                 status = "disabled";
1153         };
1154
1155         i2c4: i2c@ff3d0000 {
1156                 compatible = "rockchip,rk3399-i2c";
1157                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1158                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1159                 clock-names = "i2c", "pclk";
1160                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1161                 pinctrl-names = "default";
1162                 pinctrl-0 = <&i2c4_xfer>;
1163                 #address-cells = <1>;
1164                 #size-cells = <0>;
1165                 status = "disabled";
1166         };
1167
1168         i2c8: i2c@ff3e0000 {
1169                 compatible = "rockchip,rk3399-i2c";
1170                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1171                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1172                 clock-names = "i2c", "pclk";
1173                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1174                 pinctrl-names = "default";
1175                 pinctrl-0 = <&i2c8_xfer>;
1176                 #address-cells = <1>;
1177                 #size-cells = <0>;
1178                 status = "disabled";
1179         };
1180
1181         pcie_phy: phy@e220 {
1182                 compatible = "rockchip,rk3399-pcie-phy";
1183                 #phy-cells = <0>;
1184                 rockchip,grf = <&grf>;
1185                 clocks = <&cru SCLK_PCIEPHY_REF>;
1186                 clock-names = "refclk";
1187                 resets = <&cru SRST_PCIEPHY>;
1188                 reset-names = "phy";
1189                 status = "disabled";
1190         };
1191
1192         pcie0: pcie@f8000000 {
1193                 compatible = "rockchip,rk3399-pcie";
1194                 #address-cells = <3>;
1195                 #size-cells = <2>;
1196                 aspm-no-l0s;
1197                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
1198                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
1199                 clock-names = "aclk", "aclk-perf",
1200                               "hclk", "pm";
1201                 bus-range = <0x0 0x1>;
1202                 max-link-speed = <1>;
1203                 linux,pci-domain = <0>;
1204                 msi-map = <0x0 &its 0x0 0x1000>;
1205                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
1206                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
1207                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
1208                 interrupt-names = "sys", "legacy", "client";
1209                 #interrupt-cells = <1>;
1210                 interrupt-map-mask = <0 0 0 7>;
1211                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
1212                                 <0 0 0 2 &pcie0_intc 1>,
1213                                 <0 0 0 3 &pcie0_intc 2>,
1214                                 <0 0 0 4 &pcie0_intc 3>;
1215                 phys = <&pcie_phy>;
1216                 phy-names = "pcie-phy";
1217                 ranges = <0x82000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
1218                           0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
1219                 reg = <0x0 0xf8000000 0x0 0x2000000>,
1220                       <0x0 0xfd000000 0x0 0x1000000>;
1221                 reg-names = "axi-base", "apb-base";
1222                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
1223                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
1224                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
1225                          <&cru SRST_A_PCIE>;
1226                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
1227                               "pm", "pclk", "aclk";
1228                 status = "disabled";
1229                 pcie0_intc: interrupt-controller {
1230                         interrupt-controller;
1231                         #address-cells = <0>;
1232                         #interrupt-cells = <1>;
1233                 };
1234         };
1235
1236         pwm0: pwm@ff420000 {
1237                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1238                 reg = <0x0 0xff420000 0x0 0x10>;
1239                 #pwm-cells = <3>;
1240                 pinctrl-names = "default";
1241                 pinctrl-0 = <&pwm0_pin>;
1242                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1243                 clock-names = "pwm";
1244                 status = "disabled";
1245         };
1246
1247         pwm1: pwm@ff420010 {
1248                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1249                 reg = <0x0 0xff420010 0x0 0x10>;
1250                 #pwm-cells = <3>;
1251                 pinctrl-names = "default";
1252                 pinctrl-0 = <&pwm1_pin>;
1253                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1254                 clock-names = "pwm";
1255                 status = "disabled";
1256         };
1257
1258         pwm2: pwm@ff420020 {
1259                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1260                 reg = <0x0 0xff420020 0x0 0x10>;
1261                 #pwm-cells = <3>;
1262                 pinctrl-names = "default";
1263                 pinctrl-0 = <&pwm2_pin>;
1264                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1265                 clock-names = "pwm";
1266                 status = "disabled";
1267         };
1268
1269         pwm3: pwm@ff420030 {
1270                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1271                 reg = <0x0 0xff420030 0x0 0x10>;
1272                 #pwm-cells = <3>;
1273                 pinctrl-names = "default";
1274                 pinctrl-0 = <&pwm3a_pin>;
1275                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1276                 clock-names = "pwm";
1277                 status = "disabled";
1278         };
1279
1280         dfi: dfi@ff630000 {
1281                 reg = <0x00 0xff630000 0x00 0x4000>;
1282                 compatible = "rockchip,rk3399-dfi";
1283                 rockchip,pmu = <&pmugrf>;
1284                 clocks = <&cru PCLK_DDR_MON>;
1285                 clock-names = "pclk_ddr_mon";
1286                 status = "disabled";
1287         };
1288
1289         dmc: dmc {
1290                 compatible = "rockchip,rk3399-dmc";
1291                 devfreq-events = <&dfi>;
1292                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
1293                 clocks = <&cru SCLK_DDRCLK>;
1294                 clock-names = "dmc_clk";
1295                 ddr_timing = <&ddr_timing>;
1296                 status = "disabled";
1297         };
1298
1299         vpu: vpu_service@ff650000 {
1300                 compatible = "rockchip,vpu_service";
1301                 rockchip,grf = <&grf>;
1302                 iommus = <&vpu_mmu>;
1303                 iommu_enabled = <1>;
1304                 reg = <0x0 0xff650000 0x0 0x800>;
1305                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
1306                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
1307                 interrupt-names = "irq_dec", "irq_enc";
1308                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1309                 clock-names = "aclk_vcodec", "hclk_vcodec";
1310                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
1311                 reset-names = "video_h", "video_a";
1312                 power-domains = <&power RK3399_PD_VCODEC>;
1313                 name = "vpu_service";
1314                 dev_mode = <0>;
1315                 /* 0 means ion, 1 means drm */
1316                 allocator = <1>;
1317                 status = "disabled";
1318         };
1319
1320         vpu_mmu: iommu@ff650800 {
1321                 compatible = "rockchip,iommu";
1322                 reg = <0x0 0xff650800 0x0 0x40>;
1323                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1324                 interrupt-names = "vpu_mmu";
1325                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1326                 clock-names = "aclk", "hclk";
1327                 power-domains = <&power RK3399_PD_VCODEC>;
1328                 #iommu-cells = <0>;
1329         };
1330
1331         rkvdec: rkvdec@ff660000 {
1332                 compatible = "rockchip,rkvdec";
1333                 rockchip,grf = <&grf>;
1334                 iommus = <&vdec_mmu>;
1335                 iommu_enabled = <1>;
1336                 reg = <0x0 0xff660000 0x0 0x400>;
1337                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1338                 interrupt-names = "irq_dec";
1339                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1340                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1341                 clock-names = "aclk_vcodec", "hclk_vcodec",
1342                               "clk_cabac", "clk_core";
1343                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
1344                 reset-names = "video_h", "video_a";
1345                 power-domains = <&power RK3399_PD_VDU>;
1346                 dev_mode = <2>;
1347                 name = "rkvdec";
1348                 /* 0 means ion, 1 means drm */
1349                 allocator = <1>;
1350                 status = "disabled";
1351         };
1352
1353         vdec_mmu: iommu@ff660480 {
1354                 compatible = "rockchip,iommu";
1355                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1356                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1357                 interrupt-names = "vdec_mmu";
1358                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1359                 clock-names = "aclk", "hclk";
1360                 power-domains = <&power RK3399_PD_VDU>;
1361                 #iommu-cells = <0>;
1362         };
1363
1364         iep: iep@ff670000 {
1365                 compatible = "rockchip,iep";
1366                 iommu_enabled = <1>;
1367                 iommus = <&iep_mmu>;
1368                 reg = <0x0 0xff670000 0x0 0x800>;
1369                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1370                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1371                 clock-names = "aclk_iep", "hclk_iep";
1372                 power-domains = <&power RK3399_PD_IEP>;
1373                 allocator = <1>;
1374                 version = <2>;
1375                 status = "disabled";
1376         };
1377
1378         iep_mmu: iommu@ff670800 {
1379                 compatible = "rockchip,iommu";
1380                 reg = <0x0 0xff670800 0x0 0x40>;
1381                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1382                 interrupt-names = "iep_mmu";
1383                 #iommu-cells = <0>;
1384                 status = "disabled";
1385         };
1386
1387         rga: rga@ff680000 {
1388                 compatible = "rockchip,rk3399-rga";
1389                 reg = <0x0 0xff680000 0x0 0x10000>;
1390                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1391                 interrupt-names = "rga";
1392                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1393                 clock-names = "aclk", "hclk", "sclk";
1394                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1395                 reset-names = "core", "axi", "ahb";
1396                 power-domains = <&power RK3399_PD_RGA>;
1397                 status = "disabled";
1398         };
1399
1400         efuse0: efuse@ff690000 {
1401                 compatible = "rockchip,rk3399-efuse";
1402                 reg = <0x0 0xff690000 0x0 0x80>;
1403                 #address-cells = <1>;
1404                 #size-cells = <1>;
1405                 clocks = <&cru PCLK_EFUSE1024NS>;
1406                 clock-names = "pclk_efuse";
1407
1408                 /* Data cells */
1409                 cpul_leakage: cpul-leakage {
1410                         reg = <0x1a 0x1>;
1411                 };
1412                 cpub_leakage: cpub-leakage {
1413                         reg = <0x17 0x1>;
1414                 };
1415                 gpu_leakage: gpu-leakage {
1416                         reg = <0x18 0x1>;
1417                 };
1418                 center_leakage: center-leakage {
1419                         reg = <0x19 0x1>;
1420                 };
1421                 logic_leakage: logic-leakage {
1422                         reg = <0x1b 0x1>;
1423                 };
1424                 wafer_info: wafer-info {
1425                         reg = <0x1c 0x1>;
1426                 };
1427         };
1428
1429         pmucru: pmu-clock-controller@ff750000 {
1430                 compatible = "rockchip,rk3399-pmucru";
1431                 reg = <0x0 0xff750000 0x0 0x1000>;
1432                 #clock-cells = <1>;
1433                 #reset-cells = <1>;
1434                 assigned-clocks = <&pmucru PLL_PPLL>;
1435                 assigned-clock-rates = <676000000>;
1436         };
1437
1438         cru: clock-controller@ff760000 {
1439                 compatible = "rockchip,rk3399-cru";
1440                 reg = <0x0 0xff760000 0x0 0x1000>;
1441                 #clock-cells = <1>;
1442                 #reset-cells = <1>;
1443                 assigned-clocks =
1444                         <&cru ACLK_VOP0>, <&cru HCLK_VOP0>,
1445                         <&cru ACLK_VOP1>, <&cru HCLK_VOP1>,
1446                         <&cru ARMCLKL>, <&cru ARMCLKB>,
1447                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1448                         <&cru ACLK_GPU>, <&cru PLL_NPLL>,
1449                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1450                         <&cru PCLK_PERIHP>,
1451                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1452                         <&cru PCLK_PERILP0>,
1453                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>;
1454                 assigned-clock-rates =
1455                          <400000000>,  <200000000>,
1456                          <400000000>,  <200000000>,
1457                          <816000000>, <816000000>,
1458                          <594000000>,  <800000000>,
1459                          <200000000>, <1000000000>,
1460                          <150000000>,   <75000000>,
1461                           <37500000>,
1462                          <100000000>,  <100000000>,
1463                           <50000000>,
1464                          <100000000>,   <50000000>;
1465         };
1466
1467         grf: syscon@ff770000 {
1468                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1469                 reg = <0x0 0xff770000 0x0 0x10000>;
1470                 #address-cells = <1>;
1471                 #size-cells = <1>;
1472
1473                 io_domains: io-domains {
1474                         compatible = "rockchip,rk3399-io-voltage-domain";
1475                         status = "disabled";
1476                 };
1477
1478                 emmc_phy: phy@f780 {
1479                         compatible = "rockchip,rk3399-emmc-phy";
1480                         reg = <0xf780 0x24>;
1481                         clocks = <&sdhci>;
1482                         clock-names = "emmcclk";
1483                         #phy-cells = <0>;
1484                         status = "disabled";
1485                 };
1486
1487                 u2phy0: usb2-phy@e450 {
1488                         compatible = "rockchip,rk3399-usb2phy";
1489                         reg = <0xe450 0x10>;
1490                         clocks = <&cru SCLK_USB2PHY0_REF>;
1491                         clock-names = "phyclk";
1492                         #clock-cells = <0>;
1493                         clock-output-names = "clk_usbphy0_480m";
1494                         status = "disabled";
1495
1496                         u2phy0_otg: otg-port {
1497                                 #phy-cells = <0>;
1498                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1499                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1500                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1501                                 interrupt-names = "otg-bvalid", "otg-id",
1502                                                   "linestate";
1503                                 status = "disabled";
1504                         };
1505
1506                         u2phy0_host: host-port {
1507                                 #phy-cells = <0>;
1508                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1509                                 interrupt-names = "linestate";
1510                                 status = "disabled";
1511                         };
1512                 };
1513
1514                 u2phy1: usb2-phy@e460 {
1515                         compatible = "rockchip,rk3399-usb2phy";
1516                         reg = <0xe460 0x10>;
1517                         clocks = <&cru SCLK_USB2PHY1_REF>;
1518                         clock-names = "phyclk";
1519                         #clock-cells = <0>;
1520                         clock-output-names = "clk_usbphy1_480m";
1521                         status = "disabled";
1522
1523                         u2phy1_otg: otg-port {
1524                                 #phy-cells = <0>;
1525                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1526                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1527                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1528                                 interrupt-names = "otg-bvalid", "otg-id",
1529                                                   "linestate";
1530                                 status = "disabled";
1531                         };
1532
1533                         u2phy1_host: host-port {
1534                                 #phy-cells = <0>;
1535                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1536                                 interrupt-names = "linestate";
1537                                 status = "disabled";
1538                         };
1539                 };
1540
1541                 pvtm: pvtm {
1542                         compatible = "rockchip,rk3399-pvtm";
1543                         clocks = <&cru SCLK_PVTM_CORE_L>,
1544                                  <&cru SCLK_PVTM_CORE_B>,
1545                                  <&cru SCLK_PVTM_GPU>,
1546                                  <&cru SCLK_PVTM_DDR>;
1547                         clock-names = "core_l", "core_b", "gpu", "ddr";
1548                         status = "disabled";
1549                 };
1550         };
1551
1552         tcphy0: phy@ff7c0000 {
1553                 compatible = "rockchip,rk3399-typec-phy";
1554                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1555                 rockchip,grf = <&grf>;
1556                 #phy-cells = <1>;
1557                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1558                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1559                 clock-names = "tcpdcore", "tcpdphy-ref";
1560                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1561                 assigned-clock-rates = <50000000>;
1562                 power-domains = <&power RK3399_PD_TCPD0>;
1563                 resets = <&cru SRST_UPHY0>,
1564                          <&cru SRST_UPHY0_PIPE_L00>,
1565                          <&cru SRST_P_UPHY0_TCPHY>;
1566                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1567                 rockchip,typec-conn-dir = <0xe580 0 16>;
1568                 rockchip,usb3tousb2-en = <0xe580 3 19>;
1569                 rockchip,usb3-host-disable = <0x2434 0 16>;
1570                 rockchip,usb3-host-port = <0x2434 12 28>;
1571                 rockchip,external-psm = <0xe588 14 30>;
1572                 rockchip,pipe-status = <0xe5c0 0 0>;
1573                 rockchip,uphy-dp-sel = <0x6268 19 19>;
1574                 status = "disabled";
1575
1576                 tcphy0_dp: dp-port {
1577                         #phy-cells = <0>;
1578                 };
1579
1580                 tcphy0_usb3: usb3-port {
1581                         #phy-cells = <0>;
1582                 };
1583         };
1584
1585         tcphy1: phy@ff800000 {
1586                 compatible = "rockchip,rk3399-typec-phy";
1587                 reg = <0x0 0xff800000 0x0 0x40000>;
1588                 rockchip,grf = <&grf>;
1589                 #phy-cells = <1>;
1590                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1591                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1592                 clock-names = "tcpdcore", "tcpdphy-ref";
1593                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1594                 assigned-clock-rates = <50000000>;
1595                 power-domains = <&power RK3399_PD_TCPD1>;
1596                 resets = <&cru SRST_UPHY1>,
1597                          <&cru SRST_UPHY1_PIPE_L00>,
1598                          <&cru SRST_P_UPHY1_TCPHY>;
1599                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1600                 rockchip,typec-conn-dir = <0xe58c 0 16>;
1601                 rockchip,usb3tousb2-en = <0xe58c 3 19>;
1602                 rockchip,usb3-host-disable = <0x2444 0 16>;
1603                 rockchip,usb3-host-port = <0x2444 12 28>;
1604                 rockchip,external-psm = <0xe594 14 30>;
1605                 rockchip,pipe-status = <0xe5c0 16 16>;
1606                 rockchip,uphy-dp-sel = <0x6268 3 19>;
1607                 status = "disabled";
1608
1609                 tcphy1_dp: dp-port {
1610                         #phy-cells = <0>;
1611                 };
1612
1613                 tcphy1_usb3: usb3-port {
1614                         #phy-cells = <0>;
1615                 };
1616         };
1617
1618         watchdog@ff848000 {
1619                 compatible = "snps,dw-wdt";
1620                 reg = <0x0 0xff848000 0x0 0x100>;
1621                 clocks = <&cru PCLK_WDT>;
1622                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1623         };
1624
1625         rktimer: rktimer@ff850000 {
1626                 compatible = "rockchip,rk3399-timer";
1627                 reg = <0x0 0xff850000 0x0 0x1000>;
1628                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1629                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1630                 clock-names = "pclk", "timer";
1631         };
1632
1633         spdif: spdif@ff870000 {
1634                 compatible = "rockchip,rk3399-spdif";
1635                 reg = <0x0 0xff870000 0x0 0x1000>;
1636                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1637                 dmas = <&dmac_bus 7>;
1638                 dma-names = "tx";
1639                 clock-names = "mclk", "hclk";
1640                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1641                 pinctrl-names = "default";
1642                 pinctrl-0 = <&spdif_bus>;
1643                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1644                 status = "disabled";
1645         };
1646
1647         i2s0: i2s@ff880000 {
1648                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1649                 reg = <0x0 0xff880000 0x0 0x1000>;
1650                 rockchip,grf = <&grf>;
1651                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1652                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1653                 dma-names = "tx", "rx";
1654                 clock-names = "i2s_clk", "i2s_hclk";
1655                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1656                 pinctrl-names = "default";
1657                 pinctrl-0 = <&i2s0_8ch_bus>;
1658                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1659                 status = "disabled";
1660         };
1661
1662         i2s1: i2s@ff890000 {
1663                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1664                 reg = <0x0 0xff890000 0x0 0x1000>;
1665                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1666                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1667                 dma-names = "tx", "rx";
1668                 clock-names = "i2s_clk", "i2s_hclk";
1669                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1670                 pinctrl-names = "default";
1671                 pinctrl-0 = <&i2s1_2ch_bus>;
1672                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1673                 status = "disabled";
1674         };
1675
1676         i2s2: i2s@ff8a0000 {
1677                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1678                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1679                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1680                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1681                 dma-names = "tx", "rx";
1682                 clock-names = "i2s_clk", "i2s_hclk";
1683                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1684                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1685                 status = "disabled";
1686         };
1687
1688         gpu: gpu@ff9a0000 {
1689                 compatible = "arm,malit860",
1690                              "arm,malit86x",
1691                              "arm,malit8xx",
1692                              "arm,mali-midgard";
1693
1694                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1695
1696                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>,
1697                              <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1698                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>;
1699                 interrupt-names = "GPU", "JOB", "MMU";
1700
1701                 clocks = <&cru ACLK_GPU>;
1702                 clock-names = "clk_mali";
1703                 #cooling-cells = <2>; /* min followed by max */
1704                 power-domains = <&power RK3399_PD_GPU>;
1705                 power-off-delay-ms = <200>;
1706                 status = "disabled";
1707
1708                 gpu_power_model: power_model {
1709                         compatible = "arm,mali-simple-power-model";
1710                         voltage = <900>;
1711                         frequency = <500>;
1712                         static-power = <300>;
1713                         dynamic-power = <396>;
1714                         ts = <32000 4700 (-80) 2>;
1715                         thermal-zone = "gpu-thermal";
1716                 };
1717         };
1718
1719         vopl: vop@ff8f0000 {
1720                 compatible = "rockchip,rk3399-vop-lit";
1721                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1722                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1723                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1724                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1725                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1726                 reset-names = "axi", "ahb", "dclk";
1727                 power-domains = <&power RK3399_PD_VOPL>;
1728                 iommus = <&vopl_mmu>;
1729                 status = "disabled";
1730
1731                 vopl_out: port {
1732                         #address-cells = <1>;
1733                         #size-cells = <0>;
1734
1735                         vopl_out_mipi: endpoint@0 {
1736                                 reg = <0>;
1737                                 remote-endpoint = <&mipi_in_vopl>;
1738                         };
1739
1740                         vopl_out_edp: endpoint@1 {
1741                                 reg = <1>;
1742                                 remote-endpoint = <&edp_in_vopl>;
1743                         };
1744
1745                         vopl_out_hdmi: endpoint@2 {
1746                                 reg = <2>;
1747                                 remote-endpoint = <&hdmi_in_vopl>;
1748                         };
1749
1750                         vopl_out_dp: endpoint@3 {
1751                                 reg = <3>;
1752                                 remote-endpoint = <&dp_in_vopl>;
1753                         };
1754                 };
1755         };
1756
1757         vop1_pwm: voppwm@ff8f01a0 {
1758                 compatible = "rockchip,vop-pwm";
1759                 reg = <0x0 0xff8f01a0 0x0 0x10>;
1760                 #pwm-cells = <3>;
1761                 pinctrl-names = "default";
1762                 pinctrl-0 = <&vop1_pwm_pin>;
1763                 clocks = <&cru SCLK_VOP1_PWM>;
1764                 clock-names = "pwm";
1765                 status = "disabled";
1766         };
1767
1768         vopl_mmu: iommu@ff8f3f00 {
1769                 compatible = "rockchip,iommu";
1770                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1771                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1772                 interrupt-names = "vopl_mmu";
1773                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1774                 clock-names = "aclk", "hclk";
1775                 power-domains = <&power RK3399_PD_VOPL>;
1776                 #iommu-cells = <0>;
1777                 status = "disabled";
1778         };
1779
1780         vopb: vop@ff900000 {
1781                 compatible = "rockchip,rk3399-vop-big";
1782                 reg = <0x0 0xff900000 0x0 0x3efc>;
1783                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1784                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1785                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1786                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1787                 reset-names = "axi", "ahb", "dclk";
1788                 power-domains = <&power RK3399_PD_VOPB>;
1789                 iommus = <&vopb_mmu>;
1790                 status = "disabled";
1791
1792                 vopb_out: port {
1793                         #address-cells = <1>;
1794                         #size-cells = <0>;
1795
1796                         vopb_out_edp: endpoint@0 {
1797                                 reg = <0>;
1798                                 remote-endpoint = <&edp_in_vopb>;
1799                         };
1800
1801                         vopb_out_mipi: endpoint@1 {
1802                                 reg = <1>;
1803                                 remote-endpoint = <&mipi_in_vopb>;
1804                         };
1805
1806                         vopb_out_hdmi: endpoint@2 {
1807                                 reg = <2>;
1808                                 remote-endpoint = <&hdmi_in_vopb>;
1809                         };
1810
1811                         vopb_out_dp: endpoint@3 {
1812                                 reg = <3>;
1813                                 remote-endpoint = <&dp_in_vopb>;
1814                         };
1815                 };
1816         };
1817
1818         vop0_pwm: voppwm@ff9001a0 {
1819                 compatible = "rockchip,vop-pwm";
1820                 reg = <0x0 0xff9001a0 0x0 0x10>;
1821                 #pwm-cells = <3>;
1822                 pinctrl-names = "default";
1823                 pinctrl-0 = <&vop0_pwm_pin>;
1824                 clocks = <&cru SCLK_VOP0_PWM>;
1825                 clock-names = "pwm";
1826                 status = "disabled";
1827         };
1828
1829         vopb_mmu: iommu@ff903f00 {
1830                 compatible = "rockchip,iommu";
1831                 reg = <0x0 0xff903f00 0x0 0x100>;
1832                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1833                 interrupt-names = "vopb_mmu";
1834                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1835                 clock-names = "aclk", "hclk";
1836                 power-domains = <&power RK3399_PD_VOPB>;
1837                 #iommu-cells = <0>;
1838                 status = "disabled";
1839         };
1840
1841         isp0_mmu: iommu@ff914000 {
1842                 compatible = "rockchip,iommu";
1843                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1844                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1845                 interrupt-names = "isp0_mmu";
1846                 #iommu-cells = <0>;
1847                 clocks = <&cru ACLK_ISP0_NOC>, <&cru HCLK_ISP0_NOC>;
1848                 clock-names = "aclk", "hclk";
1849                 power-domains = <&power RK3399_PD_ISP0>;
1850                 rk_iommu,disable_reset_quirk;
1851                 status = "disabled";
1852         };
1853
1854         isp1_mmu: iommu@ff924000 {
1855                 compatible = "rockchip,iommu";
1856                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1857                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1858                 interrupt-names = "isp1_mmu";
1859                 #iommu-cells = <0>;
1860                 clocks = <&cru ACLK_ISP1_NOC>, <&cru HCLK_ISP1_NOC>;
1861                 clock-names = "aclk", "hclk";
1862                 power-domains = <&power RK3399_PD_ISP1>;
1863                 rk_iommu,disable_reset_quirk;
1864                 status = "disabled";
1865         };
1866
1867         hdmi: hdmi@ff940000 {
1868                 compatible = "rockchip,rk3399-dw-hdmi";
1869                 reg = <0x0 0xff940000 0x0 0x20000>;
1870                 reg-io-width = <4>;
1871                 rockchip,grf = <&grf>;
1872                 pinctrl-names = "default";
1873                 pinctrl-0 = <&hdmi_i2c_xfer>;
1874                 power-domains = <&power RK3399_PD_HDCP>;
1875                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1876                 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, <&cru PLL_VPLL>, <&cru PCLK_VIO_GRF>;
1877                 clock-names = "iahb", "isfr", "vpll", "grf";
1878                 status = "disabled";
1879
1880                 ports {
1881                         hdmi_in: port {
1882                                 #address-cells = <1>;
1883                                 #size-cells = <0>;
1884                                 hdmi_in_vopb: endpoint@0 {
1885                                         reg = <0>;
1886                                         remote-endpoint = <&vopb_out_hdmi>;
1887                                 };
1888                                 hdmi_in_vopl: endpoint@1 {
1889                                         reg = <1>;
1890                                         remote-endpoint = <&vopl_out_hdmi>;
1891                                 };
1892                         };
1893                 };
1894         };
1895
1896         mipi_dsi: mipi@ff960000 {
1897                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1898                 reg = <0x0 0xff960000 0x0 0x8000>;
1899                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1900                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>,
1901                          <&cru SCLK_DPHY_TX0_CFG>;
1902                 clock-names = "ref", "pclk", "phy_cfg";
1903                 power-domains = <&power RK3399_PD_VIO>;
1904                 rockchip,grf = <&grf>;
1905                 #address-cells = <1>;
1906                 #size-cells = <0>;
1907                 status = "disabled";
1908
1909                 ports {
1910                         #address-cells = <1>;
1911                         #size-cells = <0>;
1912                         reg = <1>;
1913
1914                         mipi_in: port {
1915                                 #address-cells = <1>;
1916                                 #size-cells = <0>;
1917
1918                                 mipi_in_vopb: endpoint@0 {
1919                                         reg = <0>;
1920                                         remote-endpoint = <&vopb_out_mipi>;
1921                                 };
1922                                 mipi_in_vopl: endpoint@1 {
1923                                         reg = <1>;
1924                                         remote-endpoint = <&vopl_out_mipi>;
1925                                 };
1926                         };
1927                 };
1928         };
1929
1930         edp: edp@ff970000 {
1931                 compatible = "rockchip,rk3399-edp";
1932                 reg = <0x0 0xff970000 0x0 0x8000>;
1933                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1934                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1935                 clock-names = "dp", "pclk";
1936                 power-domains = <&power RK3399_PD_EDP>;
1937                 resets = <&cru SRST_P_EDP_CTRL>;
1938                 reset-names = "dp";
1939                 rockchip,grf = <&grf>;
1940                 status = "disabled";
1941                 pinctrl-names = "default";
1942                 pinctrl-0 = <&edp_hpd>;
1943
1944                 ports {
1945                         #address-cells = <1>;
1946                         #size-cells = <0>;
1947
1948                         edp_in: port@0 {
1949                                 reg = <0>;
1950                                 #address-cells = <1>;
1951                                 #size-cells = <0>;
1952
1953                                 edp_in_vopb: endpoint@0 {
1954                                         reg = <0>;
1955                                         remote-endpoint = <&vopb_out_edp>;
1956                                 };
1957
1958                                 edp_in_vopl: endpoint@1 {
1959                                         reg = <1>;
1960                                         remote-endpoint = <&vopl_out_edp>;
1961                                 };
1962                         };
1963                 };
1964         };
1965
1966         display_subsystem: display-subsystem {
1967                 compatible = "rockchip,display-subsystem";
1968                 ports = <&vopl_out>, <&vopb_out>;
1969                 status = "disabled";
1970         };
1971
1972         pinctrl: pinctrl {
1973                 compatible = "rockchip,rk3399-pinctrl";
1974                 rockchip,grf = <&grf>;
1975                 rockchip,pmu = <&pmugrf>;
1976                 #address-cells = <0x2>;
1977                 #size-cells = <0x2>;
1978                 ranges;
1979
1980                 gpio0: gpio0@ff720000 {
1981                         compatible = "rockchip,gpio-bank";
1982                         reg = <0x0 0xff720000 0x0 0x100>;
1983                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1984                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1985
1986                         gpio-controller;
1987                         #gpio-cells = <0x2>;
1988
1989                         interrupt-controller;
1990                         #interrupt-cells = <0x2>;
1991                 };
1992
1993                 gpio1: gpio1@ff730000 {
1994                         compatible = "rockchip,gpio-bank";
1995                         reg = <0x0 0xff730000 0x0 0x100>;
1996                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1997                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1998
1999                         gpio-controller;
2000                         #gpio-cells = <0x2>;
2001
2002                         interrupt-controller;
2003                         #interrupt-cells = <0x2>;
2004                 };
2005
2006                 gpio2: gpio2@ff780000 {
2007                         compatible = "rockchip,gpio-bank";
2008                         reg = <0x0 0xff780000 0x0 0x100>;
2009                         clocks = <&cru PCLK_GPIO2>;
2010                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
2011
2012                         gpio-controller;
2013                         #gpio-cells = <0x2>;
2014
2015                         interrupt-controller;
2016                         #interrupt-cells = <0x2>;
2017                 };
2018
2019                 gpio3: gpio3@ff788000 {
2020                         compatible = "rockchip,gpio-bank";
2021                         reg = <0x0 0xff788000 0x0 0x100>;
2022                         clocks = <&cru PCLK_GPIO3>;
2023                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
2024
2025                         gpio-controller;
2026                         #gpio-cells = <0x2>;
2027
2028                         interrupt-controller;
2029                         #interrupt-cells = <0x2>;
2030                 };
2031
2032                 gpio4: gpio4@ff790000 {
2033                         compatible = "rockchip,gpio-bank";
2034                         reg = <0x0 0xff790000 0x0 0x100>;
2035                         clocks = <&cru PCLK_GPIO4>;
2036                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2037
2038                         gpio-controller;
2039                         #gpio-cells = <0x2>;
2040
2041                         interrupt-controller;
2042                         #interrupt-cells = <0x2>;
2043                 };
2044
2045                 pcfg_pull_up: pcfg-pull-up {
2046                         bias-pull-up;
2047                 };
2048
2049                 pcfg_pull_down: pcfg-pull-down {
2050                         bias-pull-down;
2051                 };
2052
2053                 pcfg_pull_none: pcfg-pull-none {
2054                         bias-disable;
2055                 };
2056
2057                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2058                         bias-pull-up;
2059                         drive-strength = <20>;
2060                 };
2061
2062                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2063                         bias-disable;
2064                         drive-strength = <20>;
2065                 };
2066
2067                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2068                         bias-disable;
2069                         drive-strength = <18>;
2070                 };
2071
2072                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2073                         bias-disable;
2074                         drive-strength = <12>;
2075                 };
2076
2077                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2078                         bias-pull-up;
2079                         drive-strength = <8>;
2080                 };
2081
2082                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2083                         bias-pull-down;
2084                         drive-strength = <4>;
2085                 };
2086
2087                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2088                         bias-pull-up;
2089                         drive-strength = <2>;
2090                 };
2091
2092                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2093                         bias-pull-down;
2094                         drive-strength = <12>;
2095                 };
2096
2097                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2098                         bias-disable;
2099                         drive-strength = <13>;
2100                 };
2101
2102                 pcfg_output_high: pcfg-output-high {
2103                         output-high;
2104                 };
2105
2106                 pcfg_output_low: pcfg-output-low {
2107                         output-low;
2108                 };
2109
2110                 pcfg_input: pcfg-input {
2111                         input-enable;
2112                 };
2113
2114                 emmc {
2115                         emmc_pwr: emmc-pwr {
2116                                 rockchip,pins =
2117                                         <0 5 RK_FUNC_1 &pcfg_pull_up>;
2118                         };
2119                 };
2120
2121                 gmac {
2122                         rgmii_pins: rgmii-pins {
2123                                 rockchip,pins =
2124                                         /* mac_txclk */
2125                                         <3 17 RK_FUNC_1 &pcfg_pull_none_13ma>,
2126                                         /* mac_rxclk */
2127                                         <3 14 RK_FUNC_1 &pcfg_pull_none>,
2128                                         /* mac_mdio */
2129                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2130                                         /* mac_txen */
2131                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2132                                         /* mac_clk */
2133                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2134                                         /* mac_rxdv */
2135                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2136                                         /* mac_mdc */
2137                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2138                                         /* mac_rxd1 */
2139                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2140                                         /* mac_rxd0 */
2141                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2142                                         /* mac_txd1 */
2143                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2144                                         /* mac_txd0 */
2145                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>,
2146                                         /* mac_rxd3 */
2147                                         <3 3 RK_FUNC_1 &pcfg_pull_none>,
2148                                         /* mac_rxd2 */
2149                                         <3 2 RK_FUNC_1 &pcfg_pull_none>,
2150                                         /* mac_txd3 */
2151                                         <3 1 RK_FUNC_1 &pcfg_pull_none_13ma>,
2152                                         /* mac_txd2 */
2153                                         <3 0 RK_FUNC_1 &pcfg_pull_none_13ma>;
2154                         };
2155
2156                         rmii_pins: rmii-pins {
2157                                 rockchip,pins =
2158                                         /* mac_mdio */
2159                                         <3 13 RK_FUNC_1 &pcfg_pull_none>,
2160                                         /* mac_txen */
2161                                         <3 12 RK_FUNC_1 &pcfg_pull_none_13ma>,
2162                                         /* mac_clk */
2163                                         <3 11 RK_FUNC_1 &pcfg_pull_none>,
2164                                         /* mac_rxer */
2165                                         <3 10 RK_FUNC_1 &pcfg_pull_none>,
2166                                         /* mac_rxdv */
2167                                         <3 9 RK_FUNC_1 &pcfg_pull_none>,
2168                                         /* mac_mdc */
2169                                         <3 8 RK_FUNC_1 &pcfg_pull_none>,
2170                                         /* mac_rxd1 */
2171                                         <3 7 RK_FUNC_1 &pcfg_pull_none>,
2172                                         /* mac_rxd0 */
2173                                         <3 6 RK_FUNC_1 &pcfg_pull_none>,
2174                                         /* mac_txd1 */
2175                                         <3 5 RK_FUNC_1 &pcfg_pull_none_13ma>,
2176                                         /* mac_txd0 */
2177                                         <3 4 RK_FUNC_1 &pcfg_pull_none_13ma>;
2178                         };
2179                 };
2180
2181                 i2c0 {
2182                         i2c0_xfer: i2c0-xfer {
2183                                 rockchip,pins =
2184                                         <1 15 RK_FUNC_2 &pcfg_pull_none>,
2185                                         <1 16 RK_FUNC_2 &pcfg_pull_none>;
2186                         };
2187                 };
2188
2189                 i2c1 {
2190                         i2c1_xfer: i2c1-xfer {
2191                                 rockchip,pins =
2192                                         <4 2 RK_FUNC_1 &pcfg_pull_none>,
2193                                         <4 1 RK_FUNC_1 &pcfg_pull_none>;
2194                         };
2195                 };
2196
2197                 i2c2 {
2198                         i2c2_xfer: i2c2-xfer {
2199                                 rockchip,pins =
2200                                         <2 1 RK_FUNC_2 &pcfg_pull_none_12ma>,
2201                                         <2 0 RK_FUNC_2 &pcfg_pull_none_12ma>;
2202                         };
2203                 };
2204
2205                 i2c3 {
2206                         i2c3_xfer: i2c3-xfer {
2207                                 rockchip,pins =
2208                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
2209                                         <4 16 RK_FUNC_1 &pcfg_pull_none>;
2210                         };
2211
2212                         i2c3_gpio: i2c3_gpio {
2213                                 rockchip,pins =
2214                                         <4 17 RK_FUNC_GPIO &pcfg_pull_none>,
2215                                         <4 16 RK_FUNC_GPIO &pcfg_pull_none>;
2216                         };
2217
2218                 };
2219
2220                 i2c4 {
2221                         i2c4_xfer: i2c4-xfer {
2222                                 rockchip,pins =
2223                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,
2224                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
2225                         };
2226                 };
2227
2228                 i2c5 {
2229                         i2c5_xfer: i2c5-xfer {
2230                                 rockchip,pins =
2231                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
2232                                         <3 10 RK_FUNC_2 &pcfg_pull_none>;
2233                         };
2234                 };
2235
2236                 i2c6 {
2237                         i2c6_xfer: i2c6-xfer {
2238                                 rockchip,pins =
2239                                         <2 10 RK_FUNC_2 &pcfg_pull_none>,
2240                                         <2 9 RK_FUNC_2 &pcfg_pull_none>;
2241                         };
2242                 };
2243
2244                 i2c7 {
2245                         i2c7_xfer: i2c7-xfer {
2246                                 rockchip,pins =
2247                                         <2 8 RK_FUNC_2 &pcfg_pull_none>,
2248                                         <2 7 RK_FUNC_2 &pcfg_pull_none>;
2249                         };
2250                 };
2251
2252                 i2c8 {
2253                         i2c8_xfer: i2c8-xfer {
2254                                 rockchip,pins =
2255                                         <1 21 RK_FUNC_1 &pcfg_pull_none>,
2256                                         <1 20 RK_FUNC_1 &pcfg_pull_none>;
2257                         };
2258                 };
2259
2260                 i2s0 {
2261                         i2s0_8ch_bus: i2s0-8ch-bus {
2262                                 rockchip,pins =
2263                                         <3 24 RK_FUNC_1 &pcfg_pull_none>,
2264                                         <3 25 RK_FUNC_1 &pcfg_pull_none>,
2265                                         <3 26 RK_FUNC_1 &pcfg_pull_none>,
2266                                         <3 27 RK_FUNC_1 &pcfg_pull_none>,
2267                                         <3 28 RK_FUNC_1 &pcfg_pull_none>,
2268                                         <3 29 RK_FUNC_1 &pcfg_pull_none>,
2269                                         <3 30 RK_FUNC_1 &pcfg_pull_none>,
2270                                         <3 31 RK_FUNC_1 &pcfg_pull_none>,
2271                                         <4 0 RK_FUNC_1 &pcfg_pull_none>;
2272                         };
2273                 };
2274
2275                 i2s1 {
2276                         i2s1_2ch_bus: i2s1-2ch-bus {
2277                                 rockchip,pins =
2278                                         <4 3 RK_FUNC_1 &pcfg_pull_none>,
2279                                         <4 4 RK_FUNC_1 &pcfg_pull_none>,
2280                                         <4 5 RK_FUNC_1 &pcfg_pull_none>,
2281                                         <4 6 RK_FUNC_1 &pcfg_pull_none>,
2282                                         <4 7 RK_FUNC_1 &pcfg_pull_none>;
2283                         };
2284                 };
2285
2286                 sdio0 {
2287                         sdio0_bus1: sdio0-bus1 {
2288                                 rockchip,pins =
2289                                         <2 20 RK_FUNC_1 &pcfg_pull_up>;
2290                         };
2291
2292                         sdio0_bus4: sdio0-bus4 {
2293                                 rockchip,pins =
2294                                         <2 20 RK_FUNC_1 &pcfg_pull_up>,
2295                                         <2 21 RK_FUNC_1 &pcfg_pull_up>,
2296                                         <2 22 RK_FUNC_1 &pcfg_pull_up>,
2297                                         <2 23 RK_FUNC_1 &pcfg_pull_up>;
2298                         };
2299
2300                         sdio0_cmd: sdio0-cmd {
2301                                 rockchip,pins =
2302                                         <2 24 RK_FUNC_1 &pcfg_pull_up>;
2303                         };
2304
2305                         sdio0_clk: sdio0-clk {
2306                                 rockchip,pins =
2307                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
2308                         };
2309
2310                         sdio0_cd: sdio0-cd {
2311                                 rockchip,pins =
2312                                         <2 26 RK_FUNC_1 &pcfg_pull_up>;
2313                         };
2314
2315                         sdio0_pwr: sdio0-pwr {
2316                                 rockchip,pins =
2317                                         <2 27 RK_FUNC_1 &pcfg_pull_up>;
2318                         };
2319
2320                         sdio0_bkpwr: sdio0-bkpwr {
2321                                 rockchip,pins =
2322                                         <2 28 RK_FUNC_1 &pcfg_pull_up>;
2323                         };
2324
2325                         sdio0_wp: sdio0-wp {
2326                                 rockchip,pins =
2327                                         <0 3 RK_FUNC_1 &pcfg_pull_up>;
2328                         };
2329
2330                         sdio0_int: sdio0-int {
2331                                 rockchip,pins =
2332                                         <0 4 RK_FUNC_1 &pcfg_pull_up>;
2333                         };
2334                 };
2335
2336                 sdmmc {
2337                         sdmmc_bus1: sdmmc-bus1 {
2338                                 rockchip,pins =
2339                                         <4 8 RK_FUNC_1 &pcfg_pull_up>;
2340                         };
2341
2342                         sdmmc_bus4: sdmmc-bus4 {
2343                                 rockchip,pins =
2344                                         <4 8 RK_FUNC_1 &pcfg_pull_up>,
2345                                         <4 9 RK_FUNC_1 &pcfg_pull_up>,
2346                                         <4 10 RK_FUNC_1 &pcfg_pull_up>,
2347                                         <4 11 RK_FUNC_1 &pcfg_pull_up>;
2348                         };
2349
2350                         sdmmc_clk: sdmmc-clk {
2351                                 rockchip,pins =
2352                                         <4 12 RK_FUNC_1 &pcfg_pull_none>;
2353                         };
2354
2355                         sdmmc_cmd: sdmmc-cmd {
2356                                 rockchip,pins =
2357                                         <4 13 RK_FUNC_1 &pcfg_pull_up>;
2358                         };
2359
2360                         sdmmc_cd: sdmcc-cd {
2361                                 rockchip,pins =
2362                                         <0 7 RK_FUNC_1 &pcfg_pull_up>;
2363                         };
2364
2365                         sdmmc_wp: sdmmc-wp {
2366                                 rockchip,pins =
2367                                         <0 8 RK_FUNC_1 &pcfg_pull_up>;
2368                         };
2369                 };
2370
2371                 spdif {
2372                         spdif_bus: spdif-bus {
2373                                 rockchip,pins =
2374                                         <4 21 RK_FUNC_1 &pcfg_pull_none>;
2375                         };
2376
2377                         spdif_bus_1: spdif-bus-1 {
2378                                 rockchip,pins =
2379                                         <3 16 RK_FUNC_3 &pcfg_pull_none>;
2380                         };
2381                 };
2382
2383                 spi0 {
2384                         spi0_clk: spi0-clk {
2385                                 rockchip,pins =
2386                                         <3 6 RK_FUNC_2 &pcfg_pull_up>;
2387                         };
2388                         spi0_cs0: spi0-cs0 {
2389                                 rockchip,pins =
2390                                         <3 7 RK_FUNC_2 &pcfg_pull_up>;
2391                         };
2392                         spi0_cs1: spi0-cs1 {
2393                                 rockchip,pins =
2394                                         <3 8 RK_FUNC_2 &pcfg_pull_up>;
2395                         };
2396                         spi0_tx: spi0-tx {
2397                                 rockchip,pins =
2398                                         <3 5 RK_FUNC_2 &pcfg_pull_up>;
2399                         };
2400                         spi0_rx: spi0-rx {
2401                                 rockchip,pins =
2402                                         <3 4 RK_FUNC_2 &pcfg_pull_up>;
2403                         };
2404                 };
2405
2406                 spi1 {
2407                         spi1_clk: spi1-clk {
2408                                 rockchip,pins =
2409                                         <1 9 RK_FUNC_2 &pcfg_pull_up>;
2410                         };
2411                         spi1_cs0: spi1-cs0 {
2412                                 rockchip,pins =
2413                                         <1 10 RK_FUNC_2 &pcfg_pull_up>;
2414                         };
2415                         spi1_rx: spi1-rx {
2416                                 rockchip,pins =
2417                                         <1 7 RK_FUNC_2 &pcfg_pull_up>;
2418                         };
2419                         spi1_tx: spi1-tx {
2420                                 rockchip,pins =
2421                                         <1 8 RK_FUNC_2 &pcfg_pull_up>;
2422                         };
2423                 };
2424
2425                 spi2 {
2426                         spi2_clk: spi2-clk {
2427                                 rockchip,pins =
2428                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
2429                         };
2430                         spi2_cs0: spi2-cs0 {
2431                                 rockchip,pins =
2432                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
2433                         };
2434                         spi2_rx: spi2-rx {
2435                                 rockchip,pins =
2436                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
2437                         };
2438                         spi2_tx: spi2-tx {
2439                                 rockchip,pins =
2440                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
2441                         };
2442                 };
2443
2444                 spi3 {
2445                         spi3_clk: spi3-clk {
2446                                 rockchip,pins =
2447                                         <1 17 RK_FUNC_1 &pcfg_pull_up>;
2448                         };
2449                         spi3_cs0: spi3-cs0 {
2450                                 rockchip,pins =
2451                                         <1 18 RK_FUNC_1 &pcfg_pull_up>;
2452                         };
2453                         spi3_rx: spi3-rx {
2454                                 rockchip,pins =
2455                                         <1 15 RK_FUNC_1 &pcfg_pull_up>;
2456                         };
2457                         spi3_tx: spi3-tx {
2458                                 rockchip,pins =
2459                                         <1 16 RK_FUNC_1 &pcfg_pull_up>;
2460                         };
2461                 };
2462
2463                 spi4 {
2464                         spi4_clk: spi4-clk {
2465                                 rockchip,pins =
2466                                         <3 2 RK_FUNC_2 &pcfg_pull_up>;
2467                         };
2468                         spi4_cs0: spi4-cs0 {
2469                                 rockchip,pins =
2470                                         <3 3 RK_FUNC_2 &pcfg_pull_up>;
2471                         };
2472                         spi4_rx: spi4-rx {
2473                                 rockchip,pins =
2474                                         <3 0 RK_FUNC_2 &pcfg_pull_up>;
2475                         };
2476                         spi4_tx: spi4-tx {
2477                                 rockchip,pins =
2478                                         <3 1 RK_FUNC_2 &pcfg_pull_up>;
2479                         };
2480                 };
2481
2482                 spi5 {
2483                         spi5_clk: spi5-clk {
2484                                 rockchip,pins =
2485                                         <2 22 RK_FUNC_2 &pcfg_pull_up>;
2486                         };
2487                         spi5_cs0: spi5-cs0 {
2488                                 rockchip,pins =
2489                                         <2 23 RK_FUNC_2 &pcfg_pull_up>;
2490                         };
2491                         spi5_rx: spi5-rx {
2492                                 rockchip,pins =
2493                                         <2 20 RK_FUNC_2 &pcfg_pull_up>;
2494                         };
2495                         spi5_tx: spi5-tx {
2496                                 rockchip,pins =
2497                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
2498                         };
2499                 };
2500
2501                 tsadc {
2502                         otp_gpio: otp-gpio {
2503                                 rockchip,pins = <1 6 RK_FUNC_GPIO &pcfg_pull_none>;
2504                         };
2505
2506                         otp_out: otp-out {
2507                                 rockchip,pins = <1 6 RK_FUNC_1 &pcfg_pull_none>;
2508                         };
2509                 };
2510
2511                 uart0 {
2512                         uart0_xfer: uart0-xfer {
2513                                 rockchip,pins =
2514                                         <2 16 RK_FUNC_1 &pcfg_pull_up>,
2515                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
2516                         };
2517
2518                         uart0_cts: uart0-cts {
2519                                 rockchip,pins =
2520                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
2521                         };
2522
2523                         uart0_rts: uart0-rts {
2524                                 rockchip,pins =
2525                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
2526                         };
2527                 };
2528
2529                 uart1 {
2530                         uart1_xfer: uart1-xfer {
2531                                 rockchip,pins =
2532                                         <3 12 RK_FUNC_2 &pcfg_pull_up>,
2533                                         <3 13 RK_FUNC_2 &pcfg_pull_none>;
2534                         };
2535                 };
2536
2537                 uart2a {
2538                         uart2a_xfer: uart2a-xfer {
2539                                 rockchip,pins =
2540                                         <4 8 RK_FUNC_2 &pcfg_pull_up>,
2541                                         <4 9 RK_FUNC_2 &pcfg_pull_none>;
2542                         };
2543                 };
2544
2545                 uart2b {
2546                         uart2b_xfer: uart2b-xfer {
2547                                 rockchip,pins =
2548                                         <4 16 RK_FUNC_2 &pcfg_pull_up>,
2549                                         <4 17 RK_FUNC_2 &pcfg_pull_none>;
2550                         };
2551                 };
2552
2553                 uart2c {
2554                         uart2c_xfer: uart2c-xfer {
2555                                 rockchip,pins =
2556                                         <4 19 RK_FUNC_1 &pcfg_pull_up>,
2557                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
2558                         };
2559                 };
2560
2561                 uart3 {
2562                         uart3_xfer: uart3-xfer {
2563                                 rockchip,pins =
2564                                         <3 14 RK_FUNC_2 &pcfg_pull_up>,
2565                                         <3 15 RK_FUNC_2 &pcfg_pull_none>;
2566                         };
2567
2568                         uart3_cts: uart3-cts {
2569                                 rockchip,pins =
2570                                         <3 18 RK_FUNC_2 &pcfg_pull_none>;
2571                         };
2572
2573                         uart3_rts: uart3-rts {
2574                                 rockchip,pins =
2575                                         <3 19 RK_FUNC_2 &pcfg_pull_none>;
2576                         };
2577                 };
2578
2579                 uart4 {
2580                         uart4_xfer: uart4-xfer {
2581                                 rockchip,pins =
2582                                         <1 7 RK_FUNC_1 &pcfg_pull_up>,
2583                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
2584                         };
2585                 };
2586
2587                 uarthdcp {
2588                         uarthdcp_xfer: uarthdcp-xfer {
2589                                 rockchip,pins =
2590                                         <4 21 RK_FUNC_2 &pcfg_pull_up>,
2591                             &