arch/arm64/boot/dts/rockchip/rk3399-vop-clk-set.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 /*
  44  * This define is for support double show any dclk frequency.
  45  * dclk_vop will have a exclusive pll as parent.
  46  * set dclk_vop will change the pll rate as well.
  47  */
  48
  49 #ifdef RK3399_TWO_PLL_FOR_VOP
  50
  51 &sdhci {
  52                 assigned-clocks = <&cru SCLK_EMMC>;
  53                 assigned-clock-parents = <&cru PLL_GPLL>;
  54                 assigned-clock-rates = <200000000>;
  55 };
  56
  57 &uart0 {
  58                 assigned-clocks = <&cru SCLK_UART0_SRC>;
  59                 assigned-clock-parents = <&cru PLL_GPLL>;
  60 };
  61
  62 &uart1 {
  63                 assigned-clocks = <&cru SCLK_UART_SRC>;
  64                 assigned-clock-parents = <&cru PLL_GPLL>;
  65 };
  66
  67 &uart2 {
  68                 assigned-clocks = <&cru SCLK_UART_SRC>;
  69                 assigned-clock-parents = <&cru PLL_GPLL>;
  70 };
  71
  72 &uart3 {
  73                 assigned-clocks = <&cru SCLK_UART_SRC>;
  74                 assigned-clock-parents = <&cru PLL_GPLL>;
  75 };
  76
  77 &uart4 {
  78                 assigned-clocks = <&cru SCLK_UART_SRC>;
  79                 assigned-clock-parents = <&cru PLL_GPLL>;
  80 };
  81
  82 &spdif {
  83                 assigned-clocks = <&cru SCLK_SPDIF_DIV>;
  84                 assigned-clock-parents = <&cru PLL_GPLL>;
  85 };
  86
  87 &i2s0{
  88                 assigned-clocks = <&cru SCLK_I2S0_DIV>;
  89                 assigned-clock-parents = <&cru PLL_GPLL>;
  90 };
  91
  92 &i2s1 {
  93                 assigned-clocks = <&cru SCLK_I2S1_DIV>;
  94                 assigned-clock-parents = <&cru PLL_GPLL>;
  95 };
  96
  97 &i2s2 {
  98                 assigned-clocks = <&cru SCLK_I2S2_DIV>;
  99                 assigned-clock-parents = <&cru PLL_GPLL>;
 100 };
 101
 102 &cru {
 103                 assigned-clocks =
 104                         <&cru ACLK_PERIHP>, <&cru ACLK_PERILP0>,
 105                         <&cru HCLK_PERILP1>, <&cru SCLK_SDMMC>,
 106                         <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
 107                         <&cru HCLK_SD>, <&cru SCLK_VDU_CA>,
 108                         <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
 109                         <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
 110                         <&cru PCLK_ALIVE>, <&cru ACLK_GMAC>,
 111                         <&cru SCLK_CS>, <&cru SCLK_CCI_TRACE>,
 112                         <&cru ARMCLKL>, <&cru ARMCLKB>,
 113                         <&cru PLL_NPLL>, <&cru ACLK_GPU>,
 114                         <&cru PLL_GPLL>, <&cru ACLK_PERIHP>,
 115                         <&cru HCLK_PERIHP>, <&cru PCLK_PERIHP>,
 116                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
 117                         <&cru PCLK_PERILP0>, <&cru HCLK_PERILP1>,
 118                         <&cru PCLK_PERILP1>, <&cru SCLK_I2C1>,
 119                         <&cru SCLK_I2C2>, <&cru SCLK_I2C3>,
 120                         <&cru SCLK_I2C5>, <&cru SCLK_I2C6>,
 121                         <&cru SCLK_I2C7>, <&cru SCLK_SPI0>,
 122                         <&cru SCLK_SPI1>, <&cru SCLK_SPI2>,
 123                         <&cru SCLK_SPI4>, <&cru SCLK_SPI5>,
 124                         <&cru ACLK_GIC>, <&cru ACLK_ISP0>,
 125                         <&cru ACLK_ISP1>, <&cru SCLK_VOP0_PWM>,
 126                         <&cru SCLK_VOP1_PWM>, <&cru PCLK_EDP>,
 127                         <&cru ACLK_HDCP>, <&cru ACLK_VIO>,
 128                         <&cru HCLK_SD>, <&cru SCLK_CRYPTO0>,
 129                         <&cru SCLK_CRYPTO1>, <&cru SCLK_EMMC>,
 130                         <&cru ACLK_EMMC>, <&cru ACLK_CENTER>,
 131                         <&cru ACLK_IEP>, <&cru ACLK_RGA>,
 132                         <&cru SCLK_RGA_CORE>, <&cru ACLK_VDU>,
 133                         <&cru ACLK_VCODEC>, <&cru PCLK_DDR>,
 134                         <&cru ACLK_GMAC>, <&cru SCLK_VDU_CA>,
 135                         <&cru SCLK_VDU_CORE>, <&cru ACLK_USB3>,
 136                         <&cru FCLK_CM0S>, <&cru ACLK_CCI>,
 137                         <&cru PCLK_ALIVE>, <&cru SCLK_CS>,
 138                         <&cru SCLK_CCI_TRACE>, <&cru ACLK_VOP0>,
 139                         <&cru HCLK_VOP0>, <&cru ACLK_VOP1>,
 140                         <&cru HCLK_VOP1>;
 141                 assigned-clock-rates =
 142                          <75000000>, <50000000>,
 143                          <50000000>, <50000000>,
 144                          <50000000>, <100000000>,
 145                          <50000000>, <150000000>,
 146                          <150000000>, <150000000>,
 147                          <50000000>, <150000000>,
 148                          <50000000>, <100000000>,
 149                          <75000000>, <75000000>,
 150                          <816000000>, <816000000>,
 151                          <600000000>, <200000000>,
 152                          <800000000>, <150000000>,
 153                          <75000000>, <37500000>,
 154                          <100000000>, <100000000>,
 155                          <50000000>, <100000000>,
 156                          <50000000>, <100000000>,
 157                          <100000000>, <100000000>,
 158                          <100000000>, <100000000>,
 159                          <100000000>, <50000000>,
 160                          <50000000>, <50000000>,
 161                          <50000000>, <50000000>,
 162                          <200000000>, <400000000>,
 163                          <400000000>, <100000000>,
 164                          <100000000>, <100000000>,
 165                          <400000000>, <400000000>,
 166                          <200000000>, <100000000>,
 167                          <200000000>, <200000000>,
 168                          <100000000>, <400000000>,
 169                          <400000000>, <400000000>,
 170                          <400000000>, <300000000>,
 171                          <400000000>, <200000000>,
 172                          <400000000>, <300000000>,
 173                          <300000000>, <300000000>,
 174                          <300000000>, <300000000>,
 175                          <100000000>, <150000000>,
 176                          <150000000>, <400000000>,
 177                          <100000000>, <400000000>,
 178                          <100000000>;
 179 };
 180 #endif
 181