arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "dt-bindings/pwm/pwm.h"
  44 #include "rk3399.dtsi"
  45
  46 / {
  47         compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
  48
  49         backlight: backlight {
  50                 status = "disabled";
  51                 compatible = "pwm-backlight";
  52                 pwms = <&pwm0 0 25000 0>;
  53                 brightness-levels = <
  54                           0   1   2   3   4   5   6   7
  55                           8   9  10  11  12  13  14  15
  56                          16  17  18  19  20  21  22  23
  57                          24  25  26  27  28  29  30  31
  58                          32  33  34  35  36  37  38  39
  59                          40  41  42  43  44  45  46  47
  60                          48  49  50  51  52  53  54  55
  61                          56  57  58  59  60  61  62  63
  62                          64  65  66  67  68  69  70  71
  63                          72  73  74  75  76  77  78  79
  64                          80  81  82  83  84  85  86  87
  65                          88  89  90  91  92  93  94  95
  66                          96  97  98  99 100 101 102 103
  67                         104 105 106 107 108 109 110 111
  68                         112 113 114 115 116 117 118 119
  69                         120 121 122 123 124 125 126 127
  70                         128 129 130 131 132 133 134 135
  71                         136 137 138 139 140 141 142 143
  72                         144 145 146 147 148 149 150 151
  73                         152 153 154 155 156 157 158 159
  74                         160 161 162 163 164 165 166 167
  75                         168 169 170 171 172 173 174 175
  76                         176 177 178 179 180 181 182 183
  77                         184 185 186 187 188 189 190 191
  78                         192 193 194 195 196 197 198 199
  79                         200 201 202 203 204 205 206 207
  80                         208 209 210 211 212 213 214 215
  81                         216 217 218 219 220 221 222 223
  82                         224 225 226 227 228 229 230 231
  83                         232 233 234 235 236 237 238 239
  84                         240 241 242 243 244 245 246 247
  85                         248 249 250 251 252 253 254 255>;
  86                 default-brightness-level = <200>;
  87         };
  88
  89         clkin_gmac: external-gmac-clock {
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <125000000>;
  92                 clock-output-names = "clkin_gmac";
  93                 #clock-cells = <0>;
  94         };
  95
  96         dw_hdmi_audio: dw-hdmi-audio {
  97                 status = "disabled";
  98                 compatible = "rockchip,dw-hdmi-audio";
  99                 #sound-dai-cells = <0>;
 100         };
 101
 102         hdmi_sound: hdmi-sound {
 103                 status = "disabled";
 104                 compatible = "simple-audio-card";
 105                 simple-audio-card,format = "i2s";
 106                 simple-audio-card,mclk-fs = <256>;
 107                 simple-audio-card,name = "rockchip,hdmi";
 108
 109                 simple-audio-card,cpu {
 110                         sound-dai = <&i2s2>;
 111                 };
 112                 simple-audio-card,codec {
 113                         sound-dai = <&dw_hdmi_audio>;
 114                 };
 115         };
 116
 117         io-domains {
 118                 compatible = "rockchip,rk3399-io-voltage-domain";
 119                 rockchip,grf = <&grf>;
 120
 121                 bt656-supply = <&vcc_3v0>;              /* bt656_gpio2ab_ms */
 122                 audio-supply = <&vcca1v8_codec>;        /* audio_gpio3d4a_ms */
 123                 sdmmc-supply = <&vcc_sd>;               /* sdmmc_gpio4b_ms */
 124                 gpio1830-supply = <&vcc_3v0>;           /* gpio1833_gpio4cd_ms */
 125         };
 126
 127         pmu-io-domains {
 128                 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 129                 rockchip,grf = <&pmugrf>;
 130                 pmu1830-supply = <&vcc_3v0>;
 131         };
 132
 133         sdio_pwrseq: sdio-pwrseq {
 134                 compatible = "mmc-pwrseq-simple";
 135                 clocks = <&rk808 1>;
 136                 clock-names = "ext_clock";
 137                 pinctrl-names = "default";
 138                 pinctrl-0 = <&wifi_enable_h>;
 139
 140                 /*
 141                  * On the module itself this is one of these (depending
 142                  * on the actual card populated):
 143                  * - SDIO_RESET_L_WL_REG_ON
 144                  * - PDN (power down when low)
 145                  */
 146                 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
 147         };
 148
 149         vcc3v3_sys: vcc3v3-sys {
 150                 compatible = "regulator-fixed";
 151                 regulator-name = "vcc3v3_sys";
 152                 regulator-always-on;
 153                 regulator-boot-on;
 154                 regulator-min-microvolt = <3300000>;
 155                 regulator-max-microvolt = <3300000>;
 156         };
 157
 158         vcc5v0_host: vcc5v0-host-regulator {
 159                 compatible = "regulator-fixed";
 160                 enable-active-high;
 161                 gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 162                 pinctrl-names = "default";
 163                 pinctrl-0 = <&host_vbus_drv>;
 164                 regulator-name = "vcc5v0_host";
 165         };
 166
 167         vcc5v0_sys: vcc5v0-sys {
 168                 compatible = "regulator-fixed";
 169                 regulator-name = "vcc5v0_sys";
 170                 regulator-always-on;
 171                 regulator-boot-on;
 172                 regulator-min-microvolt = <5000000>;
 173                 regulator-max-microvolt = <5000000>;
 174         };
 175
 176         vcc_phy: vcc-phy-regulator {
 177                 compatible = "regulator-fixed";
 178                 regulator-name = "vcc_phy";
 179                 regulator-always-on;
 180                 regulator-boot-on;
 181         };
 182
 183         vdd_log: vdd-log {
 184                 compatible = "pwm-regulator";
 185                 pwms = <&pwm2 0 25000 0>;
 186                 regulator-name = "vdd_log";
 187                 regulator-min-microvolt = <800000>;
 188                 regulator-max-microvolt = <1400000>;
 189                 regulator-always-on;
 190                 regulator-boot-on;
 191
 192                 /* for rockchip boot on */
 193                 rockchip,pwm_id= <2>;
 194                 rockchip,pwm_voltage = <1000000>;
 195         };
 196 };
 197
 198 &cpu_l0 {
 199         cpu-supply = <&vdd_cpu_l>;
 200 };
 201
 202 &cpu_l1 {
 203         cpu-supply = <&vdd_cpu_l>;
 204 };
 205
 206 &cpu_l2 {
 207         cpu-supply = <&vdd_cpu_l>;
 208 };
 209
 210 &cpu_l3 {
 211         cpu-supply = <&vdd_cpu_l>;
 212 };
 213
 214 &cpu_b0 {
 215         cpu-supply = <&vdd_cpu_b>;
 216 };
 217
 218 &cpu_b1 {
 219         cpu-supply = <&vdd_cpu_b>;
 220 };
 221
 222 &emmc_phy {
 223         freq-sel = <200000000>;
 224         dr-sel = <50>;
 225         opdelay = <4>;
 226         status = "okay";
 227 };
 228
 229 &gmac {
 230         phy-supply = <&vcc_phy>;
 231         phy-mode = "rgmii";
 232         clock_in_out = "input";
 233         snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
 234         snps,reset-active-low;
 235         snps,reset-delays-us = <0 10000 50000>;
 236         assigned-clocks = <&cru SCLK_RMII_SRC>;
 237         assigned-clock-parents = <&clkin_gmac>;
 238         pinctrl-names = "default";
 239         pinctrl-0 = <&rgmii_pins>;
 240         tx_delay = <0x28>;
 241         rx_delay = <0x11>;
 242         status = "okay";
 243 };
 244
 245 &gpu {
 246         status = "okay";
 247         mali-supply = <&vdd_gpu>;
 248 };
 249
 250 &i2c0 {
 251         status = "okay";
 252         i2c-scl-rising-time-ns = <168>;
 253         i2c-scl-falling-time-ns = <4>;
 254         clock-frequency = <400000>;
 255
 256         vdd_cpu_b: syr827@40 {
 257                 compatible = "silergy,syr827";
 258                 reg = <0x40>;
 259                 vin-supply = <&vcc5v0_sys>;
 260                 regulator-compatible = "fan53555-reg";
 261                 regulator-name = "vdd_cpu_b";
 262                 regulator-min-microvolt = <712500>;
 263                 regulator-max-microvolt = <1500000>;
 264                 regulator-ramp-delay = <1000>;
 265                 fcs,suspend-voltage-selector = <1>;
 266                 regulator-always-on;
 267                 regulator-boot-on;
 268                 regulator-initial-state = <3>;
 269                         regulator-state-mem {
 270                         regulator-off-in-suspend;
 271                 };
 272         };
 273
 274         vdd_gpu: syr828@41 {
 275                 compatible = "silergy,syr828";
 276                 reg = <0x41>;
 277                 vin-supply = <&vcc5v0_sys>;
 278                 regulator-compatible = "fan53555-reg";
 279                 regulator-name = "vdd_gpu";
 280                 regulator-min-microvolt = <712500>;
 281                 regulator-max-microvolt = <1500000>;
 282                 regulator-ramp-delay = <1000>;
 283                 fcs,suspend-voltage-selector = <1>;
 284                 regulator-always-on;
 285                 regulator-boot-on;
 286                 regulator-initial-state = <3>;
 287                         regulator-state-mem {
 288                         regulator-off-in-suspend;
 289                 };
 290         };
 291
 292         rk808: pmic@1b {
 293                 compatible = "rockchip,rk808";
 294                 reg = <0x1b>;
 295                 interrupt-parent = <&gpio1>;
 296                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 297                 pinctrl-names = "default";
 298                 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
 299                 rockchip,system-power-controller;
 300                 wakeup-source;
 301                 #clock-cells = <1>;
 302                 clock-output-names = "xin32k", "rk808-clkout2";
 303
 304                 vcc1-supply = <&vcc3v3_sys>;
 305                 vcc2-supply = <&vcc3v3_sys>;
 306                 vcc3-supply = <&vcc3v3_sys>;
 307                 vcc4-supply = <&vcc3v3_sys>;
 308                 vcc6-supply = <&vcc3v3_sys>;
 309                 vcc7-supply = <&vcc3v3_sys>;
 310                 vcc8-supply = <&vcc3v3_sys>;
 311                 vcc9-supply = <&vcc3v3_sys>;
 312                 vcc10-supply = <&vcc3v3_sys>;
 313                 vcc11-supply = <&vcc3v3_sys>;
 314                 vcc12-supply = <&vcc3v3_sys>;
 315                 vddio-supply = <&vcc1v8_pmu>;
 316
 317                 regulators {
 318                         vdd_center: DCDC_REG1 {
 319                                 regulator-always-on;
 320                                 regulator-boot-on;
 321                                 regulator-min-microvolt = <750000>;
 322                                 regulator-max-microvolt = <1350000>;
 323                                 regulator-ramp-delay = <6001>;
 324                                 regulator-name = "vdd_center";
 325                                 regulator-state-mem {
 326                                         regulator-off-in-suspend;
 327                                 };
 328                         };
 329
 330                         vdd_cpu_l: DCDC_REG2 {
 331                                 regulator-always-on;
 332                                 regulator-boot-on;
 333                                 regulator-min-microvolt = <750000>;
 334                                 regulator-max-microvolt = <1350000>;
 335                                 regulator-ramp-delay = <6001>;
 336                                 regulator-name = "vdd_cpu_l";
 337                                 regulator-state-mem {
 338                                         regulator-off-in-suspend;
 339                                 };
 340                         };
 341
 342                         vcc_ddr: DCDC_REG3 {
 343                                 regulator-always-on;
 344                                 regulator-boot-on;
 345                                 regulator-name = "vcc_ddr";
 346                                 regulator-state-mem {
 347                                         regulator-on-in-suspend;
 348                                 };
 349                         };
 350
 351                         vcc_1v8: DCDC_REG4 {
 352                                 regulator-always-on;
 353                                 regulator-boot-on;
 354                                 regulator-min-microvolt = <1800000>;
 355                                 regulator-max-microvolt = <1800000>;
 356                                 regulator-name = "vcc_1v8";
 357                                 regulator-state-mem {
 358                                         regulator-on-in-suspend;
 359                                         regulator-suspend-microvolt = <1800000>;
 360                                 };
 361                         };
 362
 363                         vcc1v8_dvp: LDO_REG1 {
 364                                 regulator-always-on;
 365                                 regulator-boot-on;
 366                                 regulator-min-microvolt = <1800000>;
 367                                 regulator-max-microvolt = <1800000>;
 368                                 regulator-name = "vcc1v8_dvp";
 369                                 regulator-state-mem {
 370                                         regulator-off-in-suspend;
 371                                 };
 372                         };
 373
 374                         vcc3v0_tp: LDO_REG2 {
 375                                 regulator-always-on;
 376                                 regulator-boot-on;
 377                                 regulator-min-microvolt = <3000000>;
 378                                 regulator-max-microvolt = <3000000>;
 379                                 regulator-name = "vcc3v0_tp";
 380                                 regulator-state-mem {
 381                                         regulator-off-in-suspend;
 382                                 };
 383                         };
 384
 385                         vcc1v8_pmu: LDO_REG3 {
 386                                 regulator-always-on;
 387                                 regulator-boot-on;
 388                                 regulator-min-microvolt = <1800000>;
 389                                 regulator-max-microvolt = <1800000>;
 390                                 regulator-name = "vcc1v8_pmu";
 391                                 regulator-state-mem {
 392                                         regulator-on-in-suspend;
 393                                         regulator-suspend-microvolt = <1800000>;
 394                                 };
 395                         };
 396
 397                         vcc_sd: LDO_REG4 {
 398                                 regulator-always-on;
 399                                 regulator-boot-on;
 400                                 regulator-min-microvolt = <1800000>;
 401                                 regulator-max-microvolt = <3300000>;
 402                                 regulator-name = "vcc_sd";
 403                                 regulator-state-mem {
 404                                         regulator-on-in-suspend;
 405                                         regulator-suspend-microvolt = <3300000>;
 406                                 };
 407                         };
 408
 409                         vcca3v0_codec: LDO_REG5 {
 410                                 regulator-always-on;
 411                                 regulator-boot-on;
 412                                 regulator-min-microvolt = <3000000>;
 413                                 regulator-max-microvolt = <3000000>;
 414                                 regulator-name = "vcca3v0_codec";
 415                                 regulator-state-mem {
 416                                         regulator-off-in-suspend;
 417                                 };
 418                         };
 419
 420                         vcc_1v5: LDO_REG6 {
 421                                 regulator-always-on;
 422                                 regulator-boot-on;
 423                                 regulator-min-microvolt = <1500000>;
 424                                 regulator-max-microvolt = <1500000>;
 425                                 regulator-name = "vcc_1v5";
 426                                 regulator-state-mem {
 427                                         regulator-on-in-suspend;
 428                                         regulator-suspend-microvolt = <1500000>;
 429                                 };
 430                         };
 431
 432                         vcca1v8_codec: LDO_REG7 {
 433                                 regulator-always-on;
 434                                 regulator-boot-on;
 435                                 regulator-min-microvolt = <1800000>;
 436                                 regulator-max-microvolt = <1800000>;
 437                                 regulator-name = "vcca1v8_codec";
 438                                 regulator-state-mem {
 439                                         regulator-off-in-suspend;
 440                                 };
 441                         };
 442
 443                         vcc_3v0: LDO_REG8 {
 444                                 regulator-always-on;
 445                                 regulator-boot-on;
 446                                 regulator-min-microvolt = <3000000>;
 447                                 regulator-max-microvolt = <3000000>;
 448                                 regulator-name = "vcc_3v0";
 449                                 regulator-state-mem {
 450                                         regulator-on-in-suspend;
 451                                         regulator-suspend-microvolt = <3000000>;
 452                                 };
 453                         };
 454
 455                         vcc3v3_s3: SWITCH_REG1 {
 456                                 regulator-always-on;
 457                                 regulator-boot-on;
 458                                 regulator-name = "vcc3v3_s3";
 459                                 regulator-state-mem {
 460                                         regulator-off-in-suspend;
 461                                 };
 462                         };
 463
 464                         vcc3v3_s0: SWITCH_REG2 {
 465                                 regulator-always-on;
 466                                 regulator-boot-on;
 467                                 regulator-name = "vcc3v3_s0";
 468                                 regulator-state-mem {
 469                                         regulator-off-in-suspend;
 470                                 };
 471                         };
 472                 };
 473         };
 474 };
 475
 476 &i2c4 {
 477         status = "okay";
 478         i2c-scl-rising-time-ns = <475>;
 479         i2c-scl-falling-time-ns = <26>;
 480
 481         fusb0: fusb30x@22 {
 482                 compatible = "fairchild,fusb302";
 483                 reg = <0x22>;
 484                 pinctrl-names = "default";
 485                 pinctrl-0 = <&fusb0_int>;
 486                 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 487                 status = "okay";
 488         };
 489 };
 490
 491 &i2s0 {
 492         status = "okay";
 493         rockchip,i2s-broken-burst-len;
 494         rockchip,playback-channels = <8>;
 495         rockchip,capture-channels = <8>;
 496         #sound-dai-cells = <0>;
 497 };
 498
 499 &i2s2 {
 500         #sound-dai-cells = <0>;
 501         status = "okay";
 502 };
 503
 504 &pcie0 {
 505         assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
 506         assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
 507         assigned-clock-rates = <100000000>;
 508         ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 509         num-lanes = <4>;
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pcie_clkreqn>;
 512         status = "okay";
 513 };
 514
 515 &pwm0 {
 516         status = "okay";
 517 };
 518
 519 &pwm2 {
 520         status = "okay";
 521 };
 522
 523 &sdhci {
 524         bus-width = <8>;
 525         mmc-hs400-1_8v;
 526         supports-emmc;
 527         non-removable;
 528         keep-power-in-suspend;
 529         mmc-hs400-enhanced-strobe;
 530         status = "okay";
 531 };
 532
 533 &sdio0 {
 534         clock-frequency = <50000000>;
 535         clock-freq-min-max = <200000 50000000>;
 536         supports-sdio;
 537         bus-width = <4>;
 538         disable-wp;
 539         cap-sd-highspeed;
 540         cap-sdio-irq;
 541         keep-power-in-suspend;
 542         mmc-pwrseq = <&sdio_pwrseq>;
 543         non-removable;
 544         num-slots = <1>;
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
 547         sd-uhs-sdr104;
 548         status = "okay";
 549 };
 550
 551 &sdmmc {
 552         clock-frequency = <150000000>;
 553         clock-freq-min-max = <100000 150000000>;
 554         supports-sd;
 555         bus-width = <4>;
 556         cap-mmc-highspeed;
 557         cap-sd-highspeed;
 558         disable-wp;
 559         num-slots = <1>;
 560         //sd-uhs-sdr104;
 561         vqmmc-supply = <&vcc_sd>;
 562         pinctrl-names = "default";
 563         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 564         status = "okay";
 565 };
 566
 567 &saradc {
 568         status = "okay";
 569 };
 570
 571 &tcphy0 {
 572         extcon = <&fusb0>;
 573         status = "okay";
 574 };
 575
 576 &tcphy1 {
 577         status = "okay";
 578 };
 579
 580 &tsadc {
 581         /* tshut mode 0:CRU 1:GPIO */
 582         rockchip,hw-tshut-mode = <1>;
 583         /* tshut polarity 0:LOW 1:HIGH */
 584         rockchip,hw-tshut-polarity = <1>;
 585         status = "okay";
 586 };
 587
 588 &u2phy0 {
 589         status = "okay";
 590         extcon = <&fusb0>;
 591
 592         u2phy0_otg: otg-port {
 593                 status = "okay";
 594         };
 595
 596         u2phy0_host: host-port {
 597                 phy-supply = <&vcc5v0_host>;
 598                 status = "okay";
 599         };
 600 };
 601
 602 &u2phy1 {
 603         status = "okay";
 604
 605         u2phy1_otg: otg-port {
 606                 status = "okay";
 607         };
 608
 609         u2phy1_host: host-port {
 610                 phy-supply = <&vcc5v0_host>;
 611                 status = "okay";
 612         };
 613 };
 614
 615 &uart2 {
 616         status = "okay";
 617 };
 618
 619 &usbdrd3_0 {
 620         status = "okay";
 621         extcon = <&fusb0>;
 622 };
 623
 624 &usbdrd3_1 {
 625         status = "okay";
 626 };
 627
 628 &usbdrd_dwc3_0 {
 629         status = "okay";
 630 };
 631
 632 &usbdrd_dwc3_1 {
 633         status = "okay";
 634         dr_mode = "host";
 635 };
 636
 637 &usb_host0_ehci {
 638         status = "okay";
 639 };
 640
 641 &usb_host0_ohci {
 642         status = "okay";
 643 };
 644
 645 &usb_host1_ehci {
 646         status = "okay";
 647 };
 648
 649 &usb_host1_ohci {
 650         status = "okay";
 651 };
 652
 653 &cluster0_opp {
 654         opp@408000000 {
 655                 opp-hz = /bits/ 64 <408000000>;
 656                 opp-microvolt = <800000>;
 657                 clock-latency-ns = <40000>;
 658         };
 659         opp@600000000 {
 660                 opp-hz = /bits/ 64 <600000000>;
 661                 opp-microvolt = <800000>;
 662                 clock-latency-ns = <40000>;
 663         };
 664         opp@816000000 {
 665                 opp-hz = /bits/ 64 <816000000>;
 666                 opp-microvolt = <800000>;
 667                 clock-latency-ns = <40000>;
 668         };
 669         opp@1008000000 {
 670                 opp-hz = /bits/ 64 <1008000000>;
 671                 opp-microvolt = <875000>;
 672                 clock-latency-ns = <40000>;
 673         };
 674         opp@1200000000 {
 675                 opp-hz = /bits/ 64 <1200000000>;
 676                 opp-microvolt = <925000>;
 677                 clock-latency-ns = <40000>;
 678         };
 679         opp@1416000000 {
 680                 opp-hz = /bits/ 64 <1416000000>;
 681                 opp-microvolt = <1050000>;
 682                 clock-latency-ns = <40000>;
 683         };
 684 };
 685
 686 &cluster1_opp {
 687         opp@408000000 {
 688                 opp-hz = /bits/ 64 <408000000>;
 689                 opp-microvolt = <800000>;
 690                 clock-latency-ns = <40000>;
 691         };
 692         opp@600000000 {
 693                 opp-hz = /bits/ 64 <600000000>;
 694                 opp-microvolt = <800000>;
 695                 clock-latency-ns = <40000>;
 696         };
 697         opp@816000000 {
 698                 opp-hz = /bits/ 64 <816000000>;
 699                 opp-microvolt = <825000>;
 700                 clock-latency-ns = <40000>;
 701         };
 702         opp@1008000000 {
 703                 opp-hz = /bits/ 64 <1008000000>;
 704                 opp-microvolt = <875000>;
 705                 clock-latency-ns = <40000>;
 706         };
 707         opp@1200000000 {
 708                 opp-hz = /bits/ 64 <1200000000>;
 709                 opp-microvolt = <950000>;
 710                 clock-latency-ns = <40000>;
 711         };
 712         opp@1416000000 {
 713                 opp-hz = /bits/ 64 <1416000000>;
 714                 opp-microvolt = <1025000>;
 715                 clock-latency-ns = <40000>;
 716         };
 717         opp@1608000000 {
 718                 opp-hz = /bits/ 64 <1608000000>;
 719                 opp-microvolt = <1100000>;
 720                 clock-latency-ns = <40000>;
 721         };
 722         opp@1800000000 {
 723                 opp-hz = /bits/ 64 <1800000000>;
 724                 opp-microvolt = <1175000>;
 725                 clock-latency-ns = <40000>;
 726         };
 727         opp@1992000000 {
 728                 opp-hz = /bits/ 64 <1992000000>;
 729                 opp-microvolt = <1250000>;
 730                 clock-latency-ns = <40000>;
 731         };
 732 };
 733
 734 &CPU_COST_A72 {
 735         busy-cost-data = <
 736                 210   129       /*  408MHz */
 737                 308   184       /*  600MHz */
 738                 419   246       /*  816MHz */
 739                 518   335       /* 1008MHz */
 740                 617   428       /* 1200MHz */
 741                 728   573       /* 1416MHz */
 742                 827   724       /* 1608MHz */
 743                 925   900       /* 1800MHz */
 744                 1024  1108      /* 1992MHz */
 745         >;
 746         idle-cost-data = <
 747                 15
 748                 15
 749                 0
 750         >;
 751 };
 752
 753 &CPU_COST_A53 {
 754         busy-cost-data = <
 755                 108    46       /*  408M */
 756                 159    67       /*  600M */
 757                 216    90       /*  816M */
 758                 267    120      /* 1008M */
 759                 318    153      /* 1200M */
 760                 375    198      /* 1416M */
 761                 401    222      /* 1512M */
 762         >;
 763         idle-cost-data = <
 764                 6
 765                 6
 766                 0
 767         >;
 768 };
 769
 770 &CLUSTER_COST_A72 {
 771         busy-cost-data = <
 772                 210   129       /*  408MHz */
 773                 308   184       /*  600MHz */
 774                 419   246       /*  816MHz */
 775                 518   335       /* 1008MHz */
 776                 617   428       /* 1200MHz */
 777                 728   573       /* 1416MHz */
 778                 827   724       /* 1608MHz */
 779                 925   900       /* 1800MHz */
 780                 1024  1108      /* 1992MHz */
 781         >;
 782         idle-cost-data = <
 783                 65
 784                 65
 785                 65
 786         >;
 787 };
 788
 789 &CLUSTER_COST_A53 {
 790         busy-cost-data = <
 791                 108    46       /*  408M */
 792                 159    67       /*  600M */
 793                 216    90       /*  816M */
 794                 267    120      /* 1008M */
 795                 318    153      /* 1200M */
 796                 375    198      /* 1416M */
 797                 401    222      /* 1512M */
 798         >;
 799         idle-cost-data = <
 800                 56
 801                 56
 802                 56
 803         >;
 804 };
 805
 806 &gpu_opp_table {
 807         opp@200000000 {
 808                 opp-hz = /bits/ 64 <200000000>;
 809                 opp-microvolt = <800000>;
 810         };
 811         opp@300000000 {
 812                 opp-hz = /bits/ 64 <300000000>;
 813                 opp-microvolt = <800000>;
 814         };
 815         opp@400000000 {
 816                 opp-hz = /bits/ 64 <400000000>;
 817                 opp-microvolt = <800000>;
 818         };
 819         opp@500000000 {
 820                 opp-hz = /bits/ 64 <500000000>;
 821                 opp-microvolt = <900000>;
 822         };
 823         opp@600000000 {
 824                 opp-hz = /bits/ 64 <600000000>;
 825                 opp-microvolt = <900000>;
 826         };
 827         opp@800000000 {
 828                 opp-hz = /bits/ 64 <800000000>;
 829                 opp-microvolt = <1000000>;
 830         };
 831 };
 832
 833 &pinctrl {
 834         pmic {
 835                 pmic_int_l: pmic-int-l {
 836                         rockchip,pins =
 837                                 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
 838                 };
 839
 840                 pmic_dvs2: pmic-dvs2 {
 841                         rockchip,pins =
 842                                 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
 843                 };
 844         };
 845
 846         usb2 {
 847                 host_vbus_drv: host-vbus-drv {
 848                         rockchip,pins =
 849                                 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
 850                 };
 851         };
 852
 853         fusb30x {
 854                 fusb0_int: fusb0-int {
 855                         rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
 856                 };
 857         };
 858 };