arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "dt-bindings/pwm/pwm.h"
  44 #include "rk3399.dtsi"
  45
  46 / {
  47         compatible = "rockchip,rk3399-sapphire", "rockchip,rk3399";
  48
  49         backlight: backlight {
  50                 status = "disabled";
  51                 compatible = "pwm-backlight";
  52                 pwms = <&pwm0 0 25000 0>;
  53                 brightness-levels = <
  54                           0   1   2   3   4   5   6   7
  55                           8   9  10  11  12  13  14  15
  56                          16  17  18  19  20  21  22  23
  57                          24  25  26  27  28  29  30  31
  58                          32  33  34  35  36  37  38  39
  59                          40  41  42  43  44  45  46  47
  60                          48  49  50  51  52  53  54  55
  61                          56  57  58  59  60  61  62  63
  62                          64  65  66  67  68  69  70  71
  63                          72  73  74  75  76  77  78  79
  64                          80  81  82  83  84  85  86  87
  65                          88  89  90  91  92  93  94  95
  66                          96  97  98  99 100 101 102 103
  67                         104 105 106 107 108 109 110 111
  68                         112 113 114 115 116 117 118 119
  69                         120 121 122 123 124 125 126 127
  70                         128 129 130 131 132 133 134 135
  71                         136 137 138 139 140 141 142 143
  72                         144 145 146 147 148 149 150 151
  73                         152 153 154 155 156 157 158 159
  74                         160 161 162 163 164 165 166 167
  75                         168 169 170 171 172 173 174 175
  76                         176 177 178 179 180 181 182 183
  77                         184 185 186 187 188 189 190 191
  78                         192 193 194 195 196 197 198 199
  79                         200 201 202 203 204 205 206 207
  80                         208 209 210 211 212 213 214 215
  81                         216 217 218 219 220 221 222 223
  82                         224 225 226 227 228 229 230 231
  83                         232 233 234 235 236 237 238 239
  84                         240 241 242 243 244 245 246 247
  85                         248 249 250 251 252 253 254 255>;
  86                 default-brightness-level = <200>;
  87         };
  88
  89         clkin_gmac: external-gmac-clock {
  90                 compatible = "fixed-clock";
  91                 clock-frequency = <125000000>;
  92                 clock-output-names = "clkin_gmac";
  93                 #clock-cells = <0>;
  94         };
  95
  96         dw_hdmi_audio: dw-hdmi-audio {
  97                 status = "disabled";
  98                 compatible = "rockchip,dw-hdmi-audio";
  99                 #sound-dai-cells = <0>;
 100         };
 101
 102         hdmi_sound: hdmi-sound {
 103                 status = "disabled";
 104                 compatible = "simple-audio-card";
 105                 simple-audio-card,format = "i2s";
 106                 simple-audio-card,mclk-fs = <256>;
 107                 simple-audio-card,name = "rockchip,hdmi";
 108
 109                 simple-audio-card,cpu {
 110                         sound-dai = <&i2s2>;
 111                 };
 112                 simple-audio-card,codec {
 113                         sound-dai = <&dw_hdmi_audio>;
 114                 };
 115         };
 116
 117         io-domains {
 118                 compatible = "rockchip,rk3399-io-voltage-domain";
 119                 rockchip,grf = <&grf>;
 120
 121                 bt656-supply = <&vcc_3v0>;              /* bt656_gpio2ab_ms */
 122                 audio-supply = <&vcca1v8_codec>;        /* audio_gpio3d4a_ms */
 123                 sdmmc-supply = <&vcc_sd>;               /* sdmmc_gpio4b_ms */
 124                 gpio1830-supply = <&vcc_3v0>;           /* gpio1833_gpio4cd_ms */
 125         };
 126
 127         pmu-io-domains {
 128                 compatible = "rockchip,rk3399-pmu-io-voltage-domain";
 129                 rockchip,grf = <&pmugrf>;
 130                 pmu1830-supply = <&vcc_3v0>;
 131         };
 132
 133         sdio_pwrseq: sdio-pwrseq {
 134                 compatible = "mmc-pwrseq-simple";
 135                 clocks = <&rk808 1>;
 136                 clock-names = "ext_clock";
 137                 pinctrl-names = "default";
 138                 pinctrl-0 = <&wifi_enable_h>;
 139
 140                 /*
 141                  * On the module itself this is one of these (depending
 142                  * on the actual card populated):
 143                  * - SDIO_RESET_L_WL_REG_ON
 144                  * - PDN (power down when low)
 145                  */
 146                 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */
 147         };
 148
 149         vcc3v3_sys: vcc3v3-sys {
 150                 compatible = "regulator-fixed";
 151                 regulator-name = "vcc3v3_sys";
 152                 regulator-always-on;
 153                 regulator-boot-on;
 154                 regulator-min-microvolt = <3300000>;
 155                 regulator-max-microvolt = <3300000>;
 156         };
 157
 158         vcc5v0_host: vcc5v0-host-regulator {
 159                 compatible = "regulator-fixed";
 160                 enable-active-high;
 161                 pinctrl-names = "default";
 162                 pinctrl-0 = <&host_vbus_drv>;
 163                 regulator-name = "vcc5v0_host";
 164         };
 165
 166         vcc5v0_sys: vcc5v0-sys {
 167                 compatible = "regulator-fixed";
 168                 regulator-name = "vcc5v0_sys";
 169                 regulator-always-on;
 170                 regulator-boot-on;
 171                 regulator-min-microvolt = <5000000>;
 172                 regulator-max-microvolt = <5000000>;
 173         };
 174
 175         vcc_phy: vcc-phy-regulator {
 176                 compatible = "regulator-fixed";
 177                 regulator-name = "vcc_phy";
 178                 regulator-always-on;
 179                 regulator-boot-on;
 180         };
 181
 182         vdd_log: vdd-log {
 183                 compatible = "pwm-regulator";
 184                 pwms = <&pwm2 0 25000 0>;
 185                 regulator-name = "vdd_log";
 186                 regulator-min-microvolt = <800000>;
 187                 regulator-max-microvolt = <1400000>;
 188                 regulator-always-on;
 189                 regulator-boot-on;
 190
 191                 /* for rockchip boot on */
 192                 rockchip,pwm_id= <2>;
 193                 rockchip,pwm_voltage = <1000000>;
 194         };
 195 };
 196
 197 &cpu_l0 {
 198         cpu-supply = <&vdd_cpu_l>;
 199 };
 200
 201 &cpu_l1 {
 202         cpu-supply = <&vdd_cpu_l>;
 203 };
 204
 205 &cpu_l2 {
 206         cpu-supply = <&vdd_cpu_l>;
 207 };
 208
 209 &cpu_l3 {
 210         cpu-supply = <&vdd_cpu_l>;
 211 };
 212
 213 &cpu_b0 {
 214         cpu-supply = <&vdd_cpu_b>;
 215 };
 216
 217 &cpu_b1 {
 218         cpu-supply = <&vdd_cpu_b>;
 219 };
 220
 221 &emmc_phy {
 222         freq-sel = <200000000>;
 223         dr-sel = <50>;
 224         opdelay = <4>;
 225         status = "okay";
 226 };
 227
 228 &gmac {
 229         phy-supply = <&vcc_phy>;
 230         phy-mode = "rgmii";
 231         clock_in_out = "input";
 232         snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>;
 233         snps,reset-active-low;
 234         snps,reset-delays-us = <0 10000 50000>;
 235         assigned-clocks = <&cru SCLK_RMII_SRC>;
 236         assigned-clock-parents = <&clkin_gmac>;
 237         pinctrl-names = "default";
 238         pinctrl-0 = <&rgmii_pins>;
 239         tx_delay = <0x28>;
 240         rx_delay = <0x11>;
 241         status = "okay";
 242 };
 243
 244 &gpu {
 245         status = "okay";
 246         mali-supply = <&vdd_gpu>;
 247 };
 248
 249 &i2c0 {
 250         status = "okay";
 251         i2c-scl-rising-time-ns = <168>;
 252         i2c-scl-falling-time-ns = <4>;
 253         clock-frequency = <400000>;
 254
 255         vdd_cpu_b: syr827@40 {
 256                 compatible = "silergy,syr827";
 257                 reg = <0x40>;
 258                 vin-supply = <&vcc5v0_sys>;
 259                 regulator-compatible = "fan53555-reg";
 260                 regulator-name = "vdd_cpu_b";
 261                 regulator-min-microvolt = <712500>;
 262                 regulator-max-microvolt = <1500000>;
 263                 regulator-ramp-delay = <1000>;
 264                 fcs,suspend-voltage-selector = <1>;
 265                 regulator-always-on;
 266                 regulator-boot-on;
 267                 regulator-initial-state = <3>;
 268                         regulator-state-mem {
 269                         regulator-off-in-suspend;
 270                 };
 271         };
 272
 273         vdd_gpu: syr828@41 {
 274                 compatible = "silergy,syr828";
 275                 reg = <0x41>;
 276                 vin-supply = <&vcc5v0_sys>;
 277                 regulator-compatible = "fan53555-reg";
 278                 regulator-name = "vdd_gpu";
 279                 regulator-min-microvolt = <712500>;
 280                 regulator-max-microvolt = <1500000>;
 281                 regulator-ramp-delay = <1000>;
 282                 fcs,suspend-voltage-selector = <1>;
 283                 regulator-always-on;
 284                 regulator-boot-on;
 285                 regulator-initial-state = <3>;
 286                         regulator-state-mem {
 287                         regulator-off-in-suspend;
 288                 };
 289         };
 290
 291         rk808: pmic@1b {
 292                 compatible = "rockchip,rk808";
 293                 reg = <0x1b>;
 294                 interrupt-parent = <&gpio1>;
 295                 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&pmic_int_l &pmic_dvs2>;
 298                 rockchip,system-power-controller;
 299                 wakeup-source;
 300                 #clock-cells = <1>;
 301                 clock-output-names = "xin32k", "rk808-clkout2";
 302
 303                 vcc1-supply = <&vcc3v3_sys>;
 304                 vcc2-supply = <&vcc3v3_sys>;
 305                 vcc3-supply = <&vcc3v3_sys>;
 306                 vcc4-supply = <&vcc3v3_sys>;
 307                 vcc6-supply = <&vcc3v3_sys>;
 308                 vcc7-supply = <&vcc3v3_sys>;
 309                 vcc8-supply = <&vcc3v3_sys>;
 310                 vcc9-supply = <&vcc3v3_sys>;
 311                 vcc10-supply = <&vcc3v3_sys>;
 312                 vcc11-supply = <&vcc3v3_sys>;
 313                 vcc12-supply = <&vcc3v3_sys>;
 314                 vddio-supply = <&vcc1v8_pmu>;
 315
 316                 regulators {
 317                         vdd_center: DCDC_REG1 {
 318                                 regulator-always-on;
 319                                 regulator-boot-on;
 320                                 regulator-min-microvolt = <750000>;
 321                                 regulator-max-microvolt = <1350000>;
 322                                 regulator-ramp-delay = <6001>;
 323                                 regulator-name = "vdd_center";
 324                                 regulator-state-mem {
 325                                         regulator-off-in-suspend;
 326                                 };
 327                         };
 328
 329                         vdd_cpu_l: DCDC_REG2 {
 330                                 regulator-always-on;
 331                                 regulator-boot-on;
 332                                 regulator-min-microvolt = <750000>;
 333                                 regulator-max-microvolt = <1350000>;
 334                                 regulator-ramp-delay = <6001>;
 335                                 regulator-name = "vdd_cpu_l";
 336                                 regulator-state-mem {
 337                                         regulator-off-in-suspend;
 338                                 };
 339                         };
 340
 341                         vcc_ddr: DCDC_REG3 {
 342                                 regulator-always-on;
 343                                 regulator-boot-on;
 344                                 regulator-name = "vcc_ddr";
 345                                 regulator-state-mem {
 346                                         regulator-on-in-suspend;
 347                                 };
 348                         };
 349
 350                         vcc_1v8: DCDC_REG4 {
 351                                 regulator-always-on;
 352                                 regulator-boot-on;
 353                                 regulator-min-microvolt = <1800000>;
 354                                 regulator-max-microvolt = <1800000>;
 355                                 regulator-name = "vcc_1v8";
 356                                 regulator-state-mem {
 357                                         regulator-on-in-suspend;
 358                                         regulator-suspend-microvolt = <1800000>;
 359                                 };
 360                         };
 361
 362                         vcc1v8_dvp: LDO_REG1 {
 363                                 regulator-always-on;
 364                                 regulator-boot-on;
 365                                 regulator-min-microvolt = <1800000>;
 366                                 regulator-max-microvolt = <1800000>;
 367                                 regulator-name = "vcc1v8_dvp";
 368                                 regulator-state-mem {
 369                                         regulator-off-in-suspend;
 370                                 };
 371                         };
 372
 373                         vcc3v0_tp: LDO_REG2 {
 374                                 regulator-always-on;
 375                                 regulator-boot-on;
 376                                 regulator-min-microvolt = <3000000>;
 377                                 regulator-max-microvolt = <3000000>;
 378                                 regulator-name = "vcc3v0_tp";
 379                                 regulator-state-mem {
 380                                         regulator-off-in-suspend;
 381                                 };
 382                         };
 383
 384                         vcc1v8_pmu: LDO_REG3 {
 385                                 regulator-always-on;
 386                                 regulator-boot-on;
 387                                 regulator-min-microvolt = <1800000>;
 388                                 regulator-max-microvolt = <1800000>;
 389                                 regulator-name = "vcc1v8_pmu";
 390                                 regulator-state-mem {
 391                                         regulator-on-in-suspend;
 392                                         regulator-suspend-microvolt = <1800000>;
 393                                 };
 394                         };
 395
 396                         vcc_sd: LDO_REG4 {
 397                                 regulator-always-on;
 398                                 regulator-boot-on;
 399                                 regulator-min-microvolt = <1800000>;
 400                                 regulator-max-microvolt = <3300000>;
 401                                 regulator-name = "vcc_sd";
 402                                 regulator-state-mem {
 403                                         regulator-on-in-suspend;
 404                                         regulator-suspend-microvolt = <3300000>;
 405                                 };
 406                         };
 407
 408                         vcca3v0_codec: LDO_REG5 {
 409                                 regulator-always-on;
 410                                 regulator-boot-on;
 411                                 regulator-min-microvolt = <3000000>;
 412                                 regulator-max-microvolt = <3000000>;
 413                                 regulator-name = "vcca3v0_codec";
 414                                 regulator-state-mem {
 415                                         regulator-off-in-suspend;
 416                                 };
 417                         };
 418
 419                         vcc_1v5: LDO_REG6 {
 420                                 regulator-always-on;
 421                                 regulator-boot-on;
 422                                 regulator-min-microvolt = <1500000>;
 423                                 regulator-max-microvolt = <1500000>;
 424                                 regulator-name = "vcc_1v5";
 425                                 regulator-state-mem {
 426                                         regulator-on-in-suspend;
 427                                         regulator-suspend-microvolt = <1500000>;
 428                                 };
 429                         };
 430
 431                         vcca1v8_codec: LDO_REG7 {
 432                                 regulator-always-on;
 433                                 regulator-boot-on;
 434                                 regulator-min-microvolt = <1800000>;
 435                                 regulator-max-microvolt = <1800000>;
 436                                 regulator-name = "vcca1v8_codec";
 437                                 regulator-state-mem {
 438                                         regulator-off-in-suspend;
 439                                 };
 440                         };
 441
 442                         vcc_3v0: LDO_REG8 {
 443                                 regulator-always-on;
 444                                 regulator-boot-on;
 445                                 regulator-min-microvolt = <3000000>;
 446                                 regulator-max-microvolt = <3000000>;
 447                                 regulator-name = "vcc_3v0";
 448                                 regulator-state-mem {
 449                                         regulator-on-in-suspend;
 450                                         regulator-suspend-microvolt = <3000000>;
 451                                 };
 452                         };
 453
 454                         vcc3v3_s3: SWITCH_REG1 {
 455                                 regulator-always-on;
 456                                 regulator-boot-on;
 457                                 regulator-name = "vcc3v3_s3";
 458                                 regulator-state-mem {
 459                                         regulator-off-in-suspend;
 460                                 };
 461                         };
 462
 463                         vcc3v3_s0: SWITCH_REG2 {
 464                                 regulator-always-on;
 465                                 regulator-boot-on;
 466                                 regulator-name = "vcc3v3_s0";
 467                                 regulator-state-mem {
 468                                         regulator-off-in-suspend;
 469                                 };
 470                         };
 471                 };
 472         };
 473 };
 474
 475 &i2c4 {
 476         status = "okay";
 477         i2c-scl-rising-time-ns = <475>;
 478         i2c-scl-falling-time-ns = <26>;
 479
 480         fusb0: fusb30x@22 {
 481                 compatible = "fairchild,fusb302";
 482                 reg = <0x22>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&fusb0_int>;
 485                 vbus-5v-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
 486                 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 487                 status = "okay";
 488         };
 489 };
 490
 491 &i2s0 {
 492         status = "okay";
 493         rockchip,i2s-broken-burst-len;
 494         rockchip,playback-channels = <8>;
 495         rockchip,capture-channels = <8>;
 496         #sound-dai-cells = <0>;
 497 };
 498
 499 &i2s2 {
 500         #sound-dai-cells = <0>;
 501         status = "okay";
 502 };
 503
 504 &pcie0 {
 505         assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
 506         assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
 507         assigned-clock-rates = <100000000>;
 508         ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
 509         num-lanes = <4>;
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pcie_clkreqn>;
 512         status = "okay";
 513 };
 514
 515 &pwm0 {
 516         status = "okay";
 517 };
 518
 519 &pwm2 {
 520         status = "okay";
 521 };
 522
 523 &sdhci {
 524         bus-width = <8>;
 525         mmc-hs400-1_8v;
 526         supports-emmc;
 527         non-removable;
 528         keep-power-in-suspend;
 529         mmc-hs400-enhanced-strobe;
 530         status = "okay";
 531 };
 532
 533 &sdio0 {
 534         clock-frequency = <50000000>;
 535         clock-freq-min-max = <200000 50000000>;
 536         supports-sdio;
 537         bus-width = <4>;
 538         disable-wp;
 539         cap-sd-highspeed;
 540         cap-sdio-irq;
 541         keep-power-in-suspend;
 542         mmc-pwrseq = <&sdio_pwrseq>;
 543         non-removable;
 544         num-slots = <1>;
 545         pinctrl-names = "default";
 546         pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
 547         sd-uhs-sdr104;
 548         status = "okay";
 549 };
 550
 551 &sdmmc {
 552         clock-frequency = <150000000>;
 553         clock-freq-min-max = <100000 150000000>;
 554         supports-sd;
 555         bus-width = <4>;
 556         cap-mmc-highspeed;
 557         cap-sd-highspeed;
 558         disable-wp;
 559         num-slots = <1>;
 560         //sd-uhs-sdr104;
 561         vqmmc-supply = <&vcc_sd>;
 562         pinctrl-names = "default";
 563         pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
 564         status = "okay";
 565 };
 566
 567 &saradc {
 568         status = "okay";
 569 };
 570
 571 &tcphy0 {
 572         extcon = <&fusb0>;
 573         status = "okay";
 574 };
 575
 576 &tcphy1 {
 577         status = "okay";
 578 };
 579
 580 &tsadc {
 581         /* tshut mode 0:CRU 1:GPIO */
 582         rockchip,hw-tshut-mode = <1>;
 583         /* tshut polarity 0:LOW 1:HIGH */
 584         rockchip,hw-tshut-polarity = <1>;
 585         status = "okay";
 586 };
 587
 588 &u2phy0 {
 589         status = "okay";
 590         extcon = <&fusb0>;
 591
 592         u2phy0_otg: otg-port {
 593                 status = "okay";
 594         };
 595
 596         u2phy0_host: host-port {
 597                 phy-supply = <&vcc5v0_host>;
 598                 status = "okay";
 599         };
 600 };
 601
 602 &u2phy1 {
 603         status = "okay";
 604
 605         u2phy1_otg: otg-port {
 606                 status = "okay";
 607         };
 608
 609         u2phy1_host: host-port {
 610                 phy-supply = <&vcc5v0_host>;
 611                 status = "okay";
 612         };
 613 };
 614
 615 &uart2 {
 616         status = "okay";
 617 };
 618
 619 &usbdrd3_0 {
 620         status = "okay";
 621         extcon = <&fusb0>;
 622 };
 623
 624 &usbdrd3_1 {
 625         status = "okay";
 626 };
 627
 628 &usbdrd_dwc3_0 {
 629         status = "okay";
 630 };
 631
 632 &usbdrd_dwc3_1 {
 633         status = "okay";
 634         dr_mode = "host";
 635 };
 636
 637 &usb_host0_ehci {
 638         status = "okay";
 639 };
 640
 641 &usb_host0_ohci {
 642         status = "okay";
 643 };
 644
 645 &usb_host1_ehci {
 646         status = "okay";
 647 };
 648
 649 &usb_host1_ohci {
 650         status = "okay";
 651 };
 652
 653 &cluster0_opp {
 654         opp@408000000 {
 655                 opp-hz = /bits/ 64 <408000000>;
 656                 opp-microvolt = <800000>;
 657                 clock-latency-ns = <40000>;
 658         };
 659         opp@600000000 {
 660                 opp-hz = /bits/ 64 <600000000>;
 661                 opp-microvolt = <800000>;
 662         };
 663         opp@816000000 {
 664                 opp-hz = /bits/ 64 <816000000>;
 665                 opp-microvolt = <800000>;
 666         };
 667         opp@1008000000 {
 668                 opp-hz = /bits/ 64 <1008000000>;
 669                 opp-microvolt = <875000>;
 670         };
 671         opp@1200000000 {
 672                 opp-hz = /bits/ 64 <1200000000>;
 673                 opp-microvolt = <925000>;
 674         };
 675         opp@1416000000 {
 676                 opp-hz = /bits/ 64 <1416000000>;
 677                 opp-microvolt = <1050000>;
 678         };
 679 };
 680
 681 &cluster1_opp {
 682         opp@408000000 {
 683                 opp-hz = /bits/ 64 <408000000>;
 684                 opp-microvolt = <800000>;
 685                 clock-latency-ns = <40000>;
 686         };
 687         opp@600000000 {
 688                 opp-hz = /bits/ 64 <600000000>;
 689                 opp-microvolt = <800000>;
 690         };
 691         opp@816000000 {
 692                 opp-hz = /bits/ 64 <816000000>;
 693                 opp-microvolt = <825000>;
 694         };
 695         opp@1008000000 {
 696                 opp-hz = /bits/ 64 <1008000000>;
 697                 opp-microvolt = <875000>;
 698         };
 699         opp@1200000000 {
 700                 opp-hz = /bits/ 64 <1200000000>;
 701                 opp-microvolt = <950000>;
 702         };
 703         opp@1416000000 {
 704                 opp-hz = /bits/ 64 <1416000000>;
 705                 opp-microvolt = <1025000>;
 706         };
 707         opp@1608000000 {
 708                 opp-hz = /bits/ 64 <1608000000>;
 709                 opp-microvolt = <1100000>;
 710         };
 711         opp@1800000000 {
 712                 opp-hz = /bits/ 64 <1800000000>;
 713                 opp-microvolt = <1175000>;
 714         };
 715         opp@1992000000 {
 716                 opp-hz = /bits/ 64 <1992000000>;
 717                 opp-microvolt = <1250000>;
 718         };
 719 };
 720
 721 &CPU_COST_A72 {
 722         busy-cost-data = <
 723                 210   129       /*  408MHz */
 724                 308   184       /*  600MHz */
 725                 419   246       /*  816MHz */
 726                 518   335       /* 1008MHz */
 727                 617   428       /* 1200MHz */
 728                 728   573       /* 1416MHz */
 729                 827   724       /* 1608MHz */
 730                 925   900       /* 1800MHz */
 731                 1024  1108      /* 1992MHz */
 732         >;
 733         idle-cost-data = <
 734                 15
 735                 15
 736                 0
 737         >;
 738 };
 739
 740 &CPU_COST_A53 {
 741         busy-cost-data = <
 742                 108    46       /*  408M */
 743                 159    67       /*  600M */
 744                 216    90       /*  816M */
 745                 267    120      /* 1008M */
 746                 318    153      /* 1200M */
 747                 375    198      /* 1416M */
 748                 401    222      /* 1512M */
 749         >;
 750         idle-cost-data = <
 751                 6
 752                 6
 753                 0
 754         >;
 755 };
 756
 757 &CLUSTER_COST_A72 {
 758         busy-cost-data = <
 759                 210   129       /*  408MHz */
 760                 308   184       /*  600MHz */
 761                 419   246       /*  816MHz */
 762                 518   335       /* 1008MHz */
 763                 617   428       /* 1200MHz */
 764                 728   573       /* 1416MHz */
 765                 827   724       /* 1608MHz */
 766                 925   900       /* 1800MHz */
 767                 1024  1108      /* 1992MHz */
 768         >;
 769         idle-cost-data = <
 770                 65
 771                 65
 772                 65
 773         >;
 774 };
 775
 776 &CLUSTER_COST_A53 {
 777         busy-cost-data = <
 778                 108    46       /*  408M */
 779                 159    67       /*  600M */
 780                 216    90       /*  816M */
 781                 267    120      /* 1008M */
 782                 318    153      /* 1200M */
 783                 375    198      /* 1416M */
 784                 401    222      /* 1512M */
 785         >;
 786         idle-cost-data = <
 787                 56
 788                 56
 789                 56
 790         >;
 791 };
 792
 793 &gpu_opp_table {
 794         opp@200000000 {
 795                 opp-hz = /bits/ 64 <200000000>;
 796                 opp-microvolt = <800000>;
 797         };
 798         opp@300000000 {
 799                 opp-hz = /bits/ 64 <300000000>;
 800                 opp-microvolt = <800000>;
 801         };
 802         opp@400000000 {
 803                 opp-hz = /bits/ 64 <400000000>;
 804                 opp-microvolt = <800000>;
 805         };
 806         opp@500000000 {
 807                 opp-hz = /bits/ 64 <500000000>;
 808                 opp-microvolt = <900000>;
 809         };
 810         opp@600000000 {
 811                 opp-hz = /bits/ 64 <600000000>;
 812                 opp-microvolt = <900000>;
 813         };
 814         opp@800000000 {
 815                 opp-hz = /bits/ 64 <800000000>;
 816                 opp-microvolt = <1000000>;
 817         };
 818 };
 819
 820 &pinctrl {
 821         pmic {
 822                 pmic_int_l: pmic-int-l {
 823                         rockchip,pins =
 824                                 <1 21 RK_FUNC_GPIO &pcfg_pull_up>;
 825                 };
 826
 827                 pmic_dvs2: pmic-dvs2 {
 828                         rockchip,pins =
 829                                 <1 18 RK_FUNC_GPIO &pcfg_pull_down>;
 830                 };
 831         };
 832
 833         usb2 {
 834                 host_vbus_drv: host-vbus-drv {
 835                         rockchip,pins =
 836                                 <4 25 RK_FUNC_GPIO &pcfg_pull_none>;
 837                 };
 838         };
 839
 840         fusb30x {
 841                 fusb0_int: fusb0-int {
 842                         rockchip,pins = <1 2 RK_FUNC_GPIO &pcfg_pull_up>;
 843                 };
 844         };
 845 };