arch/arm64/boot/dts/rockchip/rk3399-android.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42 #include <dt-bindings/display/rk_fb.h>
  43 #include <dt-bindings/display/mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         chosen {
  49                 bootargs = "console=uart,mmio32,0xff1a0000";
  50         };
  51
  52         ramoops_mem: ramoops_mem {
  53                 reg = <0x0 0x100000 0x0 0x100000>;
  54                 reg-names = "ramoops_mem";
  55         };
  56
  57         ramoops {
  58                 compatible = "ramoops";
  59                 record-size = <0x0 0x20000>;
  60                 console-size = <0x0 0x80000>;
  61                 ftrace-size = <0x0 0x10000>;
  62                 pmsg-size = <0x0 0x50000>;
  63                 memory-region = <&ramoops_mem>;
  64         };
  65
  66         reserved-memory {
  67                 #address-cells = <2>;
  68                 #size-cells = <2>;
  69                 ranges;
  70
  71                 /* global autoconfigured region for contiguous allocations */
  72                 linux,cma {
  73                         compatible = "shared-dma-pool";
  74                         reusable;
  75                         size = <0x0 0x8000000>;
  76                         linux,cma-default;
  77                 };
  78         };
  79
  80         ion {
  81                 compatible = "rockchip,ion";
  82                 #address-cells = <1>;
  83                 #size-cells = <0>;
  84
  85                 cma-heap {
  86                         reg = <0x00000000 0x02000000>;
  87                 };
  88
  89                 system-heap {
  90                 };
  91         };
  92
  93         rk_key: rockchip-key {
  94                 compatible = "rockchip,key";
  95                 status = "okay";
  96
  97                 io-channels = <&saradc 1>;
  98
  99                 vol-up-key {
 100                         linux,code = <115>;
 101                         label = "volume up";
 102                         rockchip,adc_value = <1>;
 103                 };
 104
 105                 vol-down-key {
 106                         linux,code = <114>;
 107                         label = "volume down";
 108                         rockchip,adc_value = <170>;
 109                 };
 110
 111                 power-key {
 112                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 113                         linux,code = <116>;
 114                         label = "power";
 115                         gpio-key,wakeup;
 116                 };
 117
 118                 menu-key {
 119                         linux,code = <59>;
 120                         label = "menu";
 121                         rockchip,adc_value = <746>;
 122                 };
 123
 124                 home-key {
 125                         linux,code = <102>;
 126                         label = "home";
 127                         rockchip,adc_value = <355>;
 128                 };
 129
 130                 back-key {
 131                         linux,code = <158>;
 132                         label = "back";
 133                         rockchip,adc_value = <560>;
 134                 };
 135
 136                 camera-key {
 137                         linux,code = <212>;
 138                         label = "camera";
 139                         rockchip,adc_value = <450>;
 140                 };
 141         };
 142
 143         vpu: vpu_service@ff650000 {
 144                 compatible = "rockchip,vpu_service";
 145                 rockchip,grf = <&grf>;
 146                 iommu_enabled = <1>;
 147                 reg = <0x0 0xff650000 0x0 0x800>;
 148                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 149                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 150                 interrupt-names = "irq_dec", "irq_enc";
 151                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 152                 clock-names = "aclk_vcodec", "hclk_vcodec";
 153                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 154                 reset-names = "video_h", "video_a";
 155                 name = "vpu_service";
 156                 dev_mode = <0>;
 157         };
 158
 159         vpu_mmu: vpu_mmu {
 160                 dbgname = "vpu";
 161                 compatible = "rockchip,vpu_mmu";
 162                 reg = <0x0 0xff650800 0x0 0x40>;
 163                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 164                 interrupt-names = "vpu_mmu";
 165         };
 166
 167         rkvdec: rkvdec@ff660000 {
 168                 compatible = "rockchip,rkvdec";
 169                 rockchip,grf = <&grf>;
 170                 iommu_enabled = <1>;
 171                 reg = <0x0 0xff660000 0x0 0x400>;
 172                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 173                 interrupt-names = "irq_dec";
 174                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 175                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 176                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 177                 reset-names = "video_h", "video_a";
 178                 dev_mode = <2>;
 179                 name = "rkvdec";
 180         };
 181
 182         vdec_mmu: vdec_mmu {
 183                 dbgname = "vdec";
 184                 compatible = "rockchip,vdec_mmu";
 185                 reg = <0x0 0xff660480 0x0 0x40>,
 186                       <0x0 0xff6604c0 0x0 0x40>;
 187                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 188                 interrupt-names = "vdec_mmu";
 189         };
 190
 191         iep: iep@ff670000 {
 192                 compatible = "rockchip,iep";
 193                 iommu_enabled = <1>;
 194                 reg = <0x0 0xff670000 0x0 0x800>;
 195                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 196                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 197                 clock-names = "aclk_iep", "hclk_iep";
 198                 version = <2>;
 199         };
 200
 201         iep_mmu: iep-mmu {
 202                 dbgname = "iep";
 203                 compatible = "rockchip,iep_mmu";
 204                 reg = <0x0 0xff670800 0x0 0x40>;
 205                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 206                 interrupt-names = "iep_mmu";
 207         };
 208
 209         rga: rga@ff680000 {
 210                 compatible = "rockchip,rga2";
 211                 dev_mode = <1>;
 212                 reg = <0x0 0xff680000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
 215                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 216         };
 217
 218         fb: fb {
 219                 compatible = "rockchip,rk-fb";
 220                 rockchip,disp-mode = <DUAL>;
 221         };
 222
 223         rk_screen: screen {
 224                 compatible = "rockchip,screen";
 225                 #include <dt-bindings/display/screen-timing/lcd-tv080wum-nl0-mipi.dtsi>
 226         };
 227
 228         vopb_rk_fb: vop-rk-fb@ff900000 {
 229                 compatible = "rockchip,rk3399-lcdc";
 230                 rockchip,prop = <PRMRY>;
 231                 reg = <0x0 0xff900000 0x0 0x3efc>;
 232                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 233                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 234                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 235                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
 236                 reset-names = "axi", "ahb", "dclk";
 237                 rockchip,grf = <&grf>;
 238                 rockchip,pwr18 = <0>;
 239                 rockchip,iommu-enabled = <1>;
 240                 power_ctr: power_ctr {
 241                 /*rockchip,debug = <0>;
 242                 lcd_en: lcd-en {
 243                         rockchip,power_type = <GPIO>;
 244                         gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;//GPIO_C6 = 22
 245                         rockchip,delay = <10>;
 246                 };
 247                 */
 248
 249                 /*lcd_cs: lcd-cs {
 250                         rockchip,power_type = <GPIO>;
 251                         gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;//GPIO_C5 = 21
 252                         rockchip,delay = <10>;
 253                 };*/
 254
 255                 /*lcd_rst: lcd-rst {
 256                         rockchip,power_type = <GPIO>;
 257                         gpios = <&gpio3 GPIO_D6 GPIO_ACTIVE_HIGH>;
 258                         rockchip,delay = <5>;
 259                 };*/
 260                 };
 261         };
 262
 263         vopb_mmu_rk_fb: vopb-mmu {
 264                 dbgname = "vop";
 265                 compatible = "rockchip,vopb_mmu";
 266                 reg = <0x0 0xff903f00 0x0 0x100>;
 267                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-names = "vopb_mmu";
 269         };
 270
 271         vopl_rk_fb: vop-rk-fb@ff8f0000 {
 272                 compatible = "rockchip,rk3399-lcdc";
 273                 rockchip,prop = <EXTEND>;
 274                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
 275                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 276                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 277                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 278                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
 279                 reset-names = "axi", "ahb", "dclk";
 280                 rockchip,grf = <&grf>;
 281                 rockchip,pwr18 = <0>;
 282                 rockchip,iommu-enabled = <1>;
 283         };
 284
 285         vopl_mmu_rk_fb: vopl-mmu {
 286                 dbgname = "vop";
 287                 compatible = "rockchip,vopl_mmu";
 288                 reg = <0x0 0xff8f3f00 0x0 0x100>;
 289                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 290                 interrupt-names = "vopl_mmu";
 291         };
 292
 293         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
 294                 compatible = "rockchip,rk3399-hdmi";
 295                 reg = <0x0 0xff940000 0x0 0x20000>;
 296                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
 297                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 298                 clocks = <&cru PCLK_HDMI_CTRL>,
 299                          <&cru SCLK_HDMI_SFR>,
 300                          <&cru SCLK_HDMI_CEC>,
 301                          <&cru PLL_VPLL>;
 302                 clock-names = "pclk_hdmi",
 303                               "hdcp_clk_hdmi",
 304                               "cec_clk_hdmi",
 305                               "dclk_hdmi_phy";
 306                 resets = <&cru SRST_HDMI_CTRL>;
 307                 reset-names = "hdmi";
 308                 pinctrl-names = "default", "gpio";
 309                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
 310                 pinctrl-1 = <&i2c3_gpio>;
 311                 rockchip,grf = <&grf>;
 312         };
 313
 314         mipi0_rk_fb: mipi-rk-fb@ff960000 {
 315                 compatible = "rockchip,rk3399-dsi";
 316                 rockchip,prop = <0>;
 317                 rockchip,grf = <&grf>;
 318                 reg = <0x0 0xff960000 0x0 0x8000>;
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
 321                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 322         };
 323
 324         mipi1_rk_fb: mipi-rk-fb@ff968000 {
 325                 compatible = "rockchip,rk3399-dsi";
 326                 rockchip,prop = <1>;
 327                 reg = <0x0 0xff968000 0x0 0x8000>;
 328                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 329                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
 330                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
 331         };
 332 };
 333
 334 &usbdrd_dwc3_0 {
 335         dr_mode = "peripheral";
 336 };