ARM64: dts: rk3399-android: set ddc scl clock rate to 50KHz
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399-android.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 #include <dt-bindings/display/drm_mipi_dsi.h>
44 #include <dt-bindings/display/media-bus-format.h>
45 #include "rk3399-vop-clk-set.dtsi"
46
47 / {
48         compatible = "rockchip,android", "rockchip,rk3399";
49
50         chosen {
51                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
52         };
53
54         ramoops_mem: ramoops_mem {
55                 reg = <0x0 0x110000 0x0 0xf0000>;
56                 reg-names = "ramoops_mem";
57         };
58
59         ramoops {
60                 compatible = "ramoops";
61                 record-size = <0x0 0x20000>;
62                 console-size = <0x0 0x80000>;
63                 ftrace-size = <0x0 0x00000>;
64                 pmsg-size = <0x0 0x50000>;
65                 memory-region = <&ramoops_mem>;
66         };
67
68         fiq_debugger: fiq-debugger {
69                 compatible = "rockchip,fiq-debugger";
70                 rockchip,serial-id = <2>;
71                 rockchip,signal-irq = <182>;
72                 rockchip,wake-irq = <0>;
73                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
74                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
75                 pinctrl-names = "default";
76                 pinctrl-0 = <&uart2c_xfer>;
77         };
78
79         reserved-memory {
80                 #address-cells = <2>;
81                 #size-cells = <2>;
82                 ranges;
83
84                 drm_logo: drm-logo@00000000 {
85                         compatible = "rockchip,drm-logo";
86                         reg = <0x0 0x0 0x0 0x0>;
87                 };
88         };
89
90         rk_key: rockchip-key {
91                 compatible = "rockchip,key";
92                 status = "okay";
93
94                 io-channels = <&saradc 1>;
95
96                 vol-up-key {
97                         linux,code = <115>;
98                         label = "volume up";
99                         rockchip,adc_value = <1>;
100                 };
101
102                 vol-down-key {
103                         linux,code = <114>;
104                         label = "volume down";
105                         rockchip,adc_value = <170>;
106                 };
107
108                 power-key {
109                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
110                         linux,code = <116>;
111                         label = "power";
112                         gpio-key,wakeup;
113                 };
114
115                 menu-key {
116                         linux,code = <59>;
117                         label = "menu";
118                         rockchip,adc_value = <746>;
119                 };
120
121                 home-key {
122                         linux,code = <102>;
123                         label = "home";
124                         rockchip,adc_value = <355>;
125                 };
126
127                 back-key {
128                         linux,code = <158>;
129                         label = "back";
130                         rockchip,adc_value = <560>;
131                 };
132
133                 camera-key {
134                         linux,code = <212>;
135                         label = "camera";
136                         rockchip,adc_value = <450>;
137                 };
138         };
139
140         rga: rga@ff680000 {
141                 compatible = "rockchip,rga2";
142                 dev_mode = <1>;
143                 reg = <0x0 0xff680000 0x0 0x1000>;
144                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
145                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
146                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
147                 power-domains = <&power RK3399_PD_RGA>;
148                 dma-coherent;
149                 status = "okay";
150         };
151
152         isp0: isp@ff910000 {
153                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
154                 reg = <0x0 0xff910000 0x0 0x4000>;
155                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
156                 clocks =
157                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
158                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
159                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
160                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
161                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
162                 clock-names =
163                         "clk_cif_out", "clk_cif_pll",
164                         "pclk_dphytxrx", "pclk_dphy_ref",
165                         "aclk_isp0_noc", "aclk_isp0_wrapper",
166                         "hclk_isp0_noc", "hclk_isp0_wrapper",
167                         "clk_isp0", "pclk_dphyrx";
168                 pinctrl-names =
169                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
170                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
171                         "isp_flash_as_trigger_out";
172                 pinctrl-0 = <&cif_clkout>;
173                 pinctrl-1 = <&isp_dvp_d0d7>;
174                 pinctrl-2 = <&cif_clkout>;
175                 pinctrl-3 = <&isp_prelight>;
176                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
177                 pinctrl-5 = <&isp_flash_trigger>;
178                 rockchip,isp,mipiphy = <2>;
179                 rockchip,isp,cifphy = <1>;
180                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
181                 rockchip,grf = <&grf>;
182                 rockchip,cru = <&cru>;
183                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
184                 rockchip,isp,iommu-enable = <1>;
185                 power-domains = <&power RK3399_PD_ISP0>;
186                 iommus = <&isp0_mmu>;
187                 status = "disabled";
188         };
189
190         isp1: isp@ff920000 {
191                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
192                 reg = <0x0 0xff920000 0x0 0x4000>;
193                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
194                 clocks =
195                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
196                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
197                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
198                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
199                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
200                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
201                         <&cru SCLK_MIPIDPHY_CFG>;
202                 clock-names =
203                         "aclk_isp1_noc", "aclk_isp1_wrapper",
204                         "hclk_isp1_noc", "hclk_isp1_wrapper",
205                         "clk_isp1", "clk_cif_out",
206                         "clk_cif_pll", "pclk_dphytxrx",
207                         "pclk_dphy_ref", "pclk_isp1",
208                         "pclk_dphyrx", "pclk_mipi_dsi",
209                         "mipi_dphy_cfg";
210                 pinctrl-names =
211                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
212                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
213                         "isp_flash_as_trigger_out";
214                 pinctrl-0 = <&cif_clkout>;
215                 pinctrl-1 = <&isp_dvp_d0d7>;
216                 pinctrl-2 = <&cif_clkout>;
217                 pinctrl-3 = <&isp_prelight>;
218                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
219                 pinctrl-5 = <&isp_flash_trigger>;
220                 rockchip,isp,mipiphy = <2>;
221                 rockchip,isp,cifphy = <1>;
222                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
223                 rockchip,grf = <&grf>;
224                 rockchip,cru = <&cru>;
225                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
226                 rockchip,isp,iommu-enable = <1>;
227                 power-domains = <&power RK3399_PD_ISP1>;
228                 iommus = <&isp1_mmu>;
229                 status = "disabled";
230         };
231
232         uboot-charge {
233                 compatible = "rockchip,uboot-charge";
234                 rockchip,uboot-charge-on = <1>;
235                 rockchip,android-charge-on = <0>;
236         };
237
238         hdmi_dp_sound: hdmi-dp-sound {
239                 status = "disabled";
240                 compatible = "rockchip,rk3399-hdmi-dp";
241                 rockchip,cpu = <&i2s2>;
242                 rockchip,codec = <&hdmi>, <&cdn_dp>;
243         };
244 };
245
246 &vopb {
247         status = "okay";
248 };
249
250 &vopb_mmu {
251         status = "okay";
252 };
253
254 &vopl {
255         status = "okay";
256 };
257
258 &vopl_mmu {
259         status = "okay";
260 };
261
262 &hdmi {
263         #address-cells = <1>;
264         #size-cells = <0>;
265         #sound-dai-cells = <0>;
266         ddc-i2c-scl-high-time-ns = <9625>;
267         ddc-i2c-scl-low-time-ns = <10000>;
268         status = "okay";
269 };
270
271 &display_subsystem {
272         status = "okay";
273
274         ports = <&vopb_out>, <&vopl_out>;
275         memory-region = <&drm_logo>;
276         route {
277                 route_hdmi: route-hdmi {
278                         status = "disabled";
279                         logo,uboot = "logo.bmp";
280                         logo,kernel = "logo_kernel.bmp";
281                         logo,mode = "fullscreen";
282                         charge_logo,mode = "center";
283                         connect = <&vopb_out_hdmi>;
284                 };
285
286                 route_mipi: route-mipi {
287                         status = "disabled";
288                         logo,uboot = "logo.bmp";
289                         logo,kernel = "logo_kernel.bmp";
290                         logo,mode = "fullscreen";
291                         charge_logo,mode = "center";
292                         connect = <&vopb_out_mipi>;
293                 };
294
295                 route_edp: route-edp {
296                         status = "disabled";
297                         logo,uboot = "logo.bmp";
298                         logo,kernel = "logo_kernel.bmp";
299                         logo,mode = "fullscreen";
300                         charge_logo,mode = "center";
301                         connect = <&vopb_out_edp>;
302                 };
303         };
304 };
305
306 &i2s2 {
307         #sound-dai-cells = <0>;
308 };
309
310 &rkvdec {
311         status = "okay";
312 };
313
314 &usbdrd_dwc3_0 {
315         dr_mode = "otg";
316 };
317
318 &vpu {
319         status = "okay";
320 };
321
322 &pinctrl {
323         isp {
324                 cif_clkout: cif-clkout {
325                         rockchip,pins =
326                                 /*cif_clkout*/
327                                 <2 11 RK_FUNC_3 &pcfg_pull_none>;
328                 };
329
330                 isp_dvp_d0d7: isp-dvp-d0d7 {
331                         rockchip,pins =
332                                 /*cif_data0*/
333                                 <2 0 RK_FUNC_3 &pcfg_pull_none>,
334                                 /*cif_data1*/
335                                 <2 1 RK_FUNC_3 &pcfg_pull_none>,
336                                 /*cif_data2*/
337                                 <2 2 RK_FUNC_3 &pcfg_pull_none>,
338                                 /*cif_data3*/
339                                 <2 3 RK_FUNC_3 &pcfg_pull_none>,
340                                 /*cif_data4*/
341                                 <2 4 RK_FUNC_3 &pcfg_pull_none>,
342                                 /*cif_data5*/
343                                 <2 5 RK_FUNC_3 &pcfg_pull_none>,
344                                 /*cif_data6*/
345                                 <2 6 RK_FUNC_3 &pcfg_pull_none>,
346                                 /*cif_data7*/
347                                 <2 7 RK_FUNC_3 &pcfg_pull_none>,
348                                 /*cif_sync*/
349                                 <2 8 RK_FUNC_3 &pcfg_pull_none>,
350                                 /*cif_href*/
351                                 <2 9 RK_FUNC_3 &pcfg_pull_none>,
352                                 /*cif_clkin*/
353                                 <2 10 RK_FUNC_3 &pcfg_pull_none>;
354                 };
355
356                 isp_shutter: isp-shutter {
357                         rockchip,pins =
358                                 /*SHUTTEREN*/
359                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,
360                                 /*SHUTTERTRIG*/
361                                 <1 0 RK_FUNC_1 &pcfg_pull_none>;
362                 };
363
364                 isp_flash_trigger: isp-flash-trigger {
365                         /*ISP_FLASHTRIGOU*/
366                         rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
367                 };
368
369                 isp_prelight: isp-prelight {
370                         /*ISP_PRELIGHTTRIG*/
371                         rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
372                 };
373
374                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
375                         /*ISP_FLASHTRIGOU*/
376                         rockchip,pins =
377                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
378                 };
379         };
380 };
381