e2310af11ad428e5b6d9d0478585660c3f637555
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399-android.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
44
45 / {
46         compatible = "rockchip,android", "rockchip,rk3399";
47
48         chosen {
49                 bootargs = "console=uart,mmio32,0xff1a0000";
50         };
51
52         ramoops_mem: ramoops_mem {
53                 reg = <0x0 0x100000 0x0 0x100000>;
54                 reg-names = "ramoops_mem";
55         };
56
57         ramoops {
58                 compatible = "ramoops";
59                 record-size = <0x0 0x20000>;
60                 console-size = <0x0 0x80000>;
61                 ftrace-size = <0x0 0x10000>;
62                 pmsg-size = <0x0 0x50000>;
63                 memory-region = <&ramoops_mem>;
64         };
65
66         reserved-memory {
67                 #address-cells = <2>;
68                 #size-cells = <2>;
69                 ranges;
70
71                 /* global autoconfigured region for contiguous allocations */
72                 linux,cma {
73                         compatible = "shared-dma-pool";
74                         reusable;
75                         size = <0x0 0x8000000>;
76                         linux,cma-default;
77                 };
78         };
79
80         ion {
81                 compatible = "rockchip,ion";
82                 #address-cells = <1>;
83                 #size-cells = <0>;
84
85                 cma-heap {
86                         reg = <0x00000000 0x02000000>;
87                 };
88
89                 system-heap {
90                 };
91         };
92
93         rk_key: rockchip-key {
94                 compatible = "rockchip,key";
95                 status = "okay";
96
97                 io-channels = <&saradc 1>;
98
99                 vol-up-key {
100                         linux,code = <115>;
101                         label = "volume up";
102                         rockchip,adc_value = <1>;
103                 };
104
105                 vol-down-key {
106                         linux,code = <114>;
107                         label = "volume down";
108                         rockchip,adc_value = <170>;
109                 };
110
111                 power-key {
112                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
113                         linux,code = <116>;
114                         label = "power";
115                         gpio-key,wakeup;
116                 };
117
118                 menu-key {
119                         linux,code = <59>;
120                         label = "menu";
121                         rockchip,adc_value = <746>;
122                 };
123
124                 home-key {
125                         linux,code = <102>;
126                         label = "home";
127                         rockchip,adc_value = <355>;
128                 };
129
130                 back-key {
131                         linux,code = <158>;
132                         label = "back";
133                         rockchip,adc_value = <560>;
134                 };
135
136                 camera-key {
137                         linux,code = <212>;
138                         label = "camera";
139                         rockchip,adc_value = <450>;
140                 };
141         };
142
143         vpu: vpu_service@ff650000 {
144                 compatible = "rockchip,vpu_service";
145                 rockchip,grf = <&grf>;
146                 iommu_enabled = <1>;
147                 reg = <0x0 0xff650000 0x0 0x800>;
148                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
149                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
150                 interrupt-names = "irq_dec", "irq_enc";
151                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
152                 clock-names = "aclk_vcodec", "hclk_vcodec";
153                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
154                 reset-names = "video_h", "video_a";
155                 power-domains = <&power RK3399_PD_VCODEC>;
156                 name = "vpu_service";
157                 dev_mode = <0>;
158         };
159
160         vpu_mmu: vpu_mmu {
161                 dbgname = "vpu";
162                 compatible = "rockchip,vpu_mmu";
163                 reg = <0x0 0xff650800 0x0 0x40>;
164                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
165                 interrupt-names = "vpu_mmu";
166         };
167
168         rkvdec: rkvdec@ff660000 {
169                 compatible = "rockchip,rkvdec";
170                 rockchip,grf = <&grf>;
171                 iommu_enabled = <1>;
172                 reg = <0x0 0xff660000 0x0 0x400>;
173                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
174                 interrupt-names = "irq_dec";
175                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
176                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
177                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
178                 reset-names = "video_h", "video_a";
179                 power-domains = <&power RK3399_PD_VDU>;
180                 dev_mode = <2>;
181                 name = "rkvdec";
182         };
183
184         vdec_mmu: vdec_mmu {
185                 dbgname = "vdec";
186                 compatible = "rockchip,vdec_mmu";
187                 reg = <0x0 0xff660480 0x0 0x40>,
188                       <0x0 0xff6604c0 0x0 0x40>;
189                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
190                 interrupt-names = "vdec_mmu";
191         };
192
193         iep: iep@ff670000 {
194                 compatible = "rockchip,iep";
195                 iommu_enabled = <1>;
196                 reg = <0x0 0xff670000 0x0 0x800>;
197                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
198                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
199                 clock-names = "aclk_iep", "hclk_iep";
200                 power-domains = <&power RK3399_PD_IEP>;
201                 version = <2>;
202         };
203
204         iep_mmu: iep-mmu {
205                 dbgname = "iep";
206                 compatible = "rockchip,iep_mmu";
207                 reg = <0x0 0xff670800 0x0 0x40>;
208                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
209                 interrupt-names = "iep_mmu";
210         };
211
212         rga: rga@ff680000 {
213                 compatible = "rockchip,rga2";
214                 dev_mode = <1>;
215                 reg = <0x0 0xff680000 0x0 0x1000>;
216                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
217                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
218                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
219                 power-domains = <&power RK3399_PD_RGA>;
220                 status = "okay";
221         };
222
223         fb: fb {
224                 status = "okay";
225                 compatible = "rockchip,rk-fb";
226                 rockchip,disp-mode = <DUAL>;
227         };
228
229         rk_screen: screen {
230                 status = "okay";
231                 compatible = "rockchip,screen";
232         };
233
234         vopb_rk_fb: vop-rk-fb@ff900000 {
235                 status = "disabled";
236                 compatible = "rockchip,rk3399-lcdc";
237                 rockchip,prop = <PRMRY>;
238                 reg = <0x0 0xff900000 0x0 0x3efc>;
239                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
240                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
241                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
242                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
243                 reset-names = "axi", "ahb", "dclk";
244                 rockchip,grf = <&grf>;
245                 rockchip,pwr18 = <0>;
246                 rockchip,iommu-enabled = <1>;
247                 power-domains = <&power RK3399_PD_VOPB>;
248         };
249
250         vopb_mmu_rk_fb: vopb-mmu {
251                 status = "okay";
252                 dbgname = "vop";
253                 compatible = "rockchip,vopb_mmu";
254                 reg = <0x0 0xff903f00 0x0 0x100>;
255                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
256                 interrupt-names = "vopb_mmu";
257         };
258
259         vopl_rk_fb: vop-rk-fb@ff8f0000 {
260                 status = "disabled";
261                 compatible = "rockchip,rk3399-lcdc";
262                 rockchip,prop = <EXTEND>;
263                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
264                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
265                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
266                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
267                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
268                 reset-names = "axi", "ahb", "dclk";
269                 rockchip,grf = <&grf>;
270                 rockchip,pwr18 = <0>;
271                 rockchip,iommu-enabled = <1>;
272                 power-domains = <&power RK3399_PD_VOPL>;
273         };
274
275         vopl_mmu_rk_fb: vopl-mmu {
276                 status = "okay";
277                 dbgname = "vop";
278                 compatible = "rockchip,vopl_mmu";
279                 reg = <0x0 0xff8f3f00 0x0 0x100>;
280                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
281                 interrupt-names = "vopl_mmu";
282         };
283
284         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
285                 compatible = "rockchip,rk3399-hdmi";
286                 reg = <0x0 0xff940000 0x0 0x20000>;
287                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
288                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
289                 clocks = <&cru PCLK_HDMI_CTRL>,
290                          <&cru SCLK_HDMI_SFR>,
291                          <&cru SCLK_HDMI_CEC>,
292                          <&cru PLL_VPLL>;
293                 clock-names = "pclk_hdmi",
294                               "hdcp_clk_hdmi",
295                               "cec_clk_hdmi",
296                               "dclk_hdmi_phy";
297                 resets = <&cru SRST_HDMI_CTRL>;
298                 reset-names = "hdmi";
299                 pinctrl-names = "default", "gpio";
300                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
301                 pinctrl-1 = <&i2c3_gpio>;
302                 rockchip,grf = <&grf>;
303                 power-domains = <&power RK3399_PD_HDCP>;
304         };
305
306         mipi0_rk_fb: mipi-rk-fb@ff960000 {
307                 compatible = "rockchip,rk3399-dsi";
308                 rockchip,prop = <0>;
309                 rockchip,grf = <&grf>;
310                 reg = <0x0 0xff960000 0x0 0x8000>;
311                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
312                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
313                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
314                 power-domains = <&power RK3399_PD_VIO>;
315         };
316
317         mipi1_rk_fb: mipi-rk-fb@ff968000 {
318                 compatible = "rockchip,rk3399-dsi";
319                 rockchip,prop = <1>;
320                 rockchip,grf = <&grf>;
321                 reg = <0x0 0xff968000 0x0 0x8000>;
322                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
323                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
324                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
325                 power-domains = <&power RK3399_PD_VIO>;
326         };
327
328         edp_rk_fb: edp-rk-fb@ff970000 {
329                 compatible = "rockchip,rk3399-edp-fb";
330                 reg = <0x0 0xff970000 0x0 0x8000>;
331                 rockchip,grf = <&grf>;
332                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
333                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>;
334                 clock-names = "clk_edp", "pclk_edp";
335                 resets = <&cru SRST_P_EDP_CTRL>;
336                 reset-names = "edp_apb";
337                 status = "disabled";
338         };
339
340         hdmi-sound {
341                 compatible = "simple-audio-card";
342                 simple-audio-card,format = "i2s";
343                 simple-audio-card,mclk-fs = <256>;
344                 simple-audio-card,name = "rockchip,hdmi";
345                 simple-audio-card,cpu {
346                         sound-dai = <&i2s2>;
347                 };
348                 simple-audio-card,codec {
349                         sound-dai = <&dw_hdmi_audio>;
350                 };
351         };
352
353         dw_hdmi_audio: dw-hdmi-audio {
354                 compatible = "rockchip,dw-hdmi-audio";
355                 #sound-dai-cells = <0>;
356         };
357 };
358
359 &i2s2 {
360         status = "okay";
361         #sound-dai-cells = <0>;
362 };
363
364 &usbdrd_dwc3_0 {
365         dr_mode = "peripheral";
366 };