arch/arm64/boot/dts/rockchip/rk3399-android-next.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/display/drm_mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         chosen {
  49                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
  50         };
  51
  52         ramoops_mem: ramoops_mem {
  53                 reg = <0x0 0x110000 0x0 0xf0000>;
  54                 reg-names = "ramoops_mem";
  55         };
  56
  57         ramoops {
  58                 compatible = "ramoops";
  59                 record-size = <0x0 0x20000>;
  60                 console-size = <0x0 0x80000>;
  61                 ftrace-size = <0x0 0x00000>;
  62                 pmsg-size = <0x0 0x50000>;
  63                 memory-region = <&ramoops_mem>;
  64         };
  65
  66         fiq_debugger: fiq-debugger {
  67                 compatible = "rockchip,fiq-debugger";
  68                 rockchip,serial-id = <2>;
  69                 rockchip,signal-irq = <182>;
  70                 rockchip,wake-irq = <0>;
  71                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  72                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&uart2c_xfer>;
  75         };
  76
  77         reserved-memory {
  78                 #address-cells = <2>;
  79                 #size-cells = <2>;
  80                 ranges;
  81
  82                 drm_logo: drm-logo@00000000 {
  83                         compatible = "rockchip,drm-logo";
  84                         reg = <0x0 0x0 0x0 0x0>;
  85                 };
  86         };
  87
  88         rk_key: rockchip-key {
  89                 compatible = "rockchip,key";
  90                 status = "okay";
  91
  92                 io-channels = <&saradc 1>;
  93
  94                 vol-up-key {
  95                         linux,code = <115>;
  96                         label = "volume up";
  97                         rockchip,adc_value = <1>;
  98                 };
  99
 100                 vol-down-key {
 101                         linux,code = <114>;
 102                         label = "volume down";
 103                         rockchip,adc_value = <170>;
 104                 };
 105
 106                 power-key {
 107                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 108                         linux,code = <116>;
 109                         label = "power";
 110                         gpio-key,wakeup;
 111                 };
 112
 113                 menu-key {
 114                         linux,code = <59>;
 115                         label = "menu";
 116                         rockchip,adc_value = <746>;
 117                 };
 118
 119                 home-key {
 120                         linux,code = <102>;
 121                         label = "home";
 122                         rockchip,adc_value = <355>;
 123                 };
 124
 125                 back-key {
 126                         linux,code = <158>;
 127                         label = "back";
 128                         rockchip,adc_value = <560>;
 129                 };
 130
 131                 camera-key {
 132                         linux,code = <212>;
 133                         label = "camera";
 134                         rockchip,adc_value = <450>;
 135                 };
 136         };
 137
 138         vpu: vpu_service@ff650000 {
 139                 compatible = "rockchip,vpu_service";
 140                 rockchip,grf = <&grf>;
 141                 iommus = <&vpu_mmu>;
 142                 iommu_enabled = <1>;
 143                 reg = <0x0 0xff650000 0x0 0x800>;
 144                 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>,
 145                         <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
 146                 interrupt-names = "irq_dec", "irq_enc";
 147                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
 148                 clock-names = "aclk_vcodec", "hclk_vcodec";
 149                 resets = <&cru SRST_H_VCODEC>, <&cru SRST_A_VCODEC>;
 150                 reset-names = "video_h", "video_a";
 151                 power-domains = <&power RK3399_PD_VCODEC>;
 152                 name = "vpu_service";
 153                 dev_mode = <0>;
 154                 /* 0 means ion, 1 means drm */
 155                 allocator = <1>;
 156                 status = "disabled";
 157         };
 158
 159         vpu_mmu: iommu@ff650800 {
 160                 dbgname = "vpu";
 161                 compatible = "rockchip,iommu";
 162                 reg = <0x0 0xff650800 0x0 0x40>;
 163                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
 164                 interrupt-names = "vpu_mmu";
 165                 #iommu-cells = <0>;
 166         };
 167
 168         rkvdec: rkvdec@ff660000 {
 169                 compatible = "rockchip,rkvdec";
 170                 rockchip,grf = <&grf>;
 171                 iommus = <&vdec_mmu>;
 172                 iommu_enabled = <1>;
 173                 reg = <0x0 0xff660000 0x0 0x400>;
 174                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
 175                 interrupt-names = "irq_dec";
 176                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,<&cru SCLK_VDU_CA>,<&cru SCLK_VDU_CORE>;
 177                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 178                 resets = <&cru SRST_H_VDU>, <&cru SRST_A_VDU>;
 179                 reset-names = "video_h", "video_a";
 180                 power-domains = <&power RK3399_PD_VDU>;
 181                 dev_mode = <2>;
 182                 name = "rkvdec";
 183                 /* 0 means ion, 1 means drm */
 184                 allocator = <1>;
 185                 status = "disabled";
 186         };
 187
 188         vdec_mmu: iommu@ff660480 {
 189                 dbgname = "vdec";
 190                 compatible = "rockchip,iommu";
 191                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
 192                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
 193                 interrupt-names = "vdec_mmu";
 194                 #iommu-cells = <0>;
 195         };
 196
 197         isp0: isp@ff910000 {
 198                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 199                 reg = <0x0 0xff910000 0x0 0x4000>;
 200                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 201                 clocks =
 202                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 203                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 204                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 205                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 206                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 207                 clock-names =
 208                         "clk_cif_out", "clk_cif_pll",
 209                         "pclk_dphytxrx", "pclk_dphy_ref",
 210                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 211                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 212                         "clk_isp0", "pclk_dphyrx";
 213                 pinctrl-names =
 214                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 215                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 216                         "isp_flash_as_trigger_out";
 217                 pinctrl-0 = <&cif_clkout>;
 218                 pinctrl-1 = <&isp_dvp_d0d7>;
 219                 pinctrl-2 = <&cif_clkout>;
 220                 pinctrl-3 = <&isp_prelight>;
 221                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 222                 pinctrl-5 = <&isp_flash_trigger>;
 223                 rockchip,isp,mipiphy = <2>;
 224                 rockchip,isp,cifphy = <1>;
 225                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 226                 rockchip,grf = <&grf>;
 227                 rockchip,cru = <&cru>;
 228                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 229                 rockchip,isp,iommu-enable = <1>;
 230                 power-domains = <&power RK3399_PD_ISP0>;
 231                 iommus = <&isp0_mmu>;
 232                 status = "disabled";
 233         };
 234
 235         isp1: isp@ff920000 {
 236                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 237                 reg = <0x0 0xff920000 0x0 0x4000>;
 238                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 239                 clocks =
 240                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
 241                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
 242                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
 243                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
 244                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
 245                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
 246                         <&cru SCLK_MIPIDPHY_CFG>;
 247                 clock-names =
 248                         "aclk_isp1_noc", "aclk_isp1_wrapper",
 249                         "hclk_isp1_noc", "hclk_isp1_wrapper",
 250                         "clk_isp1", "clk_cif_out",
 251                         "clk_cif_pll", "pclk_dphytxrx",
 252                         "pclk_dphy_ref", "pclk_isp1",
 253                         "pclk_dphyrx", "pclk_mipi_dsi",
 254                         "mipi_dphy_cfg";
 255                 pinctrl-names =
 256                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 257                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 258                         "isp_flash_as_trigger_out";
 259                 pinctrl-0 = <&cif_clkout>;
 260                 pinctrl-1 = <&isp_dvp_d0d7>;
 261                 pinctrl-2 = <&cif_clkout>;
 262                 pinctrl-3 = <&isp_prelight>;
 263                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 264                 pinctrl-5 = <&isp_flash_trigger>;
 265                 rockchip,isp,mipiphy = <2>;
 266                 rockchip,isp,cifphy = <1>;
 267                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 268                 rockchip,grf = <&grf>;
 269                 rockchip,cru = <&cru>;
 270                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 271                 rockchip,isp,iommu-enable = <1>;
 272                 power-domains = <&power RK3399_PD_ISP1>;
 273                 iommus = <&isp1_mmu>;
 274                 status = "disabled";
 275         };
 276
 277         uboot-charge {
 278                 compatible = "rockchip,uboot-charge";
 279                 rockchip,uboot-charge-on = <1>;
 280                 rockchip,android-charge-on = <0>;
 281         };
 282 };
 283
 284 &vopb {
 285         status = "okay";
 286 };
 287
 288 &vopb_mmu {
 289         status = "okay";
 290 };
 291
 292 &vopl {
 293         status = "okay";
 294 };
 295
 296 &vopl_mmu {
 297         status = "okay";
 298 };
 299
 300 &rga {
 301         status = "okay";
 302 };
 303
 304 &i2c3 {
 305         status = "okay";
 306         i2c-scl-rising-time-ns = <450>;
 307         i2c-scl-falling-time-ns = <15>;
 308 };
 309
 310 &hdmi {
 311         ddc-i2c-bus = <&i2c3>;
 312         status = "okay";
 313 };
 314
 315 &display_subsystem {
 316         status = "okay";
 317
 318         ports = <&vopb_out>, <&vopl_out>;
 319         memory-region = <&drm_logo>;
 320         route {
 321                 route_hdmi: route-hdmi {
 322                         status = "disabled";
 323                         logo,uboot = "logo.bmp";
 324                         logo,kernel = "logo_kernel.bmp";
 325                         logo,mode = "fullscreen";
 326                         charge_logo,mode = "center";
 327                         connect = <&vopl_out_hdmi>;
 328                 };
 329
 330                 route_mipi: route-mipi {
 331                         status = "disabled";
 332                         logo,uboot = "logo.bmp";
 333                         logo,kernel = "logo_kernel.bmp";
 334                         logo,mode = "fullscreen";
 335                         charge_logo,mode = "center";
 336                         connect = <&vopb_out_mipi>;
 337                 };
 338
 339                 route_edp: route-edp {
 340                         status = "disabled";
 341                         logo,uboot = "logo.bmp";
 342                         logo,kernel = "logo_kernel.bmp";
 343                         logo,mode = "fullscreen";
 344                         charge_logo,mode = "center";
 345                         connect = <&vopb_out_edp>;
 346                 };
 347         };
 348 };
 349
 350 &i2s2 {
 351         #sound-dai-cells = <0>;
 352 };
 353
 354 &usbdrd_dwc3_0 {
 355         dr_mode = "otg";
 356 };
 357
 358 &pinctrl {
 359         isp {
 360                 cif_clkout: cif-clkout {
 361                         rockchip,pins =
 362                                 /*cif_clkout*/
 363                                 <2 11 RK_FUNC_3 &pcfg_pull_none>;
 364                         };
 365
 366                         isp_dvp_d0d7: isp-dvp-d0d7 {
 367                                 rockchip,pins =
 368                                         /*cif_data0*/
 369                                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
 370                                         /*cif_data1*/
 371                                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
 372                                         /*cif_data2*/
 373                                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
 374                                         /*cif_data3*/
 375                                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
 376                                         /*cif_data4*/
 377                                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
 378                                         /*cif_data5*/
 379                                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
 380                                         /*cif_data6*/
 381                                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
 382                                         /*cif_data7*/
 383                                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
 384                                         /*cif_sync*/
 385                                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
 386                                         /*cif_href*/
 387                                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
 388                                         /*cif_clkin*/
 389                                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
 390                         };
 391
 392                         isp_shutter: isp-shutter {
 393                                 rockchip,pins =
 394                                         /*SHUTTEREN*/
 395                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
 396                                         /*SHUTTERTRIG*/
 397                                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
 398                         };
 399
 400                         isp_flash_trigger: isp-flash-trigger {
 401                                 /*ISP_FLASHTRIGOU*/
 402                                 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
 403                         };
 404
 405                         isp_prelight: isp-prelight {
 406                                 /*ISP_PRELIGHTTRIG*/
 407                                 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
 408                         };
 409
 410                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 411                                 /*ISP_FLASHTRIGOU*/
 412                                 rockchip,pins =
 413                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
 414                         };
 415                 };
 416 };
 417