arch/arm64/boot/dts/rockchip/rk3399-android-next.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/display/drm_mipi_dsi.h>
  44
  45 / {
  46         compatible = "rockchip,android", "rockchip,rk3399";
  47
  48         chosen {
  49                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
  50         };
  51
  52         ramoops_mem: ramoops_mem {
  53                 reg = <0x0 0x110000 0x0 0xf0000>;
  54                 reg-names = "ramoops_mem";
  55         };
  56
  57         ramoops {
  58                 compatible = "ramoops";
  59                 record-size = <0x0 0x20000>;
  60                 console-size = <0x0 0x80000>;
  61                 ftrace-size = <0x0 0x00000>;
  62                 pmsg-size = <0x0 0x50000>;
  63                 memory-region = <&ramoops_mem>;
  64         };
  65
  66         fiq_debugger: fiq-debugger {
  67                 compatible = "rockchip,fiq-debugger";
  68                 rockchip,serial-id = <2>;
  69                 rockchip,signal-irq = <182>;
  70                 rockchip,wake-irq = <0>;
  71                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  72                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&uart2c_xfer>;
  75         };
  76
  77         reserved-memory {
  78                 #address-cells = <2>;
  79                 #size-cells = <2>;
  80                 ranges;
  81
  82                 drm_logo: drm-logo@00000000 {
  83                         compatible = "rockchip,drm-logo";
  84                         reg = <0x0 0x0 0x0 0x0>;
  85                 };
  86         };
  87
  88         rk_key: rockchip-key {
  89                 compatible = "rockchip,key";
  90                 status = "okay";
  91
  92                 io-channels = <&saradc 1>;
  93
  94                 vol-up-key {
  95                         linux,code = <115>;
  96                         label = "volume up";
  97                         rockchip,adc_value = <1>;
  98                 };
  99
 100                 vol-down-key {
 101                         linux,code = <114>;
 102                         label = "volume down";
 103                         rockchip,adc_value = <170>;
 104                 };
 105
 106                 power-key {
 107                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 108                         linux,code = <116>;
 109                         label = "power";
 110                         gpio-key,wakeup;
 111                 };
 112
 113                 menu-key {
 114                         linux,code = <59>;
 115                         label = "menu";
 116                         rockchip,adc_value = <746>;
 117                 };
 118
 119                 home-key {
 120                         linux,code = <102>;
 121                         label = "home";
 122                         rockchip,adc_value = <355>;
 123                 };
 124
 125                 back-key {
 126                         linux,code = <158>;
 127                         label = "back";
 128                         rockchip,adc_value = <560>;
 129                 };
 130
 131                 camera-key {
 132                         linux,code = <212>;
 133                         label = "camera";
 134                         rockchip,adc_value = <450>;
 135                 };
 136         };
 137
 138         isp0: isp@ff910000 {
 139                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 140                 reg = <0x0 0xff910000 0x0 0x4000>;
 141                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
 142                 clocks =
 143                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
 144                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
 145                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
 146                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
 147                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
 148                 clock-names =
 149                         "clk_cif_out", "clk_cif_pll",
 150                         "pclk_dphytxrx", "pclk_dphy_ref",
 151                         "aclk_isp0_noc", "aclk_isp0_wrapper",
 152                         "hclk_isp0_noc", "hclk_isp0_wrapper",
 153                         "clk_isp0", "pclk_dphyrx";
 154                 pinctrl-names =
 155                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 156                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 157                         "isp_flash_as_trigger_out";
 158                 pinctrl-0 = <&cif_clkout>;
 159                 pinctrl-1 = <&isp_dvp_d0d7>;
 160                 pinctrl-2 = <&cif_clkout>;
 161                 pinctrl-3 = <&isp_prelight>;
 162                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 163                 pinctrl-5 = <&isp_flash_trigger>;
 164                 rockchip,isp,mipiphy = <2>;
 165                 rockchip,isp,cifphy = <1>;
 166                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 167                 rockchip,grf = <&grf>;
 168                 rockchip,cru = <&cru>;
 169                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 170                 rockchip,isp,iommu-enable = <1>;
 171                 power-domains = <&power RK3399_PD_ISP0>;
 172                 iommus = <&isp0_mmu>;
 173                 status = "disabled";
 174         };
 175
 176         isp1: isp@ff920000 {
 177                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
 178                 reg = <0x0 0xff920000 0x0 0x4000>;
 179                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
 180                 clocks =
 181                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
 182                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
 183                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
 184                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
 185                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
 186                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
 187                         <&cru SCLK_MIPIDPHY_CFG>;
 188                 clock-names =
 189                         "aclk_isp1_noc", "aclk_isp1_wrapper",
 190                         "hclk_isp1_noc", "hclk_isp1_wrapper",
 191                         "clk_isp1", "clk_cif_out",
 192                         "clk_cif_pll", "pclk_dphytxrx",
 193                         "pclk_dphy_ref", "pclk_isp1",
 194                         "pclk_dphyrx", "pclk_mipi_dsi",
 195                         "mipi_dphy_cfg";
 196                 pinctrl-names =
 197                         "cif_clkout", "isp_dvp8bit0", "isp_mipi_fl",
 198                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 199                         "isp_flash_as_trigger_out";
 200                 pinctrl-0 = <&cif_clkout>;
 201                 pinctrl-1 = <&isp_dvp_d0d7>;
 202                 pinctrl-2 = <&cif_clkout>;
 203                 pinctrl-3 = <&isp_prelight>;
 204                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
 205                 pinctrl-5 = <&isp_flash_trigger>;
 206                 rockchip,isp,mipiphy = <2>;
 207                 rockchip,isp,cifphy = <1>;
 208                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
 209                 rockchip,grf = <&grf>;
 210                 rockchip,cru = <&cru>;
 211                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
 212                 rockchip,isp,iommu-enable = <1>;
 213                 power-domains = <&power RK3399_PD_ISP1>;
 214                 iommus = <&isp1_mmu>;
 215                 status = "disabled";
 216         };
 217 };
 218
 219 &vopb {
 220         status = "okay";
 221 };
 222
 223 &vopb_mmu {
 224         status = "okay";
 225 };
 226
 227 &vopl {
 228         status = "okay";
 229 };
 230
 231 &vopl_mmu {
 232         status = "okay";
 233 };
 234
 235 &rga {
 236         status = "okay";
 237 };
 238
 239 &i2c3 {
 240         status = "okay";
 241         i2c-scl-rising-time-ns = <450>;
 242         i2c-scl-falling-time-ns = <15>;
 243 };
 244
 245 &hdmi {
 246         ddc-i2c-bus = <&i2c3>;
 247         status = "okay";
 248 };
 249
 250 &display_subsystem {
 251         status = "okay";
 252
 253         memory-region = <&drm_logo>;
 254         route {
 255                 route_hdmi: route-hdmi {
 256                         status = "disabled";
 257                         logo,uboot = "logo.bmp";
 258                         logo,kernel = "logo_kernel.bmp";
 259                         logo,mode = "fullscreen";
 260                         charge_logo,mode = "center";
 261                         connect = <&vopl_out_hdmi>;
 262                 };
 263
 264                 route_mipi: route-mipi {
 265                         status = "disabled";
 266                         logo,uboot = "logo.bmp";
 267                         logo,kernel = "logo_kernel.bmp";
 268                         logo,mode = "fullscreen";
 269                         charge_logo,mode = "center";
 270                         connect = <&vopb_out_mipi>;
 271                 };
 272
 273                 route_edp: route-edp {
 274                         status = "disabled";
 275                         logo,uboot = "logo.bmp";
 276                         logo,kernel = "logo_kernel.bmp";
 277                         logo,mode = "fullscreen";
 278                         charge_logo,mode = "center";
 279                         connect = <&vopb_out_edp>;
 280                 };
 281         };
 282 };
 283
 284 &i2s2 {
 285         #sound-dai-cells = <0>;
 286 };
 287
 288 &usbdrd_dwc3_0 {
 289         dr_mode = "otg";
 290 };
 291
 292 &pinctrl {
 293         isp {
 294                 cif_clkout: cif-clkout {
 295                         rockchip,pins =
 296                                 /*cif_clkout*/
 297                                 <2 11 RK_FUNC_3 &pcfg_pull_none>;
 298                         };
 299
 300                         isp_dvp_d0d7: isp-dvp-d0d7 {
 301                                 rockchip,pins =
 302                                         /*cif_data0*/
 303                                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
 304                                         /*cif_data1*/
 305                                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
 306                                         /*cif_data2*/
 307                                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
 308                                         /*cif_data3*/
 309                                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
 310                                         /*cif_data4*/
 311                                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
 312                                         /*cif_data5*/
 313                                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
 314                                         /*cif_data6*/
 315                                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
 316                                         /*cif_data7*/
 317                                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
 318                                         /*cif_sync*/
 319                                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
 320                                         /*cif_href*/
 321                                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
 322                                         /*cif_clkin*/
 323                                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
 324                         };
 325
 326                         isp_shutter: isp-shutter {
 327                                 rockchip,pins =
 328                                         /*SHUTTEREN*/
 329                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
 330                                         /*SHUTTERTRIG*/
 331                                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
 332                         };
 333
 334                         isp_flash_trigger: isp-flash-trigger {
 335                                 /*ISP_FLASHTRIGOU*/
 336                                 rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
 337                         };
 338
 339                         isp_prelight: isp-prelight {
 340                                 /*ISP_PRELIGHTTRIG*/
 341                                 rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
 342                         };
 343
 344                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 345                                 /*ISP_FLASHTRIGOU*/
 346                                 rockchip,pins =
 347                                         <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
 348                         };
 349                 };
 350 };
 351