arm64: dts: rockchip: rk3368 emmc add property 'mmc-hs200-1_8v'
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3399-android-6.0.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This file is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This file is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42 #include <dt-bindings/display/rk_fb.h>
43 #include <dt-bindings/display/mipi_dsi.h>
44 #include "rk3399-vop-clk-set.dtsi"
45
46 / {
47         compatible = "rockchip,android", "rockchip,rk3399";
48
49         aliases {
50                 lcdc0 = &vopb_rk_fb;
51                 lcdc1 = &vopl_rk_fb;
52         };
53
54         chosen {
55                 bootargs = "earlycon=uart8250,mmio32,0xff1a0000 swiotlb=1";
56         };
57
58         ramoops_mem: ramoops_mem {
59                 reg = <0x0 0x110000 0x0 0xf0000>;
60                 reg-names = "ramoops_mem";
61         };
62
63         ramoops {
64                 compatible = "ramoops";
65                 record-size = <0x0 0x20000>;
66                 console-size = <0x0 0x80000>;
67                 ftrace-size = <0x0 0x00000>;
68                 pmsg-size = <0x0 0x50000>;
69                 memory-region = <&ramoops_mem>;
70         };
71
72         fiq_debugger: fiq-debugger {
73                 compatible = "rockchip,fiq-debugger";
74                 rockchip,serial-id = <2>;
75                 rockchip,signal-irq = <182>;
76                 rockchip,wake-irq = <0>;
77                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
78                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
79                 pinctrl-names = "default";
80                 pinctrl-0 = <&uart2c_xfer>;
81         };
82
83         reserved-memory {
84                 #address-cells = <2>;
85                 #size-cells = <2>;
86                 ranges;
87
88                 /* global autoconfigured region for contiguous allocations */
89                 linux,cma {
90                         compatible = "shared-dma-pool";
91                         reusable;
92                         size = <0x0 0x8000000>;
93                         linux,cma-default;
94                 };
95                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
96                 rockchip_logo: rockchip-logo@00000000 {
97                         compatible = "rockchip,fb-logo";
98                         reg = <0x0 0x0 0x0 0x0>;
99                 };
100         };
101
102         ion {
103                 compatible = "rockchip,ion";
104                 #address-cells = <1>;
105                 #size-cells = <0>;
106
107                 cma-heap {
108                         reg = <0x00000000 0x02000000>;
109                 };
110
111                 system-heap {
112                 };
113         };
114
115         rk_key: rockchip-key {
116                 compatible = "rockchip,key";
117                 status = "okay";
118
119                 io-channels = <&saradc 1>;
120
121                 vol-up-key {
122                         linux,code = <115>;
123                         label = "volume up";
124                         rockchip,adc_value = <1>;
125                 };
126
127                 vol-down-key {
128                         linux,code = <114>;
129                         label = "volume down";
130                         rockchip,adc_value = <170>;
131                 };
132
133                 power-key {
134                         gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
135                         linux,code = <116>;
136                         label = "power";
137                         gpio-key,wakeup;
138                 };
139
140                 menu-key {
141                         linux,code = <59>;
142                         label = "menu";
143                         rockchip,adc_value = <746>;
144                 };
145
146                 home-key {
147                         linux,code = <102>;
148                         label = "home";
149                         rockchip,adc_value = <355>;
150                 };
151
152                 back-key {
153                         linux,code = <158>;
154                         label = "back";
155                         rockchip,adc_value = <560>;
156                 };
157
158                 camera-key {
159                         linux,code = <212>;
160                         label = "camera";
161                         rockchip,adc_value = <450>;
162                 };
163         };
164
165         cdn_dp_fb: dp-fb@fec00000 {
166                 status = "disabled";
167                 compatible = "rockchip,rk3399-cdn-dp-fb";
168                 reg = <0x0 0xfec00000 0x0 0x100000>;
169                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
170                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
171                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
172                 clock-names = "core-clk", "pclk", "spdif", "grf";
173                 assigned-clocks = <&cru SCLK_DP_CORE>;
174                 assigned-clock-rates = <100000000>;
175                 power-domains = <&power RK3399_PD_HDCP>;
176                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
177                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
178                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
179                 reset-names = "spdif", "dptx", "apb", "core";
180                 rockchip,grf = <&grf>;
181                 #address-cells = <1>;
182                 #size-cells = <0>;
183                 #sound-dai-cells = <1>;
184         };
185
186         cdn_dp_sound: cdn-dp-sound {
187                 status = "disabled";
188                 compatible = "simple-audio-card";
189                 simple-audio-card,name = "rockchip,cdn-dp-fb";
190                 simple-audio-card,widgets = "Headphone", "Out Jack",
191                                             "Line", "In Jack";
192
193                 simple-audio-card,dai-link@0 {
194                         format = "i2s";
195                         mclk-fs = <256>;
196
197                         cpu {
198                                 sound-dai = <&i2s2>;
199                         };
200
201                         codec {
202                                 sound-dai = <&cdn_dp_fb 0>;
203                         };
204                 };
205         };
206
207         iep: iep@ff670000 {
208                 compatible = "rockchip,iep";
209                 iommu_enabled = <1>;
210                 reg = <0x0 0xff670000 0x0 0x800>;
211                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
212                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
213                 clock-names = "aclk_iep", "hclk_iep";
214                 power-domains = <&power RK3399_PD_IEP>;
215                 version = <2>;
216         };
217
218         iep_mmu: iep-mmu {
219                 dbgname = "iep";
220                 compatible = "rockchip,iep_mmu";
221                 reg = <0x0 0xff670800 0x0 0x40>;
222                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
223                 interrupt-names = "iep_mmu";
224         };
225
226         rga: rga@ff680000 {
227                 compatible = "rockchip,rga2";
228                 dev_mode = <1>;
229                 reg = <0x0 0xff680000 0x0 0x1000>;
230                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
231                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
232                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
233                 power-domains = <&power RK3399_PD_RGA>;
234                 status = "okay";
235         };
236
237         fb: fb {
238                 status = "okay";
239                 compatible = "rockchip,rk-fb";
240                 rockchip,disp-mode = <DUAL>;
241                 rockchip,uboot-logo-on = <1>;
242                 memory-region = <&rockchip_logo>;
243         };
244
245         rk_screen: screen {
246                 status = "okay";
247                 compatible = "rockchip,screen";
248         };
249
250         vopb_rk_fb: vop-rk-fb@ff900000 {
251                 status = "disabled";
252                 compatible = "rockchip,rk3399-lcdc";
253                 rockchip,prop = <PRMRY>;
254                 reg = <0x0 0xff900000 0x0 0x3efc>;
255                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
256                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
257                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
258                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
259                 reset-names = "axi", "ahb", "dclk";
260                 rockchip,grf = <&grf>;
261                 rockchip,pwr18 = <0>;
262                 rockchip,iommu-enabled = <1>;
263                 power-domains = <&power RK3399_PD_VOPB>;
264                 devfreq = <&dmc>;
265         };
266
267         vopb_mmu_rk_fb: vopb-mmu {
268                 status = "okay";
269                 dbgname = "vop";
270                 compatible = "rockchip,vopb_mmu";
271                 reg = <0x0 0xff903f00 0x0 0x100>;
272                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
273                 interrupt-names = "vopb_mmu";
274         };
275
276         vopl_rk_fb: vop-rk-fb@ff8f0000 {
277                 status = "disabled";
278                 compatible = "rockchip,rk3399-lcdc";
279                 rockchip,prop = <EXTEND>;
280                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
281                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
282                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
283                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
284                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
285                 reset-names = "axi", "ahb", "dclk";
286                 rockchip,grf = <&grf>;
287                 rockchip,pwr18 = <0>;
288                 rockchip,iommu-enabled = <1>;
289                 power-domains = <&power RK3399_PD_VOPL>;
290                 devfreq = <&dmc>;
291         };
292
293         vopl_mmu_rk_fb: vopl-mmu {
294                 status = "okay";
295                 dbgname = "vop";
296                 compatible = "rockchip,vopl_mmu";
297                 reg = <0x0 0xff8f3f00 0x0 0x100>;
298                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
299                 interrupt-names = "vopl_mmu";
300         };
301
302         cif_isp0: cif_isp@ff910000 {
303                 compatible = "rockchip,rk3399-cif-isp";
304                 rockchip,grf = <&grf>;
305                 reg = <0x0 0xff910000 0x0 0x10000>, <0x0 0xff968000 0x0 0x8000>;
306                 reg-names = "register", "dsihost-register";
307                 clocks =
308                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
309                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
310                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
311                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
312                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
313                 clock-names =
314                         "clk_cif_out", "clk_cif_pll",
315                         "pclk_dphytxrx", "pclk_dphy_ref",
316                         "aclk_isp0_noc", "aclk_isp0_wrapper",
317                         "hclk_isp0_noc", "hclk_isp0_wrapper",
318                         "clk_isp0", "pclk_dphyrx";
319                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
320                 interrupt-names = "cif_isp10_irq";
321                 power-domains = <&power RK3399_PD_ISP0>;
322                 status = "disabled";
323         };
324
325         isp0: isp@ff910000 {
326                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
327                 reg = <0x0 0xff910000 0x0 0x10000>;
328                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
329                 clocks =
330                         <&cru SCLK_CIF_OUT>, <&cru SCLK_CIF_OUT>,
331                         <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru SCLK_MIPIDPHY_REF>,
332                         <&cru ACLK_ISP0_NOC>, <&cru ACLK_ISP0_WRAPPER>,
333                         <&cru HCLK_ISP0_NOC>, <&cru HCLK_ISP0_WRAPPER>,
334                         <&cru SCLK_ISP0>, <&cru SCLK_DPHY_RX0_CFG>;
335                 clock-names =
336                         "clk_cif_out", "clk_cif_pll",
337                         "pclk_dphytxrx", "pclk_dphy_ref",
338                         "aclk_isp0_noc", "aclk_isp0_wrapper",
339                         "hclk_isp0_noc", "hclk_isp0_wrapper",
340                         "clk_isp0", "pclk_dphyrx";
341                 pinctrl-names =
342                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
343                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
344                         "isp_flash_as_trigger_out";
345                 pinctrl-0 = <&cif_clkout>;
346                 pinctrl-1 = <&isp_dvp_d0d7>;
347                 pinctrl-2 = <&cif_clkout>;
348                 pinctrl-3 = <&isp_prelight>;
349                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
350                 pinctrl-5 = <&isp_flash_trigger>;
351                 rockchip,isp,mipiphy = <2>;
352                 rockchip,isp,cifphy = <1>;
353                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
354                 rockchip,grf = <&grf>;
355                 rockchip,cru = <&cru>;
356                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
357                 rockchip,isp,iommu-enable = <1>;
358                 power-domains = <&power RK3399_PD_ISP0>;
359                 status = "disabled";
360         };
361
362         isp0_mmu {
363                 dbgname = "isp0";
364                 compatible = "rockchip,isp0_mmu";
365                 reg = <0x0 0xff914000 0x0  0x100>,
366                       <0x0 0xff915000 0x0  0x100>;
367                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
368                 interrupt-names = "isp0_mmu";
369         };
370
371         isp1: isp@ff920000 {
372                 compatible = "rockchip,rk3399-isp", "rockchip,isp";
373                 reg = <0x0 0xff920000 0x0 0x10000>;
374                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
375                 clocks =
376                         <&cru ACLK_ISP1_NOC>, <&cru ACLK_ISP1_WRAPPER>,
377                         <&cru HCLK_ISP1_NOC>, <&cru HCLK_ISP1_WRAPPER>,
378                         <&cru SCLK_ISP1>, <&cru SCLK_CIF_OUT>,
379                         <&cru SCLK_CIF_OUT>, <&cru SCLK_DPHY_TX1RX1_CFG>,
380                         <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_ISP1_WRAPPER>,
381                         <&cru SCLK_DPHY_RX0_CFG>, <&cru PCLK_MIPI_DSI1>,
382                         <&cru SCLK_MIPIDPHY_CFG>;
383                 clock-names =
384                         "aclk_isp1_noc", "aclk_isp1_wrapper",
385                         "hclk_isp1_noc", "hclk_isp1_wrapper",
386                         "clk_isp1", "clk_cif_out",
387                         "clk_cif_pll", "pclk_dphytxrx",
388                         "pclk_dphy_ref", "pclk_isp1",
389                         "pclk_dphyrx", "pclk_mipi_dsi",
390                         "mipi_dphy_cfg";
391                 pinctrl-names =
392                         "cif_clkout","isp_dvp8bit0", "isp_mipi_fl",
393                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
394                         "isp_flash_as_trigger_out";
395                 pinctrl-0 = <&cif_clkout>;
396                 pinctrl-1 = <&isp_dvp_d0d7>;
397                 pinctrl-2 = <&cif_clkout>;
398                 pinctrl-3 = <&isp_prelight>;
399                 pinctrl-4 = <&isp_flash_trigger_as_gpio>;
400                 pinctrl-5 = <&isp_flash_trigger>;
401                 rockchip,isp,mipiphy = <2>;
402                 rockchip,isp,cifphy = <1>;
403                 rockchip,isp,dsiphy,reg = <0xff968000 0x8000>;
404                 rockchip,grf = <&grf>;
405                 rockchip,cru = <&cru>;
406                 rockchip,gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
407                 rockchip,isp,iommu-enable = <1>;
408                 power-domains = <&power RK3399_PD_ISP1>;
409                 status = "disabled";
410         };
411
412         isp1_mmu {
413                 dbgname = "isp1";
414                 compatible = "rockchip,isp1_mmu";
415                 reg = <0x0 0xff924000 0x0  0x100>,
416                       <0x0 0xff925000 0x0  0x100>;
417                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
418                 interrupt-names = "isp1_mmu";
419         };
420
421         hdmi_rk_fb: hdmi-rk-fb@ff940000 {
422                 status = "disabled";
423                 compatible = "rockchip,rk3399-hdmi";
424                 reg = <0x0 0xff940000 0x0 0x20000>;
425                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>,
426                              <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH 0>;
427                 clocks = <&cru PCLK_HDMI_CTRL>,
428                          <&cru HCLK_HDCP>,
429                          <&cru SCLK_HDMI_CEC>,
430                          <&cru PLL_VPLL>,
431                          <&cru SCLK_HDMI_SFR>;
432                 clock-names = "pclk_hdmi",
433                               "hdcp_clk_hdmi",
434                               "cec_clk_hdmi",
435                               "dclk_hdmi_phy",
436                               "sclk_hdmi_sfr";
437                 resets = <&cru SRST_HDMI_CTRL>;
438                 reset-names = "hdmi";
439                 pinctrl-names = "default", "gpio";
440                 pinctrl-0 = <&hdmi_i2c_xfer &hdmi_cec>;
441                 pinctrl-1 = <&i2c3_gpio>;
442                 rockchip,grf = <&grf>;
443                 power-domains = <&power RK3399_PD_HDCP>;
444         };
445
446         mipi0_rk_fb: mipi-rk-fb@ff960000 {
447                 compatible = "rockchip,rk3399-dsi";
448                 rockchip,prop = <0>;
449                 rockchip,grf = <&grf>;
450                 reg = <0x0 0xff960000 0x0 0x8000>;
451                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
452                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI0>, <&cru SCLK_MIPIDPHY_CFG>;
453                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
454                 power-domains = <&power RK3399_PD_VIO>;
455                 status = "disabled";
456         };
457
458         mipi1_rk_fb: mipi-rk-fb@ff968000 {
459                 compatible = "rockchip,rk3399-dsi";
460                 rockchip,prop = <1>;
461                 rockchip,grf = <&grf>;
462                 reg = <0x0 0xff968000 0x0 0x8000>;
463                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
464                 clocks = <&cru SCLK_MIPIDPHY_REF>, <&cru PCLK_MIPI_DSI1>, <&cru SCLK_MIPIDPHY_CFG>;
465                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "mipi_dphy_cfg";
466                 power-domains = <&power RK3399_PD_VIO>;
467                 status = "disabled";
468         };
469
470         edp_rk_fb: edp-rk-fb@ff970000 {
471                 compatible = "rockchip,rk3399-edp-fb";
472                 reg = <0x0 0xff970000 0x0 0x8000>;
473                 rockchip,grf = <&grf>;
474                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
475                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
476                 clock-names = "clk_edp", "pclk_edp", "clk_grf";
477                 resets = <&cru SRST_P_EDP_CTRL>;
478                 reset-names = "edp_apb";
479                 status = "disabled";
480                 power-domains = <&power RK3399_PD_EDP>;
481         };
482 };
483
484 &vpu {
485         status = "okay";
486         /delete-property/ iommus;
487         /* 0 means ion, 1 means drm */
488         allocator = <0>;
489 };
490
491 &vpu_mmu {
492         dbgname = "vpu";
493         compatible = "rockchip,vpu_mmu";
494 };
495
496 &rkvdec {
497         status = "okay";
498         /delete-property/ iommus;
499         /* 0 means ion, 1 means drm */
500         allocator = <0>;
501 };
502
503 &vdec_mmu {
504         dbgname = "vdec";
505         compatible = "rockchip,vdec_mmu";
506 };
507
508 &pinctrl {
509         isp {
510                 cif_clkout: cif-clkout {
511                         rockchip,pins =
512                         /*cif_clkout*/
513                         <2 11 RK_FUNC_3 &pcfg_pull_none>;
514                 };
515
516                 isp_dvp_d0d7: isp-dvp-d0d7 {
517                         rockchip,pins =
518                         /*cif_data0*/
519                         <2 0 RK_FUNC_3 &pcfg_pull_none>,
520                         /*cif_data1*/
521                         <2 1 RK_FUNC_3 &pcfg_pull_none>,
522                         /*cif_data2*/
523                         <2 2 RK_FUNC_3 &pcfg_pull_none>,
524                         /*cif_data3*/
525                         <2 3 RK_FUNC_3 &pcfg_pull_none>,
526                         /*cif_data4*/
527                         <2 4 RK_FUNC_3 &pcfg_pull_none>,
528                         /*cif_data5*/
529                         <2 5 RK_FUNC_3 &pcfg_pull_none>,
530                         /*cif_data6*/
531                         <2 6 RK_FUNC_3 &pcfg_pull_none>,
532                         /*cif_data7*/
533                         <2 7 RK_FUNC_3 &pcfg_pull_none>,
534                         /*cif_sync*/
535                         <2 8 RK_FUNC_3 &pcfg_pull_none>,
536                         /*cif_href*/
537                         <2 9 RK_FUNC_3 &pcfg_pull_none>,
538                         /*cif_clkin*/
539                         <2 10 RK_FUNC_3 &pcfg_pull_none>;
540                 };
541
542                 isp_shutter: isp-shutter {
543                         rockchip,pins =
544                         /*SHUTTEREN*/
545                         <1 1 RK_FUNC_1 &pcfg_pull_none>,
546                         /*SHUTTERTRIG*/
547                         <1 0 RK_FUNC_1 &pcfg_pull_none>;
548                 };
549
550                 isp_flash_trigger: isp-flash-trigger {
551                         /*ISP_FLASHTRIGOU*/
552                         rockchip,pins = <1 3 RK_FUNC_1 &pcfg_pull_none>;
553                 };
554
555                 isp_prelight: isp-prelight {
556                         /*ISP_PRELIGHTTRIG*/
557                         rockchip,pins = <1 4 RK_FUNC_1 &pcfg_pull_none>;
558                 };
559
560                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
561                         /*ISP_FLASHTRIGOU*/
562                         rockchip,pins = <0 17 RK_FUNC_GPIO &pcfg_pull_none>;
563                 };
564         };
565
566         cam_pins {
567                 cam0_default_pins: cam0-default-pins {
568                         rockchip,pins = <4 27 RK_FUNC_GPIO &pcfg_pull_none>,
569                                         <2 11 RK_FUNC_3 &pcfg_pull_none>;
570                 };
571                 cam0_sleep_pins: cam0-sleep-pins {
572                         rockchip,pins = <4 27 RK_FUNC_3 &pcfg_pull_none>,
573                                         <2 11 RK_FUNC_GPIO &pcfg_pull_none>;
574                 };
575         };
576 };