arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3368";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 ethernet0 = &gmac;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66                 i2c4 = &i2c4;
  67                 i2c5 = &i2c5;
  68                 serial0 = &uart0;
  69                 serial1 = &uart1;
  70                 serial2 = &uart2;
  71                 serial3 = &uart3;
  72                 serial4 = &uart4;
  73                 spi0 = &spi0;
  74                 spi1 = &spi1;
  75                 spi2 = &spi2;
  76                 lcdc = &lcdc;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_b0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_b1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_b2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_b3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_l0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_l1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_l2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_l3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster1_opp>;
 135
 136                         #cooling-cells = <2>; /* min followed by max */
 137                 };
 138
 139                 cpu_l1: cpu@1 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x1>;
 143                         cpu-idle-states = <&cpu_sleep>;
 144                         enable-method = "psci";
 145                         clocks = <&cru ARMCLKL>;
 146                         operating-points-v2 = <&cluster1_opp>;
 147                 };
 148
 149                 cpu_l2: cpu@2 {
 150                         device_type = "cpu";
 151                         compatible = "arm,cortex-a53", "arm,armv8";
 152                         reg = <0x0 0x2>;
 153                         cpu-idle-states = <&cpu_sleep>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         operating-points-v2 = <&cluster1_opp>;
 157                 };
 158
 159                 cpu_l3: cpu@3 {
 160                         device_type = "cpu";
 161                         compatible = "arm,cortex-a53", "arm,armv8";
 162                         reg = <0x0 0x3>;
 163                         cpu-idle-states = <&cpu_sleep>;
 164                         enable-method = "psci";
 165                         clocks = <&cru ARMCLKL>;
 166                         operating-points-v2 = <&cluster1_opp>;
 167                 };
 168
 169                 cpu_b0: cpu@100 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x100>;
 173                         cpu-idle-states = <&cpu_sleep>;
 174                         enable-method = "psci";
 175                         clocks = <&cru ARMCLKB>;
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         #cooling-cells = <2>; /* min followed by max */
 179                 };
 180
 181                 cpu_b1: cpu@101 {
 182                         device_type = "cpu";
 183                         compatible = "arm,cortex-a53", "arm,armv8";
 184                         reg = <0x0 0x101>;
 185                         cpu-idle-states = <&cpu_sleep>;
 186                         enable-method = "psci";
 187                         clocks = <&cru ARMCLKB>;
 188                         operating-points-v2 = <&cluster0_opp>;
 189                 };
 190
 191                 cpu_b2: cpu@102 {
 192                         device_type = "cpu";
 193                         compatible = "arm,cortex-a53", "arm,armv8";
 194                         reg = <0x0 0x102>;
 195                         cpu-idle-states = <&cpu_sleep>;
 196                         enable-method = "psci";
 197                         clocks = <&cru ARMCLKB>;
 198                         operating-points-v2 = <&cluster0_opp>;
 199                 };
 200
 201                 cpu_b3: cpu@103 {
 202                         device_type = "cpu";
 203                         compatible = "arm,cortex-a53", "arm,armv8";
 204                         reg = <0x0 0x103>;
 205                         cpu-idle-states = <&cpu_sleep>;
 206                         enable-method = "psci";
 207                         clocks = <&cru ARMCLKB>;
 208                         operating-points-v2 = <&cluster0_opp>;
 209                 };
 210         };
 211
 212         cluster0_opp: opp_table0 {
 213                 compatible = "operating-points-v2";
 214                 opp-shared;
 215
 216                 opp@408000000 {
 217                         opp-hz = /bits/ 64 <408000000>;
 218                         opp-microvolt = <1200000>;
 219                         clock-latency-ns = <40000>;
 220                         opp-suspend;
 221                 };
 222                 opp@600000000 {
 223                         opp-hz = /bits/ 64 <600000000>;
 224                         opp-microvolt = <1200000>;
 225                 };
 226                 opp@816000000 {
 227                         opp-hz = /bits/ 64 <816000000>;
 228                         opp-microvolt = <1200000>;
 229                 };
 230                 opp@1008000000 {
 231                         opp-hz = /bits/ 64 <1008000000>;
 232                         opp-microvolt = <1200000>;
 233                 };
 234                 opp@1200000000 {
 235                         opp-hz = /bits/ 64 <1200000000>;
 236                         opp-microvolt = <1200000>;
 237                 };
 238         };
 239
 240         cluster1_opp: opp_table1 {
 241                 compatible = "operating-points-v2";
 242                 opp-shared;
 243
 244                 opp@408000000 {
 245                         opp-hz = /bits/ 64 <408000000>;
 246                         opp-microvolt = <1200000>;
 247                         clock-latency-ns = <40000>;
 248                         opp-suspend;
 249                 };
 250                 opp@600000000 {
 251                         opp-hz = /bits/ 64 <600000000>;
 252                         opp-microvolt = <1200000>;
 253                 };
 254                 opp@816000000 {
 255                         opp-hz = /bits/ 64 <816000000>;
 256                         opp-microvolt = <1200000>;
 257                 };
 258                 opp@1008000000 {
 259                         opp-hz = /bits/ 64 <1008000000>;
 260                         opp-microvolt = <1200000>;
 261                 };
 262         };
 263
 264         arm-pmu {
 265                 compatible = "arm,armv8-pmuv3";
 266                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 271                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 272                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 273                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 274                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 275                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 276                                      <&cpu_b2>, <&cpu_b3>;
 277         };
 278
 279         amba {
 280                 compatible = "arm,amba-bus";
 281                 #address-cells = <2>;
 282                 #size-cells = <2>;
 283                 ranges;
 284
 285                 dmac_peri: dma-controller@ff250000 {
 286                         compatible = "arm,pl330", "arm,primecell";
 287                         reg = <0x0 0xff250000 0x0 0x4000>;
 288                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 289                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 290                         #dma-cells = <1>;
 291                         clocks = <&cru ACLK_DMAC_PERI>;
 292                         clock-names = "apb_pclk";
 293                         arm,pl330-broken-no-flushp;
 294                         peripherals-req-type-burst;
 295                 };
 296
 297                 dmac_bus: dma-controller@ff600000 {
 298                         compatible = "arm,pl330", "arm,primecell";
 299                         reg = <0x0 0xff600000 0x0 0x4000>;
 300                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 301                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 302                         #dma-cells = <1>;
 303                         clocks = <&cru ACLK_DMAC_BUS>;
 304                         clock-names = "apb_pclk";
 305                         arm,pl330-broken-no-flushp;
 306                         peripherals-req-type-burst;
 307                 };
 308         };
 309
 310         psci {
 311                 compatible = "arm,psci-0.2";
 312                 method = "smc";
 313         };
 314
 315         timer {
 316                 compatible = "arm,armv8-timer";
 317                 interrupts = <GIC_PPI 13
 318                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 319                              <GIC_PPI 14
 320                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 321                              <GIC_PPI 11
 322                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 323                              <GIC_PPI 10
 324                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 325         };
 326
 327         xin24m: oscillator {
 328                 compatible = "fixed-clock";
 329                 clock-frequency = <24000000>;
 330                 clock-output-names = "xin24m";
 331                 #clock-cells = <0>;
 332         };
 333
 334         sdmmc: rksdmmc@ff0c0000 {
 335                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 336                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 337                 clock-freq-min-max = <400000 150000000>;
 338                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 339                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 340                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 341                 fifo-depth = <0x100>;
 342                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 343                 status = "disabled";
 344         };
 345
 346         sdio0: dwmmc@ff0d0000 {
 347                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 348                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 349                 clock-freq-min-max = <400000 150000000>;
 350                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 351                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 352                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 353                 fifo-depth = <0x100>;
 354                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 355                 status = "disabled";
 356         };
 357
 358         emmc: rksdmmc@ff0f0000 {
 359                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 360                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 361                 clock-freq-min-max = <400000 150000000>;
 362                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 363                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 364                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 365                 fifo-depth = <0x100>;
 366                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 367                 status = "disabled";
 368         };
 369
 370         saradc: saradc@ff100000 {
 371                 compatible = "rockchip,saradc";
 372                 reg = <0x0 0xff100000 0x0 0x100>;
 373                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 374                 #io-channel-cells = <1>;
 375                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 376                 clock-names = "saradc", "apb_pclk";
 377                 resets = <&cru SRST_SARADC>;
 378                 reset-names = "saradc-apb";
 379                 status = "disabled";
 380         };
 381
 382         spi0: spi@ff110000 {
 383                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 384                 reg = <0x0 0xff110000 0x0 0x1000>;
 385                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 386                 clock-names = "spiclk", "apb_pclk";
 387                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 status = "disabled";
 393         };
 394
 395         spi1: spi@ff120000 {
 396                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 397                 reg = <0x0 0xff120000 0x0 0x1000>;
 398                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 399                 clock-names = "spiclk", "apb_pclk";
 400                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 401                 pinctrl-names = "default";
 402                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 status = "disabled";
 406         };
 407
 408         spi2: spi@ff130000 {
 409                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 410                 reg = <0x0 0xff130000 0x0 0x1000>;
 411                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 412                 clock-names = "spiclk", "apb_pclk";
 413                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 414                 pinctrl-names = "default";
 415                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 status = "disabled";
 419         };
 420
 421         i2c0: i2c@ff650000 {
 422                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 423                 reg = <0x0 0xff650000 0x0 0x1000>;
 424                 clocks = <&cru PCLK_I2C0>;
 425                 clock-names = "i2c";
 426                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&i2c0_xfer>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 status = "disabled";
 432         };
 433
 434         i2c2: i2c@ff140000 {
 435                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 436                 reg = <0x0 0xff140000 0x0 0x1000>;
 437                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 clock-names = "i2c";
 441                 clocks = <&cru PCLK_I2C2>;
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&i2c2_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         i2c3: i2c@ff150000 {
 448                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 449                 reg = <0x0 0xff150000 0x0 0x1000>;
 450                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 clock-names = "i2c";
 454                 clocks = <&cru PCLK_I2C3>;
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&i2c3_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         i2c4: i2c@ff160000 {
 461                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 462                 reg = <0x0 0xff160000 0x0 0x1000>;
 463                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 464                 #address-cells = <1>;
 465                 #size-cells = <0>;
 466                 clock-names = "i2c";
 467                 clocks = <&cru PCLK_I2C4>;
 468                 pinctrl-names = "default";
 469                 pinctrl-0 = <&i2c4_xfer>;
 470                 status = "disabled";
 471         };
 472
 473         i2c5: i2c@ff170000 {
 474                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 475                 reg = <0x0 0xff170000 0x0 0x1000>;
 476                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 477                 #address-cells = <1>;
 478                 #size-cells = <0>;
 479                 clock-names = "i2c";
 480                 clocks = <&cru PCLK_I2C5>;
 481                 pinctrl-names = "default";
 482                 pinctrl-0 = <&i2c5_xfer>;
 483                 status = "disabled";
 484         };
 485
 486         uart0: serial@ff180000 {
 487                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 488                 reg = <0x0 0xff180000 0x0 0x100>;
 489                 clock-frequency = <24000000>;
 490                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 491                 clock-names = "baudclk", "apb_pclk";
 492                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 493                 reg-shift = <2>;
 494                 reg-io-width = <4>;
 495                 status = "disabled";
 496         };
 497
 498         uart1: serial@ff190000 {
 499                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 500                 reg = <0x0 0xff190000 0x0 0x100>;
 501                 clock-frequency = <24000000>;
 502                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 503                 clock-names = "baudclk", "apb_pclk";
 504                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 505                 reg-shift = <2>;
 506                 reg-io-width = <4>;
 507                 status = "disabled";
 508         };
 509
 510         uart3: serial@ff1b0000 {
 511                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 512                 reg = <0x0 0xff1b0000 0x0 0x100>;
 513                 clock-frequency = <24000000>;
 514                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 515                 clock-names = "baudclk", "apb_pclk";
 516                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 517                 reg-shift = <2>;
 518                 reg-io-width = <4>;
 519                 status = "disabled";
 520         };
 521
 522         uart4: serial@ff1c0000 {
 523                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 524                 reg = <0x0 0xff1c0000 0x0 0x100>;
 525                 clock-frequency = <24000000>;
 526                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 527                 clock-names = "baudclk", "apb_pclk";
 528                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 529                 reg-shift = <2>;
 530                 reg-io-width = <4>;
 531                 status = "disabled";
 532         };
 533
 534         thermal-zones {
 535                 cpu {
 536                         polling-delay-passive = <100>; /* milliseconds */
 537                         polling-delay = <5000>; /* milliseconds */
 538
 539                         thermal-sensors = <&tsadc 0>;
 540
 541                         trips {
 542                                 cpu_alert0: cpu_alert0 {
 543                                         temperature = <75000>; /* millicelsius */
 544                                         hysteresis = <2000>; /* millicelsius */
 545                                         type = "passive";
 546                                 };
 547                                 cpu_alert1: cpu_alert1 {
 548                                         temperature = <80000>; /* millicelsius */
 549                                         hysteresis = <2000>; /* millicelsius */
 550                                         type = "passive";
 551                                 };
 552                                 cpu_crit: cpu_crit {
 553                                         temperature = <95000>; /* millicelsius */
 554                                         hysteresis = <2000>; /* millicelsius */
 555                                         type = "critical";
 556                                 };
 557                         };
 558
 559                         cooling-maps {
 560                                 map0 {
 561                                         trip = <&cpu_alert0>;
 562                                         cooling-device =
 563                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 564                                 };
 565                                 map1 {
 566                                         trip = <&cpu_alert1>;
 567                                         cooling-device =
 568                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 569                                 };
 570                         };
 571                 };
 572
 573                 gpu {
 574                         polling-delay-passive = <100>; /* milliseconds */
 575                         polling-delay = <5000>; /* milliseconds */
 576
 577                         thermal-sensors = <&tsadc 1>;
 578
 579                         trips {
 580                                 gpu_alert0: gpu_alert0 {
 581                                         temperature = <80000>; /* millicelsius */
 582                                         hysteresis = <2000>; /* millicelsius */
 583                                         type = "passive";
 584                                 };
 585                                 gpu_crit: gpu_crit {
 586                                         temperature = <115000>; /* millicelsius */
 587                                         hysteresis = <2000>; /* millicelsius */
 588                                         type = "critical";
 589                                 };
 590                         };
 591
 592                         cooling-maps {
 593                                 map0 {
 594                                         trip = <&gpu_alert0>;
 595                                         cooling-device =
 596                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 597                                 };
 598                         };
 599                 };
 600         };
 601
 602         tsadc: tsadc@ff280000 {
 603                 compatible = "rockchip,rk3368-tsadc";
 604                 reg = <0x0 0xff280000 0x0 0x100>;
 605                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 606                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 607                 clock-names = "tsadc", "apb_pclk";
 608                 resets = <&cru SRST_TSADC>;
 609                 reset-names = "tsadc-apb";
 610                 pinctrl-names = "init", "default", "sleep";
 611                 pinctrl-0 = <&otp_gpio>;
 612                 pinctrl-1 = <&otp_out>;
 613                 pinctrl-2 = <&otp_gpio>;
 614                 #thermal-sensor-cells = <1>;
 615                 rockchip,hw-tshut-temp = <95000>;
 616                 status = "disabled";
 617         };
 618
 619         gmac: ethernet@ff290000 {
 620                 compatible = "rockchip,rk3368-gmac";
 621                 reg = <0x0 0xff290000 0x0 0x10000>;
 622                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 623                 interrupt-names = "macirq";
 624                 rockchip,grf = <&grf>;
 625                 clocks = <&cru SCLK_MAC>,
 626                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 627                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 628                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 629                 clock-names = "stmmaceth",
 630                         "mac_clk_rx", "mac_clk_tx",
 631                         "clk_mac_ref", "clk_mac_refout",
 632                         "aclk_mac", "pclk_mac";
 633                 status = "disabled";
 634         };
 635
 636         nandc0: nandc@ff400000 {
 637                 compatible = "rockchip,rk-nandc";
 638                 reg = <0x0 0xff400000 0x0 0x4000>;
 639                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 640                 nandc_id = <0>;
 641                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 642                 clock-names = "clk_nandc", "hclk_nandc";
 643                 status = "disabled";
 644         };
 645
 646         usb_host0_ehci: usb@ff500000 {
 647                 compatible = "generic-ehci";
 648                 reg = <0x0 0xff500000 0x0 0x100>;
 649                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 650                 clocks = <&cru HCLK_HOST0>;
 651                 clock-names = "usbhost";
 652                 status = "disabled";
 653         };
 654
 655         usb_otg: usb@ff580000 {
 656                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 657                                 "snps,dwc2";
 658                 reg = <0x0 0xff580000 0x0 0x40000>;
 659                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 660                 clocks = <&cru HCLK_OTG0>;
 661                 clock-names = "otg";
 662                 dr_mode = "otg";
 663                 g-np-tx-fifo-size = <16>;
 664                 g-rx-fifo-size = <275>;
 665                 g-tx-fifo-size = <256 128 128 64 64 32>;
 666                 g-use-dma;
 667                 status = "disabled";
 668         };
 669
 670         ddrpctl: syscon@ff610000 {
 671                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 672                 reg = <0x0 0xff610000 0x0 0x400>;
 673         };
 674
 675         i2c1: i2c@ff660000 {
 676                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 677                 reg = <0x0 0xff660000 0x0 0x1000>;
 678                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 679                 #address-cells = <1>;
 680                 #size-cells = <0>;
 681                 clock-names = "i2c";
 682                 clocks = <&cru PCLK_I2C1>;
 683                 pinctrl-names = "default";
 684                 pinctrl-0 = <&i2c1_xfer>;
 685                 status = "disabled";
 686         };
 687
 688         pwm0: pwm@ff680000 {
 689                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 690                 reg = <0x0 0xff680000 0x0 0x10>;
 691                 #pwm-cells = <3>;
 692                 pinctrl-names = "default";
 693                 pinctrl-0 = <&pwm0_pin>;
 694                 clocks = <&cru PCLK_PWM1>;
 695                 clock-names = "pwm";
 696                 status = "disabled";
 697         };
 698
 699         pwm1: pwm@ff680010 {
 700                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 701                 reg = <0x0 0xff680010 0x0 0x10>;
 702                 #pwm-cells = <3>;
 703                 pinctrl-names = "default";
 704                 pinctrl-0 = <&pwm1_pin>;
 705                 clocks = <&cru PCLK_PWM1>;
 706                 clock-names = "pwm";
 707                 status = "disabled";
 708         };
 709
 710         pwm2: pwm@ff680020 {
 711                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 712                 reg = <0x0 0xff680020 0x0 0x10>;
 713                 #pwm-cells = <3>;
 714                 clocks = <&cru PCLK_PWM1>;
 715                 clock-names = "pwm";
 716                 status = "disabled";
 717         };
 718
 719         pwm3: pwm@ff680030 {
 720                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 721                 reg = <0x0 0xff680030 0x0 0x10>;
 722                 #pwm-cells = <3>;
 723                 pinctrl-names = "default";
 724                 pinctrl-0 = <&pwm3_pin>;
 725                 clocks = <&cru PCLK_PWM1>;
 726                 clock-names = "pwm";
 727                 status = "disabled";
 728         };
 729
 730         uart2: serial@ff690000 {
 731                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 732                 reg = <0x0 0xff690000 0x0 0x100>;
 733                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 734                 clock-names = "baudclk", "apb_pclk";
 735                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 736                 pinctrl-names = "default";
 737                 pinctrl-0 = <&uart2_xfer>;
 738                 reg-shift = <2>;
 739                 reg-io-width = <4>;
 740                 status = "disabled";
 741         };
 742
 743         mbox: mbox@ff6b0000 {
 744                 compatible = "rockchip,rk3368-mailbox";
 745                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 746                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 747                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 748                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 749                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&cru PCLK_MAILBOX>;
 751                 clock-names = "pclk_mailbox";
 752                 #mbox-cells = <1>;
 753         };
 754
 755         pmu: power-management@ff730000 {
 756                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 757                 reg = <0x0 0xff730000 0x0 0x1000>;
 758
 759                 power: power-controller {
 760                         status = "disabled";
 761                         compatible = "rockchip,rk3368-power-controller";
 762                         #power-domain-cells = <1>;
 763                         #address-cells = <1>;
 764                         #size-cells = <0>;
 765
 766                         /*
 767                          * Note: Although SCLK_* are the working clocks
 768                          * of device without including on the NOC, needed for
 769                          * synchronous reset.
 770                          *
 771                          * The clocks on the which NOC:
 772                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 773                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 774                          * ACLK_RGA is on ACLK_RGA_NIU.
 775                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 776                          *
 777                          * Which clock are device clocks:
 778                          *      clocks          devices
 779                          *      *_IEP           IEP:Image Enhancement Processor
 780                          *      *_ISP           ISP:Image Signal Processing
 781                          *      *_VIP           VIP:Video Input Processor
 782                          *      *_VOP*          VOP:Visual Output Processor
 783                          *      *_RGA           RGA
 784                          *      *_EDP*          EDP
 785                          *      *_DPHY*         LVDS
 786                          *      *_HDMI          HDMI
 787                          *      *_MIPI_*        MIPI
 788                          */
 789                         pd_vio {
 790                                 reg = <RK3368_PD_VIO>;
 791                                 clocks = <&cru ACLK_IEP>,
 792                                          <&cru ACLK_ISP>,
 793                                          <&cru ACLK_VIP>,
 794                                          <&cru ACLK_RGA>,
 795                                          <&cru ACLK_VOP>,
 796                                          <&cru ACLK_VOP_IEP>,
 797                                          <&cru DCLK_VOP>,
 798                                          <&cru HCLK_IEP>,
 799                                          <&cru HCLK_ISP>,
 800                                          <&cru HCLK_RGA>,
 801                                          <&cru HCLK_VIP>,
 802                                          <&cru HCLK_VOP>,
 803                                          <&cru HCLK_VIO_HDCPMMU>,
 804                                          <&cru PCLK_EDP_CTRL>,
 805                                          <&cru PCLK_HDMI_CTRL>,
 806                                          <&cru PCLK_HDCP>,
 807                                          <&cru PCLK_ISP>,
 808                                          <&cru PCLK_VIP>,
 809                                          <&cru PCLK_DPHYRX>,
 810                                          <&cru PCLK_DPHYTX0>,
 811                                          <&cru PCLK_MIPI_CSI>,
 812                                          <&cru PCLK_MIPI_DSI0>,
 813                                          <&cru SCLK_VOP0_PWM>,
 814                                          <&cru SCLK_EDP_24M>,
 815                                          <&cru SCLK_EDP>,
 816                                          <&cru SCLK_HDCP>,
 817                                          <&cru SCLK_ISP>,
 818                                          <&cru SCLK_RGA>,
 819                                          <&cru SCLK_HDMI_CEC>,
 820                                          <&cru SCLK_HDMI_HDCP>;
 821                         };
 822                         /*
 823                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 824                          * (video endecoder & decoder) clocks that on the
 825                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 826                          */
 827                         pd_video {
 828                                 reg = <RK3368_PD_VIDEO>;
 829                                 clocks = <&cru ACLK_VIDEO>,
 830                                          <&cru HCLK_VIDEO>,
 831                                          <&cru SCLK_HEVC_CABAC>,
 832                                          <&cru SCLK_HEVC_CORE>;
 833                         };
 834                         /*
 835                          * Note: ACLK_GPU is the GPU clock,
 836                          * and on the ACLK_GPU_NIU (NOC).
 837                          */
 838                         pd_gpu_1 {
 839                                 reg = <RK3368_PD_GPU_1>;
 840                                 clocks = <&cru ACLK_GPU_CFG>,
 841                                          <&cru ACLK_GPU_MEM>,
 842                                          <&cru SCLK_GPU_CORE>;
 843                         };
 844                 };
 845         };
 846
 847         pmugrf: syscon@ff738000 {
 848                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 849                 reg = <0x0 0xff738000 0x0 0x1000>;
 850
 851                 pmu_io_domains: io-domains {
 852                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 853                         status = "disabled";
 854                 };
 855
 856                 reboot-mode {
 857                         compatible = "syscon-reboot-mode";
 858                         offset = <0x200>;
 859                         mode-normal = <BOOT_NORMAL>;
 860                         mode-recovery = <BOOT_RECOVERY>;
 861                         mode-bootloader = <BOOT_FASTBOOT>;
 862                         mode-loader = <BOOT_BL_DOWNLOAD>;
 863                 };
 864         };
 865
 866         cru: clock-controller@ff760000 {
 867                 compatible = "rockchip,rk3368-cru";
 868                 reg = <0x0 0xff760000 0x0 0x1000>;
 869                 rockchip,grf = <&grf>;
 870                 #clock-cells = <1>;
 871                 #reset-cells = <1>;
 872                 assigned-clocks =
 873                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 874                         <&cru PLL_NPLL>,
 875                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 876                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 877                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 878                 assigned-clock-rates =
 879                         <576000000>, <400000000>,
 880                         <1188000000>,
 881                         <300000000>, <300000000>,
 882                         <150000000>, <150000000>,
 883                         <75000000>, <75000000>;
 884         };
 885
 886         grf: syscon@ff770000 {
 887                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 888                 reg = <0x0 0xff770000 0x0 0x1000>;
 889
 890                 io_domains: io-domains {
 891                         compatible = "rockchip,rk3368-io-voltage-domain";
 892                         status = "disabled";
 893                 };
 894         };
 895
 896         wdt: watchdog@ff800000 {
 897                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 898                 reg = <0x0 0xff800000 0x0 0x100>;
 899                 clocks = <&cru PCLK_WDT>;
 900                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 901                 status = "disabled";
 902         };
 903
 904         timer@ff810000 {
 905                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 906                 reg = <0x0 0xff810000 0x0 0x20>;
 907                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 908         };
 909
 910         gic: interrupt-controller@ffb71000 {
 911                 compatible = "arm,gic-400";
 912                 interrupt-controller;
 913                 #interrupt-cells = <3>;
 914                 #address-cells = <0>;
 915
 916                 reg = <0x0 0xffb71000 0x0 0x1000>,
 917                       <0x0 0xffb72000 0x0 0x2000>,
 918                       <0x0 0xffb74000 0x0 0x2000>,
 919                       <0x0 0xffb76000 0x0 0x2000>;
 920                 interrupts = <GIC_PPI 9
 921                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 922         };
 923
 924         gpu: rogue-g6110@ffa30000 {
 925                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 926                 reg = <0x0 0xffa30000 0x0 0x10000>;
 927                 clocks =
 928                         <&cru SCLK_GPU_CORE>,
 929                         <&cru ACLK_GPU_MEM>,
 930                         <&cru ACLK_GPU_CFG>;
 931                 clock-names =
 932                         "sclk_gpu_core",
 933                         "aclk_gpu_mem",
 934                         "aclk_gpu_cfg";
 935                 operating-points = <
 936                         /* KHz uV */
 937                         200000 1100000
 938                         288000 1100000
 939                         400000 1150000
 940                         576000 1200000
 941                 >;
 942                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 943                 interrupt-names = "rogue-g6110-irq";
 944         };
 945
 946         i2s_2ch: i2s-2ch@ff890000 {
 947                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 948                 reg = <0x0 0xff890000 0x0 0x1000>;
 949                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 950                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 951                 dma-names = "tx", "rx";
 952                 clock-names = "i2s_clk", "i2s_hclk";
 953                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 954                 status = "disabled";
 955         };
 956
 957         i2s_8ch: i2s-8ch@ff898000 {
 958                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 959                 reg = <0x0 0xff898000 0x0 0x1000>;
 960                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 961                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 962                 dma-names = "tx", "rx";
 963                 clock-names = "i2s_clk", "i2s_hclk";
 964                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 965                 pinctrl-names = "default";
 966                 pinctrl-0 = <&i2s_8ch_bus>;
 967                 status = "disabled";
 968         };
 969
 970         isp: isp@ff910000 {
 971                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 972                 reg = <0x0 0xff910000 0x0 0x10000>;
 973                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 974                 /*power-domains = <&power PD_VIO>;*/
 975                 clocks =
 976                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 977                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 978                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 979                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 980                 clock-names =
 981                         "aclk_isp", "hclk_isp", "clk_isp",
 982                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 983                         "clk_cif_pll", "hclk_mipiphy1",
 984                         "pclk_dphyrx", "clk_vio0_noc";
 985                 pinctrl-names =
 986                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 987                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 988                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 989                         "isp_flash_as_trigger_out";
 990                 pinctrl-0 = <&cif_clkout>;
 991                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 992                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 993                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 994                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 995                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 996                 pinctrl-6 = <&cif_clkout>;
 997                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 998                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 999                 pinctrl-9 = <&isp_flash_trigger>;
1000                 rockchip,isp,mipiphy = <2>;
1001                 rockchip,isp,cifphy = <1>;
1002                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1003                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1004                 rockchip,grf = <&grf>;
1005                 rockchip,cru = <&cru>;
1006                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1007                 rockchip,isp,iommu_enable = <1>;
1008                 status = "disabled";
1009         };
1010
1011         rga: rga@ff920000 {
1012                 compatible = "rockchip,rga2";
1013                 dev_mode = <1>;
1014                 reg = <0x0 0xff920000 0x0 0x1000>;
1015                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1016                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1017                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
1018                 status = "disabled";
1019         };
1020
1021         pinctrl: pinctrl {
1022                 compatible = "rockchip,rk3368-pinctrl";
1023                 rockchip,grf = <&grf>;
1024                 rockchip,pmu = <&pmugrf>;
1025                 #address-cells = <0x2>;
1026                 #size-cells = <0x2>;
1027                 ranges;
1028
1029                 gpio0: gpio0@ff750000 {
1030                         compatible = "rockchip,gpio-bank";
1031                         reg = <0x0 0xff750000 0x0 0x100>;
1032                         clocks = <&cru PCLK_GPIO0>;
1033                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1034
1035                         gpio-controller;
1036                         #gpio-cells = <0x2>;
1037
1038                         interrupt-controller;
1039                         #interrupt-cells = <0x2>;
1040                 };
1041
1042                 gpio1: gpio1@ff780000 {
1043                         compatible = "rockchip,gpio-bank";
1044                         reg = <0x0 0xff780000 0x0 0x100>;
1045                         clocks = <&cru PCLK_GPIO1>;
1046                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1047
1048                         gpio-controller;
1049                         #gpio-cells = <0x2>;
1050
1051                         interrupt-controller;
1052                         #interrupt-cells = <0x2>;
1053                 };
1054
1055                 gpio2: gpio2@ff790000 {
1056                         compatible = "rockchip,gpio-bank";
1057                         reg = <0x0 0xff790000 0x0 0x100>;
1058                         clocks = <&cru PCLK_GPIO2>;
1059                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1060
1061                         gpio-controller;
1062                         #gpio-cells = <0x2>;
1063
1064                         interrupt-controller;
1065                         #interrupt-cells = <0x2>;
1066                 };
1067
1068                 gpio3: gpio3@ff7a0000 {
1069                         compatible = "rockchip,gpio-bank";
1070                         reg = <0x0 0xff7a0000 0x0 0x100>;
1071                         clocks = <&cru PCLK_GPIO3>;
1072                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1073
1074                         gpio-controller;
1075                         #gpio-cells = <0x2>;
1076
1077                         interrupt-controller;
1078                         #interrupt-cells = <0x2>;
1079                 };
1080
1081                 pcfg_pull_up: pcfg-pull-up {
1082                         bias-pull-up;
1083                 };
1084
1085                 pcfg_pull_down: pcfg-pull-down {
1086                         bias-pull-down;
1087                 };
1088
1089                 pcfg_pull_none: pcfg-pull-none {
1090                         bias-disable;
1091                 };
1092
1093                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1094                         bias-disable;
1095                         drive-strength = <12>;
1096                 };
1097
1098                 emmc {
1099                         emmc_clk: emmc-clk {
1100                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1101                         };
1102
1103                         emmc_cmd: emmc-cmd {
1104                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1105                         };
1106
1107                         emmc_pwr: emmc-pwr {
1108                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1109                         };
1110
1111                         emmc_bus1: emmc-bus1 {
1112                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1113                         };
1114
1115                         emmc_bus4: emmc-bus4 {
1116                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1117                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1118                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1119                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1120                         };
1121
1122                         emmc_bus8: emmc-bus8 {
1123                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1124                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1125                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1126                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1127                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1128                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1129                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1130                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1131                         };
1132                 };
1133
1134                 gmac {
1135                         rgmii_pins: rgmii-pins {
1136                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1137                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1138                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1139                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1140                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1141                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1142                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1143                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1144                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1145                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1146                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1148                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1149                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1150                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1151                         };
1152
1153                         rmii_pins: rmii-pins {
1154                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1155                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1156                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1157                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1158                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1159                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1160                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1161                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1162                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1163                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165                 };
1166
1167                 hdmi_i2c {
1168                         hdmii2c_xfer: hdmii2c-xfer {
1169                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1170                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172                 };
1173
1174                 hdmi_pin {
1175                         hdmi_cec: hdmi-cec {
1176                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178                 };
1179
1180                 i2c0 {
1181                         i2c0_xfer: i2c0-xfer {
1182                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1183                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1184                         };
1185                 };
1186
1187                 i2c1 {
1188                         i2c1_xfer: i2c1-xfer {
1189                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1190                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 i2c2 {
1195                         i2c2_xfer: i2c2-xfer {
1196                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1197                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1198                         };
1199                 };
1200
1201                 i2c3 {
1202                         i2c3_xfer: i2c3-xfer {
1203                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1204                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1205                         };
1206                 };
1207
1208                 i2c4 {
1209                         i2c4_xfer: i2c4-xfer {
1210                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1211                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1212                         };
1213                 };
1214
1215                 i2c5 {
1216                         i2c5_xfer: i2c5-xfer {
1217                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1218                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1219                         };
1220                         i2c5_gpio: i2c5-gpio {
1221                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1222                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1223                         };
1224                 };
1225
1226                 i2s {
1227                         i2s_8ch_bus: i2s-8ch-bus {
1228                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1229                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1230                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1231                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1232                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1233                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1234                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1235                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1236                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 pwm0 {
1241                         pwm0_pin: pwm0-pin {
1242                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1243                         };
1244
1245                         vop_pwm_pin: vop-pwm {
1246                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1247                         };
1248                 };
1249
1250                 pwm1 {
1251                         pwm1_pin: pwm1-pin {
1252                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1253                         };
1254                 };
1255
1256                 pwm3 {
1257                         pwm3_pin: pwm3-pin {
1258                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1259                         };
1260                 };
1261
1262                 sdio0 {
1263                         sdio0_bus1: sdio0-bus1 {
1264                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1265                         };
1266
1267                         sdio0_bus4: sdio0-bus4 {
1268                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1269                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1270                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1271                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1272                         };
1273
1274                         sdio0_cmd: sdio0-cmd {
1275                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1276                         };
1277
1278                         sdio0_clk: sdio0-clk {
1279                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1280                         };
1281
1282                         sdio0_cd: sdio0-cd {
1283                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1284                         };
1285
1286                         sdio0_wp: sdio0-wp {
1287                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1288                         };
1289
1290                         sdio0_pwr: sdio0-pwr {
1291                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1292                         };
1293
1294                         sdio0_bkpwr: sdio0-bkpwr {
1295                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1296                         };
1297
1298                         sdio0_int: sdio0-int {
1299                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1300                         };
1301                 };
1302
1303                 sdmmc {
1304                         sdmmc_clk: sdmmc-clk {
1305                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307
1308                         sdmmc_cmd: sdmmc-cmd {
1309                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1310                         };
1311
1312                         sdmmc_cd: sdmmc-cd {
1313                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1314                         };
1315
1316                         sdmmc_bus1: sdmmc-bus1 {
1317                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1318                         };
1319
1320                         sdmmc_bus4: sdmmc-bus4 {
1321                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1322                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1323                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1324                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1325                         };
1326                 };
1327
1328                 spi0 {
1329                         spi0_clk: spi0-clk {
1330                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1331                         };
1332                         spi0_cs0: spi0-cs0 {
1333                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1334                         };
1335                         spi0_cs1: spi0-cs1 {
1336                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1337                         };
1338                         spi0_tx: spi0-tx {
1339                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1340                         };
1341                         spi0_rx: spi0-rx {
1342                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1343                         };
1344                 };
1345
1346                 spi1 {
1347                         spi1_clk: spi1-clk {
1348                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1349                         };
1350                         spi1_cs0: spi1-cs0 {
1351                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1352                         };
1353                         spi1_cs1: spi1-cs1 {
1354                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1355                         };
1356                         spi1_rx: spi1-rx {
1357                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1358                         };
1359                         spi1_tx: spi1-tx {
1360                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1361                         };
1362                 };
1363
1364                 spi2 {
1365                         spi2_clk: spi2-clk {
1366                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1367                         };
1368                         spi2_cs0: spi2-cs0 {
1369                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1370                         };
1371                         spi2_rx: spi2-rx {
1372                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1373                         };
1374                         spi2_tx: spi2-tx {
1375                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1376                         };
1377                 };
1378
1379                 tsadc {
1380                         otp_gpio: otp-gpio {
1381                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1382                         };
1383
1384                         otp_out: otp-out {
1385                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1386                         };
1387                 };
1388
1389                 uart0 {
1390                         uart0_xfer: uart0-xfer {
1391                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1392                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394
1395                         uart0_cts: uart0-cts {
1396                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1397                         };
1398
1399                         uart0_rts: uart0-rts {
1400                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1401                         };
1402                 };
1403
1404                 uart1 {
1405                         uart1_xfer: uart1-xfer {
1406                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1407                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1408                         };
1409
1410                         uart1_cts: uart1-cts {
1411                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1412                         };
1413
1414                         uart1_rts: uart1-rts {
1415                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1416                         };
1417                 };
1418
1419                 uart2 {
1420                         uart2_xfer: uart2-xfer {
1421                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1422                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1423                         };
1424                         /* no rts / cts for uart2 */
1425                 };
1426
1427                 uart3 {
1428                         uart3_xfer: uart3-xfer {
1429                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1430                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1431                         };
1432
1433                         uart3_cts: uart3-cts {
1434                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1435                         };
1436
1437                         uart3_rts: uart3-rts {
1438                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 uart4 {
1443                         uart4_xfer: uart4-xfer {
1444                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1445                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1446                         };
1447
1448                         uart4_cts: uart4-cts {
1449                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1450                         };
1451
1452                         uart4_rts: uart4-rts {
1453                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1454                         };
1455                 };
1456
1457                 lcdc {
1458                         lcdc_lcdc: lcdc-lcdc {
1459                                 rockchip,pins =
1460                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1461                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1462                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1463                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1464                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1465                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1466                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1467                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1468                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1469                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1470                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1471                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1472                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1473                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1474                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1475                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1476                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1477                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1478                         };
1479
1480                         lcdc_gpio: lcdc-gpio {
1481                                 rockchip,pins =
1482                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1483                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1484                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1485                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1486                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1487                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1488                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1489                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1490                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1491                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1492                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1493                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1494                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1495                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1496                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1497                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1498                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1499                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1500                         };
1501                 };
1502
1503                 isp {
1504                         cif_clkout: cif-clkout {
1505                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1506                         };
1507
1508                         isp_dvp_d2d9: isp-dvp-d2d9 {
1509                                 rockchip,pins =
1510                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1511                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1512                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1513                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1514                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1515                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1516                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1517                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1518                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1519                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1520                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1521                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1522                         };
1523
1524                         isp_dvp_d0d1: isp-dvp-d0d1 {
1525                                 rockchip,pins =
1526                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1527                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1528                         };
1529
1530                         isp_dvp_d10d11:isp_d10d11 {
1531                                 rockchip,pins =
1532                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1533                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1534                         };
1535
1536                         isp_dvp_d0d7: isp-dvp-d0d7 {
1537                                 rockchip,pins =
1538                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1539                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1540                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1541                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1542                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1543                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1544                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1545                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1546                         };
1547
1548                         isp_dvp_d4d11: isp-dvp-d4d11 {
1549                                 rockchip,pins =
1550                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1551                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1552                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1553                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1554                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1555                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1556                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1557                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1558                         };
1559
1560                         isp_shutter: isp-shutter {
1561                                 rockchip,pins =
1562                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1563                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1564                         };
1565
1566                         isp_flash_trigger: isp-flash-trigger {
1567                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1568                         };
1569
1570                         isp_prelight: isp-prelight {
1571                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1572                         };
1573
1574                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1575                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1576                         };
1577                 };
1578         };
1579
1580         fb: fb {
1581                 compatible = "rockchip,rk-fb";
1582                 rockchip,disp-mode = <NO_DUAL>;
1583                 status = "disabled";
1584         };
1585
1586         rk_screen: screen {
1587                 compatible = "rockchip,screen";
1588                 status = "disabled";
1589         };
1590
1591         lcdc: lcdc@ff930000 {
1592                 compatible = "rockchip,rk3368-lcdc";
1593                 rockchip,grf = <&grf>;
1594                 rockchip,pmugrf = <&pmugrf>;
1595                 rockchip,cru = <&cru>;
1596                 rockchip,prop = <PRMRY>;
1597                 rockchip,pwr18 = <0>;
1598                 rockchip,iommu-enabled = <1>;
1599                 reg = <0x0 0xff930000 0x0 0x10000>;
1600                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1601                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1602                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1603                 /*power-domains = <&power PD_VIO>;*/
1604                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1605                 reset-names = "axi", "ahb", "dclk";
1606                 status = "disabled";
1607         };
1608
1609         mipi: mipi@ff960000 {
1610                 compatible = "rockchip,rk3368-dsi";
1611                 rockchip,prop = <0>;
1612                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1613                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1614                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1615                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1616                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1617                 /*power-domains = <&power PD_VIO>;*/
1618                 status = "disabled";
1619         };
1620
1621         lvds: lvds@ff968000 {
1622                 compatible = "rockchip,rk3368-lvds";
1623                 rockchip,grf = <&grf>;
1624                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1625                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1626                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1627                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1628                 /*power-domains = <&power PD_VIO>;*/
1629                 status = "disabled";
1630         };
1631
1632         edp: edp@ff970000 {
1633                 compatible = "rockchip,rk32-edp";
1634                 reg = <0x0 0xff970000 0x0 0x4000>;
1635                 rockchip,grf = <&grf>;
1636                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1637                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1638                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1639                 /*power-domains = <&power PD_VIO>;*/
1640                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1641                 reset-names = "edp_24m", "edp_apb";
1642                 status = "disabled";
1643         };
1644
1645         hdmi: hdmi@ff980000 {
1646                 compatible = "rockchip,rk3368-hdmi";
1647                 reg = <0x0 0xff980000 0x0 0x20000>;
1648                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1649                 clocks = <&cru PCLK_HDMI_CTRL>,
1650                          <&cru SCLK_HDMI_HDCP>,
1651                          <&cru SCLK_HDMI_CEC>;
1652                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1653                 /*power-domains = <&power PD_VIO>;*/
1654                 resets = <&cru SRST_HDMI>;
1655                 reset-names = "hdmi";
1656                 pinctrl-names = "default", "gpio";
1657                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1658                 pinctrl-1 = <&i2c5_gpio>;
1659                 status = "disabled";
1660         };
1661
1662         iep_mmu: iep-mmu {
1663                 dbgname = "iep";
1664                 compatible = "rockchip,iep_mmu";
1665                 reg = <0x0 0xff900800 0x0 0x100>;
1666                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1667                 interrupt-names = "iep_mmu";
1668                 status = "disabled";
1669         };
1670
1671         vip_mmu: vip-mmu {
1672                 dbgname = "vip";
1673                 compatible = "rockchip,vip_mmu";
1674                 reg = <0x0 0xff950800 0x0 0x100>;
1675                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1676                 interrupt-names = "vip_mmu";
1677                 status = "disabled";
1678         };
1679
1680         vopb_mmu: vopb-mmu {
1681                 dbgname = "vop";
1682                 compatible = "rockchip,vopb_mmu";
1683                 reg = <0x0 0xff930300 0x0 0x100>;
1684                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1685                 interrupt-names = "vop_mmu";
1686                 status = "disabled";
1687         };
1688
1689         isp_mmu: isp-mmu {
1690                 dbgname = "isp_mmu";
1691                 compatible = "rockchip,isp_mmu";
1692                 reg = <0x0 0xff914000 0x0 0x100>,
1693                       <0x0 0xff915000 0x0 0x100>;
1694                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1695                 interrupt-names = "isp_mmu";
1696                 status = "disabled";
1697         };
1698
1699         hdcp_mmu: hdcp-mmu {
1700                  dbgname = "hdcp_mmu";
1701                  compatible = "rockchip,hdcp_mmu";
1702                  reg = <0x0 0xff940000 0x0 0x100>;
1703                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1704                  interrupt-names = "hdcp_mmu";
1705                 status = "disabled";
1706         };
1707
1708         hevc_mmu: hevc-mmu {
1709                 dbgname = "hevc";
1710                 compatible = "rockchip,hevc_mmu";
1711                 reg = <0x0 0xff9a0440 0x0 0x40>,
1712                       <0x0 0xff9a0480 0x0 0x40>;
1713                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1714                 interrupt-names = "hevc_mmu";
1715                 status = "disabled";
1716         };
1717
1718         vpu_mmu: vpu-mmu {
1719                 dbgname = "vpu";
1720                 compatible = "rockchip,vpu_mmu";
1721                 reg = <0x0 0xff9a0800 0x0 0x100>;
1722                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1723                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1724                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1725                 status = "disabled";
1726         };
1727 };