2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
53 compatible = "rockchip,rk3368";
54 interrupt-parent = <&gic>;
77 #address-cells = <0x2>;
113 entry-method = "psci";
115 cpu_sleep: cpu-sleep-0 {
116 compatible = "arm,idle-state";
117 arm,psci-suspend-param = <0x1010000>;
118 entry-latency-us = <0x3fffffff>;
119 exit-latency-us = <0x40000000>;
120 min-residency-us = <0xffffffff>;
126 compatible = "arm,cortex-a53", "arm,armv8";
128 cpu-idle-states = <&cpu_sleep>;
129 enable-method = "psci";
130 clocks = <&cru ARMCLKL>;
131 operating-points-v2 = <&cluster1_opp>;
133 #cooling-cells = <2>; /* min followed by max */
138 compatible = "arm,cortex-a53", "arm,armv8";
140 cpu-idle-states = <&cpu_sleep>;
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster1_opp>;
148 compatible = "arm,cortex-a53", "arm,armv8";
150 cpu-idle-states = <&cpu_sleep>;
151 enable-method = "psci";
152 clocks = <&cru ARMCLKL>;
153 operating-points-v2 = <&cluster1_opp>;
158 compatible = "arm,cortex-a53", "arm,armv8";
160 cpu-idle-states = <&cpu_sleep>;
161 enable-method = "psci";
162 clocks = <&cru ARMCLKL>;
163 operating-points-v2 = <&cluster1_opp>;
168 compatible = "arm,cortex-a53", "arm,armv8";
170 cpu-idle-states = <&cpu_sleep>;
171 enable-method = "psci";
172 clocks = <&cru ARMCLKB>;
173 operating-points-v2 = <&cluster0_opp>;
175 #cooling-cells = <2>; /* min followed by max */
180 compatible = "arm,cortex-a53", "arm,armv8";
182 cpu-idle-states = <&cpu_sleep>;
183 enable-method = "psci";
184 clocks = <&cru ARMCLKB>;
185 operating-points-v2 = <&cluster0_opp>;
190 compatible = "arm,cortex-a53", "arm,armv8";
192 cpu-idle-states = <&cpu_sleep>;
193 enable-method = "psci";
194 clocks = <&cru ARMCLKB>;
195 operating-points-v2 = <&cluster0_opp>;
200 compatible = "arm,cortex-a53", "arm,armv8";
202 cpu-idle-states = <&cpu_sleep>;
203 enable-method = "psci";
204 clocks = <&cru ARMCLKB>;
205 operating-points-v2 = <&cluster0_opp>;
209 cluster0_opp: opp_table0 {
210 compatible = "operating-points-v2";
214 opp-hz = /bits/ 64 <408000000>;
215 opp-microvolt = <1200000>;
216 clock-latency-ns = <40000>;
220 opp-hz = /bits/ 64 <600000000>;
221 opp-microvolt = <1200000>;
224 opp-hz = /bits/ 64 <816000000>;
225 opp-microvolt = <1200000>;
228 opp-hz = /bits/ 64 <1008000000>;
229 opp-microvolt = <1200000>;
232 opp-hz = /bits/ 64 <1200000000>;
233 opp-microvolt = <1200000>;
237 cluster1_opp: opp_table1 {
238 compatible = "operating-points-v2";
242 opp-hz = /bits/ 64 <408000000>;
243 opp-microvolt = <1200000>;
244 clock-latency-ns = <40000>;
248 opp-hz = /bits/ 64 <600000000>;
249 opp-microvolt = <1200000>;
252 opp-hz = /bits/ 64 <816000000>;
253 opp-microvolt = <1200000>;
256 opp-hz = /bits/ 64 <1008000000>;
257 opp-microvolt = <1200000>;
264 min-volt = <950000>; /* uV */
265 min-freq = <216000>; /* KHz */
266 leakage-adjust-volt = <
270 nvmem-cells = <&cpu_leakage>;
271 nvmem-cell-names = "cpu_leakage";
275 min-volt = <950000>; /* uV */
276 min-freq = <216000>; /* KHz */
277 leakage-adjust-volt = <
281 nvmem-cells = <&cpu_leakage>;
282 nvmem-cell-names = "cpu_leakage";
287 compatible = "arm,armv8-pmuv3";
288 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
296 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
297 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
298 <&cpu_b2>, <&cpu_b3>;
302 compatible = "arm,amba-bus";
303 #address-cells = <2>;
307 dmac_peri: dma-controller@ff250000 {
308 compatible = "arm,pl330", "arm,primecell";
309 reg = <0x0 0xff250000 0x0 0x4000>;
310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&cru ACLK_DMAC_PERI>;
314 clock-names = "apb_pclk";
315 arm,pl330-broken-no-flushp;
316 peripherals-req-type-burst;
319 dmac_bus: dma-controller@ff600000 {
320 compatible = "arm,pl330", "arm,primecell";
321 reg = <0x0 0xff600000 0x0 0x4000>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cru ACLK_DMAC_BUS>;
326 clock-names = "apb_pclk";
327 arm,pl330-broken-no-flushp;
328 peripherals-req-type-burst;
333 compatible = "arm,psci-0.2";
338 compatible = "arm,armv8-timer";
339 interrupts = <GIC_PPI 13
340 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
342 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
344 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
346 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
350 compatible = "fixed-clock";
351 clock-frequency = <24000000>;
352 clock-output-names = "xin24m";
356 sdmmc: rksdmmc@ff0c0000 {
357 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
358 reg = <0x0 0xff0c0000 0x0 0x4000>;
359 clock-freq-min-max = <400000 150000000>;
360 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
361 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
362 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
363 fifo-depth = <0x100>;
364 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
368 sdio0: dwmmc@ff0d0000 {
369 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
370 reg = <0x0 0xff0d0000 0x0 0x4000>;
371 clock-freq-min-max = <400000 150000000>;
372 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
373 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
374 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
375 fifo-depth = <0x100>;
376 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
380 emmc: rksdmmc@ff0f0000 {
381 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
382 reg = <0x0 0xff0f0000 0x0 0x4000>;
383 clock-freq-min-max = <400000 150000000>;
384 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
385 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
386 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
387 fifo-depth = <0x100>;
388 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
392 saradc: saradc@ff100000 {
393 compatible = "rockchip,saradc";
394 reg = <0x0 0xff100000 0x0 0x100>;
395 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
396 #io-channel-cells = <1>;
397 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
398 clock-names = "saradc", "apb_pclk";
399 resets = <&cru SRST_SARADC>;
400 reset-names = "saradc-apb";
405 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
406 reg = <0x0 0xff110000 0x0 0x1000>;
407 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
408 clock-names = "spiclk", "apb_pclk";
409 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
412 #address-cells = <1>;
418 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
419 reg = <0x0 0xff120000 0x0 0x1000>;
420 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
421 clock-names = "spiclk", "apb_pclk";
422 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
425 #address-cells = <1>;
431 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
432 reg = <0x0 0xff130000 0x0 0x1000>;
433 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
434 clock-names = "spiclk", "apb_pclk";
435 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
438 #address-cells = <1>;
444 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
445 reg = <0x0 0xff650000 0x0 0x1000>;
446 clocks = <&cru PCLK_I2C0>;
448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
449 pinctrl-names = "default";
450 pinctrl-0 = <&i2c0_xfer>;
451 #address-cells = <1>;
457 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
458 reg = <0x0 0xff140000 0x0 0x1000>;
459 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
460 #address-cells = <1>;
463 clocks = <&cru PCLK_I2C2>;
464 pinctrl-names = "default";
465 pinctrl-0 = <&i2c2_xfer>;
470 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
471 reg = <0x0 0xff150000 0x0 0x1000>;
472 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
473 #address-cells = <1>;
476 clocks = <&cru PCLK_I2C3>;
477 pinctrl-names = "default";
478 pinctrl-0 = <&i2c3_xfer>;
483 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
484 reg = <0x0 0xff160000 0x0 0x1000>;
485 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
489 clocks = <&cru PCLK_I2C4>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&i2c4_xfer>;
496 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
497 reg = <0x0 0xff170000 0x0 0x1000>;
498 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
499 #address-cells = <1>;
502 clocks = <&cru PCLK_I2C5>;
503 pinctrl-names = "default";
504 pinctrl-0 = <&i2c5_xfer>;
508 uart0: serial@ff180000 {
509 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
510 reg = <0x0 0xff180000 0x0 0x100>;
511 clock-frequency = <24000000>;
512 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
513 clock-names = "baudclk", "apb_pclk";
514 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
520 uart1: serial@ff190000 {
521 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
522 reg = <0x0 0xff190000 0x0 0x100>;
523 clock-frequency = <24000000>;
524 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
525 clock-names = "baudclk", "apb_pclk";
526 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
532 uart3: serial@ff1b0000 {
533 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
534 reg = <0x0 0xff1b0000 0x0 0x100>;
535 clock-frequency = <24000000>;
536 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
537 clock-names = "baudclk", "apb_pclk";
538 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
544 uart4: serial@ff1c0000 {
545 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff1c0000 0x0 0x100>;
547 clock-frequency = <24000000>;
548 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_pclk";
550 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
558 polling-delay-passive = <100>; /* milliseconds */
559 polling-delay = <5000>; /* milliseconds */
561 thermal-sensors = <&tsadc 0>;
564 cpu_alert0: cpu_alert0 {
565 temperature = <75000>; /* millicelsius */
566 hysteresis = <2000>; /* millicelsius */
569 cpu_alert1: cpu_alert1 {
570 temperature = <80000>; /* millicelsius */
571 hysteresis = <2000>; /* millicelsius */
575 temperature = <95000>; /* millicelsius */
576 hysteresis = <2000>; /* millicelsius */
583 trip = <&cpu_alert0>;
585 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
588 trip = <&cpu_alert1>;
590 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
596 polling-delay-passive = <100>; /* milliseconds */
597 polling-delay = <5000>; /* milliseconds */
599 thermal-sensors = <&tsadc 1>;
602 gpu_alert0: gpu_alert0 {
603 temperature = <80000>; /* millicelsius */
604 hysteresis = <2000>; /* millicelsius */
608 temperature = <115000>; /* millicelsius */
609 hysteresis = <2000>; /* millicelsius */
616 trip = <&gpu_alert0>;
618 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
624 tsadc: tsadc@ff280000 {
625 compatible = "rockchip,rk3368-tsadc";
626 reg = <0x0 0xff280000 0x0 0x100>;
627 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
628 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
629 clock-names = "tsadc", "apb_pclk";
630 resets = <&cru SRST_TSADC>;
631 reset-names = "tsadc-apb";
632 pinctrl-names = "init", "default", "sleep";
633 pinctrl-0 = <&otp_gpio>;
634 pinctrl-1 = <&otp_out>;
635 pinctrl-2 = <&otp_gpio>;
636 #thermal-sensor-cells = <1>;
637 rockchip,hw-tshut-temp = <95000>;
641 gmac: ethernet@ff290000 {
642 compatible = "rockchip,rk3368-gmac";
643 reg = <0x0 0xff290000 0x0 0x10000>;
644 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
645 interrupt-names = "macirq";
646 rockchip,grf = <&grf>;
647 clocks = <&cru SCLK_MAC>,
648 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
649 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
650 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
651 clock-names = "stmmaceth",
652 "mac_clk_rx", "mac_clk_tx",
653 "clk_mac_ref", "clk_mac_refout",
654 "aclk_mac", "pclk_mac";
658 nandc0: nandc@ff400000 {
659 compatible = "rockchip,rk-nandc";
660 reg = <0x0 0xff400000 0x0 0x4000>;
661 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
663 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
664 clock-names = "clk_nandc", "hclk_nandc";
668 usb_host0_ehci: usb@ff500000 {
669 compatible = "generic-ehci";
670 reg = <0x0 0xff500000 0x0 0x20000>;
671 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cru HCLK_HOST0>, <&u2phy>;
673 clock-names = "usbhost", "utmi";
674 phys = <&u2phy_host>;
679 usb_host0_ohci: usb@ff520000 {
680 compatible = "generic-ohci";
681 reg = <0x0 0xff520000 0x0 0x20000>;
682 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
683 clocks = <&cru HCLK_HOST0>, <&u2phy>;
684 clock-names = "usbhost", "utmi";
685 phys = <&u2phy_host>;
690 usb_otg: usb@ff580000 {
691 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
693 reg = <0x0 0xff580000 0x0 0x40000>;
694 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&cru HCLK_OTG0>;
698 g-np-tx-fifo-size = <16>;
699 g-rx-fifo-size = <275>;
700 g-tx-fifo-size = <256 128 128 64 64 32>;
705 ddrpctl: syscon@ff610000 {
706 compatible = "rockchip,rk3368-ddrpctl", "syscon";
707 reg = <0x0 0xff610000 0x0 0x400>;
711 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
712 reg = <0x0 0xff660000 0x0 0x1000>;
713 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
714 #address-cells = <1>;
717 clocks = <&cru PCLK_I2C1>;
718 pinctrl-names = "default";
719 pinctrl-0 = <&i2c1_xfer>;
724 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
725 reg = <0x0 0xff680000 0x0 0x10>;
727 pinctrl-names = "default";
728 pinctrl-0 = <&pwm0_pin>;
729 clocks = <&cru PCLK_PWM1>;
735 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
736 reg = <0x0 0xff680010 0x0 0x10>;
738 pinctrl-names = "default";
739 pinctrl-0 = <&pwm1_pin>;
740 clocks = <&cru PCLK_PWM1>;
746 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
747 reg = <0x0 0xff680020 0x0 0x10>;
749 clocks = <&cru PCLK_PWM1>;
755 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
756 reg = <0x0 0xff680030 0x0 0x10>;
758 pinctrl-names = "default";
759 pinctrl-0 = <&pwm3_pin>;
760 clocks = <&cru PCLK_PWM1>;
765 uart2: serial@ff690000 {
766 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
767 reg = <0x0 0xff690000 0x0 0x100>;
768 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
769 clock-names = "baudclk", "apb_pclk";
770 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
771 pinctrl-names = "default";
772 pinctrl-0 = <&uart2_xfer>;
778 mbox: mbox@ff6b0000 {
779 compatible = "rockchip,rk3368-mailbox";
780 reg = <0x0 0xff6b0000 0x0 0x1000>;
781 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&cru PCLK_MAILBOX>;
786 clock-names = "pclk_mailbox";
791 mailbox: mailbox@ff6b0000 {
792 compatible = "rockchip,rk3368-mbox-legacy";
793 reg = <0x0 0xff6b0000 0x0 0x1000>,
794 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
795 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&cru PCLK_MAILBOX>;
800 clock-names = "pclk_mailbox";
805 mailbox_scpi: mailbox-scpi {
806 compatible = "rockchip,rk3368-scpi-legacy";
807 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
812 pmu: power-management@ff730000 {
813 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
814 reg = <0x0 0xff730000 0x0 0x1000>;
816 power: power-controller {
818 compatible = "rockchip,rk3368-power-controller";
819 #power-domain-cells = <1>;
820 #address-cells = <1>;
824 * Note: Although SCLK_* are the working clocks
825 * of device without including on the NOC, needed for
828 * The clocks on the which NOC:
829 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
830 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
831 * ACLK_RGA is on ACLK_RGA_NIU.
832 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
834 * Which clock are device clocks:
836 * *_IEP IEP:Image Enhancement Processor
837 * *_ISP ISP:Image Signal Processing
838 * *_VIP VIP:Video Input Processor
839 * *_VOP* VOP:Visual Output Processor
847 reg = <RK3368_PD_VIO>;
848 clocks = <&cru ACLK_IEP>,
860 <&cru HCLK_VIO_HDCPMMU>,
861 <&cru PCLK_EDP_CTRL>,
862 <&cru PCLK_HDMI_CTRL>,
868 <&cru PCLK_MIPI_CSI>,
869 <&cru PCLK_MIPI_DSI0>,
870 <&cru SCLK_VOP0_PWM>,
876 <&cru SCLK_HDMI_CEC>,
877 <&cru SCLK_HDMI_HDCP>;
880 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
881 * (video endecoder & decoder) clocks that on the
882 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
885 reg = <RK3368_PD_VIDEO>;
886 clocks = <&cru ACLK_VIDEO>,
888 <&cru SCLK_HEVC_CABAC>,
889 <&cru SCLK_HEVC_CORE>;
892 * Note: ACLK_GPU is the GPU clock,
893 * and on the ACLK_GPU_NIU (NOC).
896 reg = <RK3368_PD_GPU_1>;
897 clocks = <&cru ACLK_GPU_CFG>,
899 <&cru SCLK_GPU_CORE>;
904 pmugrf: syscon@ff738000 {
905 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
906 reg = <0x0 0xff738000 0x0 0x1000>;
908 pmu_io_domains: io-domains {
909 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
914 compatible = "syscon-reboot-mode";
916 mode-normal = <BOOT_NORMAL>;
917 mode-recovery = <BOOT_RECOVERY>;
918 mode-bootloader = <BOOT_FASTBOOT>;
919 mode-loader = <BOOT_BL_DOWNLOAD>;
923 cru: clock-controller@ff760000 {
924 compatible = "rockchip,rk3368-cru";
925 reg = <0x0 0xff760000 0x0 0x1000>;
926 rockchip,grf = <&grf>;
930 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
932 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
933 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
934 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
935 assigned-clock-rates =
936 <576000000>, <400000000>,
938 <300000000>, <300000000>,
939 <150000000>, <150000000>,
940 <75000000>, <75000000>;
943 grf: syscon@ff770000 {
944 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
945 reg = <0x0 0xff770000 0x0 0x1000>;
946 #address-cells = <1>;
949 io_domains: io-domains {
950 compatible = "rockchip,rk3368-io-voltage-domain";
954 u2phy: usb2-phy@700 {
955 compatible = "rockchip,rk3368-usb2phy";
957 clocks = <&cru SCLK_OTGPHY0>;
958 clock-names = "phyclk";
960 clock-output-names = "usbotg_out";
961 assigned-clocks = <&cru SCLK_USBPHY480M>;
962 assigned-clock-parents = <&u2phy>;
965 u2phy_host: host-port {
967 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
968 interrupt-names = "linestate";
974 wdt: watchdog@ff800000 {
975 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
976 reg = <0x0 0xff800000 0x0 0x100>;
977 clocks = <&cru PCLK_WDT>;
978 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
983 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
984 reg = <0x0 0xff810000 0x0 0x20>;
985 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
988 i2s_2ch: i2s-2ch@ff890000 {
989 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
990 reg = <0x0 0xff890000 0x0 0x1000>;
991 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
992 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
993 dma-names = "tx", "rx";
994 clock-names = "i2s_clk", "i2s_hclk";
995 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
999 i2s_8ch: i2s-8ch@ff898000 {
1000 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1001 reg = <0x0 0xff898000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1003 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1004 dma-names = "tx", "rx";
1005 clock-names = "i2s_clk", "i2s_hclk";
1006 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&i2s_8ch_bus>;
1009 status = "disabled";
1012 isp_mmu: iommu@ff914000 {
1013 compatible = "rockchip,iommu";
1014 reg = <0x0 0xff914000 0x0 0x100>,
1015 <0x0 0xff915000 0x0 0x100>;
1016 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1017 interrupt-names = "isp_mmu";
1019 status = "disabled";
1023 compatible = "rockchip,rk3368-vop";
1024 reg = <0x0 0xff930000 0x0 0x2fc>;
1025 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1027 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1028 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1029 reset-names = "axi", "ahb", "dclk";
1030 power-domains = <&power RK3368_PD_VIO>;
1031 iommus = <&vop_mmu>;
1032 status = "disabled";
1035 #address-cells = <1>;
1040 display_subsystem: display-subsystem {
1041 compatible = "rockchip,display-subsystem";
1043 status = "disabled";
1046 vop_mmu: iommu@ff930300 {
1047 compatible = "rockchip,iommu";
1048 reg = <0x0 0xff930300 0x0 0x100>;
1049 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1050 interrupt-names = "vop_mmu";
1051 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1052 clock-names = "aclk", "hclk";
1053 power-domains = <&power RK3368_PD_VIO>;
1055 status = "disabled";
1058 hevc_mmu: iommu@ff9a0440 {
1059 compatible = "rockchip,iommu";
1060 reg = <0x0 0xff9a0440 0x0 0x100>,
1061 <0x0 0xff9a0480 0x0 0x100>;
1062 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1063 interrupt-names = "hevc_mmu";
1064 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1065 clock-names = "aclk", "hclk";
1066 power-domains = <&power RK3368_PD_VIDEO>;
1068 status = "disabled";
1071 vpu_mmu: iommu@ff9a0800 {
1072 compatible = "rockchip,iommu";
1073 reg = <0x0 0xff9a0800 0x0 0x100>;
1074 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1075 interrupt-names = "vpu_mmu";
1076 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1077 clock-names = "aclk", "hclk";
1078 power-domains = <&power RK3368_PD_VIDEO>;
1080 status = "disabled";
1083 gic: interrupt-controller@ffb71000 {
1084 compatible = "arm,gic-400";
1085 interrupt-controller;
1086 #interrupt-cells = <3>;
1087 #address-cells = <0>;
1089 reg = <0x0 0xffb71000 0x0 0x1000>,
1090 <0x0 0xffb72000 0x0 0x2000>,
1091 <0x0 0xffb74000 0x0 0x2000>,
1092 <0x0 0xffb76000 0x0 0x2000>;
1093 interrupts = <GIC_PPI 9
1094 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1097 gpu: rogue-g6110@ffa30000 {
1098 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1099 reg = <0x0 0xffa30000 0x0 0x10000>;
1101 <&cru SCLK_GPU_CORE>,
1102 <&cru ACLK_GPU_MEM>,
1103 <&cru ACLK_GPU_CFG>;
1108 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1109 interrupt-names = "rogue-g6110-irq";
1110 operating-points-v2 = <&gpu_opp_table>;
1113 gpu_opp_table: gpu_opp_table {
1114 compatible = "operating-points-v2";
1118 opp-hz = /bits/ 64 <200000000>;
1119 opp-microvolt = <950000>;
1122 opp-hz = /bits/ 64 <288000000>;
1123 opp-microvolt = <1025000>;
1126 opp-hz = /bits/ 64 <400000000>;
1127 opp-microvolt = <1050000>;
1130 opp-hz = /bits/ 64 <576000000>;
1131 opp-microvolt = <1200000>;
1135 efuse: efuse@ffb00000 {
1136 compatible = "rockchip,rk3368-efuse";
1137 reg = <0x0 0xffb00000 0x0 0x20>;
1138 #address-cells = <1>;
1140 clocks = <&cru PCLK_EFUSE256>;
1141 clock-names = "pclk_efuse";
1144 cpu_leakage: cpu-leakage@17 {
1147 temp_adjust: temp-adjust@1f {
1153 compatible = "rockchip,rk3368-pinctrl";
1154 rockchip,grf = <&grf>;
1155 rockchip,pmu = <&pmugrf>;
1156 #address-cells = <0x2>;
1157 #size-cells = <0x2>;
1160 gpio0: gpio0@ff750000 {
1161 compatible = "rockchip,gpio-bank";
1162 reg = <0x0 0xff750000 0x0 0x100>;
1163 clocks = <&cru PCLK_GPIO0>;
1164 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1167 #gpio-cells = <0x2>;
1169 interrupt-controller;
1170 #interrupt-cells = <0x2>;
1173 gpio1: gpio1@ff780000 {
1174 compatible = "rockchip,gpio-bank";
1175 reg = <0x0 0xff780000 0x0 0x100>;
1176 clocks = <&cru PCLK_GPIO1>;
1177 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1180 #gpio-cells = <0x2>;
1182 interrupt-controller;
1183 #interrupt-cells = <0x2>;
1186 gpio2: gpio2@ff790000 {
1187 compatible = "rockchip,gpio-bank";
1188 reg = <0x0 0xff790000 0x0 0x100>;
1189 clocks = <&cru PCLK_GPIO2>;
1190 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1193 #gpio-cells = <0x2>;
1195 interrupt-controller;
1196 #interrupt-cells = <0x2>;
1199 gpio3: gpio3@ff7a0000 {
1200 compatible = "rockchip,gpio-bank";
1201 reg = <0x0 0xff7a0000 0x0 0x100>;
1202 clocks = <&cru PCLK_GPIO3>;
1203 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1206 #gpio-cells = <0x2>;
1208 interrupt-controller;
1209 #interrupt-cells = <0x2>;
1212 pcfg_pull_up: pcfg-pull-up {
1216 pcfg_pull_down: pcfg-pull-down {
1220 pcfg_pull_none: pcfg-pull-none {
1224 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1226 drive-strength = <12>;
1230 emmc_clk: emmc-clk {
1231 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1234 emmc_cmd: emmc-cmd {
1235 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1238 emmc_pwr: emmc-pwr {
1239 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1242 emmc_bus1: emmc-bus1 {
1243 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1246 emmc_bus4: emmc-bus4 {
1247 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1248 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1249 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1250 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1253 emmc_bus8: emmc-bus8 {
1254 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1255 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1256 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1257 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1258 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1259 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1260 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1261 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1266 rgmii_pins: rgmii-pins {
1267 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1268 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1269 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1270 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1271 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1273 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1274 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1275 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1276 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1277 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1278 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1279 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1280 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1281 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1284 rmii_pins: rmii-pins {
1285 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1286 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1287 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1288 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1289 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1290 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1291 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1292 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1293 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1294 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1299 i2c0_xfer: i2c0-xfer {
1300 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1301 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1306 i2c1_xfer: i2c1-xfer {
1307 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1308 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1313 i2c2_xfer: i2c2-xfer {
1314 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1315 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1320 i2c3_xfer: i2c3-xfer {
1321 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1322 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1327 i2c4_xfer: i2c4-xfer {
1328 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1329 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1334 i2c5_xfer: i2c5-xfer {
1335 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1336 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1341 i2s_8ch_bus: i2s-8ch-bus {
1342 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1343 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1344 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1345 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1346 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1347 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1348 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1349 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1350 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1355 pwm0_pin: pwm0-pin {
1356 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1359 vop_pwm_pin: vop-pwm {
1360 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1365 pwm1_pin: pwm1-pin {
1366 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1371 pwm3_pin: pwm3-pin {
1372 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1377 sdio0_bus1: sdio0-bus1 {
1378 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1381 sdio0_bus4: sdio0-bus4 {
1382 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1383 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1384 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1385 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1388 sdio0_cmd: sdio0-cmd {
1389 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1392 sdio0_clk: sdio0-clk {
1393 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1396 sdio0_cd: sdio0-cd {
1397 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1400 sdio0_wp: sdio0-wp {
1401 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1404 sdio0_pwr: sdio0-pwr {
1405 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1408 sdio0_bkpwr: sdio0-bkpwr {
1409 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1412 sdio0_int: sdio0-int {
1413 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1418 sdmmc_clk: sdmmc-clk {
1419 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1422 sdmmc_cmd: sdmmc-cmd {
1423 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1426 sdmmc_cd: sdmmc-cd {
1427 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1430 sdmmc_bus1: sdmmc-bus1 {
1431 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1434 sdmmc_bus4: sdmmc-bus4 {
1435 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1436 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1437 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1438 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1443 spi0_clk: spi0-clk {
1444 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1446 spi0_cs0: spi0-cs0 {
1447 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1449 spi0_cs1: spi0-cs1 {
1450 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1453 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1456 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1461 spi1_clk: spi1-clk {
1462 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1464 spi1_cs0: spi1-cs0 {
1465 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1467 spi1_cs1: spi1-cs1 {
1468 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1471 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1474 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1479 spi2_clk: spi2-clk {
1480 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1482 spi2_cs0: spi2-cs0 {
1483 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1486 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1489 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1494 otp_gpio: otp-gpio {
1495 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1499 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1504 uart0_xfer: uart0-xfer {
1505 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1506 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1509 uart0_cts: uart0-cts {
1510 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1513 uart0_rts: uart0-rts {
1514 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1519 uart1_xfer: uart1-xfer {
1520 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1521 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1524 uart1_cts: uart1-cts {
1525 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1528 uart1_rts: uart1-rts {
1529 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1534 uart2_xfer: uart2-xfer {
1535 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1536 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1538 /* no rts / cts for uart2 */
1542 uart3_xfer: uart3-xfer {
1543 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1544 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1547 uart3_cts: uart3-cts {
1548 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1551 uart3_rts: uart3-rts {
1552 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1557 uart4_xfer: uart4-xfer {
1558 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1559 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1562 uart4_cts: uart4-cts {
1563 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1566 uart4_rts: uart4-rts {
1567 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;