arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3368-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52
  53 / {
  54         compatible = "rockchip,rk3368";
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74                 lcdc = &lcdc;
  75         };
  76
  77         cpus {
  78                 #address-cells = <0x2>;
  79                 #size-cells = <0x0>;
  80
  81                 cpu-map {
  82                         cluster0 {
  83                                 core0 {
  84                                         cpu = <&cpu_b0>;
  85                                 };
  86                                 core1 {
  87                                         cpu = <&cpu_b1>;
  88                                 };
  89                                 core2 {
  90                                         cpu = <&cpu_b2>;
  91                                 };
  92                                 core3 {
  93                                         cpu = <&cpu_b3>;
  94                                 };
  95                         };
  96
  97                         cluster1 {
  98                                 core0 {
  99                                         cpu = <&cpu_l0>;
 100                                 };
 101                                 core1 {
 102                                         cpu = <&cpu_l1>;
 103                                 };
 104                                 core2 {
 105                                         cpu = <&cpu_l2>;
 106                                 };
 107                                 core3 {
 108                                         cpu = <&cpu_l3>;
 109                                 };
 110                         };
 111                 };
 112
 113                 idle-states {
 114                         entry-method = "psci";
 115
 116                         cpu_sleep: cpu-sleep-0 {
 117                                 compatible = "arm,idle-state";
 118                                 arm,psci-suspend-param = <0x1010000>;
 119                                 entry-latency-us = <0x3fffffff>;
 120                                 exit-latency-us = <0x40000000>;
 121                                 min-residency-us = <0xffffffff>;
 122                         };
 123                 };
 124
 125                 cpu_l0: cpu@0 {
 126                         device_type = "cpu";
 127                         compatible = "arm,cortex-a53", "arm,armv8";
 128                         reg = <0x0 0x0>;
 129                         cpu-idle-states = <&cpu_sleep>;
 130                         enable-method = "psci";
 131                         clocks = <&cru ARMCLKL>;
 132                         operating-points-v2 = <&cluster1_opp>;
 133                 };
 134
 135                 cpu_l1: cpu@1 {
 136                         device_type = "cpu";
 137                         compatible = "arm,cortex-a53", "arm,armv8";
 138                         reg = <0x0 0x1>;
 139                         cpu-idle-states = <&cpu_sleep>;
 140                         enable-method = "psci";
 141                         clocks = <&cru ARMCLKL>;
 142                         operating-points-v2 = <&cluster1_opp>;
 143                 };
 144
 145                 cpu_l2: cpu@2 {
 146                         device_type = "cpu";
 147                         compatible = "arm,cortex-a53", "arm,armv8";
 148                         reg = <0x0 0x2>;
 149                         cpu-idle-states = <&cpu_sleep>;
 150                         enable-method = "psci";
 151                         clocks = <&cru ARMCLKL>;
 152                         operating-points-v2 = <&cluster1_opp>;
 153                 };
 154
 155                 cpu_l3: cpu@3 {
 156                         device_type = "cpu";
 157                         compatible = "arm,cortex-a53", "arm,armv8";
 158                         reg = <0x0 0x3>;
 159                         cpu-idle-states = <&cpu_sleep>;
 160                         enable-method = "psci";
 161                         clocks = <&cru ARMCLKL>;
 162                         operating-points-v2 = <&cluster1_opp>;
 163                 };
 164
 165                 cpu_b0: cpu@100 {
 166                         device_type = "cpu";
 167                         compatible = "arm,cortex-a53", "arm,armv8";
 168                         reg = <0x0 0x100>;
 169                         cpu-idle-states = <&cpu_sleep>;
 170                         enable-method = "psci";
 171                         clocks = <&cru ARMCLKB>;
 172                         operating-points-v2 = <&cluster0_opp>;
 173                 };
 174
 175                 cpu_b1: cpu@101 {
 176                         device_type = "cpu";
 177                         compatible = "arm,cortex-a53", "arm,armv8";
 178                         reg = <0x0 0x101>;
 179                         cpu-idle-states = <&cpu_sleep>;
 180                         enable-method = "psci";
 181                         clocks = <&cru ARMCLKB>;
 182                         operating-points-v2 = <&cluster0_opp>;
 183                 };
 184
 185                 cpu_b2: cpu@102 {
 186                         device_type = "cpu";
 187                         compatible = "arm,cortex-a53", "arm,armv8";
 188                         reg = <0x0 0x102>;
 189                         cpu-idle-states = <&cpu_sleep>;
 190                         enable-method = "psci";
 191                         clocks = <&cru ARMCLKB>;
 192                         operating-points-v2 = <&cluster0_opp>;
 193                 };
 194
 195                 cpu_b3: cpu@103 {
 196                         device_type = "cpu";
 197                         compatible = "arm,cortex-a53", "arm,armv8";
 198                         reg = <0x0 0x103>;
 199                         cpu-idle-states = <&cpu_sleep>;
 200                         enable-method = "psci";
 201                         clocks = <&cru ARMCLKB>;
 202                         operating-points-v2 = <&cluster0_opp>;
 203                 };
 204         };
 205
 206         cluster0_opp: opp_table0 {
 207                 compatible = "operating-points-v2";
 208                 opp-shared;
 209
 210                 opp@408000000 {
 211                         opp-hz = /bits/ 64 <408000000>;
 212                         opp-microvolt = <1200000>;
 213                         clock-latency-ns = <40000>;
 214                         opp-suspend;
 215                 };
 216                 opp@600000000 {
 217                         opp-hz = /bits/ 64 <600000000>;
 218                         opp-microvolt = <1200000>;
 219                 };
 220                 opp@816000000 {
 221                         opp-hz = /bits/ 64 <816000000>;
 222                         opp-microvolt = <1200000>;
 223                 };
 224                 opp@1008000000 {
 225                         opp-hz = /bits/ 64 <1008000000>;
 226                         opp-microvolt = <1200000>;
 227                 };
 228                 opp@1200000000 {
 229                         opp-hz = /bits/ 64 <1200000000>;
 230                         opp-microvolt = <1200000>;
 231                 };
 232         };
 233
 234         cluster1_opp: opp_table1 {
 235                 compatible = "operating-points-v2";
 236                 opp-shared;
 237
 238                 opp@408000000 {
 239                         opp-hz = /bits/ 64 <408000000>;
 240                         opp-microvolt = <1200000>;
 241                         clock-latency-ns = <40000>;
 242                         opp-suspend;
 243                 };
 244                 opp@600000000 {
 245                         opp-hz = /bits/ 64 <600000000>;
 246                         opp-microvolt = <1200000>;
 247                 };
 248                 opp@816000000 {
 249                         opp-hz = /bits/ 64 <816000000>;
 250                         opp-microvolt = <1200000>;
 251                 };
 252                 opp@1008000000 {
 253                         opp-hz = /bits/ 64 <1008000000>;
 254                         opp-microvolt = <1200000>;
 255                 };
 256         };
 257
 258         arm-pmu {
 259                 compatible = "arm,armv8-pmuv3";
 260                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 261                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 262                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 263                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 268                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 269                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 270                                      <&cpu_b2>, <&cpu_b3>;
 271         };
 272
 273         amba {
 274                 compatible = "arm,amba-bus";
 275                 #address-cells = <2>;
 276                 #size-cells = <2>;
 277                 ranges;
 278
 279                 dmac_peri: dma-controller@ff250000 {
 280                         compatible = "arm,pl330", "arm,primecell";
 281                         reg = <0x0 0xff250000 0x0 0x4000>;
 282                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 283                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 284                         #dma-cells = <1>;
 285                         clocks = <&cru ACLK_DMAC_PERI>;
 286                         clock-names = "apb_pclk";
 287                         arm,pl330-broken-no-flushp;
 288                         peripherals-req-type-burst;
 289                 };
 290
 291                 dmac_bus: dma-controller@ff600000 {
 292                         compatible = "arm,pl330", "arm,primecell";
 293                         reg = <0x0 0xff600000 0x0 0x4000>;
 294                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 295                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 296                         #dma-cells = <1>;
 297                         clocks = <&cru ACLK_DMAC_BUS>;
 298                         clock-names = "apb_pclk";
 299                         arm,pl330-broken-no-flushp;
 300                         peripherals-req-type-burst;
 301                 };
 302         };
 303
 304         psci {
 305                 compatible = "arm,psci-0.2";
 306                 method = "smc";
 307         };
 308
 309         timer {
 310                 compatible = "arm,armv8-timer";
 311                 interrupts = <GIC_PPI 13
 312                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 313                              <GIC_PPI 14
 314                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 315                              <GIC_PPI 11
 316                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 317                              <GIC_PPI 10
 318                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 319         };
 320
 321         xin24m: oscillator {
 322                 compatible = "fixed-clock";
 323                 clock-frequency = <24000000>;
 324                 clock-output-names = "xin24m";
 325                 #clock-cells = <0>;
 326         };
 327
 328         sdmmc: rksdmmc@ff0c0000 {
 329                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 330                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 331                 clock-freq-min-max = <400000 150000000>;
 332                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 333                 clock-names = "biu", "ciu";
 334                 fifo-depth = <0x100>;
 335                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 336                 status = "disabled";
 337         };
 338
 339         sdio0: dwmmc@ff0d0000 {
 340                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 341                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 342                 clock-freq-min-max = <400000 150000000>;
 343                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 344                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 345                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 346                 fifo-depth = <0x100>;
 347                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 348                 status = "disabled";
 349         };
 350
 351         emmc: rksdmmc@ff0f0000 {
 352                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 353                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 354                 clock-freq-min-max = <400000 150000000>;
 355                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 356                 clock-names = "biu", "ciu";
 357                 fifo-depth = <0x100>;
 358                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 359                 status = "disabled";
 360         };
 361
 362         saradc: saradc@ff100000 {
 363                 compatible = "rockchip,saradc";
 364                 reg = <0x0 0xff100000 0x0 0x100>;
 365                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 366                 #io-channel-cells = <1>;
 367                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 368                 clock-names = "saradc", "apb_pclk";
 369                 resets = <&cru SRST_SARADC>;
 370                 reset-names = "saradc-apb";
 371                 status = "disabled";
 372         };
 373
 374         spi0: spi@ff110000 {
 375                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 376                 reg = <0x0 0xff110000 0x0 0x1000>;
 377                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 378                 clock-names = "spiclk", "apb_pclk";
 379                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         spi1: spi@ff120000 {
 388                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 389                 reg = <0x0 0xff120000 0x0 0x1000>;
 390                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 391                 clock-names = "spiclk", "apb_pclk";
 392                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 393                 pinctrl-names = "default";
 394                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 395                 #address-cells = <1>;
 396                 #size-cells = <0>;
 397                 status = "disabled";
 398         };
 399
 400         spi2: spi@ff130000 {
 401                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 402                 reg = <0x0 0xff130000 0x0 0x1000>;
 403                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 404                 clock-names = "spiclk", "apb_pclk";
 405                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 408                 #address-cells = <1>;
 409                 #size-cells = <0>;
 410                 status = "disabled";
 411         };
 412
 413         i2c0: i2c@ff650000 {
 414                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 415                 reg = <0x0 0xff650000 0x0 0x1000>;
 416                 clocks = <&cru PCLK_I2C0>;
 417                 clock-names = "i2c";
 418                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c0_xfer>;
 421                 #address-cells = <1>;
 422                 #size-cells = <0>;
 423                 status = "disabled";
 424         };
 425
 426         i2c2: i2c@ff140000 {
 427                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 428                 reg = <0x0 0xff140000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clock-names = "i2c";
 433                 clocks = <&cru PCLK_I2C2>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&i2c2_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         i2c3: i2c@ff150000 {
 440                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 441                 reg = <0x0 0xff150000 0x0 0x1000>;
 442                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clock-names = "i2c";
 446                 clocks = <&cru PCLK_I2C3>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&i2c3_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         i2c4: i2c@ff160000 {
 453                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 454                 reg = <0x0 0xff160000 0x0 0x1000>;
 455                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 456                 #address-cells = <1>;
 457                 #size-cells = <0>;
 458                 clock-names = "i2c";
 459                 clocks = <&cru PCLK_I2C4>;
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&i2c4_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         i2c5: i2c@ff170000 {
 466                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 467                 reg = <0x0 0xff170000 0x0 0x1000>;
 468                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 469                 #address-cells = <1>;
 470                 #size-cells = <0>;
 471                 clock-names = "i2c";
 472                 clocks = <&cru PCLK_I2C5>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&i2c5_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         uart0: serial@ff180000 {
 479                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 480                 reg = <0x0 0xff180000 0x0 0x100>;
 481                 clock-frequency = <24000000>;
 482                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 483                 clock-names = "baudclk", "apb_pclk";
 484                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 485                 reg-shift = <2>;
 486                 reg-io-width = <4>;
 487                 status = "disabled";
 488         };
 489
 490         uart1: serial@ff190000 {
 491                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 492                 reg = <0x0 0xff190000 0x0 0x100>;
 493                 clock-frequency = <24000000>;
 494                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 495                 clock-names = "baudclk", "apb_pclk";
 496                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 status = "disabled";
 500         };
 501
 502         uart3: serial@ff1b0000 {
 503                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 504                 reg = <0x0 0xff1b0000 0x0 0x100>;
 505                 clock-frequency = <24000000>;
 506                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 507                 clock-names = "baudclk", "apb_pclk";
 508                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 509                 reg-shift = <2>;
 510                 reg-io-width = <4>;
 511                 status = "disabled";
 512         };
 513
 514         uart4: serial@ff1c0000 {
 515                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 516                 reg = <0x0 0xff1c0000 0x0 0x100>;
 517                 clock-frequency = <24000000>;
 518                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 519                 clock-names = "baudclk", "apb_pclk";
 520                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 521                 reg-shift = <2>;
 522                 reg-io-width = <4>;
 523                 status = "disabled";
 524         };
 525
 526         gmac: ethernet@ff290000 {
 527                 compatible = "rockchip,rk3368-gmac";
 528                 reg = <0x0 0xff290000 0x0 0x10000>;
 529                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 530                 interrupt-names = "macirq";
 531                 rockchip,grf = <&grf>;
 532                 clocks = <&cru SCLK_MAC>,
 533                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 534                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 535                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 536                 clock-names = "stmmaceth",
 537                         "mac_clk_rx", "mac_clk_tx",
 538                         "clk_mac_ref", "clk_mac_refout",
 539                         "aclk_mac", "pclk_mac";
 540                 status = "disabled";
 541         };
 542
 543         nandc0: nandc@ff400000 {
 544                 compatible = "rockchip,rk-nandc";
 545                 reg = <0x0 0xff400000 0x0 0x4000>;
 546                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 547                 nandc_id = <0>;
 548                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 549                 clock-names = "clk_nandc", "hclk_nandc";
 550                 status = "disabled";
 551         };
 552
 553         usb_host0_ehci: usb@ff500000 {
 554                 compatible = "generic-ehci";
 555                 reg = <0x0 0xff500000 0x0 0x100>;
 556                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 557                 clocks = <&cru HCLK_HOST0>;
 558                 clock-names = "usbhost";
 559                 status = "disabled";
 560         };
 561
 562         usb_otg: usb@ff580000 {
 563                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 564                                 "snps,dwc2";
 565                 reg = <0x0 0xff580000 0x0 0x40000>;
 566                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&cru HCLK_OTG0>;
 568                 clock-names = "otg";
 569                 dr_mode = "otg";
 570                 g-np-tx-fifo-size = <16>;
 571                 g-rx-fifo-size = <275>;
 572                 g-tx-fifo-size = <256 128 128 64 64 32>;
 573                 g-use-dma;
 574                 status = "disabled";
 575         };
 576
 577         ddrpctl: syscon@ff610000 {
 578                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 579                 reg = <0x0 0xff610000 0x0 0x400>;
 580         };
 581
 582         i2c1: i2c@ff660000 {
 583                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 584                 reg = <0x0 0xff660000 0x0 0x1000>;
 585                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 clock-names = "i2c";
 589                 clocks = <&cru PCLK_I2C1>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c1_xfer>;
 592                 status = "disabled";
 593         };
 594
 595         pwm0: pwm@ff680000 {
 596                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 597                 reg = <0x0 0xff680000 0x0 0x10>;
 598                 #pwm-cells = <3>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&pwm0_pin>;
 601                 clocks = <&cru PCLK_PWM1>;
 602                 clock-names = "pwm";
 603                 status = "disabled";
 604         };
 605
 606         pwm1: pwm@ff680010 {
 607                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 608                 reg = <0x0 0xff680010 0x0 0x10>;
 609                 #pwm-cells = <3>;
 610                 pinctrl-names = "default";
 611                 pinctrl-0 = <&pwm1_pin>;
 612                 clocks = <&cru PCLK_PWM1>;
 613                 clock-names = "pwm";
 614                 status = "disabled";
 615         };
 616
 617         pwm2: pwm@ff680020 {
 618                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 619                 reg = <0x0 0xff680020 0x0 0x10>;
 620                 #pwm-cells = <3>;
 621                 clocks = <&cru PCLK_PWM1>;
 622                 clock-names = "pwm";
 623                 status = "disabled";
 624         };
 625
 626         pwm3: pwm@ff680030 {
 627                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 628                 reg = <0x0 0xff680030 0x0 0x10>;
 629                 #pwm-cells = <3>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&pwm3_pin>;
 632                 clocks = <&cru PCLK_PWM1>;
 633                 clock-names = "pwm";
 634                 status = "disabled";
 635         };
 636
 637         uart2: serial@ff690000 {
 638                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 639                 reg = <0x0 0xff690000 0x0 0x100>;
 640                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 641                 clock-names = "baudclk", "apb_pclk";
 642                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart2_xfer>;
 645                 reg-shift = <2>;
 646                 reg-io-width = <4>;
 647                 status = "disabled";
 648         };
 649
 650         pmu: power-management@ff730000 {
 651                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 652                 reg = <0x0 0xff730000 0x0 0x1000>;
 653
 654                 power: power-controller {
 655                         status = "disabled";
 656                         compatible = "rockchip,rk3368-power-controller";
 657                         #power-domain-cells = <1>;
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660
 661                         /*
 662                          * Note: Although SCLK_* are the working clocks
 663                          * of device without including on the NOC, needed for
 664                          * synchronous reset.
 665                          *
 666                          * The clocks on the which NOC:
 667                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 668                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 669                          * ACLK_RGA is on ACLK_RGA_NIU.
 670                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 671                          *
 672                          * Which clock are device clocks:
 673                          *      clocks          devices
 674                          *      *_IEP           IEP:Image Enhancement Processor
 675                          *      *_ISP           ISP:Image Signal Processing
 676                          *      *_VIP           VIP:Video Input Processor
 677                          *      *_VOP*          VOP:Visual Output Processor
 678                          *      *_RGA           RGA
 679                          *      *_EDP*          EDP
 680                          *      *_DPHY*         LVDS
 681                          *      *_HDMI          HDMI
 682                          *      *_MIPI_*        MIPI
 683                          */
 684                         pd_vio {
 685                                 reg = <RK3368_PD_VIO>;
 686                                 clocks = <&cru ACLK_IEP>,
 687                                          <&cru ACLK_ISP>,
 688                                          <&cru ACLK_VIP>,
 689                                          <&cru ACLK_RGA>,
 690                                          <&cru ACLK_VOP>,
 691                                          <&cru ACLK_VOP_IEP>,
 692                                          <&cru DCLK_VOP>,
 693                                          <&cru HCLK_IEP>,
 694                                          <&cru HCLK_ISP>,
 695                                          <&cru HCLK_RGA>,
 696                                          <&cru HCLK_VIP>,
 697                                          <&cru HCLK_VOP>,
 698                                          <&cru HCLK_VIO_HDCPMMU>,
 699                                          <&cru PCLK_EDP_CTRL>,
 700                                          <&cru PCLK_HDMI_CTRL>,
 701                                          <&cru PCLK_HDCP>,
 702                                          <&cru PCLK_ISP>,
 703                                          <&cru PCLK_VIP>,
 704                                          <&cru PCLK_DPHYRX>,
 705                                          <&cru PCLK_DPHYTX0>,
 706                                          <&cru PCLK_MIPI_CSI>,
 707                                          <&cru PCLK_MIPI_DSI0>,
 708                                          <&cru SCLK_VOP0_PWM>,
 709                                          <&cru SCLK_EDP_24M>,
 710                                          <&cru SCLK_EDP>,
 711                                          <&cru SCLK_HDCP>,
 712                                          <&cru SCLK_ISP>,
 713                                          <&cru SCLK_RGA>,
 714                                          <&cru SCLK_HDMI_CEC>,
 715                                          <&cru SCLK_HDMI_HDCP>;
 716                         };
 717                         /*
 718                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 719                          * (video endecoder & decoder) clocks that on the
 720                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 721                          */
 722                         pd_video {
 723                                 reg = <RK3368_PD_VIDEO>;
 724                                 clocks = <&cru ACLK_VIDEO>,
 725                                          <&cru HCLK_VIDEO>,
 726                                          <&cru SCLK_HEVC_CABAC>,
 727                                          <&cru SCLK_HEVC_CORE>;
 728                         };
 729                         /*
 730                          * Note: ACLK_GPU is the GPU clock,
 731                          * and on the ACLK_GPU_NIU (NOC).
 732                          */
 733                         pd_gpu_1 {
 734                                 reg = <RK3368_PD_GPU_1>;
 735                                 clocks = <&cru ACLK_GPU_CFG>,
 736                                          <&cru ACLK_GPU_MEM>,
 737                                          <&cru SCLK_GPU_CORE>;
 738                         };
 739                 };
 740         };
 741
 742         pmugrf: syscon@ff738000 {
 743                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 744                 reg = <0x0 0xff738000 0x0 0x1000>;
 745
 746                 reboot-mode {
 747                         compatible = "syscon-reboot-mode";
 748                         offset = <0x200>;
 749                         mode-normal = <BOOT_NORMAL>;
 750                         mode-recovery = <BOOT_RECOVERY>;
 751                         mode-bootloader = <BOOT_FASTBOOT>;
 752                         mode-loader = <BOOT_LOADER>;
 753
 754                 };
 755         };
 756
 757         cru: clock-controller@ff760000 {
 758                 compatible = "rockchip,rk3368-cru";
 759                 reg = <0x0 0xff760000 0x0 0x1000>;
 760                 rockchip,grf = <&grf>;
 761                 #clock-cells = <1>;
 762                 #reset-cells = <1>;
 763                 assigned-clocks =
 764                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 765                         <&cru PLL_NPLL>,
 766                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 767                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 768                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 769                 assigned-clock-rates =
 770                         <576000000>, <400000000>,
 771                         <1188000000>,
 772                         <300000000>, <300000000>,
 773                         <150000000>, <150000000>,
 774                         <75000000>, <75000000>;
 775         };
 776
 777         grf: syscon@ff770000 {
 778                 compatible = "rockchip,rk3368-grf", "syscon";
 779                 reg = <0x0 0xff770000 0x0 0x1000>;
 780         };
 781
 782         wdt: watchdog@ff800000 {
 783                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 784                 reg = <0x0 0xff800000 0x0 0x100>;
 785                 clocks = <&cru PCLK_WDT>;
 786                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 787                 status = "disabled";
 788         };
 789
 790         gic: interrupt-controller@ffb71000 {
 791                 compatible = "arm,gic-400";
 792                 interrupt-controller;
 793                 #interrupt-cells = <3>;
 794                 #address-cells = <0>;
 795
 796                 reg = <0x0 0xffb71000 0x0 0x1000>,
 797                       <0x0 0xffb72000 0x0 0x2000>,
 798                       <0x0 0xffb74000 0x0 0x2000>,
 799                       <0x0 0xffb76000 0x0 0x2000>;
 800                 interrupts = <GIC_PPI 9
 801                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 802         };
 803
 804         gpu: rogue-g6110@ffa30000 {
 805                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 806                 reg = <0x0 0xffa30000 0x0 0x10000>;
 807                 clocks =
 808                         <&cru SCLK_GPU_CORE>,
 809                         <&cru ACLK_GPU_MEM>,
 810                         <&cru ACLK_GPU_CFG>;
 811                 clock-names =
 812                         "sclk_gpu_core",
 813                         "aclk_gpu_mem",
 814                         "aclk_gpu_cfg";
 815                 operating-points = <
 816                         /* KHz uV */
 817                         200000 1100000
 818                         288000 1100000
 819                         400000 1150000
 820                         576000 1200000
 821                 >;
 822                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 823                 interrupt-names = "rogue-g6110-irq";
 824         };
 825
 826         i2s_2ch: i2s-2ch@ff890000 {
 827                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 828                 reg = <0x0 0xff890000 0x0 0x1000>;
 829                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 830                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 831                 dma-names = "tx", "rx";
 832                 clock-names = "i2s_clk", "i2s_hclk";
 833                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 834                 status = "disabled";
 835         };
 836
 837         i2s_8ch: i2s-8ch@ff898000 {
 838                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 839                 reg = <0x0 0xff898000 0x0 0x1000>;
 840                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 841                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 842                 dma-names = "tx", "rx";
 843                 clock-names = "i2s_clk", "i2s_hclk";
 844                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 845                 pinctrl-names = "default";
 846                 pinctrl-0 = <&i2s_8ch_bus>;
 847                 status = "disabled";
 848         };
 849
 850         isp: isp@ff910000 {
 851                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
 852                 reg = <0x0 0xff910000 0x0 0x10000>;
 853                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 854                 /*power-domains = <&power PD_VIO>;*/
 855                 clocks =
 856                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 857                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 858                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 859                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 860                 clock-names =
 861                         "aclk_isp", "hclk_isp", "clk_isp",
 862                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 863                         "clk_cif_pll", "hclk_mipiphy1",
 864                         "pclk_dphyrx", "clk_vio0_noc";
 865                 pinctrl-names =
 866                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 867                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 868                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 869                         "isp_flash_as_trigger_out";
 870                 pinctrl-0 = <&cif_clkout>;
 871                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 872                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 873                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 874                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 875                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 876                 pinctrl-6 = <&cif_clkout>;
 877                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 878                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 879                 pinctrl-9 = <&isp_flash_trigger>;
 880                 rockchip,isp,mipiphy = <2>;
 881                 rockchip,isp,cifphy = <1>;
 882                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 883                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 884                 rockchip,grf = <&grf>;
 885                 rockchip,cru = <&cru>;
 886                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 887                 rockchip,isp,iommu_enable = <1>;
 888                 status = "disabled";
 889         };
 890
 891         rga: rga@ff920000 {
 892                 compatible = "rockchip,rga2";
 893                 dev_mode = <1>;
 894                 reg = <0x0 0xff920000 0x0 0x1000>;
 895                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 896                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 897                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 898                 status = "disabled";
 899         };
 900
 901         pinctrl: pinctrl {
 902                 compatible = "rockchip,rk3368-pinctrl";
 903                 rockchip,grf = <&grf>;
 904                 rockchip,pmu = <&pmugrf>;
 905                 #address-cells = <0x2>;
 906                 #size-cells = <0x2>;
 907                 ranges;
 908
 909                 gpio0: gpio0@ff750000 {
 910                         compatible = "rockchip,gpio-bank";
 911                         reg = <0x0 0xff750000 0x0 0x100>;
 912                         clocks = <&cru PCLK_GPIO0>;
 913                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 914
 915                         gpio-controller;
 916                         #gpio-cells = <0x2>;
 917
 918                         interrupt-controller;
 919                         #interrupt-cells = <0x2>;
 920                 };
 921
 922                 gpio1: gpio1@ff780000 {
 923                         compatible = "rockchip,gpio-bank";
 924                         reg = <0x0 0xff780000 0x0 0x100>;
 925                         clocks = <&cru PCLK_GPIO1>;
 926                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 927
 928                         gpio-controller;
 929                         #gpio-cells = <0x2>;
 930
 931                         interrupt-controller;
 932                         #interrupt-cells = <0x2>;
 933                 };
 934
 935                 gpio2: gpio2@ff790000 {
 936                         compatible = "rockchip,gpio-bank";
 937                         reg = <0x0 0xff790000 0x0 0x100>;
 938                         clocks = <&cru PCLK_GPIO2>;
 939                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 940
 941                         gpio-controller;
 942                         #gpio-cells = <0x2>;
 943
 944                         interrupt-controller;
 945                         #interrupt-cells = <0x2>;
 946                 };
 947
 948                 gpio3: gpio3@ff7a0000 {
 949                         compatible = "rockchip,gpio-bank";
 950                         reg = <0x0 0xff7a0000 0x0 0x100>;
 951                         clocks = <&cru PCLK_GPIO3>;
 952                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 953
 954                         gpio-controller;
 955                         #gpio-cells = <0x2>;
 956
 957                         interrupt-controller;
 958                         #interrupt-cells = <0x2>;
 959                 };
 960
 961                 pcfg_pull_up: pcfg-pull-up {
 962                         bias-pull-up;
 963                 };
 964
 965                 pcfg_pull_down: pcfg-pull-down {
 966                         bias-pull-down;
 967                 };
 968
 969                 pcfg_pull_none: pcfg-pull-none {
 970                         bias-disable;
 971                 };
 972
 973                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 974                         bias-disable;
 975                         drive-strength = <12>;
 976                 };
 977
 978                 emmc {
 979                         emmc_clk: emmc-clk {
 980                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 981                         };
 982
 983                         emmc_cmd: emmc-cmd {
 984                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 985                         };
 986
 987                         emmc_pwr: emmc-pwr {
 988                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 989                         };
 990
 991                         emmc_bus1: emmc-bus1 {
 992                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 993                         };
 994
 995                         emmc_bus4: emmc-bus4 {
 996                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 997                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 998                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 999                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1000                         };
1001
1002                         emmc_bus8: emmc-bus8 {
1003                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1004                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1005                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1006                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1007                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1008                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1009                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1010                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1011                         };
1012                 };
1013
1014                 gmac {
1015                         rgmii_pins: rgmii-pins {
1016                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1017                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1018                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1019                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1020                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1021                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1022                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1023                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1024                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1025                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1026                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1027                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1028                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1029                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1030                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1031                         };
1032
1033                         rmii_pins: rmii-pins {
1034                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1035                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1036                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1037                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1038                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1039                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1040                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1041                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1042                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1043                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1044                         };
1045                 };
1046
1047                 hdmi_i2c {
1048                         hdmii2c_xfer: hdmii2c-xfer {
1049                                 rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
1050                                                 <3 27 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052                 };
1053
1054                 hdmi_pin {
1055                         hdmi_cec: hdmi-cec {
1056                                 rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 i2c0 {
1061                         i2c0_xfer: i2c0-xfer {
1062                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1063                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1064                         };
1065                 };
1066
1067                 i2c1 {
1068                         i2c1_xfer: i2c1-xfer {
1069                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1070                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072                 };
1073
1074                 i2c2 {
1075                         i2c2_xfer: i2c2-xfer {
1076                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1077                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1078                         };
1079                 };
1080
1081                 i2c3 {
1082                         i2c3_xfer: i2c3-xfer {
1083                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1084                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1085                         };
1086                 };
1087
1088                 i2c4 {
1089                         i2c4_xfer: i2c4-xfer {
1090                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1091                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1092                         };
1093                 };
1094
1095                 i2c5 {
1096                         i2c5_xfer: i2c5-xfer {
1097                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1098                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1099                         };
1100                         i2c5_gpio: i2c5-gpio {
1101                                 rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
1102                                                 <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
1103                         };
1104                 };
1105
1106                 i2s {
1107                         i2s_8ch_bus: i2s-8ch-bus {
1108                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1109                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1110                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1111                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1112                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1113                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1114                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1115                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1116                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1117                         };
1118                 };
1119
1120                 sdio0 {
1121                         sdio0_bus1: sdio0-bus1 {
1122                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1123                         };
1124
1125                         sdio0_bus4: sdio0-bus4 {
1126                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1127                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1128                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1129                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1130                         };
1131
1132                         sdio0_cmd: sdio0-cmd {
1133                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1134                         };
1135
1136                         sdio0_clk: sdio0-clk {
1137                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1138                         };
1139
1140                         sdio0_cd: sdio0-cd {
1141                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1142                         };
1143
1144                         sdio0_wp: sdio0-wp {
1145                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1146                         };
1147
1148                         sdio0_pwr: sdio0-pwr {
1149                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1150                         };
1151
1152                         sdio0_bkpwr: sdio0-bkpwr {
1153                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1154                         };
1155
1156                         sdio0_int: sdio0-int {
1157                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1158                         };
1159                 };
1160
1161                 sdmmc {
1162                         sdmmc_clk: sdmmc-clk {
1163                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165
1166                         sdmmc_cmd: sdmmc-cmd {
1167                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1168                         };
1169
1170                         sdmmc_cd: sdmcc-cd {
1171                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1172                         };
1173
1174                         sdmmc_bus1: sdmmc-bus1 {
1175                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1176                         };
1177
1178                         sdmmc_bus4: sdmmc-bus4 {
1179                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1180                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1181                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1182                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1183                         };
1184                 };
1185
1186                 spi0 {
1187                         spi0_clk: spi0-clk {
1188                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1189                         };
1190                         spi0_cs0: spi0-cs0 {
1191                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1192                         };
1193                         spi0_cs1: spi0-cs1 {
1194                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1195                         };
1196                         spi0_tx: spi0-tx {
1197                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1198                         };
1199                         spi0_rx: spi0-rx {
1200                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1201                         };
1202                 };
1203
1204                 spi1 {
1205                         spi1_clk: spi1-clk {
1206                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1207                         };
1208                         spi1_cs0: spi1-cs0 {
1209                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1210                         };
1211                         spi1_cs1: spi1-cs1 {
1212                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1213                         };
1214                         spi1_rx: spi1-rx {
1215                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1216                         };
1217                         spi1_tx: spi1-tx {
1218                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1219                         };
1220                 };
1221
1222                 spi2 {
1223                         spi2_clk: spi2-clk {
1224                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1225                         };
1226                         spi2_cs0: spi2-cs0 {
1227                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1228                         };
1229                         spi2_rx: spi2-rx {
1230                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1231                         };
1232                         spi2_tx: spi2-tx {
1233                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1234                         };
1235                 };
1236
1237                 uart0 {
1238                         uart0_xfer: uart0-xfer {
1239                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1240                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1241                         };
1242
1243                         uart0_cts: uart0-cts {
1244                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1245                         };
1246
1247                         uart0_rts: uart0-rts {
1248                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1249                         };
1250                 };
1251
1252                 uart1 {
1253                         uart1_xfer: uart1-xfer {
1254                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1255                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1256                         };
1257
1258                         uart1_cts: uart1-cts {
1259                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1260                         };
1261
1262                         uart1_rts: uart1-rts {
1263                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1264                         };
1265                 };
1266
1267                 uart2 {
1268                         uart2_xfer: uart2-xfer {
1269                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1270                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1271                         };
1272                         /* no rts / cts for uart2 */
1273                 };
1274
1275                 uart3 {
1276                         uart3_xfer: uart3-xfer {
1277                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1278                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1279                         };
1280
1281                         uart3_cts: uart3-cts {
1282                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1283                         };
1284
1285                         uart3_rts: uart3-rts {
1286                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1287                         };
1288                 };
1289
1290                 uart4 {
1291                         uart4_xfer: uart4-xfer {
1292                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1293                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1294                         };
1295
1296                         uart4_cts: uart4-cts {
1297                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1298                         };
1299
1300                         uart4_rts: uart4-rts {
1301                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1302                         };
1303                 };
1304
1305                 pwm0 {
1306                         pwm0_pin: pwm0-pin {
1307                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1308                         };
1309
1310                         vop_pwm_pin: vop-pwm {
1311                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1312                         };
1313                 };
1314
1315                 pwm1 {
1316                         pwm1_pin: pwm1-pin {
1317                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1318                         };
1319                 };
1320
1321                 pwm3 {
1322                         pwm3_pin: pwm3-pin {
1323                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1324                         };
1325                 };
1326
1327                 lcdc {
1328                         lcdc_lcdc: lcdc-lcdc {
1329                                 rockchip,pins =
1330                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1331                                                 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1332                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1333                                                 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1334                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1335                                                 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1336                                                 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1337                                                 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1338                                                 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1339                                                 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1340                                                 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1341                                                 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1342                                                 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1343                                                 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1344                                                 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1345                                                 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1346                                                 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1347                                                 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1348                         };
1349
1350                         lcdc_gpio: lcdc-gpio {
1351                                 rockchip,pins =
1352                                                 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1353                                                 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1354                                                 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1355                                                 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1356                                                 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1357                                                 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1358                                                 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1359                                                 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1360                                                 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1361                                                 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1362                                                 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1363                                                 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1364                                                 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1365                                                 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1366                                                 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1367                                                 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1368                                                 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1369                                                 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1370                         };
1371                 };
1372
1373                 isp {
1374                         cif_clkout: cif-clkout {
1375                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1376                         };
1377
1378                         isp_dvp_d2d9: isp-dvp-d2d9 {
1379                                 rockchip,pins =
1380                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1381                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1382                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1383                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1384                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1385                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1386                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1387                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1388                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1389                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1390                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1391                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1392                         };
1393
1394                         isp_dvp_d0d1: isp-dvp-d0d1 {
1395                                 rockchip,pins =
1396                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1397                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1398                         };
1399
1400                         isp_dvp_d10d11:isp_d10d11 {
1401                                 rockchip,pins =
1402                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1403                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1404                         };
1405
1406                         isp_dvp_d0d7: isp-dvp-d0d7 {
1407                                 rockchip,pins =
1408                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1409                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1410                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1411                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1412                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1413                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1414                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1415                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1416                         };
1417
1418                         isp_dvp_d4d11: isp-dvp-d4d11 {
1419                                 rockchip,pins =
1420                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1421                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1422                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1423                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1424                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1425                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1426                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1427                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1428                         };
1429
1430                         isp_shutter: isp-shutter {
1431                                 rockchip,pins =
1432                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1433                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1434                         };
1435
1436                         isp_flash_trigger: isp-flash-trigger {
1437                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1438                         };
1439
1440                         isp_prelight: isp-prelight {
1441                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1442                         };
1443
1444                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1445                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
1446                         };
1447                 };
1448         };
1449
1450         fb: fb {
1451                 compatible = "rockchip,rk-fb";
1452                 rockchip,disp-mode = <NO_DUAL>;
1453                 status = "disabled";
1454         };
1455
1456         rk_screen: screen {
1457                 compatible = "rockchip,screen";
1458                 status = "disabled";
1459         };
1460
1461         lcdc: lcdc@ff930000 {
1462                 compatible = "rockchip,rk3368-lcdc";
1463                 rockchip,grf = <&grf>;
1464                 rockchip,pmugrf = <&pmugrf>;
1465                 rockchip,cru = <&cru>;
1466                 rockchip,prop = <PRMRY>;
1467                 rockchip,pwr18 = <0>;
1468                 rockchip,iommu-enabled = <1>;
1469                 reg = <0x0 0xff930000 0x0 0x10000>;
1470                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1471                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1472                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1473                 /*power-domains = <&power PD_VIO>;*/
1474                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1475                 reset-names = "axi", "ahb", "dclk";
1476                 status = "disabled";
1477         };
1478
1479         mipi: mipi@ff960000 {
1480                 compatible = "rockchip,rk3368-dsi";
1481                 rockchip,prop = <0>;
1482                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1483                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1484                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1485                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1486                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1487                 /*power-domains = <&power PD_VIO>;*/
1488                 status = "disabled";
1489         };
1490
1491         lvds: lvds@ff968000 {
1492                 compatible = "rockchip,rk3368-lvds";
1493                 rockchip,grf = <&grf>;
1494                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1495                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1496                 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1497                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1498                 /*power-domains = <&power PD_VIO>;*/
1499                 status = "disabled";
1500         };
1501
1502         edp: edp@ff970000 {
1503                 compatible = "rockchip,rk32-edp";
1504                 reg = <0x0 0xff970000 0x0 0x4000>;
1505                 rockchip,grf = <&grf>;
1506                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1507                 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1508                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1509                 /*power-domains = <&power PD_VIO>;*/
1510                 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1511                 reset-names = "edp_24m", "edp_apb";
1512                 status = "disabled";
1513         };
1514
1515         hdmi: hdmi@ff980000 {
1516                 compatible = "rockchip,rk3368-hdmi";
1517                 reg = <0x0 0xff980000 0x0 0x20000>;
1518                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1519                 clocks = <&cru PCLK_HDMI_CTRL>,
1520                          <&cru SCLK_HDMI_HDCP>,
1521                          <&cru SCLK_HDMI_CEC>;
1522                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
1523                 /*power-domains = <&power PD_VIO>;*/
1524                 resets = <&cru SRST_HDMI>;
1525                 reset-names = "hdmi";
1526                 pinctrl-names = "default", "gpio";
1527                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1528                 pinctrl-1 = <&i2c5_gpio>;
1529                 status = "disabled";
1530         };
1531
1532         iep_mmu: iep-mmu {
1533                 dbgname = "iep";
1534                 compatible = "rockchip,iep_mmu";
1535                 reg = <0x0 0xff900800 0x0 0x100>;
1536                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1537                 interrupt-names = "iep_mmu";
1538                 status = "disabled";
1539         };
1540
1541         vip_mmu: vip-mmu {
1542                 dbgname = "vip";
1543                 compatible = "rockchip,vip_mmu";
1544                 reg = <0x0 0xff950800 0x0 0x100>;
1545                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1546                 interrupt-names = "vip_mmu";
1547                 status = "disabled";
1548         };
1549
1550         vopb_mmu: vopb-mmu {
1551                 dbgname = "vop";
1552                 compatible = "rockchip,vopb_mmu";
1553                 reg = <0x0 0xff930300 0x0 0x100>;
1554                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1555                 interrupt-names = "vop_mmu";
1556                 status = "disabled";
1557         };
1558
1559         isp_mmu: isp-mmu {
1560                 dbgname = "isp_mmu";
1561                 compatible = "rockchip,isp_mmu";
1562                 reg = <0x0 0xff914000 0x0 0x100>,
1563                       <0x0 0xff915000 0x0 0x100>;
1564                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1565                 interrupt-names = "isp_mmu";
1566                 status = "disabled";
1567         };
1568
1569         hdcp_mmu: hdcp-mmu {
1570                  dbgname = "hdcp_mmu";
1571                  compatible = "rockchip,hdcp_mmu";
1572                  reg = <0x0 0xff940000 0x0 0x100>;
1573                  interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1574                  interrupt-names = "hdcp_mmu";
1575                 status = "disabled";
1576         };
1577
1578         hevc_mmu: hevc-mmu {
1579                 dbgname = "hevc";
1580                 compatible = "rockchip,hevc_mmu";
1581                 reg = <0x0 0xff9a0440 0x0 0x40>,
1582                       <0x0 0xff9a0480 0x0 0x40>;
1583                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1584                 interrupt-names = "hevc_mmu";
1585                 status = "disabled";
1586         };
1587
1588         vpu_mmu: vpu-mmu {
1589                 dbgname = "vpu";
1590                 compatible = "rockchip,vpu_mmu";
1591                 reg = <0x0 0xff9a0800 0x0 0x100>;
1592                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1593                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1594                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1595                 status = "disabled";
1596         };
1597 };