2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3368-power.h>
52 compatible = "rockchip,rk3368";
53 interrupt-parent = <&gic>;
76 #address-cells = <0x2>;
112 entry-method = "psci";
114 cpu_sleep: cpu-sleep-0 {
115 compatible = "arm,idle-state";
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
125 compatible = "arm,cortex-a53", "arm,armv8";
127 cpu-idle-states = <&cpu_sleep>;
128 enable-method = "psci";
133 compatible = "arm,cortex-a53", "arm,armv8";
135 cpu-idle-states = <&cpu_sleep>;
136 enable-method = "psci";
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
149 compatible = "arm,cortex-a53", "arm,armv8";
151 cpu-idle-states = <&cpu_sleep>;
152 enable-method = "psci";
157 compatible = "arm,cortex-a53", "arm,armv8";
159 cpu-idle-states = <&cpu_sleep>;
160 enable-method = "psci";
165 compatible = "arm,cortex-a53", "arm,armv8";
167 cpu-idle-states = <&cpu_sleep>;
168 enable-method = "psci";
173 compatible = "arm,cortex-a53", "arm,armv8";
175 cpu-idle-states = <&cpu_sleep>;
176 enable-method = "psci";
181 compatible = "arm,cortex-a53", "arm,armv8";
183 cpu-idle-states = <&cpu_sleep>;
184 enable-method = "psci";
189 compatible = "arm,armv8-pmuv3";
190 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
191 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
198 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
199 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
200 <&cpu_b2>, <&cpu_b3>;
204 compatible = "arm,amba-bus";
205 #address-cells = <2>;
209 dmac_peri: dma-controller@ff250000 {
210 compatible = "arm,pl330", "arm,primecell";
211 reg = <0x0 0xff250000 0x0 0x4000>;
212 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&cru ACLK_DMAC_PERI>;
216 clock-names = "apb_pclk";
219 dmac_bus: dma-controller@ff600000 {
220 compatible = "arm,pl330", "arm,primecell";
221 reg = <0x0 0xff600000 0x0 0x4000>;
222 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
225 clocks = <&cru ACLK_DMAC_BUS>;
226 clock-names = "apb_pclk";
231 compatible = "arm,psci-0.2";
236 compatible = "arm,armv8-timer";
237 interrupts = <GIC_PPI 13
238 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
240 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
242 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
244 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
248 compatible = "fixed-clock";
249 clock-frequency = <24000000>;
250 clock-output-names = "xin24m";
254 sdmmc: rksdmmc@ff0c0000 {
255 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
256 reg = <0x0 0xff0c0000 0x0 0x4000>;
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
259 clock-names = "biu", "ciu";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
265 sdio0: dwmmc@ff0d0000 {
266 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
267 reg = <0x0 0xff0d0000 0x0 0x4000>;
268 clock-freq-min-max = <400000 150000000>;
269 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
270 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
277 emmc: rksdmmc@ff0f0000 {
278 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
279 reg = <0x0 0xff0f0000 0x0 0x4000>;
280 clock-freq-min-max = <400000 150000000>;
281 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
282 clock-names = "biu", "ciu";
283 fifo-depth = <0x100>;
284 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
288 saradc: saradc@ff100000 {
289 compatible = "rockchip,saradc";
290 reg = <0x0 0xff100000 0x0 0x100>;
291 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
292 #io-channel-cells = <1>;
293 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
294 clock-names = "saradc", "apb_pclk";
299 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
300 reg = <0x0 0xff110000 0x0 0x1000>;
301 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
302 clock-names = "spiclk", "apb_pclk";
303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
306 #address-cells = <1>;
312 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
313 reg = <0x0 0xff120000 0x0 0x1000>;
314 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
315 clock-names = "spiclk", "apb_pclk";
316 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
319 #address-cells = <1>;
325 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
326 reg = <0x0 0xff130000 0x0 0x1000>;
327 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
328 clock-names = "spiclk", "apb_pclk";
329 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
332 #address-cells = <1>;
338 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
339 reg = <0x0 0xff650000 0x0 0x1000>;
340 clocks = <&cru PCLK_I2C0>;
342 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&i2c0_xfer>;
345 #address-cells = <1>;
351 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
352 reg = <0x0 0xff140000 0x0 0x1000>;
353 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
357 clocks = <&cru PCLK_I2C2>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c2_xfer>;
364 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
365 reg = <0x0 0xff150000 0x0 0x1000>;
366 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
370 clocks = <&cru PCLK_I2C3>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c3_xfer>;
377 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
378 reg = <0x0 0xff160000 0x0 0x1000>;
379 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
383 clocks = <&cru PCLK_I2C4>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c4_xfer>;
390 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
391 reg = <0x0 0xff170000 0x0 0x1000>;
392 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
393 #address-cells = <1>;
396 clocks = <&cru PCLK_I2C5>;
397 pinctrl-names = "default";
398 pinctrl-0 = <&i2c5_xfer>;
402 uart0: serial@ff180000 {
403 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
404 reg = <0x0 0xff180000 0x0 0x100>;
405 clock-frequency = <24000000>;
406 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
407 clock-names = "baudclk", "apb_pclk";
408 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
414 uart1: serial@ff190000 {
415 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
416 reg = <0x0 0xff190000 0x0 0x100>;
417 clock-frequency = <24000000>;
418 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
419 clock-names = "baudclk", "apb_pclk";
420 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
426 uart3: serial@ff1b0000 {
427 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
428 reg = <0x0 0xff1b0000 0x0 0x100>;
429 clock-frequency = <24000000>;
430 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
431 clock-names = "baudclk", "apb_pclk";
432 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
438 uart4: serial@ff1c0000 {
439 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
440 reg = <0x0 0xff1c0000 0x0 0x100>;
441 clock-frequency = <24000000>;
442 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
443 clock-names = "baudclk", "apb_pclk";
444 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
450 gmac: ethernet@ff290000 {
451 compatible = "rockchip,rk3368-gmac";
452 reg = <0x0 0xff290000 0x0 0x10000>;
453 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
454 interrupt-names = "macirq";
455 rockchip,grf = <&grf>;
456 clocks = <&cru SCLK_MAC>,
457 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
458 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
459 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
460 clock-names = "stmmaceth",
461 "mac_clk_rx", "mac_clk_tx",
462 "clk_mac_ref", "clk_mac_refout",
463 "aclk_mac", "pclk_mac";
467 usb_host0_ehci: usb@ff500000 {
468 compatible = "generic-ehci";
469 reg = <0x0 0xff500000 0x0 0x100>;
470 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&cru HCLK_HOST0>;
472 clock-names = "usbhost";
476 usb_otg: usb@ff580000 {
477 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
479 reg = <0x0 0xff580000 0x0 0x40000>;
480 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&cru HCLK_OTG0>;
484 g-np-tx-fifo-size = <16>;
485 g-rx-fifo-size = <275>;
486 g-tx-fifo-size = <256 128 128 64 64 32>;
491 ddrpctl: syscon@ff610000 {
492 compatible = "rockchip,rk3368-ddrpctl", "syscon";
493 reg = <0x0 0xff610000 0x0 0x400>;
497 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
498 reg = <0x0 0xff660000 0x0 0x1000>;
499 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
503 clocks = <&cru PCLK_I2C1>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&i2c1_xfer>;
510 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
511 reg = <0x0 0xff680000 0x0 0x10>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pwm0_pin>;
515 clocks = <&cru PCLK_PWM1>;
521 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
522 reg = <0x0 0xff680010 0x0 0x10>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&pwm1_pin>;
526 clocks = <&cru PCLK_PWM1>;
532 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
533 reg = <0x0 0xff680020 0x0 0x10>;
535 clocks = <&cru PCLK_PWM1>;
541 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
542 reg = <0x0 0xff680030 0x0 0x10>;
544 pinctrl-names = "default";
545 pinctrl-0 = <&pwm3_pin>;
546 clocks = <&cru PCLK_PWM1>;
551 uart2: serial@ff690000 {
552 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
553 reg = <0x0 0xff690000 0x0 0x100>;
554 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
555 clock-names = "baudclk", "apb_pclk";
556 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
557 pinctrl-names = "default";
558 pinctrl-0 = <&uart2_xfer>;
564 pmu: power-management@ff730000 {
565 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
566 reg = <0x0 0xff730000 0x0 0x1000>;
568 power: power-controller {
570 compatible = "rockchip,rk3368-power-controller";
571 #power-domain-cells = <1>;
572 #address-cells = <1>;
576 * Note: Although SCLK_* are the working clocks
577 * of device without including on the NOC, needed for
580 * The clocks on the which NOC:
581 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
582 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
583 * ACLK_RGA is on ACLK_RGA_NIU.
584 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
586 * Which clock are device clocks:
588 * *_IEP IEP:Image Enhancement Processor
589 * *_ISP ISP:Image Signal Processing
590 * *_VIP VIP:Video Input Processor
591 * *_VOP* VOP:Visual Output Processor
599 reg = <RK3368_PD_VIO>;
600 clocks = <&cru ACLK_IEP>,
612 <&cru HCLK_VIO_HDCPMMU>,
613 <&cru PCLK_EDP_CTRL>,
614 <&cru PCLK_HDMI_CTRL>,
620 <&cru PCLK_MIPI_CSI>,
621 <&cru PCLK_MIPI_DSI0>,
622 <&cru SCLK_VOP0_PWM>,
628 <&cru SCLK_HDMI_CEC>,
629 <&cru SCLK_HDMI_HDCP>;
632 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
633 * (video endecoder & decoder) clocks that on the
634 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
637 reg = <RK3368_PD_VIDEO>;
638 clocks = <&cru ACLK_VIDEO>,
640 <&cru SCLK_HEVC_CABAC>,
641 <&cru SCLK_HEVC_CORE>;
644 * Note: ACLK_GPU is the GPU clock,
645 * and on the ACLK_GPU_NIU (NOC).
648 reg = <RK3368_PD_GPU_1>;
649 clocks = <&cru ACLK_GPU_CFG>,
651 <&cru SCLK_GPU_CORE>;
656 pmugrf: syscon@ff738000 {
657 compatible = "rockchip,rk3368-pmugrf", "syscon";
658 reg = <0x0 0xff738000 0x0 0x1000>;
661 cru: clock-controller@ff760000 {
662 compatible = "rockchip,rk3368-cru";
663 reg = <0x0 0xff760000 0x0 0x1000>;
664 rockchip,grf = <&grf>;
669 grf: syscon@ff770000 {
670 compatible = "rockchip,rk3368-grf", "syscon";
671 reg = <0x0 0xff770000 0x0 0x1000>;
674 wdt: watchdog@ff800000 {
675 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
676 reg = <0x0 0xff800000 0x0 0x100>;
677 clocks = <&cru PCLK_WDT>;
678 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
682 gic: interrupt-controller@ffb71000 {
683 compatible = "arm,gic-400";
684 interrupt-controller;
685 #interrupt-cells = <3>;
686 #address-cells = <0>;
688 reg = <0x0 0xffb71000 0x0 0x1000>,
689 <0x0 0xffb72000 0x0 0x1000>,
690 <0x0 0xffb74000 0x0 0x2000>,
691 <0x0 0xffb76000 0x0 0x2000>;
692 interrupts = <GIC_PPI 9
693 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
696 gpu: rogue-g6110@ffa30000 {
697 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
698 reg = <0x0 0xffa30000 0x0 0x10000>;
700 <&cru SCLK_GPU_CORE>,
707 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
708 interrupt-names = "rogue-g6110-irq";
711 i2s_2ch: i2s-2ch@ff890000 {
712 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
713 reg = <0x0 0xff898000 0x0 0x1000>;
714 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
715 #address-cells = <2>;
717 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
718 dma-names = "tx", "rx";
719 clock-names = "i2s_hclk", "i2s_clk";
720 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
724 i2s_8ch: i2s-8ch@ff898000 {
725 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
726 reg = <0x0 0xff898000 0x0 0x1000>;
727 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
728 #address-cells = <1>;
730 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
731 dma-names = "tx", "rx";
732 clock-names = "i2s_hclk", "i2s_clk";
733 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
734 pinctrl-names = "default";
735 pinctrl-0 = <&i2s_8ch_bus>;
740 compatible = "rockchip,rk3368-pinctrl";
741 rockchip,grf = <&grf>;
742 rockchip,pmu = <&pmugrf>;
743 #address-cells = <0x2>;
747 gpio0: gpio0@ff750000 {
748 compatible = "rockchip,gpio-bank";
749 reg = <0x0 0xff750000 0x0 0x100>;
750 clocks = <&cru PCLK_GPIO0>;
751 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
756 interrupt-controller;
757 #interrupt-cells = <0x2>;
760 gpio1: gpio1@ff780000 {
761 compatible = "rockchip,gpio-bank";
762 reg = <0x0 0xff780000 0x0 0x100>;
763 clocks = <&cru PCLK_GPIO1>;
764 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
769 interrupt-controller;
770 #interrupt-cells = <0x2>;
773 gpio2: gpio2@ff790000 {
774 compatible = "rockchip,gpio-bank";
775 reg = <0x0 0xff790000 0x0 0x100>;
776 clocks = <&cru PCLK_GPIO2>;
777 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
782 interrupt-controller;
783 #interrupt-cells = <0x2>;
786 gpio3: gpio3@ff7a0000 {
787 compatible = "rockchip,gpio-bank";
788 reg = <0x0 0xff7a0000 0x0 0x100>;
789 clocks = <&cru PCLK_GPIO3>;
790 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
795 interrupt-controller;
796 #interrupt-cells = <0x2>;
799 pcfg_pull_up: pcfg-pull-up {
803 pcfg_pull_down: pcfg-pull-down {
807 pcfg_pull_none: pcfg-pull-none {
811 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
813 drive-strength = <12>;
818 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
822 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
826 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
829 emmc_bus1: emmc-bus1 {
830 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
833 emmc_bus4: emmc-bus4 {
834 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
835 <1 19 RK_FUNC_2 &pcfg_pull_up>,
836 <1 20 RK_FUNC_2 &pcfg_pull_up>,
837 <1 21 RK_FUNC_2 &pcfg_pull_up>;
840 emmc_bus8: emmc-bus8 {
841 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
842 <1 19 RK_FUNC_2 &pcfg_pull_up>,
843 <1 20 RK_FUNC_2 &pcfg_pull_up>,
844 <1 21 RK_FUNC_2 &pcfg_pull_up>,
845 <1 22 RK_FUNC_2 &pcfg_pull_up>,
846 <1 23 RK_FUNC_2 &pcfg_pull_up>,
847 <1 24 RK_FUNC_2 &pcfg_pull_up>,
848 <1 25 RK_FUNC_2 &pcfg_pull_up>;
853 rgmii_pins: rgmii-pins {
854 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
855 <3 24 RK_FUNC_1 &pcfg_pull_none>,
856 <3 19 RK_FUNC_1 &pcfg_pull_none>,
857 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
858 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
859 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
860 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
861 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
862 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
863 <3 15 RK_FUNC_1 &pcfg_pull_none>,
864 <3 16 RK_FUNC_1 &pcfg_pull_none>,
865 <3 17 RK_FUNC_1 &pcfg_pull_none>,
866 <3 18 RK_FUNC_1 &pcfg_pull_none>,
867 <3 25 RK_FUNC_1 &pcfg_pull_none>,
868 <3 20 RK_FUNC_1 &pcfg_pull_none>;
871 rmii_pins: rmii-pins {
872 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
873 <3 24 RK_FUNC_1 &pcfg_pull_none>,
874 <3 19 RK_FUNC_1 &pcfg_pull_none>,
875 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
876 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
877 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
878 <3 15 RK_FUNC_1 &pcfg_pull_none>,
879 <3 16 RK_FUNC_1 &pcfg_pull_none>,
880 <3 20 RK_FUNC_1 &pcfg_pull_none>,
881 <3 21 RK_FUNC_1 &pcfg_pull_none>;
886 i2c0_xfer: i2c0-xfer {
887 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
888 <0 7 RK_FUNC_1 &pcfg_pull_none>;
893 i2c1_xfer: i2c1-xfer {
894 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
895 <2 22 RK_FUNC_1 &pcfg_pull_none>;
900 i2c2_xfer: i2c2-xfer {
901 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
902 <3 31 RK_FUNC_2 &pcfg_pull_none>;
907 i2c3_xfer: i2c3-xfer {
908 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
909 <1 17 RK_FUNC_1 &pcfg_pull_none>;
914 i2c4_xfer: i2c4-xfer {
915 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
916 <3 25 RK_FUNC_2 &pcfg_pull_none>;
921 i2c5_xfer: i2c5-xfer {
922 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
923 <3 27 RK_FUNC_2 &pcfg_pull_none>;
928 i2s_8ch_bus: i2s-8ch-bus {
929 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
930 <2 13 RK_FUNC_1 &pcfg_pull_none>,
931 <2 14 RK_FUNC_1 &pcfg_pull_none>,
932 <2 15 RK_FUNC_1 &pcfg_pull_none>,
933 <2 16 RK_FUNC_1 &pcfg_pull_none>,
934 <2 17 RK_FUNC_1 &pcfg_pull_none>,
935 <2 18 RK_FUNC_1 &pcfg_pull_none>,
936 <2 19 RK_FUNC_1 &pcfg_pull_none>,
937 <2 20 RK_FUNC_1 &pcfg_pull_none>;
942 sdio0_bus1: sdio0-bus1 {
943 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
946 sdio0_bus4: sdio0-bus4 {
947 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
948 <2 29 RK_FUNC_1 &pcfg_pull_up>,
949 <2 30 RK_FUNC_1 &pcfg_pull_up>,
950 <2 31 RK_FUNC_1 &pcfg_pull_up>;
953 sdio0_cmd: sdio0-cmd {
954 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
957 sdio0_clk: sdio0-clk {
958 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
962 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
966 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
969 sdio0_pwr: sdio0-pwr {
970 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
973 sdio0_bkpwr: sdio0-bkpwr {
974 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
977 sdio0_int: sdio0-int {
978 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
983 sdmmc_clk: sdmmc-clk {
984 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
987 sdmmc_cmd: sdmmc-cmd {
988 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
992 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
995 sdmmc_bus1: sdmmc-bus1 {
996 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
999 sdmmc_bus4: sdmmc-bus4 {
1000 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1001 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1002 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1003 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1008 spi0_clk: spi0-clk {
1009 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1011 spi0_cs0: spi0-cs0 {
1012 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1014 spi0_cs1: spi0-cs1 {
1015 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1018 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1021 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1026 spi1_clk: spi1-clk {
1027 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1029 spi1_cs0: spi1-cs0 {
1030 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1032 spi1_cs1: spi1-cs1 {
1033 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1036 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1039 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1044 spi2_clk: spi2-clk {
1045 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1047 spi2_cs0: spi2-cs0 {
1048 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1051 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1054 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1059 uart0_xfer: uart0-xfer {
1060 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1061 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1064 uart0_cts: uart0-cts {
1065 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1068 uart0_rts: uart0-rts {
1069 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1074 uart1_xfer: uart1-xfer {
1075 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1076 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1079 uart1_cts: uart1-cts {
1080 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1083 uart1_rts: uart1-rts {
1084 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1089 uart2_xfer: uart2-xfer {
1090 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1091 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1093 /* no rts / cts for uart2 */
1097 uart3_xfer: uart3-xfer {
1098 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1099 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1102 uart3_cts: uart3-cts {
1103 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1106 uart3_rts: uart3-rts {
1107 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1112 uart4_xfer: uart4-xfer {
1113 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1114 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1117 uart4_cts: uart4-cts {
1118 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1121 uart4_rts: uart4-rts {
1122 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1127 pwm0_pin: pwm0-pin {
1128 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1131 vop_pwm_pin: vop-pwm {
1132 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1137 pwm1_pin: pwm1-pin {
1138 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1143 pwm3_pin: pwm3-pin {
1144 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1149 lcdc_lcdc: lcdc-lcdc {
1151 <0 14 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1152 <0 15 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1153 <0 16 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1154 <0 17 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1155 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1156 <0 18 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1157 <0 20 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1158 <0 21 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1159 <0 22 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1160 <0 23 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1161 <0 24 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1162 <0 25 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1163 <0 26 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1164 <0 27 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1165 <0 31 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1166 <0 30 RK_FUNC_1 &pcfg_pull_none>,//DEN
1167 <0 28 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1168 <0 29 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1171 lcdc_gpio: lcdc-gpio {
1173 <0 14 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1174 <0 15 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1175 <0 16 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1176 <0 17 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1177 <0 18 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1178 <0 19 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1179 <0 20 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1180 <0 21 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1181 <0 22 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1182 <0 23 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1183 <0 24 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1184 <0 25 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1185 <0 26 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1186 <0 27 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1187 <0 31 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1188 <0 30 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1189 <0 28 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1190 <0 29 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1196 compatible = "rockchip,rk-fb";
1197 rockchip,disp-mode = <NO_DUAL>;
1198 status = "disabled";
1202 compatible = "rockchip,screen";
1203 status = "disabled";
1206 lcdc: lcdc@ff930000 {
1207 compatible = "rockchip,rk3368-lcdc";
1208 rockchip,grf = <&grf>;
1209 rockchip,pmugrf = <&pmugrf>;
1210 rockchip,cru = <&cru>;
1211 rockchip,prop = <PRMRY>;
1212 rockchip,pwr18 = <0>;
1213 rockchip,iommu-enabled = <1>;
1214 reg = <0x0 0xff930000 0x0 0x10000>;
1215 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1217 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
1218 /*power-domains = <&power PD_VIO>;*/
1219 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1220 reset-names = "axi", "ahb", "dclk";
1221 status = "disabled";
1224 mipi: mipi@ff960000 {
1225 compatible = "rockchip,rk3368-dsi";
1226 rockchip,prop = <0>;
1227 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1228 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
1229 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1231 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1232 /*power-domains = <&power PD_VIO>;*/
1233 status = "disabled";
1236 lvds: lvds@ff968000 {
1237 compatible = "rockchip,rk3368-lvds";
1238 rockchip,grf = <&grf>;
1239 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1240 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1241 clocks = <&cru PCLK_DPHYTX0>, <&cru PCLK_MIPI_DSI0>;
1242 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1243 /*power-domains = <&power PD_VIO>;*/
1244 status = "disabled";
1248 compatible = "rockchip,rk32-edp";
1249 reg = <0x0 0xff970000 0x0 0x4000>;
1250 rockchip,grf = <&grf>;
1251 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>;
1253 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
1254 /*power-domains = <&power PD_VIO>;*/
1255 resets = <&cru SRST_EDP_24M>, <&cru SRST_EDP>;
1256 reset-names = "edp_24m", "edp_apb";
1257 status = "disabled";
1262 compatible = "rockchip,iep_mmu";
1263 reg = <0x0 0xff900800 0x0 0x100>;
1264 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1265 interrupt-names = "iep_mmu";
1266 status = "disabled";
1271 compatible = "rockchip,vip_mmu";
1272 reg = <0x0 0xff950800 0x0 0x100>;
1273 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1274 interrupt-names = "vip_mmu";
1275 status = "disabled";
1278 vopb_mmu: vopb-mmu {
1280 compatible = "rockchip,vopb_mmu";
1281 reg = <0x0 0xff930300 0x0 0x100>;
1282 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1283 interrupt-names = "vop_mmu";
1284 status = "disabled";
1288 dbgname = "isp_mmu";
1289 compatible = "rockchip,isp_mmu";
1290 reg = <0x0 0xff914000 0x0 0x100>,
1291 <0x0 0xff915000 0x0 0x100>;
1292 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1293 interrupt-names = "isp_mmu";
1294 status = "disabled";
1297 hdcp_mmu: hdcp-mmu {
1298 dbgname = "hdcp_mmu";
1299 compatible = "rockchip,hdcp_mmu";
1300 reg = <0x0 0xff940000 0x0 0x100>;
1301 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1302 interrupt-names = "hdcp_mmu";
1303 status = "disabled";
1306 hevc_mmu: hevc-mmu {
1308 compatible = "rockchip,hevc_mmu";
1309 reg = <0x0 0xff9a0440 0x0 0x40>,
1310 <0x0 0xff9a0480 0x0 0x40>;
1311 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1312 interrupt-names = "hevc_mmu";
1313 status = "disabled";
1318 compatible = "rockchip,vpu_mmu";
1319 reg = <0x0 0xff9a0800 0x0 0x100>;
1320 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1321 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1322 interrupt-names = "vepu_mmu", "vdpu_mmu";
1323 status = "disabled";