2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
135 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
136 #cooling-cells = <2>; /* min followed by max */
137 dynamic-power-coefficient = <149>;
142 compatible = "arm,cortex-a53", "arm,armv8";
144 cpu-idle-states = <&cpu_sleep>;
145 enable-method = "psci";
146 clocks = <&cru ARMCLKL>;
147 operating-points-v2 = <&cluster0_opp>;
148 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
153 compatible = "arm,cortex-a53", "arm,armv8";
155 cpu-idle-states = <&cpu_sleep>;
156 enable-method = "psci";
157 clocks = <&cru ARMCLKL>;
158 operating-points-v2 = <&cluster0_opp>;
159 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
164 compatible = "arm,cortex-a53", "arm,armv8";
166 cpu-idle-states = <&cpu_sleep>;
167 enable-method = "psci";
168 clocks = <&cru ARMCLKL>;
169 operating-points-v2 = <&cluster0_opp>;
170 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
175 compatible = "arm,cortex-a53", "arm,armv8";
177 cpu-idle-states = <&cpu_sleep>;
178 enable-method = "psci";
179 clocks = <&cru ARMCLKB>;
180 operating-points-v2 = <&cluster1_opp>;
181 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
182 #cooling-cells = <2>; /* min followed by max */
183 dynamic-power-coefficient = <160>;
188 compatible = "arm,cortex-a53", "arm,armv8";
190 cpu-idle-states = <&cpu_sleep>;
191 enable-method = "psci";
192 clocks = <&cru ARMCLKB>;
193 operating-points-v2 = <&cluster1_opp>;
194 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
199 compatible = "arm,cortex-a53", "arm,armv8";
201 cpu-idle-states = <&cpu_sleep>;
202 enable-method = "psci";
203 clocks = <&cru ARMCLKB>;
204 operating-points-v2 = <&cluster1_opp>;
205 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
210 compatible = "arm,cortex-a53", "arm,armv8";
212 cpu-idle-states = <&cpu_sleep>;
213 enable-method = "psci";
214 clocks = <&cru ARMCLKB>;
215 operating-points-v2 = <&cluster1_opp>;
216 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
220 cluster0_opp: opp_table0 {
221 compatible = "operating-points-v2";
225 opp-hz = /bits/ 64 <216000000>;
226 opp-microvolt = <950000 950000 1350000>;
227 clock-latency-ns = <40000>;
231 opp-hz = /bits/ 64 <408000000>;
232 opp-microvolt = <950000 950000 1350000>;
233 clock-latency-ns = <40000>;
236 opp-hz = /bits/ 64 <600000000>;
237 opp-microvolt = <950000 950000 1350000>;
238 clock-latency-ns = <40000>;
241 opp-hz = /bits/ 64 <816000000>;
242 opp-microvolt = <1025000 1025000 1350000>;
243 clock-latency-ns = <40000>;
246 opp-hz = /bits/ 64 <1008000000>;
247 opp-microvolt = <1125000 1125000 1350000>;
248 clock-latency-ns = <40000>;
251 opp-hz = /bits/ 64 <1200000000>;
252 opp-microvolt = <1225000 1225000 1350000>;
253 clock-latency-ns = <40000>;
257 cluster1_opp: opp_table1 {
258 compatible = "operating-points-v2";
262 opp-hz = /bits/ 64 <216000000>;
263 opp-microvolt = <950000 950000 1350000>;
264 clock-latency-ns = <40000>;
268 opp-hz = /bits/ 64 <408000000>;
269 opp-microvolt = <950000 950000 1350000>;
270 clock-latency-ns = <40000>;
273 opp-hz = /bits/ 64 <600000000>;
274 opp-microvolt = <950000 950000 1350000>;
275 clock-latency-ns = <40000>;
278 opp-hz = /bits/ 64 <816000000>;
279 opp-microvolt = <975000 975000 1350000>;
280 clock-latency-ns = <40000>;
283 opp-hz = /bits/ 64 <1008000000>;
284 opp-microvolt = <1050000 1050000 1350000>;
285 clock-latency-ns = <40000>;
288 opp-hz = /bits/ 64 <1200000000>;
289 opp-microvolt = <1150000 1150000 1350000>;
290 clock-latency-ns = <40000>;
293 opp-hz = /bits/ 64 <1296000000>;
294 opp-microvolt = <1225000 1225000 1350000>;
295 clock-latency-ns = <40000>;
298 opp-hz = /bits/ 64 <1416000000>;
299 opp-microvolt = <1300000 1300000 1350000>;
300 clock-latency-ns = <40000>;
303 opp-hz = /bits/ 64 <1512000000>;
304 opp-microvolt = <1350000 1350000 1350000>;
305 clock-latency-ns = <40000>;
310 RK3368_CPU_COST_0: rk3368-core-cost0 {
326 RK3368_CPU_COST_1: rk3368-core-cost1 {
345 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
361 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
384 min-volt = <950000>; /* uV */
385 min-freq = <216000>; /* KHz */
386 leakage-adjust-volt = <
390 nvmem-cells = <&cpu_leakage>;
391 nvmem-cell-names = "cpu_leakage";
395 min-volt = <950000>; /* uV */
396 min-freq = <216000>; /* KHz */
397 leakage-adjust-volt = <
401 nvmem-cells = <&cpu_leakage>;
402 nvmem-cell-names = "cpu_leakage";
407 compatible = "arm,armv8-pmuv3";
408 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
412 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
416 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
417 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
418 <&cpu_b2>, <&cpu_b3>;
422 compatible = "arm,amba-bus";
423 #address-cells = <2>;
427 dmac_peri: dma-controller@ff250000 {
428 compatible = "arm,pl330", "arm,primecell";
429 reg = <0x0 0xff250000 0x0 0x4000>;
430 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru ACLK_DMAC_PERI>;
434 clock-names = "apb_pclk";
435 arm,pl330-broken-no-flushp;
436 peripherals-req-type-burst;
439 dmac_bus: dma-controller@ff600000 {
440 compatible = "arm,pl330", "arm,primecell";
441 reg = <0x0 0xff600000 0x0 0x4000>;
442 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&cru ACLK_DMAC_BUS>;
446 clock-names = "apb_pclk";
447 arm,pl330-broken-no-flushp;
448 peripherals-req-type-burst;
453 compatible = "arm,psci-0.2";
458 compatible = "arm,armv8-timer";
459 interrupts = <GIC_PPI 13
460 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
462 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
464 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
466 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
470 compatible = "fixed-clock";
471 clock-frequency = <24000000>;
472 clock-output-names = "xin24m";
476 sdmmc: dwmmc@ff0c0000 {
477 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
478 reg = <0x0 0xff0c0000 0x0 0x4000>;
479 clock-freq-min-max = <400000 150000000>;
480 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
481 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
482 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
483 fifo-depth = <0x100>;
484 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
488 sdio0: dwmmc@ff0d0000 {
489 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
490 reg = <0x0 0xff0d0000 0x0 0x4000>;
491 clock-freq-min-max = <400000 150000000>;
492 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
493 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
494 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
495 fifo-depth = <0x100>;
496 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
500 emmc: dwmmc@ff0f0000 {
501 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
502 reg = <0x0 0xff0f0000 0x0 0x4000>;
503 clock-freq-min-max = <400000 150000000>;
504 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
505 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
506 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
507 fifo-depth = <0x100>;
508 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
512 saradc: saradc@ff100000 {
513 compatible = "rockchip,saradc";
514 reg = <0x0 0xff100000 0x0 0x100>;
515 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
516 #io-channel-cells = <1>;
517 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
518 clock-names = "saradc", "apb_pclk";
519 resets = <&cru SRST_SARADC>;
520 reset-names = "saradc-apb";
525 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
526 reg = <0x0 0xff110000 0x0 0x1000>;
527 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
528 clock-names = "spiclk", "apb_pclk";
529 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
532 #address-cells = <1>;
538 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
539 reg = <0x0 0xff120000 0x0 0x1000>;
540 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
541 clock-names = "spiclk", "apb_pclk";
542 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
545 #address-cells = <1>;
551 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
552 reg = <0x0 0xff130000 0x0 0x1000>;
553 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
554 clock-names = "spiclk", "apb_pclk";
555 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
558 #address-cells = <1>;
564 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
565 reg = <0x0 0xff650000 0x0 0x1000>;
566 clocks = <&cru PCLK_I2C0>;
568 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&i2c0_xfer>;
571 #address-cells = <1>;
577 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
578 reg = <0x0 0xff140000 0x0 0x1000>;
579 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <1>;
583 clocks = <&cru PCLK_I2C2>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&i2c2_xfer>;
590 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
591 reg = <0x0 0xff150000 0x0 0x1000>;
592 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
593 #address-cells = <1>;
596 clocks = <&cru PCLK_I2C3>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&i2c3_xfer>;
603 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
604 reg = <0x0 0xff160000 0x0 0x1000>;
605 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
606 #address-cells = <1>;
609 clocks = <&cru PCLK_I2C4>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&i2c4_xfer>;
616 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
617 reg = <0x0 0xff170000 0x0 0x1000>;
618 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
619 #address-cells = <1>;
622 clocks = <&cru PCLK_I2C5>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&i2c5_xfer>;
628 uart0: serial@ff180000 {
629 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
630 reg = <0x0 0xff180000 0x0 0x100>;
631 clock-frequency = <24000000>;
632 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
633 clock-names = "baudclk", "apb_pclk";
634 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
640 uart1: serial@ff190000 {
641 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
642 reg = <0x0 0xff190000 0x0 0x100>;
643 clock-frequency = <24000000>;
644 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
645 clock-names = "baudclk", "apb_pclk";
646 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
652 uart3: serial@ff1b0000 {
653 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
654 reg = <0x0 0xff1b0000 0x0 0x100>;
655 clock-frequency = <24000000>;
656 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
657 clock-names = "baudclk", "apb_pclk";
658 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
664 uart4: serial@ff1c0000 {
665 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
666 reg = <0x0 0xff1c0000 0x0 0x100>;
667 clock-frequency = <24000000>;
668 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
669 clock-names = "baudclk", "apb_pclk";
670 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
676 thermal_zones: thermal-zones {
677 soc_thermal: soc-thermal {
678 polling-delay-passive = <200>; /* milliseconds */
679 polling-delay = <200>; /* milliseconds */
680 sustainable-power = <600>; /* milliwatts */
682 thermal-sensors = <&tsadc 0>;
684 threshold: trip-point@0 {
685 temperature = <70000>; /* millicelsius */
686 hysteresis = <2000>; /* millicelsius */
689 target: trip-point@1 {
690 temperature = <80000>; /* millicelsius */
691 hysteresis = <2000>; /* millicelsius */
695 temperature = <95000>; /* millicelsius */
696 hysteresis = <2000>; /* millicelsius */
705 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
706 contribution = <1024>;
711 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
712 contribution = <1024>;
717 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
718 contribution = <1024>;
723 gpu_thermal: gpu-thermal {
724 polling-delay-passive = <200>; /* milliseconds */
725 polling-delay = <200>; /* milliseconds */
726 thermal-sensors = <&tsadc 1>;
730 tsadc: tsadc@ff280000 {
731 compatible = "rockchip,rk3368-tsadc-legacy";
732 reg = <0x0 0xff280000 0x0 0x100>;
733 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
735 clock-names = "tsadc", "apb_pclk";
736 clock-frequency = <32768>;
737 resets = <&cru SRST_TSADC>;
738 reset-names = "tsadc-apb";
739 nvmem-cells = <&temp_adjust>;
740 nvmem-cell-names = "temp_adjust";
741 #thermal-sensor-cells = <1>;
742 hw-shut-temp = <95000>;
743 latency-bound = <50000>;
747 gmac: ethernet@ff290000 {
748 compatible = "rockchip,rk3368-gmac";
749 reg = <0x0 0xff290000 0x0 0x10000>;
750 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
751 interrupt-names = "macirq";
752 rockchip,grf = <&grf>;
753 clocks = <&cru SCLK_MAC>,
754 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
755 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
756 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
757 clock-names = "stmmaceth",
758 "mac_clk_rx", "mac_clk_tx",
759 "clk_mac_ref", "clk_mac_refout",
760 "aclk_mac", "pclk_mac";
764 nandc0: nandc@ff400000 {
765 compatible = "rockchip,rk-nandc";
766 reg = <0x0 0xff400000 0x0 0x4000>;
767 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
770 clock-names = "clk_nandc", "hclk_nandc";
774 usb_host0_ehci: usb@ff500000 {
775 compatible = "generic-ehci";
776 reg = <0x0 0xff500000 0x0 0x20000>;
777 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&cru HCLK_HOST0>, <&u2phy>;
779 clock-names = "usbhost", "utmi";
780 phys = <&u2phy_host>;
785 usb_host0_ohci: usb@ff520000 {
786 compatible = "generic-ohci";
787 reg = <0x0 0xff520000 0x0 0x20000>;
788 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
789 clocks = <&cru HCLK_HOST0>, <&u2phy>;
790 clock-names = "usbhost", "utmi";
791 phys = <&u2phy_host>;
796 usb_otg: usb@ff580000 {
797 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
799 reg = <0x0 0xff580000 0x0 0x40000>;
800 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru HCLK_OTG0>;
804 g-np-tx-fifo-size = <16>;
805 g-rx-fifo-size = <275>;
806 g-tx-fifo-size = <256 128 128 64 64 32>;
811 ddrpctl: syscon@ff610000 {
812 compatible = "rockchip,rk3368-ddrpctl", "syscon";
813 reg = <0x0 0xff610000 0x0 0x400>;
817 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
818 reg = <0x0 0xff660000 0x0 0x1000>;
819 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
820 #address-cells = <1>;
823 clocks = <&cru PCLK_I2C1>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&i2c1_xfer>;
830 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
831 reg = <0x0 0xff680000 0x0 0x10>;
833 pinctrl-names = "default";
834 pinctrl-0 = <&pwm0_pin>;
835 clocks = <&cru PCLK_PWM1>;
841 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
842 reg = <0x0 0xff680010 0x0 0x10>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&pwm1_pin>;
846 clocks = <&cru PCLK_PWM1>;
852 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
853 reg = <0x0 0xff680020 0x0 0x10>;
855 clocks = <&cru PCLK_PWM1>;
861 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
862 reg = <0x0 0xff680030 0x0 0x10>;
864 pinctrl-names = "default";
865 pinctrl-0 = <&pwm3_pin>;
866 clocks = <&cru PCLK_PWM1>;
871 uart2: serial@ff690000 {
872 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
873 reg = <0x0 0xff690000 0x0 0x100>;
874 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
875 clock-names = "baudclk", "apb_pclk";
876 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
877 pinctrl-names = "default";
878 pinctrl-0 = <&uart2_xfer>;
884 mbox: mbox@ff6b0000 {
885 compatible = "rockchip,rk3368-mailbox";
886 reg = <0x0 0xff6b0000 0x0 0x1000>;
887 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
891 clocks = <&cru PCLK_MAILBOX>;
892 clock-names = "pclk_mailbox";
897 mailbox: mailbox@ff6b0000 {
898 compatible = "rockchip,rk3368-mbox-legacy";
899 reg = <0x0 0xff6b0000 0x0 0x1000>,
900 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
901 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
903 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
904 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&cru PCLK_MAILBOX>;
906 clock-names = "pclk_mailbox";
911 mailbox_scpi: mailbox-scpi {
912 compatible = "rockchip,rk3368-scpi-legacy";
913 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
918 qos_iep: qos@ffad0000 {
919 compatible = "syscon";
920 reg = <0x0 0xffad0000 0x0 0x20>;
923 qos_isp_r0: qos@ffad0080 {
924 compatible = "syscon";
925 reg = <0x0 0xffad0080 0x0 0x20>;
928 qos_isp_r1: qos@ffad0100 {
929 compatible = "syscon";
930 reg = <0x0 0xffad0100 0x0 0x20>;
933 qos_isp_w0: qos@ffad0180 {
934 compatible = "syscon";
935 reg = <0x0 0xffad0180 0x0 0x20>;
938 qos_isp_w1: qos@ffad0200 {
939 compatible = "syscon";
940 reg = <0x0 0xffad0200 0x0 0x20>;
943 qos_vip: qos@ffad0280 {
944 compatible = "syscon";
945 reg = <0x0 0xffad0280 0x0 0x20>;
948 qos_vop: qos@ffad0300 {
949 compatible = "syscon";
950 reg = <0x0 0xffad0300 0x0 0x20>;
953 qos_rga_r: qos@ffad0380 {
954 compatible = "syscon";
955 reg = <0x0 0xffad0380 0x0 0x20>;
958 qos_rga_w: qos@ffad0400 {
959 compatible = "syscon";
960 reg = <0x0 0xffad0400 0x0 0x20>;
963 qos_hevc_r: qos@ffae0000 {
964 compatible = "syscon";
965 reg = <0x0 0xffae0000 0x0 0x20>;
968 qos_vpu_r: qos@ffae0100 {
969 compatible = "syscon";
970 reg = <0x0 0xffae0100 0x0 0x20>;
973 qos_vpu_w: qos@ffae0180 {
974 compatible = "syscon";
975 reg = <0x0 0xffae0180 0x0 0x20>;
978 qos_gpu: qos@ffaf0000 {
979 compatible = "syscon";
980 reg = <0x0 0xffaf0000 0x0 0x20>;
983 pmu: power-management@ff730000 {
984 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
985 reg = <0x0 0xff730000 0x0 0x1000>;
987 power: power-controller {
988 compatible = "rockchip,rk3368-power-controller";
989 #power-domain-cells = <1>;
990 #address-cells = <1>;
994 * Note: Although SCLK_* are the working clocks
995 * of device without including on the NOC, needed for
998 * The clocks on the which NOC:
999 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1000 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1001 * ACLK_RGA is on ACLK_RGA_NIU.
1002 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1004 * Which clock are device clocks:
1006 * *_IEP IEP:Image Enhancement Processor
1007 * *_ISP ISP:Image Signal Processing
1008 * *_VIP VIP:Video Input Processor
1009 * *_VOP* VOP:Visual Output Processor
1017 reg = <RK3368_PD_VIO>;
1018 clocks = <&cru ACLK_IEP>,
1023 <&cru ACLK_VOP_IEP>,
1030 <&cru HCLK_VIO_HDCPMMU>,
1031 <&cru PCLK_EDP_CTRL>,
1032 <&cru PCLK_HDMI_CTRL>,
1037 <&cru PCLK_DPHYTX0>,
1038 <&cru PCLK_MIPI_CSI>,
1039 <&cru PCLK_MIPI_DSI0>,
1040 <&cru SCLK_VOP0_PWM>,
1041 <&cru SCLK_EDP_24M>,
1046 <&cru SCLK_HDMI_CEC>,
1047 <&cru SCLK_HDMI_HDCP>;
1048 pm_qos = <&qos_iep>,
1059 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1060 * (video endecoder & decoder) clocks that on the
1061 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1064 reg = <RK3368_PD_VIDEO>;
1065 clocks = <&cru ACLK_VIDEO>,
1067 <&cru SCLK_HEVC_CABAC>,
1068 <&cru SCLK_HEVC_CORE>;
1069 pm_qos = <&qos_hevc_r>,
1074 * Note: ACLK_GPU is the GPU clock,
1075 * and on the ACLK_GPU_NIU (NOC).
1078 reg = <RK3368_PD_GPU_1>;
1079 clocks = <&cru ACLK_GPU_CFG>,
1080 <&cru ACLK_GPU_MEM>,
1081 <&cru SCLK_GPU_CORE>;
1082 pm_qos = <&qos_gpu>;
1087 pmugrf: syscon@ff738000 {
1088 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1089 reg = <0x0 0xff738000 0x0 0x1000>;
1091 pmu_io_domains: io-domains {
1092 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1093 status = "disabled";
1097 compatible = "syscon-reboot-mode";
1099 mode-normal = <BOOT_NORMAL>;
1100 mode-recovery = <BOOT_RECOVERY>;
1101 mode-bootloader = <BOOT_FASTBOOT>;
1102 mode-loader = <BOOT_BL_DOWNLOAD>;
1106 cru: clock-controller@ff760000 {
1107 compatible = "rockchip,rk3368-cru";
1108 reg = <0x0 0xff760000 0x0 0x1000>;
1109 rockchip,grf = <&grf>;
1113 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1114 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1115 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1116 <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1117 <&cru ACLK_CCI_PRE>;
1118 assigned-clock-rates =
1119 <576000000>, <400000000>,
1120 <300000000>, <300000000>,
1121 <150000000>, <150000000>,
1122 <75000000>, <75000000>,
1126 grf: syscon@ff770000 {
1127 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1128 reg = <0x0 0xff770000 0x0 0x1000>;
1129 #address-cells = <1>;
1133 compatible = "rockchip,rk3368-dp-phy";
1134 clocks = <&cru SCLK_EDP_24M>;
1135 clock-names = "24m";
1136 resets = <&cru SRST_EDP_24M>;
1137 reset-names = "edp_24m";
1139 status = "disabled";
1142 io_domains: io-domains {
1143 compatible = "rockchip,rk3368-io-voltage-domain";
1144 status = "disabled";
1147 u2phy: usb2-phy@700 {
1148 compatible = "rockchip,rk3368-usb2phy";
1150 clocks = <&cru SCLK_OTGPHY0>;
1151 clock-names = "phyclk";
1153 clock-output-names = "usbotg_out";
1154 assigned-clocks = <&cru SCLK_USBPHY480M>;
1155 assigned-clock-parents = <&u2phy>;
1156 status = "disabled";
1158 u2phy_host: host-port {
1160 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1161 interrupt-names = "linestate";
1162 status = "disabled";
1167 wdt: watchdog@ff800000 {
1168 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1169 reg = <0x0 0xff800000 0x0 0x100>;
1170 clocks = <&cru PCLK_WDT>;
1171 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1172 status = "disabled";
1176 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1177 reg = <0x0 0xff810000 0x0 0x20>;
1178 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1181 i2s_2ch: i2s-2ch@ff890000 {
1182 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1183 reg = <0x0 0xff890000 0x0 0x1000>;
1184 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1185 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1186 dma-names = "tx", "rx";
1187 clock-names = "i2s_clk", "i2s_hclk";
1188 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1189 status = "disabled";
1192 i2s_8ch: i2s-8ch@ff898000 {
1193 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1194 reg = <0x0 0xff898000 0x0 0x1000>;
1195 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1196 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1197 dma-names = "tx", "rx";
1198 clock-names = "i2s_clk", "i2s_hclk";
1199 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1200 pinctrl-names = "default";
1201 pinctrl-0 = <&i2s_8ch_bus>;
1202 status = "disabled";
1206 compatible = "rockchip,iep";
1207 iommu_enabled = <1>;
1208 iommus = <&iep_mmu>;
1209 reg = <0x0 0xff900000 0x0 0x800>;
1210 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1211 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1212 clock-names = "aclk_iep", "hclk_iep";
1213 power-domains = <&power RK3368_PD_VIO>;
1216 status = "disabled";
1219 iep_mmu: iommu@ff900800 {
1220 compatible = "rockchip,iommu";
1221 reg = <0x0 0xff900800 0x0 0x100>;
1222 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1223 interrupt-names = "iep_mmu";
1224 power-domains = <&power RK3368_PD_VIO>;
1226 status = "disabled";
1230 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1231 reg = <0x0 0xff910000 0x0 0x4000>;
1232 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1233 power-domains = <&power RK3368_PD_VIO>;
1235 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1236 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1237 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1238 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1240 "aclk_isp", "hclk_isp", "clk_isp",
1241 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1242 "clk_cif_pll", "hclk_mipiphy1",
1243 "pclk_dphyrx", "clk_vio0_noc";
1246 "default", "isp_dvp8bit2", "isp_dvp10bit",
1247 "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1248 "isp_mipi_fl", "isp_mipi_fl_prefl",
1249 "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1250 pinctrl-0 = <&cif_clkout>;
1251 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1252 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1253 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1254 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1255 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1256 pinctrl-6 = <&cif_clkout>;
1257 pinctrl-7 = <&cif_clkout &isp_prelight>;
1258 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1259 pinctrl-9 = <&isp_flash_trigger>;
1260 rockchip,isp,mipiphy = <2>;
1261 rockchip,isp,cifphy = <1>;
1262 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1263 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1264 rockchip,grf = <&grf>;
1265 rockchip,cru = <&cru>;
1266 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1267 rockchip,isp,iommu-enable = <1>;
1268 iommus = <&isp_mmu>;
1269 status = "disabled";
1272 isp_mmu: iommu@ff914000 {
1273 compatible = "rockchip,iommu";
1274 reg = <0x0 0xff914000 0x0 0x100>,
1275 <0x0 0xff915000 0x0 0x100>;
1276 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1277 interrupt-names = "isp_mmu";
1278 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1279 clock-names = "aclk", "hclk";
1280 rk_iommu,disable_reset_quirk;
1282 power-domains = <&power RK3368_PD_VIO>;
1283 status = "disabled";
1287 compatible = "rockchip,rk3368-vop";
1288 reg = <0x0 0xff930000 0x0 0x2fc>;
1289 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1290 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1291 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1292 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1293 assigned-clock-rates = <400000000>, <200000000>;
1294 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1295 reset-names = "axi", "ahb", "dclk";
1296 power-domains = <&power RK3368_PD_VIO>;
1297 iommus = <&vop_mmu>;
1298 status = "disabled";
1301 #address-cells = <1>;
1304 vop_out_mipi: endpoint@0 {
1306 remote-endpoint = <&mipi_in_vop>;
1309 vop_out_edp: endpoint@1 {
1311 remote-endpoint = <&edp_in_vop>;
1316 display_subsystem: display-subsystem {
1317 compatible = "rockchip,display-subsystem";
1319 status = "disabled";
1322 vop_mmu: iommu@ff930300 {
1323 compatible = "rockchip,iommu";
1324 reg = <0x0 0xff930300 0x0 0x100>;
1325 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1326 interrupt-names = "vop_mmu";
1327 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1328 clock-names = "aclk", "hclk";
1329 power-domains = <&power RK3368_PD_VIO>;
1331 status = "disabled";
1334 mipi_dsi_host: mipi-dsi-host@ff960000 {
1335 compatible = "rockchip,rk3368-mipi-dsi";
1336 reg = <0x0 0xff960000 0x0 0x4000>;
1337 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1338 clocks = <&cru PCLK_MIPI_DSI0>;
1339 clock-names = "pclk";
1340 resets = <&cru SRST_MIPIDSI0>;
1341 reset-names = "apb";
1342 phys = <&mipi_dphy>;
1343 phy-names = "mipi_dphy";
1344 rockchip,grf = <&grf>;
1345 power-domains = <&power RK3368_PD_VIO>;
1346 #address-cells = <1>;
1348 status = "disabled";
1352 mipi_in_vop: endpoint {
1353 remote-endpoint = <&vop_out_mipi>;
1359 mipi_dphy: mipi-dphy@ff968000 {
1360 compatible = "rockchip,rk3368-mipi-dphy";
1361 reg = <0x0 0xff968000 0x0 0x4000>;
1363 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1364 clock-names = "ref", "pclk";
1365 resets = <&cru SRST_MIPIDPHYTX>;
1366 reset-names = "apb";
1367 status = "disabled";
1371 compatible = "rockchip,rk3368-edp";
1372 reg = <0x0 0xff970000 0x0 0x8000>;
1373 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1375 clock-names = "dp", "pclk";
1376 resets = <&cru SRST_EDP>;
1378 power-domains = <&power RK3368_PD_VIO>;
1379 rockchip,grf = <&grf>;
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&edp_hpd>;
1384 status = "disabled";
1387 #address-cells = <1>;
1393 edp_in_vop: endpoint {
1394 remote-endpoint = <&vop_out_edp>;
1400 hevc_mmu: iommu@ff9a0440 {
1401 compatible = "rockchip,iommu";
1402 reg = <0x0 0xff9a0440 0x0 0x40>,
1403 <0x0 0xff9a0480 0x0 0x40>;
1404 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1405 interrupt-names = "hevc_mmu";
1406 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1407 clock-names = "aclk", "hclk";
1408 power-domains = <&power RK3368_PD_VIDEO>;
1410 status = "disabled";
1413 vpu_mmu: iommu@ff9a0800 {
1414 compatible = "rockchip,iommu";
1415 reg = <0x0 0xff9a0800 0x0 0x100>;
1416 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1418 interrupt-names = "vepu_mmu", "vdpu_mmu";
1419 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1420 clock-names = "aclk", "hclk";
1421 power-domains = <&power RK3368_PD_VIDEO>;
1423 status = "disabled";
1427 compatible = "rockchip,vpu_sub";
1428 iommu_enabled = <1>;
1429 iommus = <&vpu_mmu>;
1430 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1431 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1432 interrupt-names = "irq_enc","irq_dec";
1434 name = "vpu_service";
1438 hevc: hevc_service {
1439 compatible = "rockchip,hevc_sub";
1440 iommu_enabled = <1>;
1441 iommus = <&hevc_mmu>;
1442 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1443 interrupt-names = "irq_dec";
1445 name = "hevc_service";
1449 vpu_combo: vpu_combo@ff9a0000 {
1450 compatible = "rockchip,vpu_combo";
1451 reg = <0x0 0xff9a0000 0x0 0x440>;
1452 rockchip,grf = <&grf>;
1454 rockchip,sub = <&vpu>, <&hevc>;
1455 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1456 <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1457 clock-names = "aclk_vcodec", "hclk_vcodec",
1458 "clk_core", "clk_cabac";
1459 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1461 reset-names = "video_a", "video_h", "video";
1463 mode_ctrl = <0x418>;
1465 power-domains = <&power RK3368_PD_VIDEO>;
1466 status = "disabled";
1469 gic: interrupt-controller@ffb71000 {
1470 compatible = "arm,gic-400";
1471 interrupt-controller;
1472 #interrupt-cells = <3>;
1473 #address-cells = <0>;
1475 reg = <0x0 0xffb71000 0x0 0x1000>,
1476 <0x0 0xffb72000 0x0 0x2000>,
1477 <0x0 0xffb74000 0x0 0x2000>,
1478 <0x0 0xffb76000 0x0 0x2000>;
1479 interrupts = <GIC_PPI 9
1480 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1483 gpu: rogue-g6110@ffa30000 {
1484 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1485 reg = <0x0 0xffa30000 0x0 0x10000>;
1487 <&cru SCLK_GPU_CORE>,
1488 <&cru ACLK_GPU_MEM>,
1489 <&cru ACLK_GPU_CFG>;
1494 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1495 interrupt-names = "rogue-g6110-irq";
1496 power-domains = <&power RK3368_PD_GPU_1>;
1497 operating-points-v2 = <&gpu_opp_table>;
1498 #cooling-cells = <2>; /* min followed by max */
1499 gpu_power_model: power_model {
1500 compatible = "arm,mali-simple-power-model";
1503 static-power = <300>;
1504 dynamic-power = <396>;
1505 ts = <32000 4700 (-80) 2>;
1506 thermal-zone = "gpu-thermal";
1510 gpu_opp_table: gpu_opp_table {
1511 compatible = "operating-points-v2";
1515 opp-hz = /bits/ 64 <200000000>;
1516 opp-microvolt = <1100000>;
1519 opp-hz = /bits/ 64 <288000000>;
1520 opp-microvolt = <1100000>;
1523 opp-hz = /bits/ 64 <400000000>;
1524 opp-microvolt = <1100000>;
1527 opp-hz = /bits/ 64 <576000000>;
1528 opp-microvolt = <1200000>;
1532 efuse: efuse@ffb00000 {
1533 compatible = "rockchip,rk3368-efuse";
1534 reg = <0x0 0xffb00000 0x0 0x20>;
1535 #address-cells = <1>;
1537 clocks = <&cru PCLK_EFUSE256>;
1538 clock-names = "pclk_efuse";
1541 cpu_leakage: cpu-leakage@17 {
1544 temp_adjust: temp-adjust@1f {
1550 compatible = "rockchip,rk3368-pinctrl";
1551 rockchip,grf = <&grf>;
1552 rockchip,pmu = <&pmugrf>;
1553 #address-cells = <0x2>;
1554 #size-cells = <0x2>;
1557 gpio0: gpio0@ff750000 {
1558 compatible = "rockchip,gpio-bank";
1559 reg = <0x0 0xff750000 0x0 0x100>;
1560 clocks = <&cru PCLK_GPIO0>;
1561 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1564 #gpio-cells = <0x2>;
1566 interrupt-controller;
1567 #interrupt-cells = <0x2>;
1570 gpio1: gpio1@ff780000 {
1571 compatible = "rockchip,gpio-bank";
1572 reg = <0x0 0xff780000 0x0 0x100>;
1573 clocks = <&cru PCLK_GPIO1>;
1574 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1577 #gpio-cells = <0x2>;
1579 interrupt-controller;
1580 #interrupt-cells = <0x2>;
1583 gpio2: gpio2@ff790000 {
1584 compatible = "rockchip,gpio-bank";
1585 reg = <0x0 0xff790000 0x0 0x100>;
1586 clocks = <&cru PCLK_GPIO2>;
1587 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1590 #gpio-cells = <0x2>;
1592 interrupt-controller;
1593 #interrupt-cells = <0x2>;
1596 gpio3: gpio3@ff7a0000 {
1597 compatible = "rockchip,gpio-bank";
1598 reg = <0x0 0xff7a0000 0x0 0x100>;
1599 clocks = <&cru PCLK_GPIO3>;
1600 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1603 #gpio-cells = <0x2>;
1605 interrupt-controller;
1606 #interrupt-cells = <0x2>;
1609 pcfg_pull_up: pcfg-pull-up {
1613 pcfg_pull_down: pcfg-pull-down {
1617 pcfg_pull_none: pcfg-pull-none {
1621 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1623 drive-strength = <12>;
1628 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1633 emmc_clk: emmc-clk {
1634 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1637 emmc_cmd: emmc-cmd {
1638 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1641 emmc_pwr: emmc-pwr {
1642 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1645 emmc_bus1: emmc-bus1 {
1646 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1649 emmc_bus4: emmc-bus4 {
1650 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1651 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1652 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1653 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1656 emmc_bus8: emmc-bus8 {
1657 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1658 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1659 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1660 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1661 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1662 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1663 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1664 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1669 rgmii_pins: rgmii-pins {
1670 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1671 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1672 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1673 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1674 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1675 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1676 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1677 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1678 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1679 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1680 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1681 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1682 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1683 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1684 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1687 rmii_pins: rmii-pins {
1688 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1689 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1690 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1691 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1692 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1693 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1694 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1695 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1696 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1697 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1702 i2c0_xfer: i2c0-xfer {
1703 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1704 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1709 i2c1_xfer: i2c1-xfer {
1710 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1711 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1716 i2c2_xfer: i2c2-xfer {
1717 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1718 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1723 i2c3_xfer: i2c3-xfer {
1724 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1725 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1730 i2c4_xfer: i2c4-xfer {
1731 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1732 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1737 i2c5_xfer: i2c5-xfer {
1738 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1739 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1744 i2s_8ch_bus: i2s-8ch-bus {
1745 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1746 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1747 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1748 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1749 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1750 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1751 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1752 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1753 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1758 pwm0_pin: pwm0-pin {
1759 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1762 vop_pwm_pin: vop-pwm {
1763 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1768 pwm1_pin: pwm1-pin {
1769 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1774 pwm3_pin: pwm3-pin {
1775 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1780 sdio0_bus1: sdio0-bus1 {
1781 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1784 sdio0_bus4: sdio0-bus4 {
1785 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1786 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1787 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1788 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1791 sdio0_cmd: sdio0-cmd {
1792 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1795 sdio0_clk: sdio0-clk {
1796 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1799 sdio0_cd: sdio0-cd {
1800 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1803 sdio0_wp: sdio0-wp {
1804 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1807 sdio0_pwr: sdio0-pwr {
1808 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1811 sdio0_bkpwr: sdio0-bkpwr {
1812 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1815 sdio0_int: sdio0-int {
1816 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1821 sdmmc_clk: sdmmc-clk {
1822 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1825 sdmmc_cmd: sdmmc-cmd {
1826 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1829 sdmmc_cd: sdmmc-cd {
1830 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1833 sdmmc_bus1: sdmmc-bus1 {
1834 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1837 sdmmc_bus4: sdmmc-bus4 {
1838 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1839 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1840 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1841 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1846 spi0_clk: spi0-clk {
1847 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1849 spi0_cs0: spi0-cs0 {
1850 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1852 spi0_cs1: spi0-cs1 {
1853 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1856 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1859 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1864 spi1_clk: spi1-clk {
1865 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1867 spi1_cs0: spi1-cs0 {
1868 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1870 spi1_cs1: spi1-cs1 {
1871 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1874 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1877 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1882 spi2_clk: spi2-clk {
1883 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1885 spi2_cs0: spi2-cs0 {
1886 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1889 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1892 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1897 uart0_xfer: uart0-xfer {
1898 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1899 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1902 uart0_cts: uart0-cts {
1903 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1906 uart0_rts: uart0-rts {
1907 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1912 uart1_xfer: uart1-xfer {
1913 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1914 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1917 uart1_cts: uart1-cts {
1918 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1921 uart1_rts: uart1-rts {
1922 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1927 uart2_xfer: uart2-xfer {
1928 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1929 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1931 /* no rts / cts for uart2 */
1935 uart3_xfer: uart3-xfer {
1936 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1937 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1940 uart3_cts: uart3-cts {
1941 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1944 uart3_rts: uart3-rts {
1945 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1950 uart4_xfer: uart4-xfer {
1951 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1952 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1955 uart4_cts: uart4-cts {
1956 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1959 uart4_rts: uart4-rts {
1960 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1965 cif_clkout: cif-clkout {
1966 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1969 isp_dvp_d2d9: isp-dvp-d2d9 {
1971 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1972 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1973 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1974 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1975 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1976 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1977 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1978 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1979 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1980 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1981 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1982 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1985 isp_dvp_d0d1: isp-dvp-d0d1 {
1987 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1988 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1991 isp_dvp_d10d11:isp_d10d11 {
1993 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1994 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1997 isp_dvp_d0d7: isp-dvp-d0d7 {
1999 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2000 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2001 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2002 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2003 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2004 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2005 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2006 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2009 isp_dvp_d4d11: isp-dvp-d4d11 {
2011 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2012 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2013 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2014 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2015 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2016 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2017 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2018 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2021 isp_shutter: isp-shutter {
2023 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2024 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2027 isp_flash_trigger: isp-flash-trigger {
2028 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2031 isp_prelight: isp-prelight {
2032 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2035 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2036 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU