arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3368";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_b0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_b1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_b2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_b3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_l0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_l1>;
 102                                 };
 103                                 core2 {
 104                                         cpu = <&cpu_l2>;
 105                                 };
 106                                 core3 {
 107                                         cpu = <&cpu_l3>;
 108                                 };
 109                         };
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 arm,psci-suspend-param = <0x1010000>;
 118                                 entry-latency-us = <0x3fffffff>;
 119                                 exit-latency-us = <0x40000000>;
 120                                 min-residency-us = <0xffffffff>;
 121                         };
 122                 };
 123
 124                 cpu_l0: cpu@0 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x0>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         operating-points-v2 = <&cluster1_opp>;
 132
 133                         #cooling-cells = <2>; /* min followed by max */
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster1_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster1_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster0_opp>;
 174
 175                         #cooling-cells = <2>; /* min followed by max */
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster0_opp>;
 186                 };
 187
 188                 cpu_b2: cpu@102 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x102>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster0_opp>;
 196                 };
 197
 198                 cpu_b3: cpu@103 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a53", "arm,armv8";
 201                         reg = <0x0 0x103>;
 202                         cpu-idle-states = <&cpu_sleep>;
 203                         enable-method = "psci";
 204                         clocks = <&cru ARMCLKB>;
 205                         operating-points-v2 = <&cluster0_opp>;
 206                 };
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <1200000>;
 216                         clock-latency-ns = <40000>;
 217                         opp-suspend;
 218                 };
 219                 opp@600000000 {
 220                         opp-hz = /bits/ 64 <600000000>;
 221                         opp-microvolt = <1200000>;
 222                 };
 223                 opp@816000000 {
 224                         opp-hz = /bits/ 64 <816000000>;
 225                         opp-microvolt = <1200000>;
 226                 };
 227                 opp@1008000000 {
 228                         opp-hz = /bits/ 64 <1008000000>;
 229                         opp-microvolt = <1200000>;
 230                 };
 231                 opp@1200000000 {
 232                         opp-hz = /bits/ 64 <1200000000>;
 233                         opp-microvolt = <1200000>;
 234                 };
 235         };
 236
 237         cluster1_opp: opp_table1 {
 238                 compatible = "operating-points-v2";
 239                 opp-shared;
 240
 241                 opp@408000000 {
 242                         opp-hz = /bits/ 64 <408000000>;
 243                         opp-microvolt = <1200000>;
 244                         clock-latency-ns = <40000>;
 245                         opp-suspend;
 246                 };
 247                 opp@600000000 {
 248                         opp-hz = /bits/ 64 <600000000>;
 249                         opp-microvolt = <1200000>;
 250                 };
 251                 opp@816000000 {
 252                         opp-hz = /bits/ 64 <816000000>;
 253                         opp-microvolt = <1200000>;
 254                 };
 255                 opp@1008000000 {
 256                         opp-hz = /bits/ 64 <1008000000>;
 257                         opp-microvolt = <1200000>;
 258                 };
 259         };
 260
 261         arm-pmu {
 262                 compatible = "arm,armv8-pmuv3";
 263                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 264                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 265                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 266                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 267                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 268                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 269                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 270                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 271                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 272                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 273                                      <&cpu_b2>, <&cpu_b3>;
 274         };
 275
 276         amba {
 277                 compatible = "arm,amba-bus";
 278                 #address-cells = <2>;
 279                 #size-cells = <2>;
 280                 ranges;
 281
 282                 dmac_peri: dma-controller@ff250000 {
 283                         compatible = "arm,pl330", "arm,primecell";
 284                         reg = <0x0 0xff250000 0x0 0x4000>;
 285                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 286                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 287                         #dma-cells = <1>;
 288                         clocks = <&cru ACLK_DMAC_PERI>;
 289                         clock-names = "apb_pclk";
 290                         arm,pl330-broken-no-flushp;
 291                         peripherals-req-type-burst;
 292                 };
 293
 294                 dmac_bus: dma-controller@ff600000 {
 295                         compatible = "arm,pl330", "arm,primecell";
 296                         reg = <0x0 0xff600000 0x0 0x4000>;
 297                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 298                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 299                         #dma-cells = <1>;
 300                         clocks = <&cru ACLK_DMAC_BUS>;
 301                         clock-names = "apb_pclk";
 302                         arm,pl330-broken-no-flushp;
 303                         peripherals-req-type-burst;
 304                 };
 305         };
 306
 307         psci {
 308                 compatible = "arm,psci-0.2";
 309                 method = "smc";
 310         };
 311
 312         timer {
 313                 compatible = "arm,armv8-timer";
 314                 interrupts = <GIC_PPI 13
 315                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 316                              <GIC_PPI 14
 317                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 318                              <GIC_PPI 11
 319                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 320                              <GIC_PPI 10
 321                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 322         };
 323
 324         xin24m: oscillator {
 325                 compatible = "fixed-clock";
 326                 clock-frequency = <24000000>;
 327                 clock-output-names = "xin24m";
 328                 #clock-cells = <0>;
 329         };
 330
 331         sdmmc: rksdmmc@ff0c0000 {
 332                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 333                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 334                 clock-freq-min-max = <400000 150000000>;
 335                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 336                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 337                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 338                 fifo-depth = <0x100>;
 339                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 340                 status = "disabled";
 341         };
 342
 343         sdio0: dwmmc@ff0d0000 {
 344                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 345                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 346                 clock-freq-min-max = <400000 150000000>;
 347                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 348                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 349                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 350                 fifo-depth = <0x100>;
 351                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 352                 status = "disabled";
 353         };
 354
 355         emmc: rksdmmc@ff0f0000 {
 356                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 357                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 358                 clock-freq-min-max = <400000 150000000>;
 359                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 360                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 361                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 362                 fifo-depth = <0x100>;
 363                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 364                 status = "disabled";
 365         };
 366
 367         saradc: saradc@ff100000 {
 368                 compatible = "rockchip,saradc";
 369                 reg = <0x0 0xff100000 0x0 0x100>;
 370                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 371                 #io-channel-cells = <1>;
 372                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 373                 clock-names = "saradc", "apb_pclk";
 374                 resets = <&cru SRST_SARADC>;
 375                 reset-names = "saradc-apb";
 376                 status = "disabled";
 377         };
 378
 379         spi0: spi@ff110000 {
 380                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 381                 reg = <0x0 0xff110000 0x0 0x1000>;
 382                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 383                 clock-names = "spiclk", "apb_pclk";
 384                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389                 status = "disabled";
 390         };
 391
 392         spi1: spi@ff120000 {
 393                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 394                 reg = <0x0 0xff120000 0x0 0x1000>;
 395                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 396                 clock-names = "spiclk", "apb_pclk";
 397                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 400                 #address-cells = <1>;
 401                 #size-cells = <0>;
 402                 status = "disabled";
 403         };
 404
 405         spi2: spi@ff130000 {
 406                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 407                 reg = <0x0 0xff130000 0x0 0x1000>;
 408                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 409                 clock-names = "spiclk", "apb_pclk";
 410                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 413                 #address-cells = <1>;
 414                 #size-cells = <0>;
 415                 status = "disabled";
 416         };
 417
 418         i2c0: i2c@ff650000 {
 419                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 420                 reg = <0x0 0xff650000 0x0 0x1000>;
 421                 clocks = <&cru PCLK_I2C0>;
 422                 clock-names = "i2c";
 423                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&i2c0_xfer>;
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 status = "disabled";
 429         };
 430
 431         i2c2: i2c@ff140000 {
 432                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 433                 reg = <0x0 0xff140000 0x0 0x1000>;
 434                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clock-names = "i2c";
 438                 clocks = <&cru PCLK_I2C2>;
 439                 pinctrl-names = "default";
 440                 pinctrl-0 = <&i2c2_xfer>;
 441                 status = "disabled";
 442         };
 443
 444         i2c3: i2c@ff150000 {
 445                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 446                 reg = <0x0 0xff150000 0x0 0x1000>;
 447                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 448                 #address-cells = <1>;
 449                 #size-cells = <0>;
 450                 clock-names = "i2c";
 451                 clocks = <&cru PCLK_I2C3>;
 452                 pinctrl-names = "default";
 453                 pinctrl-0 = <&i2c3_xfer>;
 454                 status = "disabled";
 455         };
 456
 457         i2c4: i2c@ff160000 {
 458                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 459                 reg = <0x0 0xff160000 0x0 0x1000>;
 460                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 461                 #address-cells = <1>;
 462                 #size-cells = <0>;
 463                 clock-names = "i2c";
 464                 clocks = <&cru PCLK_I2C4>;
 465                 pinctrl-names = "default";
 466                 pinctrl-0 = <&i2c4_xfer>;
 467                 status = "disabled";
 468         };
 469
 470         i2c5: i2c@ff170000 {
 471                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 472                 reg = <0x0 0xff170000 0x0 0x1000>;
 473                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 474                 #address-cells = <1>;
 475                 #size-cells = <0>;
 476                 clock-names = "i2c";
 477                 clocks = <&cru PCLK_I2C5>;
 478                 pinctrl-names = "default";
 479                 pinctrl-0 = <&i2c5_xfer>;
 480                 status = "disabled";
 481         };
 482
 483         uart0: serial@ff180000 {
 484                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 485                 reg = <0x0 0xff180000 0x0 0x100>;
 486                 clock-frequency = <24000000>;
 487                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 488                 clock-names = "baudclk", "apb_pclk";
 489                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 490                 reg-shift = <2>;
 491                 reg-io-width = <4>;
 492                 status = "disabled";
 493         };
 494
 495         uart1: serial@ff190000 {
 496                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 497                 reg = <0x0 0xff190000 0x0 0x100>;
 498                 clock-frequency = <24000000>;
 499                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 502                 reg-shift = <2>;
 503                 reg-io-width = <4>;
 504                 status = "disabled";
 505         };
 506
 507         uart3: serial@ff1b0000 {
 508                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 509                 reg = <0x0 0xff1b0000 0x0 0x100>;
 510                 clock-frequency = <24000000>;
 511                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 512                 clock-names = "baudclk", "apb_pclk";
 513                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 514                 reg-shift = <2>;
 515                 reg-io-width = <4>;
 516                 status = "disabled";
 517         };
 518
 519         uart4: serial@ff1c0000 {
 520                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 521                 reg = <0x0 0xff1c0000 0x0 0x100>;
 522                 clock-frequency = <24000000>;
 523                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 524                 clock-names = "baudclk", "apb_pclk";
 525                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 526                 reg-shift = <2>;
 527                 reg-io-width = <4>;
 528                 status = "disabled";
 529         };
 530
 531         thermal-zones {
 532                 cpu {
 533                         polling-delay-passive = <100>; /* milliseconds */
 534                         polling-delay = <5000>; /* milliseconds */
 535
 536                         thermal-sensors = <&tsadc 0>;
 537
 538                         trips {
 539                                 cpu_alert0: cpu_alert0 {
 540                                         temperature = <75000>; /* millicelsius */
 541                                         hysteresis = <2000>; /* millicelsius */
 542                                         type = "passive";
 543                                 };
 544                                 cpu_alert1: cpu_alert1 {
 545                                         temperature = <80000>; /* millicelsius */
 546                                         hysteresis = <2000>; /* millicelsius */
 547                                         type = "passive";
 548                                 };
 549                                 cpu_crit: cpu_crit {
 550                                         temperature = <95000>; /* millicelsius */
 551                                         hysteresis = <2000>; /* millicelsius */
 552                                         type = "critical";
 553                                 };
 554                         };
 555
 556                         cooling-maps {
 557                                 map0 {
 558                                         trip = <&cpu_alert0>;
 559                                         cooling-device =
 560                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 561                                 };
 562                                 map1 {
 563                                         trip = <&cpu_alert1>;
 564                                         cooling-device =
 565                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 566                                 };
 567                         };
 568                 };
 569
 570                 gpu {
 571                         polling-delay-passive = <100>; /* milliseconds */
 572                         polling-delay = <5000>; /* milliseconds */
 573
 574                         thermal-sensors = <&tsadc 1>;
 575
 576                         trips {
 577                                 gpu_alert0: gpu_alert0 {
 578                                         temperature = <80000>; /* millicelsius */
 579                                         hysteresis = <2000>; /* millicelsius */
 580                                         type = "passive";
 581                                 };
 582                                 gpu_crit: gpu_crit {
 583                                         temperature = <115000>; /* millicelsius */
 584                                         hysteresis = <2000>; /* millicelsius */
 585                                         type = "critical";
 586                                 };
 587                         };
 588
 589                         cooling-maps {
 590                                 map0 {
 591                                         trip = <&gpu_alert0>;
 592                                         cooling-device =
 593                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 594                                 };
 595                         };
 596                 };
 597         };
 598
 599         tsadc: tsadc@ff280000 {
 600                 compatible = "rockchip,rk3368-tsadc";
 601                 reg = <0x0 0xff280000 0x0 0x100>;
 602                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 603                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 604                 clock-names = "tsadc", "apb_pclk";
 605                 resets = <&cru SRST_TSADC>;
 606                 reset-names = "tsadc-apb";
 607                 pinctrl-names = "init", "default", "sleep";
 608                 pinctrl-0 = <&otp_gpio>;
 609                 pinctrl-1 = <&otp_out>;
 610                 pinctrl-2 = <&otp_gpio>;
 611                 #thermal-sensor-cells = <1>;
 612                 rockchip,hw-tshut-temp = <95000>;
 613                 status = "disabled";
 614         };
 615
 616         gmac: ethernet@ff290000 {
 617                 compatible = "rockchip,rk3368-gmac";
 618                 reg = <0x0 0xff290000 0x0 0x10000>;
 619                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 620                 interrupt-names = "macirq";
 621                 rockchip,grf = <&grf>;
 622                 clocks = <&cru SCLK_MAC>,
 623                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 624                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 625                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 626                 clock-names = "stmmaceth",
 627                         "mac_clk_rx", "mac_clk_tx",
 628                         "clk_mac_ref", "clk_mac_refout",
 629                         "aclk_mac", "pclk_mac";
 630                 status = "disabled";
 631         };
 632
 633         nandc0: nandc@ff400000 {
 634                 compatible = "rockchip,rk-nandc";
 635                 reg = <0x0 0xff400000 0x0 0x4000>;
 636                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 637                 nandc_id = <0>;
 638                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 639                 clock-names = "clk_nandc", "hclk_nandc";
 640                 status = "disabled";
 641         };
 642
 643         usb_host0_ehci: usb@ff500000 {
 644                 compatible = "generic-ehci";
 645                 reg = <0x0 0xff500000 0x0 0x100>;
 646                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 647                 clocks = <&cru HCLK_HOST0>;
 648                 clock-names = "usbhost";
 649                 status = "disabled";
 650         };
 651
 652         usb_otg: usb@ff580000 {
 653                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 654                                 "snps,dwc2";
 655                 reg = <0x0 0xff580000 0x0 0x40000>;
 656                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 657                 clocks = <&cru HCLK_OTG0>;
 658                 clock-names = "otg";
 659                 dr_mode = "otg";
 660                 g-np-tx-fifo-size = <16>;
 661                 g-rx-fifo-size = <275>;
 662                 g-tx-fifo-size = <256 128 128 64 64 32>;
 663                 g-use-dma;
 664                 status = "disabled";
 665         };
 666
 667         ddrpctl: syscon@ff610000 {
 668                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 669                 reg = <0x0 0xff610000 0x0 0x400>;
 670         };
 671
 672         i2c1: i2c@ff660000 {
 673                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 674                 reg = <0x0 0xff660000 0x0 0x1000>;
 675                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 676                 #address-cells = <1>;
 677                 #size-cells = <0>;
 678                 clock-names = "i2c";
 679                 clocks = <&cru PCLK_I2C1>;
 680                 pinctrl-names = "default";
 681                 pinctrl-0 = <&i2c1_xfer>;
 682                 status = "disabled";
 683         };
 684
 685         pwm0: pwm@ff680000 {
 686                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 687                 reg = <0x0 0xff680000 0x0 0x10>;
 688                 #pwm-cells = <3>;
 689                 pinctrl-names = "default";
 690                 pinctrl-0 = <&pwm0_pin>;
 691                 clocks = <&cru PCLK_PWM1>;
 692                 clock-names = "pwm";
 693                 status = "disabled";
 694         };
 695
 696         pwm1: pwm@ff680010 {
 697                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 698                 reg = <0x0 0xff680010 0x0 0x10>;
 699                 #pwm-cells = <3>;
 700                 pinctrl-names = "default";
 701                 pinctrl-0 = <&pwm1_pin>;
 702                 clocks = <&cru PCLK_PWM1>;
 703                 clock-names = "pwm";
 704                 status = "disabled";
 705         };
 706
 707         pwm2: pwm@ff680020 {
 708                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 709                 reg = <0x0 0xff680020 0x0 0x10>;
 710                 #pwm-cells = <3>;
 711                 clocks = <&cru PCLK_PWM1>;
 712                 clock-names = "pwm";
 713                 status = "disabled";
 714         };
 715
 716         pwm3: pwm@ff680030 {
 717                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 718                 reg = <0x0 0xff680030 0x0 0x10>;
 719                 #pwm-cells = <3>;
 720                 pinctrl-names = "default";
 721                 pinctrl-0 = <&pwm3_pin>;
 722                 clocks = <&cru PCLK_PWM1>;
 723                 clock-names = "pwm";
 724                 status = "disabled";
 725         };
 726
 727         uart2: serial@ff690000 {
 728                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 729                 reg = <0x0 0xff690000 0x0 0x100>;
 730                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 731                 clock-names = "baudclk", "apb_pclk";
 732                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 733                 pinctrl-names = "default";
 734                 pinctrl-0 = <&uart2_xfer>;
 735                 reg-shift = <2>;
 736                 reg-io-width = <4>;
 737                 status = "disabled";
 738         };
 739
 740         mbox: mbox@ff6b0000 {
 741                 compatible = "rockchip,rk3368-mailbox";
 742                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 743                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 744                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 745                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 746                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 747                 clocks = <&cru PCLK_MAILBOX>;
 748                 clock-names = "pclk_mailbox";
 749                 #mbox-cells = <1>;
 750                 status = "disabled";
 751         };
 752
 753         mailbox: mailbox@ff6b0000 {
 754                 compatible = "rockchip,rk3368-mbox-legacy";
 755                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 756                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 757                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 758                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 759                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 760                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 761                 clocks = <&cru PCLK_MAILBOX>;
 762                 clock-names = "pclk_mailbox";
 763                 #mbox-cells = <1>;
 764                 status = "disabled";
 765         };
 766
 767         mailbox_scpi: mailbox-scpi {
 768                 compatible = "rockchip,rk3368-scpi-legacy";
 769                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 770                 chan-nums = <3>;
 771                 status = "disabled";
 772         };
 773
 774         pmu: power-management@ff730000 {
 775                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 776                 reg = <0x0 0xff730000 0x0 0x1000>;
 777
 778                 power: power-controller {
 779                         status = "disabled";
 780                         compatible = "rockchip,rk3368-power-controller";
 781                         #power-domain-cells = <1>;
 782                         #address-cells = <1>;
 783                         #size-cells = <0>;
 784
 785                         /*
 786                          * Note: Although SCLK_* are the working clocks
 787                          * of device without including on the NOC, needed for
 788                          * synchronous reset.
 789                          *
 790                          * The clocks on the which NOC:
 791                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 792                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 793                          * ACLK_RGA is on ACLK_RGA_NIU.
 794                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 795                          *
 796                          * Which clock are device clocks:
 797                          *      clocks          devices
 798                          *      *_IEP           IEP:Image Enhancement Processor
 799                          *      *_ISP           ISP:Image Signal Processing
 800                          *      *_VIP           VIP:Video Input Processor
 801                          *      *_VOP*          VOP:Visual Output Processor
 802                          *      *_RGA           RGA
 803                          *      *_EDP*          EDP
 804                          *      *_DPHY*         LVDS
 805                          *      *_HDMI          HDMI
 806                          *      *_MIPI_*        MIPI
 807                          */
 808                         pd_vio {
 809                                 reg = <RK3368_PD_VIO>;
 810                                 clocks = <&cru ACLK_IEP>,
 811                                          <&cru ACLK_ISP>,
 812                                          <&cru ACLK_VIP>,
 813                                          <&cru ACLK_RGA>,
 814                                          <&cru ACLK_VOP>,
 815                                          <&cru ACLK_VOP_IEP>,
 816                                          <&cru DCLK_VOP>,
 817                                          <&cru HCLK_IEP>,
 818                                          <&cru HCLK_ISP>,
 819                                          <&cru HCLK_RGA>,
 820                                          <&cru HCLK_VIP>,
 821                                          <&cru HCLK_VOP>,
 822                                          <&cru HCLK_VIO_HDCPMMU>,
 823                                          <&cru PCLK_EDP_CTRL>,
 824                                          <&cru PCLK_HDMI_CTRL>,
 825                                          <&cru PCLK_HDCP>,
 826                                          <&cru PCLK_ISP>,
 827                                          <&cru PCLK_VIP>,
 828                                          <&cru PCLK_DPHYRX>,
 829                                          <&cru PCLK_DPHYTX0>,
 830                                          <&cru PCLK_MIPI_CSI>,
 831                                          <&cru PCLK_MIPI_DSI0>,
 832                                          <&cru SCLK_VOP0_PWM>,
 833                                          <&cru SCLK_EDP_24M>,
 834                                          <&cru SCLK_EDP>,
 835                                          <&cru SCLK_HDCP>,
 836                                          <&cru SCLK_ISP>,
 837                                          <&cru SCLK_RGA>,
 838                                          <&cru SCLK_HDMI_CEC>,
 839                                          <&cru SCLK_HDMI_HDCP>;
 840                         };
 841                         /*
 842                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 843                          * (video endecoder & decoder) clocks that on the
 844                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 845                          */
 846                         pd_video {
 847                                 reg = <RK3368_PD_VIDEO>;
 848                                 clocks = <&cru ACLK_VIDEO>,
 849                                          <&cru HCLK_VIDEO>,
 850                                          <&cru SCLK_HEVC_CABAC>,
 851                                          <&cru SCLK_HEVC_CORE>;
 852                         };
 853                         /*
 854                          * Note: ACLK_GPU is the GPU clock,
 855                          * and on the ACLK_GPU_NIU (NOC).
 856                          */
 857                         pd_gpu_1 {
 858                                 reg = <RK3368_PD_GPU_1>;
 859                                 clocks = <&cru ACLK_GPU_CFG>,
 860                                          <&cru ACLK_GPU_MEM>,
 861                                          <&cru SCLK_GPU_CORE>;
 862                         };
 863                 };
 864         };
 865
 866         pmugrf: syscon@ff738000 {
 867                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 868                 reg = <0x0 0xff738000 0x0 0x1000>;
 869
 870                 pmu_io_domains: io-domains {
 871                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 872                         status = "disabled";
 873                 };
 874
 875                 reboot-mode {
 876                         compatible = "syscon-reboot-mode";
 877                         offset = <0x200>;
 878                         mode-normal = <BOOT_NORMAL>;
 879                         mode-recovery = <BOOT_RECOVERY>;
 880                         mode-bootloader = <BOOT_FASTBOOT>;
 881                         mode-loader = <BOOT_BL_DOWNLOAD>;
 882                 };
 883         };
 884
 885         cru: clock-controller@ff760000 {
 886                 compatible = "rockchip,rk3368-cru";
 887                 reg = <0x0 0xff760000 0x0 0x1000>;
 888                 rockchip,grf = <&grf>;
 889                 #clock-cells = <1>;
 890                 #reset-cells = <1>;
 891                 assigned-clocks =
 892                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 893                         <&cru PLL_NPLL>,
 894                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 895                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 896                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 897                 assigned-clock-rates =
 898                         <576000000>, <400000000>,
 899                         <1188000000>,
 900                         <300000000>, <300000000>,
 901                         <150000000>, <150000000>,
 902                         <75000000>, <75000000>;
 903         };
 904
 905         grf: syscon@ff770000 {
 906                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 907                 reg = <0x0 0xff770000 0x0 0x1000>;
 908
 909                 io_domains: io-domains {
 910                         compatible = "rockchip,rk3368-io-voltage-domain";
 911                         status = "disabled";
 912                 };
 913         };
 914
 915         wdt: watchdog@ff800000 {
 916                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 917                 reg = <0x0 0xff800000 0x0 0x100>;
 918                 clocks = <&cru PCLK_WDT>;
 919                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 920                 status = "disabled";
 921         };
 922
 923         timer@ff810000 {
 924                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 925                 reg = <0x0 0xff810000 0x0 0x20>;
 926                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 927         };
 928
 929         i2s_2ch: i2s-2ch@ff890000 {
 930                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 931                 reg = <0x0 0xff890000 0x0 0x1000>;
 932                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 933                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 934                 dma-names = "tx", "rx";
 935                 clock-names = "i2s_clk", "i2s_hclk";
 936                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 937                 status = "disabled";
 938         };
 939
 940         i2s_8ch: i2s-8ch@ff898000 {
 941                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 942                 reg = <0x0 0xff898000 0x0 0x1000>;
 943                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 944                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 945                 dma-names = "tx", "rx";
 946                 clock-names = "i2s_clk", "i2s_hclk";
 947                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 948                 pinctrl-names = "default";
 949                 pinctrl-0 = <&i2s_8ch_bus>;
 950                 status = "disabled";
 951         };
 952
 953         gic: interrupt-controller@ffb71000 {
 954                 compatible = "arm,gic-400";
 955                 interrupt-controller;
 956                 #interrupt-cells = <3>;
 957                 #address-cells = <0>;
 958
 959                 reg = <0x0 0xffb71000 0x0 0x1000>,
 960                       <0x0 0xffb72000 0x0 0x2000>,
 961                       <0x0 0xffb74000 0x0 0x2000>,
 962                       <0x0 0xffb76000 0x0 0x2000>;
 963                 interrupts = <GIC_PPI 9
 964                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 965         };
 966
 967         gpu: rogue-g6110@ffa30000 {
 968                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
 969                 reg = <0x0 0xffa30000 0x0 0x10000>;
 970                 clocks =
 971                         <&cru SCLK_GPU_CORE>,
 972                         <&cru ACLK_GPU_MEM>,
 973                         <&cru ACLK_GPU_CFG>;
 974                 clock-names =
 975                         "sclk_gpu_core",
 976                         "aclk_gpu_mem",
 977                         "aclk_gpu_cfg";
 978                 operating-points = <
 979                         /* KHz uV */
 980                         200000 1100000
 981                         288000 1100000
 982                         400000 1150000
 983                         576000 1200000
 984                 >;
 985                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 986                 interrupt-names = "rogue-g6110-irq";
 987         };
 988
 989         efuse: efuse@ffb00000 {
 990                 compatible = "rockchip,rk3368-efuse";
 991                 reg = <0x0 0xffb00000 0x0 0x20>;
 992                 #address-cells = <1>;
 993                 #size-cells = <1>;
 994                 clocks = <&cru PCLK_EFUSE256>;
 995                 clock-names = "pclk_efuse";
 996
 997                 /* Data cells */
 998                 cpu_leakage: cpu-leakage@17 {
 999                         reg = <0x17 0x1>;
1000                 };
1001                 temp_adjust: temp-adjust@1f {
1002                         reg = <0x1f 0x1>;
1003                 };
1004         };
1005
1006         pinctrl: pinctrl {
1007                 compatible = "rockchip,rk3368-pinctrl";
1008                 rockchip,grf = <&grf>;
1009                 rockchip,pmu = <&pmugrf>;
1010                 #address-cells = <0x2>;
1011                 #size-cells = <0x2>;
1012                 ranges;
1013
1014                 gpio0: gpio0@ff750000 {
1015                         compatible = "rockchip,gpio-bank";
1016                         reg = <0x0 0xff750000 0x0 0x100>;
1017                         clocks = <&cru PCLK_GPIO0>;
1018                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1019
1020                         gpio-controller;
1021                         #gpio-cells = <0x2>;
1022
1023                         interrupt-controller;
1024                         #interrupt-cells = <0x2>;
1025                 };
1026
1027                 gpio1: gpio1@ff780000 {
1028                         compatible = "rockchip,gpio-bank";
1029                         reg = <0x0 0xff780000 0x0 0x100>;
1030                         clocks = <&cru PCLK_GPIO1>;
1031                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1032
1033                         gpio-controller;
1034                         #gpio-cells = <0x2>;
1035
1036                         interrupt-controller;
1037                         #interrupt-cells = <0x2>;
1038                 };
1039
1040                 gpio2: gpio2@ff790000 {
1041                         compatible = "rockchip,gpio-bank";
1042                         reg = <0x0 0xff790000 0x0 0x100>;
1043                         clocks = <&cru PCLK_GPIO2>;
1044                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1045
1046                         gpio-controller;
1047                         #gpio-cells = <0x2>;
1048
1049                         interrupt-controller;
1050                         #interrupt-cells = <0x2>;
1051                 };
1052
1053                 gpio3: gpio3@ff7a0000 {
1054                         compatible = "rockchip,gpio-bank";
1055                         reg = <0x0 0xff7a0000 0x0 0x100>;
1056                         clocks = <&cru PCLK_GPIO3>;
1057                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1058
1059                         gpio-controller;
1060                         #gpio-cells = <0x2>;
1061
1062                         interrupt-controller;
1063                         #interrupt-cells = <0x2>;
1064                 };
1065
1066                 pcfg_pull_up: pcfg-pull-up {
1067                         bias-pull-up;
1068                 };
1069
1070                 pcfg_pull_down: pcfg-pull-down {
1071                         bias-pull-down;
1072                 };
1073
1074                 pcfg_pull_none: pcfg-pull-none {
1075                         bias-disable;
1076                 };
1077
1078                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1079                         bias-disable;
1080                         drive-strength = <12>;
1081                 };
1082
1083                 emmc {
1084                         emmc_clk: emmc-clk {
1085                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1086                         };
1087
1088                         emmc_cmd: emmc-cmd {
1089                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1090                         };
1091
1092                         emmc_pwr: emmc-pwr {
1093                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1094                         };
1095
1096                         emmc_bus1: emmc-bus1 {
1097                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1098                         };
1099
1100                         emmc_bus4: emmc-bus4 {
1101                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1102                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1103                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1104                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1105                         };
1106
1107                         emmc_bus8: emmc-bus8 {
1108                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1109                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1110                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1111                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1112                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1113                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1114                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1115                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1116                         };
1117                 };
1118
1119                 gmac {
1120                         rgmii_pins: rgmii-pins {
1121                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1122                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1123                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1124                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1125                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1126                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1127                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1128                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1129                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1130                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1131                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1132                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1133                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1134                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1135                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1136                         };
1137
1138                         rmii_pins: rmii-pins {
1139                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1140                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1141                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1142                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1143                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1144                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1145                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1146                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1147                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1148                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1149                         };
1150                 };
1151
1152                 i2c0 {
1153                         i2c0_xfer: i2c0-xfer {
1154                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1155                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1156                         };
1157                 };
1158
1159                 i2c1 {
1160                         i2c1_xfer: i2c1-xfer {
1161                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1162                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1163                         };
1164                 };
1165
1166                 i2c2 {
1167                         i2c2_xfer: i2c2-xfer {
1168                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1169                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1170                         };
1171                 };
1172
1173                 i2c3 {
1174                         i2c3_xfer: i2c3-xfer {
1175                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1176                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1177                         };
1178                 };
1179
1180                 i2c4 {
1181                         i2c4_xfer: i2c4-xfer {
1182                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1183                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1184                         };
1185                 };
1186
1187                 i2c5 {
1188                         i2c5_xfer: i2c5-xfer {
1189                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1190                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1191                         };
1192                 };
1193
1194                 i2s {
1195                         i2s_8ch_bus: i2s-8ch-bus {
1196                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1197                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1198                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1199                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1200                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1201                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1202                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1203                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1204                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1205                         };
1206                 };
1207
1208                 pwm0 {
1209                         pwm0_pin: pwm0-pin {
1210                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1211                         };
1212
1213                         vop_pwm_pin: vop-pwm {
1214                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1215                         };
1216                 };
1217
1218                 pwm1 {
1219                         pwm1_pin: pwm1-pin {
1220                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1221                         };
1222                 };
1223
1224                 pwm3 {
1225                         pwm3_pin: pwm3-pin {
1226                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 sdio0 {
1231                         sdio0_bus1: sdio0-bus1 {
1232                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1233                         };
1234
1235                         sdio0_bus4: sdio0-bus4 {
1236                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1237                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1238                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1239                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1240                         };
1241
1242                         sdio0_cmd: sdio0-cmd {
1243                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1244                         };
1245
1246                         sdio0_clk: sdio0-clk {
1247                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1248                         };
1249
1250                         sdio0_cd: sdio0-cd {
1251                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1252                         };
1253
1254                         sdio0_wp: sdio0-wp {
1255                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1256                         };
1257
1258                         sdio0_pwr: sdio0-pwr {
1259                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1260                         };
1261
1262                         sdio0_bkpwr: sdio0-bkpwr {
1263                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1264                         };
1265
1266                         sdio0_int: sdio0-int {
1267                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1268                         };
1269                 };
1270
1271                 sdmmc {
1272                         sdmmc_clk: sdmmc-clk {
1273                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1274                         };
1275
1276                         sdmmc_cmd: sdmmc-cmd {
1277                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1278                         };
1279
1280                         sdmmc_cd: sdmmc-cd {
1281                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1282                         };
1283
1284                         sdmmc_bus1: sdmmc-bus1 {
1285                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1286                         };
1287
1288                         sdmmc_bus4: sdmmc-bus4 {
1289                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1290                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1291                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1292                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1293                         };
1294                 };
1295
1296                 spi0 {
1297                         spi0_clk: spi0-clk {
1298                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1299                         };
1300                         spi0_cs0: spi0-cs0 {
1301                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1302                         };
1303                         spi0_cs1: spi0-cs1 {
1304                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1305                         };
1306                         spi0_tx: spi0-tx {
1307                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1308                         };
1309                         spi0_rx: spi0-rx {
1310                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1311                         };
1312                 };
1313
1314                 spi1 {
1315                         spi1_clk: spi1-clk {
1316                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1317                         };
1318                         spi1_cs0: spi1-cs0 {
1319                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1320                         };
1321                         spi1_cs1: spi1-cs1 {
1322                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1323                         };
1324                         spi1_rx: spi1-rx {
1325                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1326                         };
1327                         spi1_tx: spi1-tx {
1328                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1329                         };
1330                 };
1331
1332                 spi2 {
1333                         spi2_clk: spi2-clk {
1334                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1335                         };
1336                         spi2_cs0: spi2-cs0 {
1337                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1338                         };
1339                         spi2_rx: spi2-rx {
1340                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1341                         };
1342                         spi2_tx: spi2-tx {
1343                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1344                         };
1345                 };
1346
1347                 tsadc {
1348                         otp_gpio: otp-gpio {
1349                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1350                         };
1351
1352                         otp_out: otp-out {
1353                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1354                         };
1355                 };
1356
1357                 uart0 {
1358                         uart0_xfer: uart0-xfer {
1359                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1360                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1361                         };
1362
1363                         uart0_cts: uart0-cts {
1364                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1365                         };
1366
1367                         uart0_rts: uart0-rts {
1368                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370                 };
1371
1372                 uart1 {
1373                         uart1_xfer: uart1-xfer {
1374                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1375                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1376                         };
1377
1378                         uart1_cts: uart1-cts {
1379                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1380                         };
1381
1382                         uart1_rts: uart1-rts {
1383                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1384                         };
1385                 };
1386
1387                 uart2 {
1388                         uart2_xfer: uart2-xfer {
1389                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1390                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1391                         };
1392                         /* no rts / cts for uart2 */
1393                 };
1394
1395                 uart3 {
1396                         uart3_xfer: uart3-xfer {
1397                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1398                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1399                         };
1400
1401                         uart3_cts: uart3-cts {
1402                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1403                         };
1404
1405                         uart3_rts: uart3-rts {
1406                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1407                         };
1408                 };
1409
1410                 uart4 {
1411                         uart4_xfer: uart4-xfer {
1412                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1413                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1414                         };
1415
1416                         uart4_cts: uart4-cts {
1417                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1418                         };
1419
1420                         uart4_rts: uart4-rts {
1421                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1422                         };
1423                 };
1424         };
1425 };