arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 idle-states {
 116                         entry-method = "psci";
 117
 118                         cpu_sleep: cpu-sleep-0 {
 119                                 compatible = "arm,idle-state";
 120                                 arm,psci-suspend-param = <0x1010000>;
 121                                 entry-latency-us = <0x3fffffff>;
 122                                 exit-latency-us = <0x40000000>;
 123                                 min-residency-us = <0xffffffff>;
 124                         };
 125                 };
 126
 127                 cpu_l0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x0>;
 131                         cpu-idle-states = <&cpu_sleep>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         operating-points-v2 = <&cluster0_opp>;
 135                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 136                         #cooling-cells = <2>; /* min followed by max */
 137                         dynamic-power-coefficient = <149>;
 138                 };
 139
 140                 cpu_l1: cpu@1 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a53", "arm,armv8";
 143                         reg = <0x0 0x1>;
 144                         cpu-idle-states = <&cpu_sleep>;
 145                         enable-method = "psci";
 146                         clocks = <&cru ARMCLKL>;
 147                         operating-points-v2 = <&cluster0_opp>;
 148                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 149                 };
 150
 151                 cpu_l2: cpu@2 {
 152                         device_type = "cpu";
 153                         compatible = "arm,cortex-a53", "arm,armv8";
 154                         reg = <0x0 0x2>;
 155                         cpu-idle-states = <&cpu_sleep>;
 156                         enable-method = "psci";
 157                         clocks = <&cru ARMCLKL>;
 158                         operating-points-v2 = <&cluster0_opp>;
 159                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 160                 };
 161
 162                 cpu_l3: cpu@3 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a53", "arm,armv8";
 165                         reg = <0x0 0x3>;
 166                         cpu-idle-states = <&cpu_sleep>;
 167                         enable-method = "psci";
 168                         clocks = <&cru ARMCLKL>;
 169                         operating-points-v2 = <&cluster0_opp>;
 170                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 171                 };
 172
 173                 cpu_b0: cpu@100 {
 174                         device_type = "cpu";
 175                         compatible = "arm,cortex-a53", "arm,armv8";
 176                         reg = <0x0 0x100>;
 177                         cpu-idle-states = <&cpu_sleep>;
 178                         enable-method = "psci";
 179                         clocks = <&cru ARMCLKB>;
 180                         operating-points-v2 = <&cluster1_opp>;
 181                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 182                         #cooling-cells = <2>; /* min followed by max */
 183                         dynamic-power-coefficient = <160>;
 184                 };
 185
 186                 cpu_b1: cpu@101 {
 187                         device_type = "cpu";
 188                         compatible = "arm,cortex-a53", "arm,armv8";
 189                         reg = <0x0 0x101>;
 190                         cpu-idle-states = <&cpu_sleep>;
 191                         enable-method = "psci";
 192                         clocks = <&cru ARMCLKB>;
 193                         operating-points-v2 = <&cluster1_opp>;
 194                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 195                 };
 196
 197                 cpu_b2: cpu@102 {
 198                         device_type = "cpu";
 199                         compatible = "arm,cortex-a53", "arm,armv8";
 200                         reg = <0x0 0x102>;
 201                         cpu-idle-states = <&cpu_sleep>;
 202                         enable-method = "psci";
 203                         clocks = <&cru ARMCLKB>;
 204                         operating-points-v2 = <&cluster1_opp>;
 205                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 206                 };
 207
 208                 cpu_b3: cpu@103 {
 209                         device_type = "cpu";
 210                         compatible = "arm,cortex-a53", "arm,armv8";
 211                         reg = <0x0 0x103>;
 212                         cpu-idle-states = <&cpu_sleep>;
 213                         enable-method = "psci";
 214                         clocks = <&cru ARMCLKB>;
 215                         operating-points-v2 = <&cluster1_opp>;
 216                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 217                 };
 218         };
 219
 220         cluster0_opp: opp_table0 {
 221                 compatible = "operating-points-v2";
 222                 opp-shared;
 223
 224                 opp@216000000 {
 225                         opp-hz = /bits/ 64 <216000000>;
 226                         opp-microvolt = <950000 950000 1350000>;
 227                         clock-latency-ns = <40000>;
 228                         opp-suspend;
 229                 };
 230                 opp@408000000 {
 231                         opp-hz = /bits/ 64 <408000000>;
 232                         opp-microvolt = <950000 950000 1350000>;
 233                         clock-latency-ns = <40000>;
 234                 };
 235                 opp@600000000 {
 236                         opp-hz = /bits/ 64 <600000000>;
 237                         opp-microvolt = <950000 950000 1350000>;
 238                         clock-latency-ns = <40000>;
 239                 };
 240                 opp@816000000 {
 241                         opp-hz = /bits/ 64 <816000000>;
 242                         opp-microvolt = <1025000 1025000 1350000>;
 243                         clock-latency-ns = <40000>;
 244                 };
 245                 opp@1008000000 {
 246                         opp-hz = /bits/ 64 <1008000000>;
 247                         opp-microvolt = <1125000 1125000 1350000>;
 248                         clock-latency-ns = <40000>;
 249                 };
 250                 opp@1200000000 {
 251                         opp-hz = /bits/ 64 <1200000000>;
 252                         opp-microvolt = <1225000 1225000 1350000>;
 253                         clock-latency-ns = <40000>;
 254                 };
 255         };
 256
 257         cluster1_opp: opp_table1 {
 258                 compatible = "operating-points-v2";
 259                 opp-shared;
 260
 261                 opp@216000000 {
 262                         opp-hz = /bits/ 64 <216000000>;
 263                         opp-microvolt = <950000 950000 1350000>;
 264                         clock-latency-ns = <40000>;
 265                         opp-suspend;
 266                 };
 267                 opp@408000000 {
 268                         opp-hz = /bits/ 64 <408000000>;
 269                         opp-microvolt = <950000 950000 1350000>;
 270                         clock-latency-ns = <40000>;
 271                 };
 272                 opp@600000000 {
 273                         opp-hz = /bits/ 64 <600000000>;
 274                         opp-microvolt = <950000 950000 1350000>;
 275                         clock-latency-ns = <40000>;
 276                 };
 277                 opp@816000000 {
 278                         opp-hz = /bits/ 64 <816000000>;
 279                         opp-microvolt = <975000 975000 1350000>;
 280                         clock-latency-ns = <40000>;
 281                 };
 282                 opp@1008000000 {
 283                         opp-hz = /bits/ 64 <1008000000>;
 284                         opp-microvolt = <1050000 1050000 1350000>;
 285                         clock-latency-ns = <40000>;
 286                 };
 287                 opp@1200000000 {
 288                         opp-hz = /bits/ 64 <1200000000>;
 289                         opp-microvolt = <1150000 1150000 1350000>;
 290                         clock-latency-ns = <40000>;
 291                 };
 292                 opp@1296000000 {
 293                         opp-hz = /bits/ 64 <1296000000>;
 294                         opp-microvolt = <1225000 1225000 1350000>;
 295                         clock-latency-ns = <40000>;
 296                 };
 297                 opp@1416000000 {
 298                         opp-hz = /bits/ 64 <1416000000>;
 299                         opp-microvolt = <1300000 1300000 1350000>;
 300                         clock-latency-ns = <40000>;
 301                 };
 302                 opp@1512000000 {
 303                         opp-hz = /bits/ 64 <1512000000>;
 304                         opp-microvolt = <1350000 1350000 1350000>;
 305                         clock-latency-ns = <40000>;
 306                 };
 307         };
 308
 309         energy-costs {
 310                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 311                         busy-cost-data = <
 312                                 146    44       /*  216M */
 313                                 276    72       /*  408M */
 314                                 406    99       /*  600M */
 315                                 552    147      /*  816M */
 316                                 682    200      /* 1008M */
 317                                 812    255      /* 1200M */
 318                         >;
 319                         idle-cost-data = <
 320                                   6
 321                                   6
 322                                   0
 323                         >;
 324                 };
 325
 326                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 327                         busy-cost-data = <
 328                                 146    53       /*  216M */
 329                                 276    86       /*  408M */
 330                                 406    118      /*  600M */
 331                                 552    166      /*  816M */
 332                                 682    226      /* 1008M */
 333                                 812    309      /* 1200M */
 334                                 878    371      /* 1200M */
 335                                 959    446      /* 1416M */
 336                                 1024   513      /* 1512M */
 337                         >;
 338                         idle-cost-data = <
 339                                    6
 340                                    6
 341                                    0
 342                         >;
 343                 };
 344
 345                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 346                         busy-cost-data = <
 347                                 146    9        /*  216M */
 348                                 276    14       /*  408M */
 349                                 406    20       /*  600M */
 350                                 552    29       /*  816M */
 351                                 682    40       /* 1008M */
 352                                 812    51       /* 1200M */
 353                         >;
 354                         idle-cost-data = <
 355                                 56
 356                                 56
 357                                 56
 358                         >;
 359                 };
 360
 361                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 362                         busy-cost-data = <
 363                                 146    11       /*  216M */
 364                                 276    17       /*  408M */
 365                                 406    24       /*  600M */
 366                                 552    33       /*  816M */
 367                                 682    45       /* 1008M */
 368                                 812    62       /* 1200M */
 369                                 878    74       /* 1200M */
 370                                 959    89       /* 1416M */
 371                                 1024   103      /* 1512M */
 372                         >;
 373                         idle-cost-data = <
 374                                 56
 375                                 56
 376                                 56
 377                         >;
 378                 };
 379         };
 380
 381         cpu_avs: cpu-avs {
 382                 cluster0-avs {
 383                         cluster-id = <0>;
 384                         min-volt = <950000>; /* uV */
 385                         min-freq = <216000>; /* KHz */
 386                         leakage-adjust-volt = <
 387                         /*  mA        mA         uV */
 388                             0         254        0
 389                         >;
 390                         nvmem-cells = <&cpu_leakage>;
 391                         nvmem-cell-names = "cpu_leakage";
 392                 };
 393                 cluster1-avs {
 394                         cluster-id = <1>;
 395                         min-volt = <950000>; /* uV */
 396                         min-freq = <216000>; /* KHz */
 397                         leakage-adjust-volt = <
 398                         /*  mA        mA         uV */
 399                             0         254        0
 400                         >;
 401                         nvmem-cells = <&cpu_leakage>;
 402                         nvmem-cell-names = "cpu_leakage";
 403                 };
 404         };
 405
 406         arm-pmu {
 407                 compatible = "arm,armv8-pmuv3";
 408                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 409                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 410                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 411                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 412                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 413                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 414                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 415                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 416                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 417                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 418                                      <&cpu_b2>, <&cpu_b3>;
 419         };
 420
 421         amba {
 422                 compatible = "arm,amba-bus";
 423                 #address-cells = <2>;
 424                 #size-cells = <2>;
 425                 ranges;
 426
 427                 dmac_peri: dma-controller@ff250000 {
 428                         compatible = "arm,pl330", "arm,primecell";
 429                         reg = <0x0 0xff250000 0x0 0x4000>;
 430                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 431                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 432                         #dma-cells = <1>;
 433                         clocks = <&cru ACLK_DMAC_PERI>;
 434                         clock-names = "apb_pclk";
 435                         arm,pl330-broken-no-flushp;
 436                         peripherals-req-type-burst;
 437                 };
 438
 439                 dmac_bus: dma-controller@ff600000 {
 440                         compatible = "arm,pl330", "arm,primecell";
 441                         reg = <0x0 0xff600000 0x0 0x4000>;
 442                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 443                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 444                         #dma-cells = <1>;
 445                         clocks = <&cru ACLK_DMAC_BUS>;
 446                         clock-names = "apb_pclk";
 447                         arm,pl330-broken-no-flushp;
 448                         peripherals-req-type-burst;
 449                 };
 450         };
 451
 452         psci {
 453                 compatible = "arm,psci-0.2";
 454                 method = "smc";
 455         };
 456
 457         timer {
 458                 compatible = "arm,armv8-timer";
 459                 interrupts = <GIC_PPI 13
 460                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 461                              <GIC_PPI 14
 462                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 463                              <GIC_PPI 11
 464                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 465                              <GIC_PPI 10
 466                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 467         };
 468
 469         xin24m: oscillator {
 470                 compatible = "fixed-clock";
 471                 clock-frequency = <24000000>;
 472                 clock-output-names = "xin24m";
 473                 #clock-cells = <0>;
 474         };
 475
 476         xin32k: xin32k {
 477                 compatible = "fixed-clock";
 478                 clock-frequency = <32768>;
 479                 clock-output-names = "xin32k";
 480                 #clock-cells = <0>;
 481         };
 482
 483         sdmmc: dwmmc@ff0c0000 {
 484                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 485                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 486                 clock-freq-min-max = <400000 150000000>;
 487                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 488                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 489                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 490                 fifo-depth = <0x100>;
 491                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 492                 status = "disabled";
 493         };
 494
 495         sdio0: dwmmc@ff0d0000 {
 496                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 497                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 498                 clock-freq-min-max = <400000 150000000>;
 499                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 500                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 501                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 502                 fifo-depth = <0x100>;
 503                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 504                 status = "disabled";
 505         };
 506
 507         emmc: dwmmc@ff0f0000 {
 508                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 509                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 510                 clock-freq-min-max = <400000 150000000>;
 511                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 512                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 513                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 514                 fifo-depth = <0x100>;
 515                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 516                 status = "disabled";
 517         };
 518
 519         saradc: saradc@ff100000 {
 520                 compatible = "rockchip,saradc";
 521                 reg = <0x0 0xff100000 0x0 0x100>;
 522                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 523                 #io-channel-cells = <1>;
 524                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 525                 clock-names = "saradc", "apb_pclk";
 526                 resets = <&cru SRST_SARADC>;
 527                 reset-names = "saradc-apb";
 528                 status = "disabled";
 529         };
 530
 531         spi0: spi@ff110000 {
 532                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 533                 reg = <0x0 0xff110000 0x0 0x1000>;
 534                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 535                 clock-names = "spiclk", "apb_pclk";
 536                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 539                 #address-cells = <1>;
 540                 #size-cells = <0>;
 541                 status = "disabled";
 542         };
 543
 544         spi1: spi@ff120000 {
 545                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 546                 reg = <0x0 0xff120000 0x0 0x1000>;
 547                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 548                 clock-names = "spiclk", "apb_pclk";
 549                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 550                 pinctrl-names = "default";
 551                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 552                 #address-cells = <1>;
 553                 #size-cells = <0>;
 554                 status = "disabled";
 555         };
 556
 557         spi2: spi@ff130000 {
 558                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 559                 reg = <0x0 0xff130000 0x0 0x1000>;
 560                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 561                 clock-names = "spiclk", "apb_pclk";
 562                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 563                 pinctrl-names = "default";
 564                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 565                 #address-cells = <1>;
 566                 #size-cells = <0>;
 567                 status = "disabled";
 568         };
 569
 570         i2c0: i2c@ff650000 {
 571                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 572                 reg = <0x0 0xff650000 0x0 0x1000>;
 573                 clocks = <&cru PCLK_I2C0>;
 574                 clock-names = "i2c";
 575                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&i2c0_xfer>;
 578                 #address-cells = <1>;
 579                 #size-cells = <0>;
 580                 status = "disabled";
 581         };
 582
 583         i2c2: i2c@ff140000 {
 584                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 585                 reg = <0x0 0xff140000 0x0 0x1000>;
 586                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 587                 #address-cells = <1>;
 588                 #size-cells = <0>;
 589                 clock-names = "i2c";
 590                 clocks = <&cru PCLK_I2C2>;
 591                 pinctrl-names = "default";
 592                 pinctrl-0 = <&i2c2_xfer>;
 593                 status = "disabled";
 594         };
 595
 596         i2c3: i2c@ff150000 {
 597                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 598                 reg = <0x0 0xff150000 0x0 0x1000>;
 599                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 600                 #address-cells = <1>;
 601                 #size-cells = <0>;
 602                 clock-names = "i2c";
 603                 clocks = <&cru PCLK_I2C3>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&i2c3_xfer>;
 606                 status = "disabled";
 607         };
 608
 609         i2c4: i2c@ff160000 {
 610                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 611                 reg = <0x0 0xff160000 0x0 0x1000>;
 612                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 clock-names = "i2c";
 616                 clocks = <&cru PCLK_I2C4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&i2c4_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         i2c5: i2c@ff170000 {
 623                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 624                 reg = <0x0 0xff170000 0x0 0x1000>;
 625                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 626                 #address-cells = <1>;
 627                 #size-cells = <0>;
 628                 clock-names = "i2c";
 629                 clocks = <&cru PCLK_I2C5>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&i2c5_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart0: serial@ff180000 {
 636                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff180000 0x0 0x100>;
 638                 clock-frequency = <24000000>;
 639                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 640                 clock-names = "baudclk", "apb_pclk";
 641                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 642                 reg-shift = <2>;
 643                 reg-io-width = <4>;
 644                 status = "disabled";
 645         };
 646
 647         uart1: serial@ff190000 {
 648                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 649                 reg = <0x0 0xff190000 0x0 0x100>;
 650                 clock-frequency = <24000000>;
 651                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 status = "disabled";
 657         };
 658
 659         uart3: serial@ff1b0000 {
 660                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 661                 reg = <0x0 0xff1b0000 0x0 0x100>;
 662                 clock-frequency = <24000000>;
 663                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 664                 clock-names = "baudclk", "apb_pclk";
 665                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 666                 reg-shift = <2>;
 667                 reg-io-width = <4>;
 668                 status = "disabled";
 669         };
 670
 671         uart4: serial@ff1c0000 {
 672                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 673                 reg = <0x0 0xff1c0000 0x0 0x100>;
 674                 clock-frequency = <24000000>;
 675                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 676                 clock-names = "baudclk", "apb_pclk";
 677                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 678                 reg-shift = <2>;
 679                 reg-io-width = <4>;
 680                 status = "disabled";
 681         };
 682
 683         thermal_zones: thermal-zones {
 684                 soc_thermal: soc-thermal {
 685                         polling-delay-passive = <200>; /* milliseconds */
 686                         polling-delay = <200>; /* milliseconds */
 687                         sustainable-power = <600>; /* milliwatts */
 688
 689                         thermal-sensors = <&tsadc 0>;
 690                         trips {
 691                                 threshold: trip-point@0 {
 692                                         temperature = <70000>; /* millicelsius */
 693                                         hysteresis = <2000>; /* millicelsius */
 694                                         type = "passive";
 695                                 };
 696                                 target: trip-point@1 {
 697                                         temperature = <80000>; /* millicelsius */
 698                                         hysteresis = <2000>; /* millicelsius */
 699                                         type = "passive";
 700                                 };
 701                                 soc_crit: soc-crit {
 702                                         temperature = <95000>; /* millicelsius */
 703                                         hysteresis = <2000>; /* millicelsius */
 704                                         type = "critical";
 705                                 };
 706                         };
 707
 708                         cooling-maps {
 709                                 map0 {
 710                                         trip = <&target>;
 711                                         cooling-device =
 712                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 713                                         contribution = <1024>;
 714                                 };
 715                                 map1 {
 716                                         trip = <&target>;
 717                                         cooling-device =
 718                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 719                                         contribution = <1024>;
 720                                 };
 721                                 map2 {
 722                                         trip = <&target>;
 723                                         cooling-device =
 724                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 725                                         contribution = <1024>;
 726                                 };
 727                         };
 728                 };
 729
 730                 gpu_thermal: gpu-thermal {
 731                         polling-delay-passive = <200>; /* milliseconds */
 732                         polling-delay = <200>; /* milliseconds */
 733                         thermal-sensors = <&tsadc 1>;
 734                 };
 735         };
 736
 737         tsadc: tsadc@ff280000 {
 738                 compatible = "rockchip,rk3368-tsadc-legacy";
 739                 reg = <0x0 0xff280000 0x0 0x100>;
 740                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 741                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 742                 clock-names = "tsadc", "apb_pclk";
 743                 clock-frequency = <32768>;
 744                 resets = <&cru SRST_TSADC>;
 745                 reset-names = "tsadc-apb";
 746                 nvmem-cells = <&temp_adjust>;
 747                 nvmem-cell-names = "temp_adjust";
 748                 #thermal-sensor-cells = <1>;
 749                 hw-shut-temp = <95000>;
 750                 status = "disabled";
 751         };
 752
 753         gmac: ethernet@ff290000 {
 754                 compatible = "rockchip,rk3368-gmac";
 755                 reg = <0x0 0xff290000 0x0 0x10000>;
 756                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 757                 interrupt-names = "macirq";
 758                 rockchip,grf = <&grf>;
 759                 clocks = <&cru SCLK_MAC>,
 760                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 761                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 762                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 763                 clock-names = "stmmaceth",
 764                         "mac_clk_rx", "mac_clk_tx",
 765                         "clk_mac_ref", "clk_mac_refout",
 766                         "aclk_mac", "pclk_mac";
 767                 status = "disabled";
 768         };
 769
 770         nandc0: nandc@ff400000 {
 771                 compatible = "rockchip,rk-nandc";
 772                 reg = <0x0 0xff400000 0x0 0x4000>;
 773                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 774                 nandc_id = <0>;
 775                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 776                 clock-names = "clk_nandc", "hclk_nandc";
 777                 status = "disabled";
 778         };
 779
 780         usb_host0_ehci: usb@ff500000 {
 781                 compatible = "generic-ehci";
 782                 reg = <0x0 0xff500000 0x0 0x20000>;
 783                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 784                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 785                 clock-names = "usbhost", "utmi";
 786                 phys = <&u2phy_host>;
 787                 phy-names = "usb";
 788                 status = "disabled";
 789         };
 790
 791         usb_host0_ohci: usb@ff520000 {
 792                 compatible = "generic-ohci";
 793                 reg = <0x0 0xff520000 0x0 0x20000>;
 794                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 795                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 796                 clock-names = "usbhost", "utmi";
 797                 phys = <&u2phy_host>;
 798                 phy-names = "usb";
 799                 status = "disabled";
 800         };
 801
 802         usb_otg: usb@ff580000 {
 803                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 804                                 "snps,dwc2";
 805                 reg = <0x0 0xff580000 0x0 0x40000>;
 806                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&cru HCLK_OTG0>;
 808                 clock-names = "otg";
 809                 dr_mode = "otg";
 810                 g-np-tx-fifo-size = <16>;
 811                 g-rx-fifo-size = <275>;
 812                 g-tx-fifo-size = <256 128 128 64 64 32>;
 813                 g-use-dma;
 814                 status = "disabled";
 815         };
 816
 817         ddrpctl: syscon@ff610000 {
 818                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 819                 reg = <0x0 0xff610000 0x0 0x400>;
 820         };
 821
 822         i2c1: i2c@ff660000 {
 823                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 824                 reg = <0x0 0xff660000 0x0 0x1000>;
 825                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 826                 #address-cells = <1>;
 827                 #size-cells = <0>;
 828                 clock-names = "i2c";
 829                 clocks = <&cru PCLK_I2C1>;
 830                 pinctrl-names = "default";
 831                 pinctrl-0 = <&i2c1_xfer>;
 832                 status = "disabled";
 833         };
 834
 835         pwm0: pwm@ff680000 {
 836                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 837                 reg = <0x0 0xff680000 0x0 0x10>;
 838                 #pwm-cells = <3>;
 839                 pinctrl-names = "default";
 840                 pinctrl-0 = <&pwm0_pin>;
 841                 clocks = <&cru PCLK_PWM1>;
 842                 clock-names = "pwm";
 843                 status = "disabled";
 844         };
 845
 846         pwm1: pwm@ff680010 {
 847                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 848                 reg = <0x0 0xff680010 0x0 0x10>;
 849                 #pwm-cells = <3>;
 850                 pinctrl-names = "default";
 851                 pinctrl-0 = <&pwm1_pin>;
 852                 clocks = <&cru PCLK_PWM1>;
 853                 clock-names = "pwm";
 854                 status = "disabled";
 855         };
 856
 857         pwm2: pwm@ff680020 {
 858                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 859                 reg = <0x0 0xff680020 0x0 0x10>;
 860                 #pwm-cells = <3>;
 861                 clocks = <&cru PCLK_PWM1>;
 862                 clock-names = "pwm";
 863                 status = "disabled";
 864         };
 865
 866         pwm3: pwm@ff680030 {
 867                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 868                 reg = <0x0 0xff680030 0x0 0x10>;
 869                 #pwm-cells = <3>;
 870                 pinctrl-names = "default";
 871                 pinctrl-0 = <&pwm3_pin>;
 872                 clocks = <&cru PCLK_PWM1>;
 873                 clock-names = "pwm";
 874                 status = "disabled";
 875         };
 876
 877         uart2: serial@ff690000 {
 878                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 879                 reg = <0x0 0xff690000 0x0 0x100>;
 880                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 881                 clock-names = "baudclk", "apb_pclk";
 882                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 883                 pinctrl-names = "default";
 884                 pinctrl-0 = <&uart2_xfer>;
 885                 reg-shift = <2>;
 886                 reg-io-width = <4>;
 887                 status = "disabled";
 888         };
 889
 890         mbox: mbox@ff6b0000 {
 891                 compatible = "rockchip,rk3368-mailbox";
 892                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 893                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 894                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 895                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 896                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 897                 clocks = <&cru PCLK_MAILBOX>;
 898                 clock-names = "pclk_mailbox";
 899                 #mbox-cells = <1>;
 900                 status = "disabled";
 901         };
 902
 903         mailbox: mailbox@ff6b0000 {
 904                 compatible = "rockchip,rk3368-mbox-legacy";
 905                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 906                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 907                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 908                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 909                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 910                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 911                 clocks = <&cru PCLK_MAILBOX>;
 912                 clock-names = "pclk_mailbox";
 913                 #mbox-cells = <1>;
 914                 status = "disabled";
 915         };
 916
 917         mailbox_scpi: mailbox-scpi {
 918                 compatible = "rockchip,rk3368-scpi-legacy";
 919                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 920                 chan-nums = <3>;
 921                 status = "disabled";
 922         };
 923
 924         qos_iep: qos@ffad0000 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffad0000 0x0 0x20>;
 927         };
 928
 929         qos_isp_r0: qos@ffad0080 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffad0080 0x0 0x20>;
 932         };
 933
 934         qos_isp_r1: qos@ffad0100 {
 935                 compatible = "syscon";
 936                 reg = <0x0 0xffad0100 0x0 0x20>;
 937         };
 938
 939         qos_isp_w0: qos@ffad0180 {
 940                 compatible = "syscon";
 941                 reg = <0x0 0xffad0180 0x0 0x20>;
 942         };
 943
 944         qos_isp_w1: qos@ffad0200 {
 945                 compatible = "syscon";
 946                 reg = <0x0 0xffad0200 0x0 0x20>;
 947         };
 948
 949         qos_vip: qos@ffad0280 {
 950                 compatible = "syscon";
 951                 reg = <0x0 0xffad0280 0x0 0x20>;
 952         };
 953
 954         qos_vop: qos@ffad0300 {
 955                 compatible = "syscon";
 956                 reg = <0x0 0xffad0300 0x0 0x20>;
 957         };
 958
 959         qos_rga_r: qos@ffad0380 {
 960                 compatible = "syscon";
 961                 reg = <0x0 0xffad0380 0x0 0x20>;
 962         };
 963
 964         qos_rga_w: qos@ffad0400 {
 965                 compatible = "syscon";
 966                 reg = <0x0 0xffad0400 0x0 0x20>;
 967         };
 968
 969         qos_hevc_r: qos@ffae0000 {
 970                 compatible = "syscon";
 971                 reg = <0x0 0xffae0000 0x0 0x20>;
 972         };
 973
 974         qos_vpu_r: qos@ffae0100 {
 975                 compatible = "syscon";
 976                 reg = <0x0 0xffae0100 0x0 0x20>;
 977         };
 978
 979         qos_vpu_w: qos@ffae0180 {
 980                 compatible = "syscon";
 981                 reg = <0x0 0xffae0180 0x0 0x20>;
 982         };
 983
 984         qos_gpu: qos@ffaf0000 {
 985                 compatible = "syscon";
 986                 reg = <0x0 0xffaf0000 0x0 0x20>;
 987         };
 988
 989         pmu: power-management@ff730000 {
 990                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 991                 reg = <0x0 0xff730000 0x0 0x1000>;
 992
 993                 power: power-controller {
 994                         compatible = "rockchip,rk3368-power-controller";
 995                         #power-domain-cells = <1>;
 996                         #address-cells = <1>;
 997                         #size-cells = <0>;
 998
 999                         /*
1000                          * Note: Although SCLK_* are the working clocks
1001                          * of device without including on the NOC, needed for
1002                          * synchronous reset.
1003                          *
1004                          * The clocks on the which NOC:
1005                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
1006                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
1007                          * ACLK_RGA is on ACLK_RGA_NIU.
1008                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
1009                          *
1010                          * Which clock are device clocks:
1011                          *      clocks          devices
1012                          *      *_IEP           IEP:Image Enhancement Processor
1013                          *      *_ISP           ISP:Image Signal Processing
1014                          *      *_VIP           VIP:Video Input Processor
1015                          *      *_VOP*          VOP:Visual Output Processor
1016                          *      *_RGA           RGA
1017                          *      *_EDP*          EDP
1018                          *      *_DPHY*         LVDS
1019                          *      *_HDMI          HDMI
1020                          *      *_MIPI_*        MIPI
1021                          */
1022                         pd_vio {
1023                                 reg = <RK3368_PD_VIO>;
1024                                 clocks = <&cru ACLK_IEP>,
1025                                          <&cru ACLK_ISP>,
1026                                          <&cru ACLK_VIP>,
1027                                          <&cru ACLK_RGA>,
1028                                          <&cru ACLK_VOP>,
1029                                          <&cru ACLK_VOP_IEP>,
1030                                          <&cru DCLK_VOP>,
1031                                          <&cru HCLK_IEP>,
1032                                          <&cru HCLK_ISP>,
1033                                          <&cru HCLK_RGA>,
1034                                          <&cru HCLK_VIP>,
1035                                          <&cru HCLK_VOP>,
1036                                          <&cru HCLK_VIO_HDCPMMU>,
1037                                          <&cru PCLK_EDP_CTRL>,
1038                                          <&cru PCLK_HDMI_CTRL>,
1039                                          <&cru PCLK_HDCP>,
1040                                          <&cru PCLK_ISP>,
1041                                          <&cru PCLK_VIP>,
1042                                          <&cru PCLK_DPHYRX>,
1043                                          <&cru PCLK_DPHYTX0>,
1044                                          <&cru PCLK_MIPI_CSI>,
1045                                          <&cru PCLK_MIPI_DSI0>,
1046                                          <&cru SCLK_VOP0_PWM>,
1047                                          <&cru SCLK_EDP_24M>,
1048                                          <&cru SCLK_EDP>,
1049                                          <&cru SCLK_HDCP>,
1050                                          <&cru SCLK_ISP>,
1051                                          <&cru SCLK_RGA>,
1052                                          <&cru SCLK_HDMI_CEC>,
1053                                          <&cru SCLK_HDMI_HDCP>;
1054                                 pm_qos = <&qos_iep>,
1055                                          <&qos_isp_r0>,
1056                                          <&qos_isp_r1>,
1057                                          <&qos_isp_w0>,
1058                                          <&qos_isp_w1>,
1059                                          <&qos_vip>,
1060                                          <&qos_vop>,
1061                                          <&qos_rga_r>,
1062                                          <&qos_rga_w>;
1063                         };
1064                         /*
1065                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1066                          * (video endecoder & decoder) clocks that on the
1067                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1068                          */
1069                         pd_video {
1070                                 reg = <RK3368_PD_VIDEO>;
1071                                 clocks = <&cru ACLK_VIDEO>,
1072                                          <&cru HCLK_VIDEO>,
1073                                          <&cru SCLK_HEVC_CABAC>,
1074                                          <&cru SCLK_HEVC_CORE>;
1075                                 pm_qos = <&qos_hevc_r>,
1076                                          <&qos_vpu_r>,
1077                                          <&qos_vpu_w>;
1078                         };
1079                         /*
1080                          * Note: ACLK_GPU is the GPU clock,
1081                          * and on the ACLK_GPU_NIU (NOC).
1082                          */
1083                         pd_gpu_1 {
1084                                 reg = <RK3368_PD_GPU_1>;
1085                                 clocks = <&cru ACLK_GPU_CFG>,
1086                                          <&cru ACLK_GPU_MEM>,
1087                                          <&cru SCLK_GPU_CORE>;
1088                                 pm_qos = <&qos_gpu>;
1089                         };
1090                 };
1091         };
1092
1093         pmugrf: syscon@ff738000 {
1094                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1095                 reg = <0x0 0xff738000 0x0 0x1000>;
1096
1097                 pmu_io_domains: io-domains {
1098                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1099                         status = "disabled";
1100                 };
1101
1102                 reboot-mode {
1103                         compatible = "syscon-reboot-mode";
1104                         offset = <0x200>;
1105                         mode-normal = <BOOT_NORMAL>;
1106                         mode-recovery = <BOOT_RECOVERY>;
1107                         mode-bootloader = <BOOT_FASTBOOT>;
1108                         mode-loader = <BOOT_BL_DOWNLOAD>;
1109                 };
1110         };
1111
1112         cru: clock-controller@ff760000 {
1113                 compatible = "rockchip,rk3368-cru";
1114                 reg = <0x0 0xff760000 0x0 0x1000>;
1115                 rockchip,grf = <&grf>;
1116                 #clock-cells = <1>;
1117                 #reset-cells = <1>;
1118                 assigned-clocks =
1119                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1120                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1121                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1122                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1123                 assigned-clock-rates =
1124                         <576000000>, <400000000>,
1125                         <300000000>, <300000000>,
1126                         <150000000>, <150000000>,
1127                         <75000000>, <75000000>;
1128         };
1129
1130         grf: syscon@ff770000 {
1131                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1132                 reg = <0x0 0xff770000 0x0 0x1000>;
1133                 #address-cells = <1>;
1134                 #size-cells = <1>;
1135
1136                 edp_phy: edp-phy {
1137                         compatible = "rockchip,rk3368-dp-phy";
1138                         clocks = <&cru SCLK_EDP_24M>;
1139                         clock-names = "24m";
1140                         resets = <&cru SRST_EDP_24M>;
1141                         reset-names = "edp_24m";
1142                         #phy-cells = <0>;
1143                         status = "disabled";
1144                 };
1145
1146                 io_domains: io-domains {
1147                         compatible = "rockchip,rk3368-io-voltage-domain";
1148                         status = "disabled";
1149                 };
1150
1151                 u2phy: usb2-phy@700 {
1152                         compatible = "rockchip,rk3368-usb2phy";
1153                         reg = <0x700 0x2c>;
1154                         clocks = <&cru SCLK_OTGPHY0>;
1155                         clock-names = "phyclk";
1156                         #clock-cells = <0>;
1157                         clock-output-names = "usbotg_out";
1158                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1159                         assigned-clock-parents = <&u2phy>;
1160                         status = "disabled";
1161
1162                         u2phy_host: host-port {
1163                                 #phy-cells = <0>;
1164                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1165                                 interrupt-names = "linestate";
1166                                 status = "disabled";
1167                         };
1168                 };
1169         };
1170
1171         wdt: watchdog@ff800000 {
1172                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1173                 reg = <0x0 0xff800000 0x0 0x100>;
1174                 clocks = <&cru PCLK_WDT>;
1175                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1176                 status = "disabled";
1177         };
1178
1179         timer@ff810000 {
1180                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1181                 reg = <0x0 0xff810000 0x0 0x20>;
1182                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1183         };
1184
1185         i2s_2ch: i2s-2ch@ff890000 {
1186                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1187                 reg = <0x0 0xff890000 0x0 0x1000>;
1188                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1189                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1190                 dma-names = "tx", "rx";
1191                 clock-names = "i2s_clk", "i2s_hclk";
1192                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1193                 status = "disabled";
1194         };
1195
1196         i2s_8ch: i2s-8ch@ff898000 {
1197                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1198                 reg = <0x0 0xff898000 0x0 0x1000>;
1199                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1200                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1201                 dma-names = "tx", "rx";
1202                 clock-names = "i2s_clk", "i2s_hclk";
1203                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1204                 pinctrl-names = "default";
1205                 pinctrl-0 = <&i2s_8ch_bus>;
1206                 status = "disabled";
1207         };
1208
1209         iep: iep@ff900000 {
1210                 compatible = "rockchip,iep";
1211                 iommu_enabled = <1>;
1212                 iommus = <&iep_mmu>;
1213                 reg = <0x0 0xff900000 0x0 0x800>;
1214                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1215                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1216                 clock-names = "aclk_iep", "hclk_iep";
1217                 power-domains = <&power RK3368_PD_VIO>;
1218                 allocator = <1>;
1219                 version = <2>;
1220                 status = "disabled";
1221         };
1222
1223         iep_mmu: iommu@ff900800 {
1224                 compatible = "rockchip,iommu";
1225                 reg = <0x0 0xff900800 0x0 0x100>;
1226                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1227                 interrupt-names = "iep_mmu";
1228                 power-domains = <&power RK3368_PD_VIO>;
1229                 #iommu-cells = <0>;
1230                 status = "disabled";
1231         };
1232
1233         isp: isp@ff910000 {
1234                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1235                 reg = <0x0 0xff910000 0x0 0x4000>;
1236                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1237                 power-domains = <&power RK3368_PD_VIO>;
1238                 clocks =
1239                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1240                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1241                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1242                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1243                 clock-names =
1244                         "aclk_isp", "hclk_isp", "clk_isp",
1245                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1246                         "clk_cif_pll", "hclk_mipiphy1",
1247                         "pclk_dphyrx", "clk_vio0_noc";
1248
1249                 pinctrl-names =
1250                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1251                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1252                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1253                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1254                 pinctrl-0 = <&cif_clkout>;
1255                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1256                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1257                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1258                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1259                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1260                 pinctrl-6 = <&cif_clkout>;
1261                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1262                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1263                 pinctrl-9 = <&isp_flash_trigger>;
1264                 rockchip,isp,mipiphy = <2>;
1265                 rockchip,isp,cifphy = <1>;
1266                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1267                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1268                 rockchip,grf = <&grf>;
1269                 rockchip,cru = <&cru>;
1270                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1271                 rockchip,isp,iommu-enable = <1>;
1272                 iommus = <&isp_mmu>;
1273                 status = "disabled";
1274         };
1275
1276         isp_mmu: iommu@ff914000 {
1277                 compatible = "rockchip,iommu";
1278                 reg = <0x0 0xff914000 0x0 0x100>,
1279                       <0x0 0xff915000 0x0 0x100>;
1280                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1281                 interrupt-names = "isp_mmu";
1282                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1283                 clock-names = "aclk", "hclk";
1284                 rk_iommu,disable_reset_quirk;
1285                 #iommu-cells = <0>;
1286                 power-domains = <&power RK3368_PD_VIO>;
1287                 status = "disabled";
1288         };
1289
1290         vop: vop@ff930000 {
1291                 compatible = "rockchip,rk3368-vop";
1292                 reg = <0x0 0xff930000 0x0 0x2fc>;
1293                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1294                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1295                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1296                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1297                 assigned-clock-rates = <400000000>, <200000000>;
1298                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1299                 reset-names = "axi", "ahb", "dclk";
1300                 power-domains = <&power RK3368_PD_VIO>;
1301                 iommus = <&vop_mmu>;
1302                 status = "disabled";
1303
1304                 vop_out: port {
1305                         #address-cells = <1>;
1306                         #size-cells = <0>;
1307
1308                         vop_out_mipi: endpoint@0 {
1309                                 reg = <0>;
1310                                 remote-endpoint = <&mipi_in_vop>;
1311                         };
1312
1313                         vop_out_edp: endpoint@1 {
1314                                 reg = <1>;
1315                                 remote-endpoint = <&edp_in_vop>;
1316                         };
1317                 };
1318         };
1319
1320         display_subsystem: display-subsystem {
1321                 compatible = "rockchip,display-subsystem";
1322                 ports = <&vop_out>;
1323                 status = "disabled";
1324         };
1325
1326         vop_mmu: iommu@ff930300 {
1327                 compatible = "rockchip,iommu";
1328                 reg = <0x0 0xff930300 0x0 0x100>;
1329                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1330                 interrupt-names = "vop_mmu";
1331                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1332                 clock-names = "aclk", "hclk";
1333                 power-domains = <&power RK3368_PD_VIO>;
1334                 #iommu-cells = <0>;
1335                 status = "disabled";
1336         };
1337
1338         mipi_dsi_host: mipi-dsi-host@ff960000 {
1339                 compatible = "rockchip,rk3368-mipi-dsi";
1340                 reg = <0x0 0xff960000 0x0 0x4000>;
1341                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1342                 clocks = <&cru PCLK_MIPI_DSI0>;
1343                 clock-names = "pclk";
1344                 resets = <&cru SRST_MIPIDSI0>;
1345                 reset-names = "apb";
1346                 phys = <&mipi_dphy>;
1347                 phy-names = "mipi_dphy";
1348                 rockchip,grf = <&grf>;
1349                 power-domains = <&power RK3368_PD_VIO>;
1350                 #address-cells = <1>;
1351                 #size-cells = <0>;
1352                 status = "disabled";
1353
1354                 ports {
1355                         port {
1356                                 mipi_in_vop: endpoint {
1357                                         remote-endpoint = <&vop_out_mipi>;
1358                                 };
1359                         };
1360                 };
1361         };
1362
1363         mipi_dphy: mipi-dphy@ff968000 {
1364                 compatible = "rockchip,rk3368-mipi-dphy";
1365                 reg = <0x0 0xff968000 0x0 0x4000>;
1366                 #phy-cells = <0>;
1367                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1368                 clock-names = "ref", "pclk";
1369                 resets = <&cru SRST_MIPIDPHYTX>;
1370                 reset-names = "apb";
1371                 status = "disabled";
1372         };
1373
1374         edp: edp@ff970000 {
1375                 compatible = "rockchip,rk3368-edp";
1376                 reg = <0x0 0xff970000 0x0 0x8000>;
1377                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1378                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1379                 clock-names = "dp", "pclk";
1380                 resets = <&cru SRST_EDP>;
1381                 reset-names = "dp";
1382                 power-domains = <&power RK3368_PD_VIO>;
1383                 rockchip,grf = <&grf>;
1384                 phys = <&edp_phy>;
1385                 phy-names = "dp";
1386                 pinctrl-names = "default";
1387                 pinctrl-0 = <&edp_hpd>;
1388                 status = "disabled";
1389
1390                 ports {
1391                         #address-cells = <1>;
1392                         #size-cells = <0>;
1393
1394                         edp_in: port@0 {
1395                                 reg = <0>;
1396
1397                                 edp_in_vop: endpoint {
1398                                         remote-endpoint = <&vop_out_edp>;
1399                                 };
1400                         };
1401                 };
1402         };
1403
1404         hevc_mmu: iommu@ff9a0440 {
1405                 compatible = "rockchip,iommu";
1406                 reg = <0x0 0xff9a0440 0x0 0x40>,
1407                       <0x0 0xff9a0480 0x0 0x40>;
1408                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1409                 interrupt-names = "hevc_mmu";
1410                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1411                 clock-names = "aclk", "hclk";
1412                 power-domains = <&power RK3368_PD_VIDEO>;
1413                 #iommu-cells = <0>;
1414                 status = "disabled";
1415         };
1416
1417         vpu_mmu: iommu@ff9a0800 {
1418                 compatible = "rockchip,iommu";
1419                 reg = <0x0 0xff9a0800 0x0 0x100>;
1420                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1421                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1422                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1423                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1424                 clock-names = "aclk", "hclk";
1425                 power-domains = <&power RK3368_PD_VIDEO>;
1426                 #iommu-cells = <0>;
1427                 status = "disabled";
1428         };
1429
1430         vpu: vpu_service {
1431                 compatible = "rockchip,vpu_sub";
1432                 iommu_enabled = <1>;
1433                 iommus = <&vpu_mmu>;
1434                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1435                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1436                 interrupt-names = "irq_enc","irq_dec";
1437                 dev_mode = <0>;
1438                 name = "vpu_service";
1439                 allocator = <1>;
1440         };
1441
1442         hevc: hevc_service {
1443                 compatible = "rockchip,hevc_sub";
1444                 iommu_enabled = <1>;
1445                 iommus = <&hevc_mmu>;
1446                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1447                 interrupt-names = "irq_dec";
1448                 dev_mode = <1>;
1449                 name = "hevc_service";
1450                 allocator = <1>;
1451         };
1452
1453         vpu_combo: vpu_combo@ff9a0000 {
1454                 compatible = "rockchip,vpu_combo";
1455                 reg = <0x0 0xff9a0000 0x0 0x440>;
1456                 rockchip,grf = <&grf>;
1457                 subcnt = <2>;
1458                 rockchip,sub = <&vpu>, <&hevc>;
1459                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1460                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1461                 clock-names = "aclk_vcodec", "hclk_vcodec",
1462                               "clk_core", "clk_cabac";
1463                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1464                          <&cru SRST_VIDEO>;
1465                 reset-names = "video_a", "video_h", "video";
1466                 mode_bit = <12>;
1467                 mode_ctrl = <0x418>;
1468                 name = "vpu_combo";
1469                 power-domains = <&power RK3368_PD_VIDEO>;
1470                 status = "disabled";
1471         };
1472
1473         gic: interrupt-controller@ffb71000 {
1474                 compatible = "arm,gic-400";
1475                 interrupt-controller;
1476                 #interrupt-cells = <3>;
1477                 #address-cells = <0>;
1478
1479                 reg = <0x0 0xffb71000 0x0 0x1000>,
1480                       <0x0 0xffb72000 0x0 0x2000>,
1481                       <0x0 0xffb74000 0x0 0x2000>,
1482                       <0x0 0xffb76000 0x0 0x2000>;
1483                 interrupts = <GIC_PPI 9
1484                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1485         };
1486
1487         gpu: rogue-g6110@ffa30000 {
1488                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1489                 reg = <0x0 0xffa30000 0x0 0x10000>;
1490                 clocks =
1491                         <&cru SCLK_GPU_CORE>,
1492                         <&cru ACLK_GPU_MEM>,
1493                         <&cru ACLK_GPU_CFG>;
1494                 clock-names =
1495                         "sclk_gpu_core",
1496                         "aclk_gpu_mem",
1497                         "aclk_gpu_cfg";
1498                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1499                 interrupt-names = "rogue-g6110-irq";
1500                 power-domains = <&power RK3368_PD_GPU_1>;
1501                 operating-points-v2 = <&gpu_opp_table>;
1502                 #cooling-cells = <2>; /* min followed by max */
1503                 gpu_power_model: power_model {
1504                         compatible = "arm,mali-simple-power-model";
1505                         voltage = <900>;
1506                         frequency = <500>;
1507                         static-power = <300>;
1508                         dynamic-power = <396>;
1509                         ts = <32000 4700 (-80) 2>;
1510                         thermal-zone = "gpu-thermal";
1511                 };
1512         };
1513
1514         gpu_opp_table: gpu_opp_table {
1515                 compatible = "operating-points-v2";
1516                 opp-shared;
1517
1518                 opp@200000000 {
1519                         opp-hz = /bits/ 64 <200000000>;
1520                         opp-microvolt = <1100000>;
1521                 };
1522                 opp@288000000 {
1523                         opp-hz = /bits/ 64 <288000000>;
1524                         opp-microvolt = <1100000>;
1525                 };
1526                 opp@400000000 {
1527                         opp-hz = /bits/ 64 <400000000>;
1528                         opp-microvolt = <1100000>;
1529                 };
1530                 opp@576000000 {
1531                         opp-hz = /bits/ 64 <576000000>;
1532                         opp-microvolt = <1200000>;
1533                 };
1534         };
1535
1536         efuse: efuse@ffb00000 {
1537                 compatible = "rockchip,rk3368-efuse";
1538                 reg = <0x0 0xffb00000 0x0 0x20>;
1539                 #address-cells = <1>;
1540                 #size-cells = <1>;
1541                 clocks = <&cru PCLK_EFUSE256>;
1542                 clock-names = "pclk_efuse";
1543
1544                 /* Data cells */
1545                 cpu_leakage: cpu-leakage@17 {
1546                         reg = <0x17 0x1>;
1547                 };
1548                 temp_adjust: temp-adjust@1f {
1549                         reg = <0x1f 0x1>;
1550                 };
1551         };
1552
1553         pinctrl: pinctrl {
1554                 compatible = "rockchip,rk3368-pinctrl";
1555                 rockchip,grf = <&grf>;
1556                 rockchip,pmu = <&pmugrf>;
1557                 #address-cells = <0x2>;
1558                 #size-cells = <0x2>;
1559                 ranges;
1560
1561                 gpio0: gpio0@ff750000 {
1562                         compatible = "rockchip,gpio-bank";
1563                         reg = <0x0 0xff750000 0x0 0x100>;
1564                         clocks = <&cru PCLK_GPIO0>;
1565                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1566
1567                         gpio-controller;
1568                         #gpio-cells = <0x2>;
1569
1570                         interrupt-controller;
1571                         #interrupt-cells = <0x2>;
1572                 };
1573
1574                 gpio1: gpio1@ff780000 {
1575                         compatible = "rockchip,gpio-bank";
1576                         reg = <0x0 0xff780000 0x0 0x100>;
1577                         clocks = <&cru PCLK_GPIO1>;
1578                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1579
1580                         gpio-controller;
1581                         #gpio-cells = <0x2>;
1582
1583                         interrupt-controller;
1584                         #interrupt-cells = <0x2>;
1585                 };
1586
1587                 gpio2: gpio2@ff790000 {
1588                         compatible = "rockchip,gpio-bank";
1589                         reg = <0x0 0xff790000 0x0 0x100>;
1590                         clocks = <&cru PCLK_GPIO2>;
1591                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1592
1593                         gpio-controller;
1594                         #gpio-cells = <0x2>;
1595
1596                         interrupt-controller;
1597                         #interrupt-cells = <0x2>;
1598                 };
1599
1600                 gpio3: gpio3@ff7a0000 {
1601                         compatible = "rockchip,gpio-bank";
1602                         reg = <0x0 0xff7a0000 0x0 0x100>;
1603                         clocks = <&cru PCLK_GPIO3>;
1604                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1605
1606                         gpio-controller;
1607                         #gpio-cells = <0x2>;
1608
1609                         interrupt-controller;
1610                         #interrupt-cells = <0x2>;
1611                 };
1612
1613                 pcfg_pull_up: pcfg-pull-up {
1614                         bias-pull-up;
1615                 };
1616
1617                 pcfg_pull_down: pcfg-pull-down {
1618                         bias-pull-down;
1619                 };
1620
1621                 pcfg_pull_none: pcfg-pull-none {
1622                         bias-disable;
1623                 };
1624
1625                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1626                         bias-disable;
1627                         drive-strength = <12>;
1628                 };
1629
1630                 edp {
1631                         edp_hpd: edp-hpd {
1632                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 emmc {
1637                         emmc_clk: emmc-clk {
1638                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1639                         };
1640
1641                         emmc_cmd: emmc-cmd {
1642                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1643                         };
1644
1645                         emmc_pwr: emmc-pwr {
1646                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1647                         };
1648
1649                         emmc_bus1: emmc-bus1 {
1650                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1651                         };
1652
1653                         emmc_bus4: emmc-bus4 {
1654                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1655                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1656                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1657                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1658                         };
1659
1660                         emmc_bus8: emmc-bus8 {
1661                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1662                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1663                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1664                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1665                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1666                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1667                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1668                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1669                         };
1670                 };
1671
1672                 gmac {
1673                         rgmii_pins: rgmii-pins {
1674                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1675                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1676                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1677                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1678                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1679                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1680                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1681                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1682                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1683                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1684                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1685                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1686                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1687                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1688                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1689                         };
1690
1691                         rmii_pins: rmii-pins {
1692                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1693                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1694                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1695                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1696                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1697                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1698                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1699                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1700                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1701                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703                 };
1704
1705                 i2c0 {
1706                         i2c0_xfer: i2c0-xfer {
1707                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1708                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1709                         };
1710                 };
1711
1712                 i2c1 {
1713                         i2c1_xfer: i2c1-xfer {
1714                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1715                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1716                         };
1717                 };
1718
1719                 i2c2 {
1720                         i2c2_xfer: i2c2-xfer {
1721                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1722                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1723                         };
1724                 };
1725
1726                 i2c3 {
1727                         i2c3_xfer: i2c3-xfer {
1728                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1729                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1730                         };
1731                 };
1732
1733                 i2c4 {
1734                         i2c4_xfer: i2c4-xfer {
1735                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1736                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1737                         };
1738                 };
1739
1740                 i2c5 {
1741                         i2c5_xfer: i2c5-xfer {
1742                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1743                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1744                         };
1745                 };
1746
1747                 i2s {
1748                         i2s_8ch_bus: i2s-8ch-bus {
1749                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1750                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1751                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1752                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1753                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1754                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1755                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1756                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1757                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1758                         };
1759                 };
1760
1761                 pwm0 {
1762                         pwm0_pin: pwm0-pin {
1763                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1764                         };
1765
1766                         vop_pwm_pin: vop-pwm {
1767                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1768                         };
1769                 };
1770
1771                 pwm1 {
1772                         pwm1_pin: pwm1-pin {
1773                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1774                         };
1775                 };
1776
1777                 pwm3 {
1778                         pwm3_pin: pwm3-pin {
1779                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1780                         };
1781                 };
1782
1783                 sdio0 {
1784                         sdio0_bus1: sdio0-bus1 {
1785                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1786                         };
1787
1788                         sdio0_bus4: sdio0-bus4 {
1789                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1790                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1791                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1792                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1793                         };
1794
1795                         sdio0_cmd: sdio0-cmd {
1796                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798
1799                         sdio0_clk: sdio0-clk {
1800                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1801                         };
1802
1803                         sdio0_cd: sdio0-cd {
1804                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806
1807                         sdio0_wp: sdio0-wp {
1808                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810
1811                         sdio0_pwr: sdio0-pwr {
1812                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814
1815                         sdio0_bkpwr: sdio0-bkpwr {
1816                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1817                         };
1818
1819                         sdio0_int: sdio0-int {
1820                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1821                         };
1822                 };
1823
1824                 sdmmc {
1825                         sdmmc_clk: sdmmc-clk {
1826                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1827                         };
1828
1829                         sdmmc_cmd: sdmmc-cmd {
1830                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1831                         };
1832
1833                         sdmmc_cd: sdmmc-cd {
1834                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1835                         };
1836
1837                         sdmmc_bus1: sdmmc-bus1 {
1838                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1839                         };
1840
1841                         sdmmc_bus4: sdmmc-bus4 {
1842                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1843                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1844                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1845                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1846                         };
1847                 };
1848
1849                 spi0 {
1850                         spi0_clk: spi0-clk {
1851                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1852                         };
1853                         spi0_cs0: spi0-cs0 {
1854                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1855                         };
1856                         spi0_cs1: spi0-cs1 {
1857                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1858                         };
1859                         spi0_tx: spi0-tx {
1860                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1861                         };
1862                         spi0_rx: spi0-rx {
1863                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1864                         };
1865                 };
1866
1867                 spi1 {
1868                         spi1_clk: spi1-clk {
1869                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1870                         };
1871                         spi1_cs0: spi1-cs0 {
1872                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1873                         };
1874                         spi1_cs1: spi1-cs1 {
1875                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1876                         };
1877                         spi1_rx: spi1-rx {
1878                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1879                         };
1880                         spi1_tx: spi1-tx {
1881                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1882                         };
1883                 };
1884
1885                 spi2 {
1886                         spi2_clk: spi2-clk {
1887                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1888                         };
1889                         spi2_cs0: spi2-cs0 {
1890                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1891                         };
1892                         spi2_rx: spi2-rx {
1893                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1894                         };
1895                         spi2_tx: spi2-tx {
1896                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1897                         };
1898                 };
1899
1900                 uart0 {
1901                         uart0_xfer: uart0-xfer {
1902                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1903                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1904                         };
1905
1906                         uart0_cts: uart0-cts {
1907                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1908                         };
1909
1910                         uart0_rts: uart0-rts {
1911                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1912                         };
1913                 };
1914
1915                 uart1 {
1916                         uart1_xfer: uart1-xfer {
1917                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1918                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1919                         };
1920
1921                         uart1_cts: uart1-cts {
1922                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1923                         };
1924
1925                         uart1_rts: uart1-rts {
1926                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1927                         };
1928                 };
1929
1930                 uart2 {
1931                         uart2_xfer: uart2-xfer {
1932                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1933                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1934                         };
1935                         /* no rts / cts for uart2 */
1936                 };
1937
1938                 uart3 {
1939                         uart3_xfer: uart3-xfer {
1940                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1941                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1942                         };
1943
1944                         uart3_cts: uart3-cts {
1945                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1946                         };
1947
1948                         uart3_rts: uart3-rts {
1949                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1950                         };
1951                 };
1952
1953                 uart4 {
1954                         uart4_xfer: uart4-xfer {
1955                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1956                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1957                         };
1958
1959                         uart4_cts: uart4-cts {
1960                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1961                         };
1962
1963                         uart4_rts: uart4-rts {
1964                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1965                         };
1966                 };
1967
1968                 isp {
1969                         cif_clkout: cif-clkout {
1970                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1971                         };
1972
1973                         isp_dvp_d2d9: isp-dvp-d2d9 {
1974                                 rockchip,pins =
1975                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1976                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1977                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1978                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1979                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1980                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1981                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1982                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1983                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1984                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1985                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1986                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1987                         };
1988
1989                         isp_dvp_d0d1: isp-dvp-d0d1 {
1990                                 rockchip,pins =
1991                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1992                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1993                         };
1994
1995                         isp_dvp_d10d11:isp_d10d11 {
1996                                 rockchip,pins =
1997                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1998                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1999                         };
2000
2001                         isp_dvp_d0d7: isp-dvp-d0d7 {
2002                                 rockchip,pins =
2003                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
2004                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
2005                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
2006                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
2007                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2008                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2009                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2010                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2011                         };
2012
2013                         isp_dvp_d4d11: isp-dvp-d4d11 {
2014                                 rockchip,pins =
2015                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2016                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2017                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2018                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2019                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2020                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2021                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2022                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2023                         };
2024
2025                         isp_shutter: isp-shutter {
2026                                 rockchip,pins =
2027                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2028                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2029                         };
2030
2031                         isp_flash_trigger: isp-flash-trigger {
2032                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2033                         };
2034
2035                         isp_prelight: isp-prelight {
2036                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2037                         };
2038
2039                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2040                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2041                         };
2042                 };
2043         };
2044 };