arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3368";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_b0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_b1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_b2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_b3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_l0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_l1>;
 102                                 };
 103                                 core2 {
 104                                         cpu = <&cpu_l2>;
 105                                 };
 106                                 core3 {
 107                                         cpu = <&cpu_l3>;
 108                                 };
 109                         };
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 arm,psci-suspend-param = <0x1010000>;
 118                                 entry-latency-us = <0x3fffffff>;
 119                                 exit-latency-us = <0x40000000>;
 120                                 min-residency-us = <0xffffffff>;
 121                         };
 122                 };
 123
 124                 cpu_l0: cpu@0 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x0>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         operating-points-v2 = <&cluster1_opp>;
 132
 133                         #cooling-cells = <2>; /* min followed by max */
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster1_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster1_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster0_opp>;
 174
 175                         #cooling-cells = <2>; /* min followed by max */
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster0_opp>;
 186                 };
 187
 188                 cpu_b2: cpu@102 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x102>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster0_opp>;
 196                 };
 197
 198                 cpu_b3: cpu@103 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a53", "arm,armv8";
 201                         reg = <0x0 0x103>;
 202                         cpu-idle-states = <&cpu_sleep>;
 203                         enable-method = "psci";
 204                         clocks = <&cru ARMCLKB>;
 205                         operating-points-v2 = <&cluster0_opp>;
 206                 };
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <1200000>;
 216                         clock-latency-ns = <40000>;
 217                         opp-suspend;
 218                 };
 219                 opp@600000000 {
 220                         opp-hz = /bits/ 64 <600000000>;
 221                         opp-microvolt = <1200000>;
 222                 };
 223                 opp@816000000 {
 224                         opp-hz = /bits/ 64 <816000000>;
 225                         opp-microvolt = <1200000>;
 226                 };
 227                 opp@1008000000 {
 228                         opp-hz = /bits/ 64 <1008000000>;
 229                         opp-microvolt = <1200000>;
 230                 };
 231                 opp@1200000000 {
 232                         opp-hz = /bits/ 64 <1200000000>;
 233                         opp-microvolt = <1200000>;
 234                 };
 235         };
 236
 237         cluster1_opp: opp_table1 {
 238                 compatible = "operating-points-v2";
 239                 opp-shared;
 240
 241                 opp@408000000 {
 242                         opp-hz = /bits/ 64 <408000000>;
 243                         opp-microvolt = <1200000>;
 244                         clock-latency-ns = <40000>;
 245                         opp-suspend;
 246                 };
 247                 opp@600000000 {
 248                         opp-hz = /bits/ 64 <600000000>;
 249                         opp-microvolt = <1200000>;
 250                 };
 251                 opp@816000000 {
 252                         opp-hz = /bits/ 64 <816000000>;
 253                         opp-microvolt = <1200000>;
 254                 };
 255                 opp@1008000000 {
 256                         opp-hz = /bits/ 64 <1008000000>;
 257                         opp-microvolt = <1200000>;
 258                 };
 259         };
 260
 261         cpu_avs: cpu-avs {
 262                 cluster0-avs {
 263                         cluster-id = <0>;
 264                         min-volt = <950000>; /* uV */
 265                         min-freq = <216000>; /* KHz */
 266                         leakage-adjust-volt = <
 267                         /*  mA        mA         uV */
 268                             0         254        0
 269                         >;
 270                         nvmem-cells = <&cpu_leakage>;
 271                         nvmem-cell-names = "cpu_leakage";
 272                 };
 273                 cluster1-avs {
 274                         cluster-id = <1>;
 275                         min-volt = <950000>; /* uV */
 276                         min-freq = <216000>; /* KHz */
 277                         leakage-adjust-volt = <
 278                         /*  mA        mA         uV */
 279                             0         254        0
 280                         >;
 281                         nvmem-cells = <&cpu_leakage>;
 282                         nvmem-cell-names = "cpu_leakage";
 283                 };
 284         };
 285
 286         arm-pmu {
 287                 compatible = "arm,armv8-pmuv3";
 288                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 296                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 297                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 298                                      <&cpu_b2>, <&cpu_b3>;
 299         };
 300
 301         amba {
 302                 compatible = "arm,amba-bus";
 303                 #address-cells = <2>;
 304                 #size-cells = <2>;
 305                 ranges;
 306
 307                 dmac_peri: dma-controller@ff250000 {
 308                         compatible = "arm,pl330", "arm,primecell";
 309                         reg = <0x0 0xff250000 0x0 0x4000>;
 310                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 312                         #dma-cells = <1>;
 313                         clocks = <&cru ACLK_DMAC_PERI>;
 314                         clock-names = "apb_pclk";
 315                         arm,pl330-broken-no-flushp;
 316                         peripherals-req-type-burst;
 317                 };
 318
 319                 dmac_bus: dma-controller@ff600000 {
 320                         compatible = "arm,pl330", "arm,primecell";
 321                         reg = <0x0 0xff600000 0x0 0x4000>;
 322                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 324                         #dma-cells = <1>;
 325                         clocks = <&cru ACLK_DMAC_BUS>;
 326                         clock-names = "apb_pclk";
 327                         arm,pl330-broken-no-flushp;
 328                         peripherals-req-type-burst;
 329                 };
 330         };
 331
 332         psci {
 333                 compatible = "arm,psci-0.2";
 334                 method = "smc";
 335         };
 336
 337         timer {
 338                 compatible = "arm,armv8-timer";
 339                 interrupts = <GIC_PPI 13
 340                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 341                              <GIC_PPI 14
 342                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 343                              <GIC_PPI 11
 344                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 345                              <GIC_PPI 10
 346                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 347         };
 348
 349         xin24m: oscillator {
 350                 compatible = "fixed-clock";
 351                 clock-frequency = <24000000>;
 352                 clock-output-names = "xin24m";
 353                 #clock-cells = <0>;
 354         };
 355
 356         sdmmc: rksdmmc@ff0c0000 {
 357                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 358                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 359                 clock-freq-min-max = <400000 150000000>;
 360                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 361                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 362                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 363                 fifo-depth = <0x100>;
 364                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 365                 status = "disabled";
 366         };
 367
 368         sdio0: dwmmc@ff0d0000 {
 369                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 370                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 371                 clock-freq-min-max = <400000 150000000>;
 372                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 373                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 374                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 375                 fifo-depth = <0x100>;
 376                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 377                 status = "disabled";
 378         };
 379
 380         emmc: rksdmmc@ff0f0000 {
 381                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 382                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 383                 clock-freq-min-max = <400000 150000000>;
 384                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 385                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 386                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 387                 fifo-depth = <0x100>;
 388                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 389                 status = "disabled";
 390         };
 391
 392         saradc: saradc@ff100000 {
 393                 compatible = "rockchip,saradc";
 394                 reg = <0x0 0xff100000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 396                 #io-channel-cells = <1>;
 397                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 398                 clock-names = "saradc", "apb_pclk";
 399                 resets = <&cru SRST_SARADC>;
 400                 reset-names = "saradc-apb";
 401                 status = "disabled";
 402         };
 403
 404         spi0: spi@ff110000 {
 405                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 406                 reg = <0x0 0xff110000 0x0 0x1000>;
 407                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 408                 clock-names = "spiclk", "apb_pclk";
 409                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 status = "disabled";
 415         };
 416
 417         spi1: spi@ff120000 {
 418                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 419                 reg = <0x0 0xff120000 0x0 0x1000>;
 420                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 421                 clock-names = "spiclk", "apb_pclk";
 422                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 status = "disabled";
 428         };
 429
 430         spi2: spi@ff130000 {
 431                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 432                 reg = <0x0 0xff130000 0x0 0x1000>;
 433                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 434                 clock-names = "spiclk", "apb_pclk";
 435                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 status = "disabled";
 441         };
 442
 443         i2c0: i2c@ff650000 {
 444                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 445                 reg = <0x0 0xff650000 0x0 0x1000>;
 446                 clocks = <&cru PCLK_I2C0>;
 447                 clock-names = "i2c";
 448                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c0_xfer>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         i2c2: i2c@ff140000 {
 457                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 458                 reg = <0x0 0xff140000 0x0 0x1000>;
 459                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clock-names = "i2c";
 463                 clocks = <&cru PCLK_I2C2>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&i2c2_xfer>;
 466                 status = "disabled";
 467         };
 468
 469         i2c3: i2c@ff150000 {
 470                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 471                 reg = <0x0 0xff150000 0x0 0x1000>;
 472                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clock-names = "i2c";
 476                 clocks = <&cru PCLK_I2C3>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c3_xfer>;
 479                 status = "disabled";
 480         };
 481
 482         i2c4: i2c@ff160000 {
 483                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 484                 reg = <0x0 0xff160000 0x0 0x1000>;
 485                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clock-names = "i2c";
 489                 clocks = <&cru PCLK_I2C4>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c4_xfer>;
 492                 status = "disabled";
 493         };
 494
 495         i2c5: i2c@ff170000 {
 496                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 497                 reg = <0x0 0xff170000 0x0 0x1000>;
 498                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clock-names = "i2c";
 502                 clocks = <&cru PCLK_I2C5>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c5_xfer>;
 505                 status = "disabled";
 506         };
 507
 508         uart0: serial@ff180000 {
 509                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 510                 reg = <0x0 0xff180000 0x0 0x100>;
 511                 clock-frequency = <24000000>;
 512                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 515                 reg-shift = <2>;
 516                 reg-io-width = <4>;
 517                 status = "disabled";
 518         };
 519
 520         uart1: serial@ff190000 {
 521                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff190000 0x0 0x100>;
 523                 clock-frequency = <24000000>;
 524                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 status = "disabled";
 530         };
 531
 532         uart3: serial@ff1b0000 {
 533                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 534                 reg = <0x0 0xff1b0000 0x0 0x100>;
 535                 clock-frequency = <24000000>;
 536                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 537                 clock-names = "baudclk", "apb_pclk";
 538                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 539                 reg-shift = <2>;
 540                 reg-io-width = <4>;
 541                 status = "disabled";
 542         };
 543
 544         uart4: serial@ff1c0000 {
 545                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 546                 reg = <0x0 0xff1c0000 0x0 0x100>;
 547                 clock-frequency = <24000000>;
 548                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 549                 clock-names = "baudclk", "apb_pclk";
 550                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 551                 reg-shift = <2>;
 552                 reg-io-width = <4>;
 553                 status = "disabled";
 554         };
 555
 556         thermal-zones {
 557                 cpu {
 558                         polling-delay-passive = <100>; /* milliseconds */
 559                         polling-delay = <5000>; /* milliseconds */
 560
 561                         thermal-sensors = <&tsadc 0>;
 562
 563                         trips {
 564                                 cpu_alert0: cpu_alert0 {
 565                                         temperature = <75000>; /* millicelsius */
 566                                         hysteresis = <2000>; /* millicelsius */
 567                                         type = "passive";
 568                                 };
 569                                 cpu_alert1: cpu_alert1 {
 570                                         temperature = <80000>; /* millicelsius */
 571                                         hysteresis = <2000>; /* millicelsius */
 572                                         type = "passive";
 573                                 };
 574                                 cpu_crit: cpu_crit {
 575                                         temperature = <95000>; /* millicelsius */
 576                                         hysteresis = <2000>; /* millicelsius */
 577                                         type = "critical";
 578                                 };
 579                         };
 580
 581                         cooling-maps {
 582                                 map0 {
 583                                         trip = <&cpu_alert0>;
 584                                         cooling-device =
 585                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 586                                 };
 587                                 map1 {
 588                                         trip = <&cpu_alert1>;
 589                                         cooling-device =
 590                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 591                                 };
 592                         };
 593                 };
 594
 595                 gpu {
 596                         polling-delay-passive = <100>; /* milliseconds */
 597                         polling-delay = <5000>; /* milliseconds */
 598
 599                         thermal-sensors = <&tsadc 1>;
 600
 601                         trips {
 602                                 gpu_alert0: gpu_alert0 {
 603                                         temperature = <80000>; /* millicelsius */
 604                                         hysteresis = <2000>; /* millicelsius */
 605                                         type = "passive";
 606                                 };
 607                                 gpu_crit: gpu_crit {
 608                                         temperature = <115000>; /* millicelsius */
 609                                         hysteresis = <2000>; /* millicelsius */
 610                                         type = "critical";
 611                                 };
 612                         };
 613
 614                         cooling-maps {
 615                                 map0 {
 616                                         trip = <&gpu_alert0>;
 617                                         cooling-device =
 618                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 619                                 };
 620                         };
 621                 };
 622         };
 623
 624         tsadc: tsadc@ff280000 {
 625                 compatible = "rockchip,rk3368-tsadc";
 626                 reg = <0x0 0xff280000 0x0 0x100>;
 627                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 629                 clock-names = "tsadc", "apb_pclk";
 630                 resets = <&cru SRST_TSADC>;
 631                 reset-names = "tsadc-apb";
 632                 pinctrl-names = "init", "default", "sleep";
 633                 pinctrl-0 = <&otp_gpio>;
 634                 pinctrl-1 = <&otp_out>;
 635                 pinctrl-2 = <&otp_gpio>;
 636                 #thermal-sensor-cells = <1>;
 637                 rockchip,hw-tshut-temp = <95000>;
 638                 status = "disabled";
 639         };
 640
 641         gmac: ethernet@ff290000 {
 642                 compatible = "rockchip,rk3368-gmac";
 643                 reg = <0x0 0xff290000 0x0 0x10000>;
 644                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 645                 interrupt-names = "macirq";
 646                 rockchip,grf = <&grf>;
 647                 clocks = <&cru SCLK_MAC>,
 648                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 649                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 650                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 651                 clock-names = "stmmaceth",
 652                         "mac_clk_rx", "mac_clk_tx",
 653                         "clk_mac_ref", "clk_mac_refout",
 654                         "aclk_mac", "pclk_mac";
 655                 status = "disabled";
 656         };
 657
 658         nandc0: nandc@ff400000 {
 659                 compatible = "rockchip,rk-nandc";
 660                 reg = <0x0 0xff400000 0x0 0x4000>;
 661                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 662                 nandc_id = <0>;
 663                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 664                 clock-names = "clk_nandc", "hclk_nandc";
 665                 status = "disabled";
 666         };
 667
 668         usb_host0_ehci: usb@ff500000 {
 669                 compatible = "generic-ehci";
 670                 reg = <0x0 0xff500000 0x0 0x100>;
 671                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 672                 clocks = <&cru HCLK_HOST0>;
 673                 clock-names = "usbhost";
 674                 status = "disabled";
 675         };
 676
 677         usb_otg: usb@ff580000 {
 678                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 679                                 "snps,dwc2";
 680                 reg = <0x0 0xff580000 0x0 0x40000>;
 681                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 682                 clocks = <&cru HCLK_OTG0>;
 683                 clock-names = "otg";
 684                 dr_mode = "otg";
 685                 g-np-tx-fifo-size = <16>;
 686                 g-rx-fifo-size = <275>;
 687                 g-tx-fifo-size = <256 128 128 64 64 32>;
 688                 g-use-dma;
 689                 status = "disabled";
 690         };
 691
 692         ddrpctl: syscon@ff610000 {
 693                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 694                 reg = <0x0 0xff610000 0x0 0x400>;
 695         };
 696
 697         i2c1: i2c@ff660000 {
 698                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 699                 reg = <0x0 0xff660000 0x0 0x1000>;
 700                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 clock-names = "i2c";
 704                 clocks = <&cru PCLK_I2C1>;
 705                 pinctrl-names = "default";
 706                 pinctrl-0 = <&i2c1_xfer>;
 707                 status = "disabled";
 708         };
 709
 710         pwm0: pwm@ff680000 {
 711                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 712                 reg = <0x0 0xff680000 0x0 0x10>;
 713                 #pwm-cells = <3>;
 714                 pinctrl-names = "default";
 715                 pinctrl-0 = <&pwm0_pin>;
 716                 clocks = <&cru PCLK_PWM1>;
 717                 clock-names = "pwm";
 718                 status = "disabled";
 719         };
 720
 721         pwm1: pwm@ff680010 {
 722                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 723                 reg = <0x0 0xff680010 0x0 0x10>;
 724                 #pwm-cells = <3>;
 725                 pinctrl-names = "default";
 726                 pinctrl-0 = <&pwm1_pin>;
 727                 clocks = <&cru PCLK_PWM1>;
 728                 clock-names = "pwm";
 729                 status = "disabled";
 730         };
 731
 732         pwm2: pwm@ff680020 {
 733                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 734                 reg = <0x0 0xff680020 0x0 0x10>;
 735                 #pwm-cells = <3>;
 736                 clocks = <&cru PCLK_PWM1>;
 737                 clock-names = "pwm";
 738                 status = "disabled";
 739         };
 740
 741         pwm3: pwm@ff680030 {
 742                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 743                 reg = <0x0 0xff680030 0x0 0x10>;
 744                 #pwm-cells = <3>;
 745                 pinctrl-names = "default";
 746                 pinctrl-0 = <&pwm3_pin>;
 747                 clocks = <&cru PCLK_PWM1>;
 748                 clock-names = "pwm";
 749                 status = "disabled";
 750         };
 751
 752         uart2: serial@ff690000 {
 753                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 754                 reg = <0x0 0xff690000 0x0 0x100>;
 755                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 756                 clock-names = "baudclk", "apb_pclk";
 757                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 758                 pinctrl-names = "default";
 759                 pinctrl-0 = <&uart2_xfer>;
 760                 reg-shift = <2>;
 761                 reg-io-width = <4>;
 762                 status = "disabled";
 763         };
 764
 765         mbox: mbox@ff6b0000 {
 766                 compatible = "rockchip,rk3368-mailbox";
 767                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 768                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 769                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 770                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 771                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 772                 clocks = <&cru PCLK_MAILBOX>;
 773                 clock-names = "pclk_mailbox";
 774                 #mbox-cells = <1>;
 775                 status = "disabled";
 776         };
 777
 778         mailbox: mailbox@ff6b0000 {
 779                 compatible = "rockchip,rk3368-mbox-legacy";
 780                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 781                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 782                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 783                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 784                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 785                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 786                 clocks = <&cru PCLK_MAILBOX>;
 787                 clock-names = "pclk_mailbox";
 788                 #mbox-cells = <1>;
 789                 status = "disabled";
 790         };
 791
 792         mailbox_scpi: mailbox-scpi {
 793                 compatible = "rockchip,rk3368-scpi-legacy";
 794                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 795                 chan-nums = <3>;
 796                 status = "disabled";
 797         };
 798
 799         pmu: power-management@ff730000 {
 800                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 801                 reg = <0x0 0xff730000 0x0 0x1000>;
 802
 803                 power: power-controller {
 804                         status = "disabled";
 805                         compatible = "rockchip,rk3368-power-controller";
 806                         #power-domain-cells = <1>;
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809
 810                         /*
 811                          * Note: Although SCLK_* are the working clocks
 812                          * of device without including on the NOC, needed for
 813                          * synchronous reset.
 814                          *
 815                          * The clocks on the which NOC:
 816                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 817                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 818                          * ACLK_RGA is on ACLK_RGA_NIU.
 819                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 820                          *
 821                          * Which clock are device clocks:
 822                          *      clocks          devices
 823                          *      *_IEP           IEP:Image Enhancement Processor
 824                          *      *_ISP           ISP:Image Signal Processing
 825                          *      *_VIP           VIP:Video Input Processor
 826                          *      *_VOP*          VOP:Visual Output Processor
 827                          *      *_RGA           RGA
 828                          *      *_EDP*          EDP
 829                          *      *_DPHY*         LVDS
 830                          *      *_HDMI          HDMI
 831                          *      *_MIPI_*        MIPI
 832                          */
 833                         pd_vio {
 834                                 reg = <RK3368_PD_VIO>;
 835                                 clocks = <&cru ACLK_IEP>,
 836                                          <&cru ACLK_ISP>,
 837                                          <&cru ACLK_VIP>,
 838                                          <&cru ACLK_RGA>,
 839                                          <&cru ACLK_VOP>,
 840                                          <&cru ACLK_VOP_IEP>,
 841                                          <&cru DCLK_VOP>,
 842                                          <&cru HCLK_IEP>,
 843                                          <&cru HCLK_ISP>,
 844                                          <&cru HCLK_RGA>,
 845                                          <&cru HCLK_VIP>,
 846                                          <&cru HCLK_VOP>,
 847                                          <&cru HCLK_VIO_HDCPMMU>,
 848                                          <&cru PCLK_EDP_CTRL>,
 849                                          <&cru PCLK_HDMI_CTRL>,
 850                                          <&cru PCLK_HDCP>,
 851                                          <&cru PCLK_ISP>,
 852                                          <&cru PCLK_VIP>,
 853                                          <&cru PCLK_DPHYRX>,
 854                                          <&cru PCLK_DPHYTX0>,
 855                                          <&cru PCLK_MIPI_CSI>,
 856                                          <&cru PCLK_MIPI_DSI0>,
 857                                          <&cru SCLK_VOP0_PWM>,
 858                                          <&cru SCLK_EDP_24M>,
 859                                          <&cru SCLK_EDP>,
 860                                          <&cru SCLK_HDCP>,
 861                                          <&cru SCLK_ISP>,
 862                                          <&cru SCLK_RGA>,
 863                                          <&cru SCLK_HDMI_CEC>,
 864                                          <&cru SCLK_HDMI_HDCP>;
 865                         };
 866                         /*
 867                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 868                          * (video endecoder & decoder) clocks that on the
 869                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 870                          */
 871                         pd_video {
 872                                 reg = <RK3368_PD_VIDEO>;
 873                                 clocks = <&cru ACLK_VIDEO>,
 874                                          <&cru HCLK_VIDEO>,
 875                                          <&cru SCLK_HEVC_CABAC>,
 876                                          <&cru SCLK_HEVC_CORE>;
 877                         };
 878                         /*
 879                          * Note: ACLK_GPU is the GPU clock,
 880                          * and on the ACLK_GPU_NIU (NOC).
 881                          */
 882                         pd_gpu_1 {
 883                                 reg = <RK3368_PD_GPU_1>;
 884                                 clocks = <&cru ACLK_GPU_CFG>,
 885                                          <&cru ACLK_GPU_MEM>,
 886                                          <&cru SCLK_GPU_CORE>;
 887                         };
 888                 };
 889         };
 890
 891         pmugrf: syscon@ff738000 {
 892                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 893                 reg = <0x0 0xff738000 0x0 0x1000>;
 894
 895                 pmu_io_domains: io-domains {
 896                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 897                         status = "disabled";
 898                 };
 899
 900                 reboot-mode {
 901                         compatible = "syscon-reboot-mode";
 902                         offset = <0x200>;
 903                         mode-normal = <BOOT_NORMAL>;
 904                         mode-recovery = <BOOT_RECOVERY>;
 905                         mode-bootloader = <BOOT_FASTBOOT>;
 906                         mode-loader = <BOOT_BL_DOWNLOAD>;
 907                 };
 908         };
 909
 910         cru: clock-controller@ff760000 {
 911                 compatible = "rockchip,rk3368-cru";
 912                 reg = <0x0 0xff760000 0x0 0x1000>;
 913                 rockchip,grf = <&grf>;
 914                 #clock-cells = <1>;
 915                 #reset-cells = <1>;
 916                 assigned-clocks =
 917                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 918                         <&cru PLL_NPLL>,
 919                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 920                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 921                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 922                 assigned-clock-rates =
 923                         <576000000>, <400000000>,
 924                         <1188000000>,
 925                         <300000000>, <300000000>,
 926                         <150000000>, <150000000>,
 927                         <75000000>, <75000000>;
 928         };
 929
 930         grf: syscon@ff770000 {
 931                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 932                 reg = <0x0 0xff770000 0x0 0x1000>;
 933
 934                 io_domains: io-domains {
 935                         compatible = "rockchip,rk3368-io-voltage-domain";
 936                         status = "disabled";
 937                 };
 938         };
 939
 940         wdt: watchdog@ff800000 {
 941                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 942                 reg = <0x0 0xff800000 0x0 0x100>;
 943                 clocks = <&cru PCLK_WDT>;
 944                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 945                 status = "disabled";
 946         };
 947
 948         timer@ff810000 {
 949                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 950                 reg = <0x0 0xff810000 0x0 0x20>;
 951                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 952         };
 953
 954         i2s_2ch: i2s-2ch@ff890000 {
 955                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 956                 reg = <0x0 0xff890000 0x0 0x1000>;
 957                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 958                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 959                 dma-names = "tx", "rx";
 960                 clock-names = "i2s_clk", "i2s_hclk";
 961                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 962                 status = "disabled";
 963         };
 964
 965         i2s_8ch: i2s-8ch@ff898000 {
 966                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 967                 reg = <0x0 0xff898000 0x0 0x1000>;
 968                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 969                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 970                 dma-names = "tx", "rx";
 971                 clock-names = "i2s_clk", "i2s_hclk";
 972                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 973                 pinctrl-names = "default";
 974                 pinctrl-0 = <&i2s_8ch_bus>;
 975                 status = "disabled";
 976         };
 977
 978         isp_mmu: iommu@ff914000 {
 979                 compatible = "rockchip,iommu";
 980                 reg = <0x0 0xff914000 0x0 0x100>,
 981                       <0x0 0xff915000 0x0 0x100>;
 982                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 983                 interrupt-names = "isp_mmu";
 984                 #iommu-cells = <0>;
 985                 status = "disabled";
 986         };
 987
 988         vop_mmu: iommu@ff930300 {
 989                 compatible = "rockchip,iommu";
 990                 reg = <0x0 0xff930300 0x0 0x100>;
 991                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 992                 interrupt-names = "vop_mmu";
 993                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 994                 clock-names = "aclk", "hclk";
 995                 power-domains = <&power RK3368_PD_VIO>;
 996                 #iommu-cells = <0>;
 997                 status = "disabled";
 998         };
 999
1000         hevc_mmu: iommu@ff9a0440 {
1001                 compatible = "rockchip,iommu";
1002                 reg = <0x0 0xff9a0440 0x0 0x100>,
1003                       <0x0 0xff9a0480 0x0 0x100>;
1004                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1005                 interrupt-names = "hevc_mmu";
1006                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1007                 clock-names = "aclk", "hclk";
1008                 power-domains = <&power RK3368_PD_VIDEO>;
1009                 #iommu-cells = <0>;
1010                 status = "disabled";
1011         };
1012
1013         vpu_mmu: iommu@ff9a0800 {
1014                 compatible = "rockchip,iommu";
1015                 reg = <0x0 0xff9a0800 0x0 0x100>;
1016                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1017                 interrupt-names = "vpu_mmu";
1018                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1019                 clock-names = "aclk", "hclk";
1020                 power-domains = <&power RK3368_PD_VIDEO>;
1021                 #iommu-cells = <0>;
1022                 status = "disabled";
1023         };
1024
1025         gic: interrupt-controller@ffb71000 {
1026                 compatible = "arm,gic-400";
1027                 interrupt-controller;
1028                 #interrupt-cells = <3>;
1029                 #address-cells = <0>;
1030
1031                 reg = <0x0 0xffb71000 0x0 0x1000>,
1032                       <0x0 0xffb72000 0x0 0x2000>,
1033                       <0x0 0xffb74000 0x0 0x2000>,
1034                       <0x0 0xffb76000 0x0 0x2000>;
1035                 interrupts = <GIC_PPI 9
1036                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1037         };
1038
1039         gpu: rogue-g6110@ffa30000 {
1040                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1041                 reg = <0x0 0xffa30000 0x0 0x10000>;
1042                 clocks =
1043                         <&cru SCLK_GPU_CORE>,
1044                         <&cru ACLK_GPU_MEM>,
1045                         <&cru ACLK_GPU_CFG>;
1046                 clock-names =
1047                         "sclk_gpu_core",
1048                         "aclk_gpu_mem",
1049                         "aclk_gpu_cfg";
1050                 operating-points = <
1051                         /* KHz uV */
1052                         200000 1100000
1053                         288000 1100000
1054                         400000 1150000
1055                         576000 1200000
1056                 >;
1057                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1058                 interrupt-names = "rogue-g6110-irq";
1059         };
1060
1061         efuse: efuse@ffb00000 {
1062                 compatible = "rockchip,rk3368-efuse";
1063                 reg = <0x0 0xffb00000 0x0 0x20>;
1064                 #address-cells = <1>;
1065                 #size-cells = <1>;
1066                 clocks = <&cru PCLK_EFUSE256>;
1067                 clock-names = "pclk_efuse";
1068
1069                 /* Data cells */
1070                 cpu_leakage: cpu-leakage@17 {
1071                         reg = <0x17 0x1>;
1072                 };
1073                 temp_adjust: temp-adjust@1f {
1074                         reg = <0x1f 0x1>;
1075                 };
1076         };
1077
1078         pinctrl: pinctrl {
1079                 compatible = "rockchip,rk3368-pinctrl";
1080                 rockchip,grf = <&grf>;
1081                 rockchip,pmu = <&pmugrf>;
1082                 #address-cells = <0x2>;
1083                 #size-cells = <0x2>;
1084                 ranges;
1085
1086                 gpio0: gpio0@ff750000 {
1087                         compatible = "rockchip,gpio-bank";
1088                         reg = <0x0 0xff750000 0x0 0x100>;
1089                         clocks = <&cru PCLK_GPIO0>;
1090                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1091
1092                         gpio-controller;
1093                         #gpio-cells = <0x2>;
1094
1095                         interrupt-controller;
1096                         #interrupt-cells = <0x2>;
1097                 };
1098
1099                 gpio1: gpio1@ff780000 {
1100                         compatible = "rockchip,gpio-bank";
1101                         reg = <0x0 0xff780000 0x0 0x100>;
1102                         clocks = <&cru PCLK_GPIO1>;
1103                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1104
1105                         gpio-controller;
1106                         #gpio-cells = <0x2>;
1107
1108                         interrupt-controller;
1109                         #interrupt-cells = <0x2>;
1110                 };
1111
1112                 gpio2: gpio2@ff790000 {
1113                         compatible = "rockchip,gpio-bank";
1114                         reg = <0x0 0xff790000 0x0 0x100>;
1115                         clocks = <&cru PCLK_GPIO2>;
1116                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1117
1118                         gpio-controller;
1119                         #gpio-cells = <0x2>;
1120
1121                         interrupt-controller;
1122                         #interrupt-cells = <0x2>;
1123                 };
1124
1125                 gpio3: gpio3@ff7a0000 {
1126                         compatible = "rockchip,gpio-bank";
1127                         reg = <0x0 0xff7a0000 0x0 0x100>;
1128                         clocks = <&cru PCLK_GPIO3>;
1129                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1130
1131                         gpio-controller;
1132                         #gpio-cells = <0x2>;
1133
1134                         interrupt-controller;
1135                         #interrupt-cells = <0x2>;
1136                 };
1137
1138                 pcfg_pull_up: pcfg-pull-up {
1139                         bias-pull-up;
1140                 };
1141
1142                 pcfg_pull_down: pcfg-pull-down {
1143                         bias-pull-down;
1144                 };
1145
1146                 pcfg_pull_none: pcfg-pull-none {
1147                         bias-disable;
1148                 };
1149
1150                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1151                         bias-disable;
1152                         drive-strength = <12>;
1153                 };
1154
1155                 emmc {
1156                         emmc_clk: emmc-clk {
1157                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1158                         };
1159
1160                         emmc_cmd: emmc-cmd {
1161                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1162                         };
1163
1164                         emmc_pwr: emmc-pwr {
1165                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1166                         };
1167
1168                         emmc_bus1: emmc-bus1 {
1169                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1170                         };
1171
1172                         emmc_bus4: emmc-bus4 {
1173                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1174                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1175                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1176                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1177                         };
1178
1179                         emmc_bus8: emmc-bus8 {
1180                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1181                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1182                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1183                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1184                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1185                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1186                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1187                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1188                         };
1189                 };
1190
1191                 gmac {
1192                         rgmii_pins: rgmii-pins {
1193                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1194                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1195                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1196                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1197                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1198                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1199                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1200                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1201                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1202                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1203                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1204                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1205                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1206                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1207                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1208                         };
1209
1210                         rmii_pins: rmii-pins {
1211                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1212                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1213                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1214                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1215                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1216                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1217                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1218                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1219                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1220                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1221                         };
1222                 };
1223
1224                 i2c0 {
1225                         i2c0_xfer: i2c0-xfer {
1226                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1227                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1228                         };
1229                 };
1230
1231                 i2c1 {
1232                         i2c1_xfer: i2c1-xfer {
1233                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1234                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236                 };
1237
1238                 i2c2 {
1239                         i2c2_xfer: i2c2-xfer {
1240                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1241                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1242                         };
1243                 };
1244
1245                 i2c3 {
1246                         i2c3_xfer: i2c3-xfer {
1247                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1248                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1249                         };
1250                 };
1251
1252                 i2c4 {
1253                         i2c4_xfer: i2c4-xfer {
1254                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1255                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1256                         };
1257                 };
1258
1259                 i2c5 {
1260                         i2c5_xfer: i2c5-xfer {
1261                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1262                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1263                         };
1264                 };
1265
1266                 i2s {
1267                         i2s_8ch_bus: i2s-8ch-bus {
1268                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1269                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1270                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1271                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1272                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1273                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1274                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1275                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1276                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1277                         };
1278                 };
1279
1280                 pwm0 {
1281                         pwm0_pin: pwm0-pin {
1282                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1283                         };
1284
1285                         vop_pwm_pin: vop-pwm {
1286                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1287                         };
1288                 };
1289
1290                 pwm1 {
1291                         pwm1_pin: pwm1-pin {
1292                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1293                         };
1294                 };
1295
1296                 pwm3 {
1297                         pwm3_pin: pwm3-pin {
1298                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1299                         };
1300                 };
1301
1302                 sdio0 {
1303                         sdio0_bus1: sdio0-bus1 {
1304                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1305                         };
1306
1307                         sdio0_bus4: sdio0-bus4 {
1308                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1309                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1310                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1311                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1312                         };
1313
1314                         sdio0_cmd: sdio0-cmd {
1315                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1316                         };
1317
1318                         sdio0_clk: sdio0-clk {
1319                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321
1322                         sdio0_cd: sdio0-cd {
1323                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1324                         };
1325
1326                         sdio0_wp: sdio0-wp {
1327                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1328                         };
1329
1330                         sdio0_pwr: sdio0-pwr {
1331                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1332                         };
1333
1334                         sdio0_bkpwr: sdio0-bkpwr {
1335                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1336                         };
1337
1338                         sdio0_int: sdio0-int {
1339                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1340                         };
1341                 };
1342
1343                 sdmmc {
1344                         sdmmc_clk: sdmmc-clk {
1345                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1346                         };
1347
1348                         sdmmc_cmd: sdmmc-cmd {
1349                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1350                         };
1351
1352                         sdmmc_cd: sdmmc-cd {
1353                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1354                         };
1355
1356                         sdmmc_bus1: sdmmc-bus1 {
1357                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1358                         };
1359
1360                         sdmmc_bus4: sdmmc-bus4 {
1361                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1362                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1363                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1364                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1365                         };
1366                 };
1367
1368                 spi0 {
1369                         spi0_clk: spi0-clk {
1370                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1371                         };
1372                         spi0_cs0: spi0-cs0 {
1373                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1374                         };
1375                         spi0_cs1: spi0-cs1 {
1376                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1377                         };
1378                         spi0_tx: spi0-tx {
1379                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1380                         };
1381                         spi0_rx: spi0-rx {
1382                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1383                         };
1384                 };
1385
1386                 spi1 {
1387                         spi1_clk: spi1-clk {
1388                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1389                         };
1390                         spi1_cs0: spi1-cs0 {
1391                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1392                         };
1393                         spi1_cs1: spi1-cs1 {
1394                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1395                         };
1396                         spi1_rx: spi1-rx {
1397                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1398                         };
1399                         spi1_tx: spi1-tx {
1400                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1401                         };
1402                 };
1403
1404                 spi2 {
1405                         spi2_clk: spi2-clk {
1406                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1407                         };
1408                         spi2_cs0: spi2-cs0 {
1409                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1410                         };
1411                         spi2_rx: spi2-rx {
1412                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1413                         };
1414                         spi2_tx: spi2-tx {
1415                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1416                         };
1417                 };
1418
1419                 tsadc {
1420                         otp_gpio: otp-gpio {
1421                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1422                         };
1423
1424                         otp_out: otp-out {
1425                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1426                         };
1427                 };
1428
1429                 uart0 {
1430                         uart0_xfer: uart0-xfer {
1431                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1432                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1433                         };
1434
1435                         uart0_cts: uart0-cts {
1436                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1437                         };
1438
1439                         uart0_rts: uart0-rts {
1440                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1441                         };
1442                 };
1443
1444                 uart1 {
1445                         uart1_xfer: uart1-xfer {
1446                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1447                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1448                         };
1449
1450                         uart1_cts: uart1-cts {
1451                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1452                         };
1453
1454                         uart1_rts: uart1-rts {
1455                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 uart2 {
1460                         uart2_xfer: uart2-xfer {
1461                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1462                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1463                         };
1464                         /* no rts / cts for uart2 */
1465                 };
1466
1467                 uart3 {
1468                         uart3_xfer: uart3-xfer {
1469                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1470                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1471                         };
1472
1473                         uart3_cts: uart3-cts {
1474                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1475                         };
1476
1477                         uart3_rts: uart3-rts {
1478                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1479                         };
1480                 };
1481
1482                 uart4 {
1483                         uart4_xfer: uart4-xfer {
1484                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1485                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1486                         };
1487
1488                         uart4_cts: uart4-cts {
1489                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1490                         };
1491
1492                         uart4_rts: uart4-rts {
1493                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1494                         };
1495                 };
1496         };
1497 };