2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
116 entry-method = "psci";
118 cpu_sleep: cpu-sleep-0 {
119 compatible = "arm,idle-state";
120 arm,psci-suspend-param = <0x1010000>;
121 entry-latency-us = <0x3fffffff>;
122 exit-latency-us = <0x40000000>;
123 min-residency-us = <0xffffffff>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 cpu-idle-states = <&cpu_sleep>;
132 enable-method = "psci";
133 clocks = <&cru ARMCLKL>;
134 operating-points-v2 = <&cluster0_opp>;
135 #cooling-cells = <2>; /* min followed by max */
136 dynamic-power-coefficient = <149>;
141 compatible = "arm,cortex-a53", "arm,armv8";
143 cpu-idle-states = <&cpu_sleep>;
144 enable-method = "psci";
145 clocks = <&cru ARMCLKL>;
146 operating-points-v2 = <&cluster0_opp>;
151 compatible = "arm,cortex-a53", "arm,armv8";
153 cpu-idle-states = <&cpu_sleep>;
154 enable-method = "psci";
155 clocks = <&cru ARMCLKL>;
156 operating-points-v2 = <&cluster0_opp>;
161 compatible = "arm,cortex-a53", "arm,armv8";
163 cpu-idle-states = <&cpu_sleep>;
164 enable-method = "psci";
165 clocks = <&cru ARMCLKL>;
166 operating-points-v2 = <&cluster0_opp>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 cpu-idle-states = <&cpu_sleep>;
174 enable-method = "psci";
175 clocks = <&cru ARMCLKB>;
176 operating-points-v2 = <&cluster1_opp>;
177 #cooling-cells = <2>; /* min followed by max */
178 dynamic-power-coefficient = <160>;
183 compatible = "arm,cortex-a53", "arm,armv8";
185 cpu-idle-states = <&cpu_sleep>;
186 enable-method = "psci";
187 clocks = <&cru ARMCLKB>;
188 operating-points-v2 = <&cluster1_opp>;
193 compatible = "arm,cortex-a53", "arm,armv8";
195 cpu-idle-states = <&cpu_sleep>;
196 enable-method = "psci";
197 clocks = <&cru ARMCLKB>;
198 operating-points-v2 = <&cluster1_opp>;
203 compatible = "arm,cortex-a53", "arm,armv8";
205 cpu-idle-states = <&cpu_sleep>;
206 enable-method = "psci";
207 clocks = <&cru ARMCLKB>;
208 operating-points-v2 = <&cluster1_opp>;
212 cluster0_opp: opp_table0 {
213 compatible = "operating-points-v2";
217 opp-hz = /bits/ 64 <216000000>;
218 opp-microvolt = <950000 950000 1350000>;
219 clock-latency-ns = <40000>;
223 opp-hz = /bits/ 64 <408000000>;
224 opp-microvolt = <950000 950000 1350000>;
225 clock-latency-ns = <40000>;
228 opp-hz = /bits/ 64 <600000000>;
229 opp-microvolt = <950000 950000 1350000>;
230 clock-latency-ns = <40000>;
233 opp-hz = /bits/ 64 <816000000>;
234 opp-microvolt = <1025000 1025000 1350000>;
235 clock-latency-ns = <40000>;
238 opp-hz = /bits/ 64 <1008000000>;
239 opp-microvolt = <1125000 1125000 1350000>;
240 clock-latency-ns = <40000>;
243 opp-hz = /bits/ 64 <1200000000>;
244 opp-microvolt = <1225000 1225000 1350000>;
245 clock-latency-ns = <40000>;
249 cluster1_opp: opp_table1 {
250 compatible = "operating-points-v2";
254 opp-hz = /bits/ 64 <216000000>;
255 opp-microvolt = <950000 950000 1350000>;
256 clock-latency-ns = <40000>;
260 opp-hz = /bits/ 64 <408000000>;
261 opp-microvolt = <950000 950000 1350000>;
262 clock-latency-ns = <40000>;
265 opp-hz = /bits/ 64 <600000000>;
266 opp-microvolt = <950000 950000 1350000>;
267 clock-latency-ns = <40000>;
270 opp-hz = /bits/ 64 <816000000>;
271 opp-microvolt = <975000 975000 1350000>;
272 clock-latency-ns = <40000>;
275 opp-hz = /bits/ 64 <1008000000>;
276 opp-microvolt = <1050000 1050000 1350000>;
277 clock-latency-ns = <40000>;
280 opp-hz = /bits/ 64 <1200000000>;
281 opp-microvolt = <1150000 1150000 1350000>;
282 clock-latency-ns = <40000>;
285 opp-hz = /bits/ 64 <1296000000>;
286 opp-microvolt = <1225000 1225000 1350000>;
287 clock-latency-ns = <40000>;
290 opp-hz = /bits/ 64 <1416000000>;
291 opp-microvolt = <1300000 1300000 1350000>;
292 clock-latency-ns = <40000>;
295 opp-hz = /bits/ 64 <1512000000>;
296 opp-microvolt = <1350000 1350000 1350000>;
297 clock-latency-ns = <40000>;
304 min-volt = <950000>; /* uV */
305 min-freq = <216000>; /* KHz */
306 leakage-adjust-volt = <
310 nvmem-cells = <&cpu_leakage>;
311 nvmem-cell-names = "cpu_leakage";
315 min-volt = <950000>; /* uV */
316 min-freq = <216000>; /* KHz */
317 leakage-adjust-volt = <
321 nvmem-cells = <&cpu_leakage>;
322 nvmem-cell-names = "cpu_leakage";
327 compatible = "arm,armv8-pmuv3";
328 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
336 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
337 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
338 <&cpu_b2>, <&cpu_b3>;
342 compatible = "arm,amba-bus";
343 #address-cells = <2>;
347 dmac_peri: dma-controller@ff250000 {
348 compatible = "arm,pl330", "arm,primecell";
349 reg = <0x0 0xff250000 0x0 0x4000>;
350 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
353 clocks = <&cru ACLK_DMAC_PERI>;
354 clock-names = "apb_pclk";
355 arm,pl330-broken-no-flushp;
356 peripherals-req-type-burst;
359 dmac_bus: dma-controller@ff600000 {
360 compatible = "arm,pl330", "arm,primecell";
361 reg = <0x0 0xff600000 0x0 0x4000>;
362 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cru ACLK_DMAC_BUS>;
366 clock-names = "apb_pclk";
367 arm,pl330-broken-no-flushp;
368 peripherals-req-type-burst;
373 compatible = "arm,psci-0.2";
378 compatible = "arm,armv8-timer";
379 interrupts = <GIC_PPI 13
380 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
382 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
384 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
386 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
390 compatible = "fixed-clock";
391 clock-frequency = <24000000>;
392 clock-output-names = "xin24m";
397 compatible = "fixed-clock";
398 clock-frequency = <32768>;
399 clock-output-names = "xin32k";
403 sdmmc: rksdmmc@ff0c0000 {
404 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
405 reg = <0x0 0xff0c0000 0x0 0x4000>;
406 clock-freq-min-max = <400000 150000000>;
407 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
408 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
409 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
410 fifo-depth = <0x100>;
411 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
415 sdio0: dwmmc@ff0d0000 {
416 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
417 reg = <0x0 0xff0d0000 0x0 0x4000>;
418 clock-freq-min-max = <400000 150000000>;
419 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
420 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
421 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
422 fifo-depth = <0x100>;
423 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
427 emmc: rksdmmc@ff0f0000 {
428 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
429 reg = <0x0 0xff0f0000 0x0 0x4000>;
430 clock-freq-min-max = <400000 150000000>;
431 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
432 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
433 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
434 fifo-depth = <0x100>;
435 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
439 saradc: saradc@ff100000 {
440 compatible = "rockchip,saradc";
441 reg = <0x0 0xff100000 0x0 0x100>;
442 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
443 #io-channel-cells = <1>;
444 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
445 clock-names = "saradc", "apb_pclk";
446 resets = <&cru SRST_SARADC>;
447 reset-names = "saradc-apb";
452 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
453 reg = <0x0 0xff110000 0x0 0x1000>;
454 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
455 clock-names = "spiclk", "apb_pclk";
456 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
457 pinctrl-names = "default";
458 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
459 #address-cells = <1>;
465 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
466 reg = <0x0 0xff120000 0x0 0x1000>;
467 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
468 clock-names = "spiclk", "apb_pclk";
469 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
472 #address-cells = <1>;
478 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
479 reg = <0x0 0xff130000 0x0 0x1000>;
480 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
481 clock-names = "spiclk", "apb_pclk";
482 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
485 #address-cells = <1>;
491 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
492 reg = <0x0 0xff650000 0x0 0x1000>;
493 clocks = <&cru PCLK_I2C0>;
495 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&i2c0_xfer>;
498 #address-cells = <1>;
504 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
505 reg = <0x0 0xff140000 0x0 0x1000>;
506 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
507 #address-cells = <1>;
510 clocks = <&cru PCLK_I2C2>;
511 pinctrl-names = "default";
512 pinctrl-0 = <&i2c2_xfer>;
517 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
518 reg = <0x0 0xff150000 0x0 0x1000>;
519 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
523 clocks = <&cru PCLK_I2C3>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&i2c3_xfer>;
530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
531 reg = <0x0 0xff160000 0x0 0x1000>;
532 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
533 #address-cells = <1>;
536 clocks = <&cru PCLK_I2C4>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&i2c4_xfer>;
543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
544 reg = <0x0 0xff170000 0x0 0x1000>;
545 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
549 clocks = <&cru PCLK_I2C5>;
550 pinctrl-names = "default";
551 pinctrl-0 = <&i2c5_xfer>;
555 uart0: serial@ff180000 {
556 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
557 reg = <0x0 0xff180000 0x0 0x100>;
558 clock-frequency = <24000000>;
559 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
560 clock-names = "baudclk", "apb_pclk";
561 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
567 uart1: serial@ff190000 {
568 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
569 reg = <0x0 0xff190000 0x0 0x100>;
570 clock-frequency = <24000000>;
571 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
572 clock-names = "baudclk", "apb_pclk";
573 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
579 uart3: serial@ff1b0000 {
580 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
581 reg = <0x0 0xff1b0000 0x0 0x100>;
582 clock-frequency = <24000000>;
583 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
584 clock-names = "baudclk", "apb_pclk";
585 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
591 uart4: serial@ff1c0000 {
592 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
593 reg = <0x0 0xff1c0000 0x0 0x100>;
594 clock-frequency = <24000000>;
595 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
596 clock-names = "baudclk", "apb_pclk";
597 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
605 polling-delay-passive = <300>; /* milliseconds */
606 polling-delay = <300>; /* milliseconds */
607 sustainable-power = <600>; /* milliwatts */
609 thermal-sensors = <&tsadc 0>;
611 cpu_alert0: cpu_alert0 {
612 temperature = <70000>; /* millicelsius */
613 hysteresis = <2000>; /* millicelsius */
616 cpu_alert1: cpu_alert1 {
617 temperature = <80000>; /* millicelsius */
618 hysteresis = <2000>; /* millicelsius */
622 temperature = <90000>; /* millicelsius */
623 hysteresis = <2000>; /* millicelsius */
630 trip = <&cpu_alert1>;
632 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
633 contribution = <1024>;
636 trip = <&cpu_alert1>;
638 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
639 contribution = <1024>;
644 gpu_thermal: gpu-thermal {
645 polling-delay-passive = <300>; /* milliseconds */
646 polling-delay = <300>; /* milliseconds */
647 thermal-sensors = <&tsadc 1>;
651 tsadc: tsadc@ff280000 {
652 compatible = "rockchip,rk3368-tsadc-legacy";
653 reg = <0x0 0xff280000 0x0 0x100>;
654 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
656 clock-names = "tsadc", "apb_pclk";
657 clock-frequency = <32768>;
658 resets = <&cru SRST_TSADC>;
659 reset-names = "tsadc-apb";
660 nvmem-cells = <&temp_adjust>;
661 nvmem-cell-names = "temp_adjust";
662 #thermal-sensor-cells = <1>;
663 hw-shut-temp = <95000>;
667 gmac: ethernet@ff290000 {
668 compatible = "rockchip,rk3368-gmac";
669 reg = <0x0 0xff290000 0x0 0x10000>;
670 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
671 interrupt-names = "macirq";
672 rockchip,grf = <&grf>;
673 clocks = <&cru SCLK_MAC>,
674 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
675 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
676 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
677 clock-names = "stmmaceth",
678 "mac_clk_rx", "mac_clk_tx",
679 "clk_mac_ref", "clk_mac_refout",
680 "aclk_mac", "pclk_mac";
684 nandc0: nandc@ff400000 {
685 compatible = "rockchip,rk-nandc";
686 reg = <0x0 0xff400000 0x0 0x4000>;
687 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
690 clock-names = "clk_nandc", "hclk_nandc";
694 usb_host0_ehci: usb@ff500000 {
695 compatible = "generic-ehci";
696 reg = <0x0 0xff500000 0x0 0x20000>;
697 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&cru HCLK_HOST0>, <&u2phy>;
699 clock-names = "usbhost", "utmi";
700 phys = <&u2phy_host>;
705 usb_host0_ohci: usb@ff520000 {
706 compatible = "generic-ohci";
707 reg = <0x0 0xff520000 0x0 0x20000>;
708 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru HCLK_HOST0>, <&u2phy>;
710 clock-names = "usbhost", "utmi";
711 phys = <&u2phy_host>;
716 usb_otg: usb@ff580000 {
717 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
719 reg = <0x0 0xff580000 0x0 0x40000>;
720 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
721 clocks = <&cru HCLK_OTG0>;
724 g-np-tx-fifo-size = <16>;
725 g-rx-fifo-size = <275>;
726 g-tx-fifo-size = <256 128 128 64 64 32>;
731 ddrpctl: syscon@ff610000 {
732 compatible = "rockchip,rk3368-ddrpctl", "syscon";
733 reg = <0x0 0xff610000 0x0 0x400>;
737 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
738 reg = <0x0 0xff660000 0x0 0x1000>;
739 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>;
743 clocks = <&cru PCLK_I2C1>;
744 pinctrl-names = "default";
745 pinctrl-0 = <&i2c1_xfer>;
750 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
751 reg = <0x0 0xff680000 0x0 0x10>;
753 pinctrl-names = "default";
754 pinctrl-0 = <&pwm0_pin>;
755 clocks = <&cru PCLK_PWM1>;
761 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
762 reg = <0x0 0xff680010 0x0 0x10>;
764 pinctrl-names = "default";
765 pinctrl-0 = <&pwm1_pin>;
766 clocks = <&cru PCLK_PWM1>;
772 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
773 reg = <0x0 0xff680020 0x0 0x10>;
775 clocks = <&cru PCLK_PWM1>;
781 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
782 reg = <0x0 0xff680030 0x0 0x10>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&pwm3_pin>;
786 clocks = <&cru PCLK_PWM1>;
791 uart2: serial@ff690000 {
792 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
793 reg = <0x0 0xff690000 0x0 0x100>;
794 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
795 clock-names = "baudclk", "apb_pclk";
796 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&uart2_xfer>;
804 mbox: mbox@ff6b0000 {
805 compatible = "rockchip,rk3368-mailbox";
806 reg = <0x0 0xff6b0000 0x0 0x1000>;
807 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&cru PCLK_MAILBOX>;
812 clock-names = "pclk_mailbox";
817 mailbox: mailbox@ff6b0000 {
818 compatible = "rockchip,rk3368-mbox-legacy";
819 reg = <0x0 0xff6b0000 0x0 0x1000>,
820 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
821 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&cru PCLK_MAILBOX>;
826 clock-names = "pclk_mailbox";
831 mailbox_scpi: mailbox-scpi {
832 compatible = "rockchip,rk3368-scpi-legacy";
833 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
838 qos_iep: qos@ffad0000 {
839 compatible = "syscon";
840 reg = <0x0 0xffad0000 0x0 0x20>;
843 qos_isp_r0: qos@ffad0080 {
844 compatible = "syscon";
845 reg = <0x0 0xffad0080 0x0 0x20>;
848 qos_isp_r1: qos@ffad0100 {
849 compatible = "syscon";
850 reg = <0x0 0xffad0100 0x0 0x20>;
853 qos_isp_w0: qos@ffad0180 {
854 compatible = "syscon";
855 reg = <0x0 0xffad0180 0x0 0x20>;
858 qos_isp_w1: qos@ffad0200 {
859 compatible = "syscon";
860 reg = <0x0 0xffad0200 0x0 0x20>;
863 qos_vip: qos@ffad0280 {
864 compatible = "syscon";
865 reg = <0x0 0xffad0280 0x0 0x20>;
868 qos_vop: qos@ffad0300 {
869 compatible = "syscon";
870 reg = <0x0 0xffad0300 0x0 0x20>;
873 qos_rga_r: qos@ffad0380 {
874 compatible = "syscon";
875 reg = <0x0 0xffad0380 0x0 0x20>;
878 qos_rga_w: qos@ffad0400 {
879 compatible = "syscon";
880 reg = <0x0 0xffad0400 0x0 0x20>;
883 qos_hevc_r: qos@ffae0000 {
884 compatible = "syscon";
885 reg = <0x0 0xffae0000 0x0 0x20>;
888 qos_vpu_r: qos@ffae0100 {
889 compatible = "syscon";
890 reg = <0x0 0xffae0100 0x0 0x20>;
893 qos_vpu_w: qos@ffae0180 {
894 compatible = "syscon";
895 reg = <0x0 0xffae0180 0x0 0x20>;
898 qos_gpu: qos@ffaf0000 {
899 compatible = "syscon";
900 reg = <0x0 0xffaf0000 0x0 0x20>;
903 pmu: power-management@ff730000 {
904 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
905 reg = <0x0 0xff730000 0x0 0x1000>;
907 power: power-controller {
908 compatible = "rockchip,rk3368-power-controller";
909 #power-domain-cells = <1>;
910 #address-cells = <1>;
914 * Note: Although SCLK_* are the working clocks
915 * of device without including on the NOC, needed for
918 * The clocks on the which NOC:
919 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
920 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
921 * ACLK_RGA is on ACLK_RGA_NIU.
922 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
924 * Which clock are device clocks:
926 * *_IEP IEP:Image Enhancement Processor
927 * *_ISP ISP:Image Signal Processing
928 * *_VIP VIP:Video Input Processor
929 * *_VOP* VOP:Visual Output Processor
937 reg = <RK3368_PD_VIO>;
938 clocks = <&cru ACLK_IEP>,
950 <&cru HCLK_VIO_HDCPMMU>,
951 <&cru PCLK_EDP_CTRL>,
952 <&cru PCLK_HDMI_CTRL>,
958 <&cru PCLK_MIPI_CSI>,
959 <&cru PCLK_MIPI_DSI0>,
960 <&cru SCLK_VOP0_PWM>,
966 <&cru SCLK_HDMI_CEC>,
967 <&cru SCLK_HDMI_HDCP>;
979 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
980 * (video endecoder & decoder) clocks that on the
981 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
984 reg = <RK3368_PD_VIDEO>;
985 clocks = <&cru ACLK_VIDEO>,
987 <&cru SCLK_HEVC_CABAC>,
988 <&cru SCLK_HEVC_CORE>;
989 pm_qos = <&qos_hevc_r>,
994 * Note: ACLK_GPU is the GPU clock,
995 * and on the ACLK_GPU_NIU (NOC).
998 reg = <RK3368_PD_GPU_1>;
999 clocks = <&cru ACLK_GPU_CFG>,
1000 <&cru ACLK_GPU_MEM>,
1001 <&cru SCLK_GPU_CORE>;
1002 pm_qos = <&qos_gpu>;
1007 pmugrf: syscon@ff738000 {
1008 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1009 reg = <0x0 0xff738000 0x0 0x1000>;
1011 pmu_io_domains: io-domains {
1012 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1013 status = "disabled";
1017 compatible = "syscon-reboot-mode";
1019 mode-normal = <BOOT_NORMAL>;
1020 mode-recovery = <BOOT_RECOVERY>;
1021 mode-bootloader = <BOOT_FASTBOOT>;
1022 mode-loader = <BOOT_BL_DOWNLOAD>;
1026 cru: clock-controller@ff760000 {
1027 compatible = "rockchip,rk3368-cru";
1028 reg = <0x0 0xff760000 0x0 0x1000>;
1029 rockchip,grf = <&grf>;
1033 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1034 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1035 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1036 <&cru PCLK_BUS>, <&cru PCLK_PERI>;
1037 assigned-clock-rates =
1038 <576000000>, <400000000>,
1039 <300000000>, <300000000>,
1040 <150000000>, <150000000>,
1041 <75000000>, <75000000>;
1044 grf: syscon@ff770000 {
1045 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1046 reg = <0x0 0xff770000 0x0 0x1000>;
1047 #address-cells = <1>;
1050 io_domains: io-domains {
1051 compatible = "rockchip,rk3368-io-voltage-domain";
1052 status = "disabled";
1055 u2phy: usb2-phy@700 {
1056 compatible = "rockchip,rk3368-usb2phy";
1058 clocks = <&cru SCLK_OTGPHY0>;
1059 clock-names = "phyclk";
1061 clock-output-names = "usbotg_out";
1062 assigned-clocks = <&cru SCLK_USBPHY480M>;
1063 assigned-clock-parents = <&u2phy>;
1064 status = "disabled";
1066 u2phy_host: host-port {
1068 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1069 interrupt-names = "linestate";
1070 status = "disabled";
1075 wdt: watchdog@ff800000 {
1076 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1077 reg = <0x0 0xff800000 0x0 0x100>;
1078 clocks = <&cru PCLK_WDT>;
1079 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1080 status = "disabled";
1084 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1085 reg = <0x0 0xff810000 0x0 0x20>;
1086 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1089 i2s_2ch: i2s-2ch@ff890000 {
1090 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1091 reg = <0x0 0xff890000 0x0 0x1000>;
1092 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1093 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1094 dma-names = "tx", "rx";
1095 clock-names = "i2s_clk", "i2s_hclk";
1096 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1097 status = "disabled";
1100 i2s_8ch: i2s-8ch@ff898000 {
1101 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1102 reg = <0x0 0xff898000 0x0 0x1000>;
1103 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1104 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1105 dma-names = "tx", "rx";
1106 clock-names = "i2s_clk", "i2s_hclk";
1107 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&i2s_8ch_bus>;
1110 status = "disabled";
1113 isp_mmu: iommu@ff914000 {
1114 compatible = "rockchip,iommu";
1115 reg = <0x0 0xff914000 0x0 0x100>,
1116 <0x0 0xff915000 0x0 0x100>;
1117 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "isp_mmu";
1120 status = "disabled";
1124 compatible = "rockchip,rk3368-vop";
1125 reg = <0x0 0xff930000 0x0 0x2fc>;
1126 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1128 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1129 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1130 assigned-clock-rates = <400000000>, <200000000>;
1131 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1132 reset-names = "axi", "ahb", "dclk";
1133 power-domains = <&power RK3368_PD_VIO>;
1134 iommus = <&vop_mmu>;
1135 status = "disabled";
1138 #address-cells = <1>;
1141 vop_out_mipi: endpoint@0 {
1143 remote-endpoint = <&mipi_in_vop>;
1148 display_subsystem: display-subsystem {
1149 compatible = "rockchip,display-subsystem";
1151 status = "disabled";
1154 vop_mmu: iommu@ff930300 {
1155 compatible = "rockchip,iommu";
1156 reg = <0x0 0xff930300 0x0 0x100>;
1157 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1158 interrupt-names = "vop_mmu";
1159 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1160 clock-names = "aclk", "hclk";
1161 power-domains = <&power RK3368_PD_VIO>;
1163 status = "disabled";
1166 mipi_dsi_host: mipi-dsi-host@ff960000 {
1167 compatible = "rockchip,rk3368-mipi-dsi";
1168 reg = <0x0 0xff960000 0x0 0x4000>;
1169 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cru PCLK_MIPI_DSI0>;
1171 clock-names = "pclk";
1172 phys = <&mipi_dphy>;
1173 phy-names = "mipi_dphy";
1174 rockchip,grf = <&grf>;
1175 power-domains = <&power RK3368_PD_VIO>;
1176 #address-cells = <1>;
1178 status = "disabled";
1181 #address-cells = <1>;
1186 #address-cells = <1>;
1189 mipi_in_vop: endpoint@0 {
1191 remote-endpoint = <&vop_out_mipi>;
1197 mipi_dphy: mipi-dphy@ff968000 {
1198 compatible = "rockchip,rk3368-mipi-dphy";
1199 reg = <0x0 0xff968000 0x0 0x4000>;
1201 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1202 clock-names = "ref", "pclk";
1203 status = "disabled";
1206 hevc_mmu: iommu@ff9a0440 {
1207 compatible = "rockchip,iommu";
1208 reg = <0x0 0xff9a0440 0x0 0x100>,
1209 <0x0 0xff9a0480 0x0 0x100>;
1210 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1211 interrupt-names = "hevc_mmu";
1212 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1213 clock-names = "aclk", "hclk";
1214 power-domains = <&power RK3368_PD_VIDEO>;
1216 status = "disabled";
1219 vpu_mmu: iommu@ff9a0800 {
1220 compatible = "rockchip,iommu";
1221 reg = <0x0 0xff9a0800 0x0 0x100>;
1222 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1223 interrupt-names = "vpu_mmu";
1224 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1225 clock-names = "aclk", "hclk";
1226 power-domains = <&power RK3368_PD_VIDEO>;
1228 status = "disabled";
1231 gic: interrupt-controller@ffb71000 {
1232 compatible = "arm,gic-400";
1233 interrupt-controller;
1234 #interrupt-cells = <3>;
1235 #address-cells = <0>;
1237 reg = <0x0 0xffb71000 0x0 0x1000>,
1238 <0x0 0xffb72000 0x0 0x2000>,
1239 <0x0 0xffb74000 0x0 0x2000>,
1240 <0x0 0xffb76000 0x0 0x2000>;
1241 interrupts = <GIC_PPI 9
1242 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1245 gpu: rogue-g6110@ffa30000 {
1246 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1247 reg = <0x0 0xffa30000 0x0 0x10000>;
1249 <&cru SCLK_GPU_CORE>,
1250 <&cru ACLK_GPU_MEM>,
1251 <&cru ACLK_GPU_CFG>;
1256 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1257 interrupt-names = "rogue-g6110-irq";
1258 power-domains = <&power RK3368_PD_GPU_1>;
1259 operating-points-v2 = <&gpu_opp_table>;
1262 gpu_opp_table: gpu_opp_table {
1263 compatible = "operating-points-v2";
1267 opp-hz = /bits/ 64 <200000000>;
1268 opp-microvolt = <1100000>;
1271 opp-hz = /bits/ 64 <288000000>;
1272 opp-microvolt = <1100000>;
1275 opp-hz = /bits/ 64 <400000000>;
1276 opp-microvolt = <1100000>;
1279 opp-hz = /bits/ 64 <576000000>;
1280 opp-microvolt = <1200000>;
1284 efuse: efuse@ffb00000 {
1285 compatible = "rockchip,rk3368-efuse";
1286 reg = <0x0 0xffb00000 0x0 0x20>;
1287 #address-cells = <1>;
1289 clocks = <&cru PCLK_EFUSE256>;
1290 clock-names = "pclk_efuse";
1293 cpu_leakage: cpu-leakage@17 {
1296 temp_adjust: temp-adjust@1f {
1302 compatible = "rockchip,rk3368-pinctrl";
1303 rockchip,grf = <&grf>;
1304 rockchip,pmu = <&pmugrf>;
1305 #address-cells = <0x2>;
1306 #size-cells = <0x2>;
1309 gpio0: gpio0@ff750000 {
1310 compatible = "rockchip,gpio-bank";
1311 reg = <0x0 0xff750000 0x0 0x100>;
1312 clocks = <&cru PCLK_GPIO0>;
1313 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1316 #gpio-cells = <0x2>;
1318 interrupt-controller;
1319 #interrupt-cells = <0x2>;
1322 gpio1: gpio1@ff780000 {
1323 compatible = "rockchip,gpio-bank";
1324 reg = <0x0 0xff780000 0x0 0x100>;
1325 clocks = <&cru PCLK_GPIO1>;
1326 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1329 #gpio-cells = <0x2>;
1331 interrupt-controller;
1332 #interrupt-cells = <0x2>;
1335 gpio2: gpio2@ff790000 {
1336 compatible = "rockchip,gpio-bank";
1337 reg = <0x0 0xff790000 0x0 0x100>;
1338 clocks = <&cru PCLK_GPIO2>;
1339 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1342 #gpio-cells = <0x2>;
1344 interrupt-controller;
1345 #interrupt-cells = <0x2>;
1348 gpio3: gpio3@ff7a0000 {
1349 compatible = "rockchip,gpio-bank";
1350 reg = <0x0 0xff7a0000 0x0 0x100>;
1351 clocks = <&cru PCLK_GPIO3>;
1352 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1355 #gpio-cells = <0x2>;
1357 interrupt-controller;
1358 #interrupt-cells = <0x2>;
1361 pcfg_pull_up: pcfg-pull-up {
1365 pcfg_pull_down: pcfg-pull-down {
1369 pcfg_pull_none: pcfg-pull-none {
1373 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1375 drive-strength = <12>;
1379 emmc_clk: emmc-clk {
1380 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1383 emmc_cmd: emmc-cmd {
1384 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1387 emmc_pwr: emmc-pwr {
1388 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1391 emmc_bus1: emmc-bus1 {
1392 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1395 emmc_bus4: emmc-bus4 {
1396 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1397 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1398 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1399 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1402 emmc_bus8: emmc-bus8 {
1403 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1404 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1405 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1406 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1407 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1408 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1409 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1410 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1415 rgmii_pins: rgmii-pins {
1416 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1417 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1418 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1419 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1420 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1421 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1422 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1423 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1424 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1425 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1426 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1427 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1428 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1429 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1430 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1433 rmii_pins: rmii-pins {
1434 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1435 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1436 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1437 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1438 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1439 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1440 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1441 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1442 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1443 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1448 i2c0_xfer: i2c0-xfer {
1449 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1450 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1455 i2c1_xfer: i2c1-xfer {
1456 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1457 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1462 i2c2_xfer: i2c2-xfer {
1463 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1464 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1469 i2c3_xfer: i2c3-xfer {
1470 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1471 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1476 i2c4_xfer: i2c4-xfer {
1477 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1478 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1483 i2c5_xfer: i2c5-xfer {
1484 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1485 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1490 i2s_8ch_bus: i2s-8ch-bus {
1491 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1492 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1493 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1494 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1495 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1496 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1497 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1498 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1499 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1504 pwm0_pin: pwm0-pin {
1505 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1508 vop_pwm_pin: vop-pwm {
1509 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1514 pwm1_pin: pwm1-pin {
1515 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1520 pwm3_pin: pwm3-pin {
1521 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1526 sdio0_bus1: sdio0-bus1 {
1527 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1530 sdio0_bus4: sdio0-bus4 {
1531 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1532 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1533 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1534 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1537 sdio0_cmd: sdio0-cmd {
1538 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1541 sdio0_clk: sdio0-clk {
1542 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1545 sdio0_cd: sdio0-cd {
1546 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1549 sdio0_wp: sdio0-wp {
1550 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1553 sdio0_pwr: sdio0-pwr {
1554 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1557 sdio0_bkpwr: sdio0-bkpwr {
1558 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1561 sdio0_int: sdio0-int {
1562 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1567 sdmmc_clk: sdmmc-clk {
1568 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1571 sdmmc_cmd: sdmmc-cmd {
1572 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1575 sdmmc_cd: sdmmc-cd {
1576 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1579 sdmmc_bus1: sdmmc-bus1 {
1580 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1583 sdmmc_bus4: sdmmc-bus4 {
1584 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1585 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1586 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1587 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1592 spi0_clk: spi0-clk {
1593 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1595 spi0_cs0: spi0-cs0 {
1596 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1598 spi0_cs1: spi0-cs1 {
1599 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1602 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1605 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1610 spi1_clk: spi1-clk {
1611 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1613 spi1_cs0: spi1-cs0 {
1614 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1616 spi1_cs1: spi1-cs1 {
1617 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1620 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1623 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1628 spi2_clk: spi2-clk {
1629 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1631 spi2_cs0: spi2-cs0 {
1632 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1635 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1638 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1643 uart0_xfer: uart0-xfer {
1644 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1645 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1648 uart0_cts: uart0-cts {
1649 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1652 uart0_rts: uart0-rts {
1653 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1658 uart1_xfer: uart1-xfer {
1659 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1660 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1663 uart1_cts: uart1-cts {
1664 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1667 uart1_rts: uart1-rts {
1668 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1673 uart2_xfer: uart2-xfer {
1674 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1675 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1677 /* no rts / cts for uart2 */
1681 uart3_xfer: uart3-xfer {
1682 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1683 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1686 uart3_cts: uart3-cts {
1687 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1690 uart3_rts: uart3-rts {
1691 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1696 uart4_xfer: uart4-xfer {
1697 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1698 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1701 uart4_cts: uart4-cts {
1702 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1705 uart4_rts: uart4-rts {
1706 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;