arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3368";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         cpus {
  77                 #address-cells = <0x2>;
  78                 #size-cells = <0x0>;
  79
  80                 cpu-map {
  81                         cluster0 {
  82                                 core0 {
  83                                         cpu = <&cpu_b0>;
  84                                 };
  85                                 core1 {
  86                                         cpu = <&cpu_b1>;
  87                                 };
  88                                 core2 {
  89                                         cpu = <&cpu_b2>;
  90                                 };
  91                                 core3 {
  92                                         cpu = <&cpu_b3>;
  93                                 };
  94                         };
  95
  96                         cluster1 {
  97                                 core0 {
  98                                         cpu = <&cpu_l0>;
  99                                 };
 100                                 core1 {
 101                                         cpu = <&cpu_l1>;
 102                                 };
 103                                 core2 {
 104                                         cpu = <&cpu_l2>;
 105                                 };
 106                                 core3 {
 107                                         cpu = <&cpu_l3>;
 108                                 };
 109                         };
 110                 };
 111
 112                 idle-states {
 113                         entry-method = "psci";
 114
 115                         cpu_sleep: cpu-sleep-0 {
 116                                 compatible = "arm,idle-state";
 117                                 arm,psci-suspend-param = <0x1010000>;
 118                                 entry-latency-us = <0x3fffffff>;
 119                                 exit-latency-us = <0x40000000>;
 120                                 min-residency-us = <0xffffffff>;
 121                         };
 122                 };
 123
 124                 cpu_l0: cpu@0 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a53", "arm,armv8";
 127                         reg = <0x0 0x0>;
 128                         cpu-idle-states = <&cpu_sleep>;
 129                         enable-method = "psci";
 130                         clocks = <&cru ARMCLKL>;
 131                         operating-points-v2 = <&cluster1_opp>;
 132
 133                         #cooling-cells = <2>; /* min followed by max */
 134                 };
 135
 136                 cpu_l1: cpu@1 {
 137                         device_type = "cpu";
 138                         compatible = "arm,cortex-a53", "arm,armv8";
 139                         reg = <0x0 0x1>;
 140                         cpu-idle-states = <&cpu_sleep>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster1_opp>;
 144                 };
 145
 146                 cpu_l2: cpu@2 {
 147                         device_type = "cpu";
 148                         compatible = "arm,cortex-a53", "arm,armv8";
 149                         reg = <0x0 0x2>;
 150                         cpu-idle-states = <&cpu_sleep>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster1_opp>;
 154                 };
 155
 156                 cpu_l3: cpu@3 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a53", "arm,armv8";
 159                         reg = <0x0 0x3>;
 160                         cpu-idle-states = <&cpu_sleep>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKL>;
 163                         operating-points-v2 = <&cluster1_opp>;
 164                 };
 165
 166                 cpu_b0: cpu@100 {
 167                         device_type = "cpu";
 168                         compatible = "arm,cortex-a53", "arm,armv8";
 169                         reg = <0x0 0x100>;
 170                         cpu-idle-states = <&cpu_sleep>;
 171                         enable-method = "psci";
 172                         clocks = <&cru ARMCLKB>;
 173                         operating-points-v2 = <&cluster0_opp>;
 174
 175                         #cooling-cells = <2>; /* min followed by max */
 176                 };
 177
 178                 cpu_b1: cpu@101 {
 179                         device_type = "cpu";
 180                         compatible = "arm,cortex-a53", "arm,armv8";
 181                         reg = <0x0 0x101>;
 182                         cpu-idle-states = <&cpu_sleep>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster0_opp>;
 186                 };
 187
 188                 cpu_b2: cpu@102 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a53", "arm,armv8";
 191                         reg = <0x0 0x102>;
 192                         cpu-idle-states = <&cpu_sleep>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster0_opp>;
 196                 };
 197
 198                 cpu_b3: cpu@103 {
 199                         device_type = "cpu";
 200                         compatible = "arm,cortex-a53", "arm,armv8";
 201                         reg = <0x0 0x103>;
 202                         cpu-idle-states = <&cpu_sleep>;
 203                         enable-method = "psci";
 204                         clocks = <&cru ARMCLKB>;
 205                         operating-points-v2 = <&cluster0_opp>;
 206                 };
 207         };
 208
 209         cluster0_opp: opp_table0 {
 210                 compatible = "operating-points-v2";
 211                 opp-shared;
 212
 213                 opp@408000000 {
 214                         opp-hz = /bits/ 64 <408000000>;
 215                         opp-microvolt = <1200000>;
 216                         clock-latency-ns = <40000>;
 217                         opp-suspend;
 218                 };
 219                 opp@600000000 {
 220                         opp-hz = /bits/ 64 <600000000>;
 221                         opp-microvolt = <1200000>;
 222                 };
 223                 opp@816000000 {
 224                         opp-hz = /bits/ 64 <816000000>;
 225                         opp-microvolt = <1200000>;
 226                 };
 227                 opp@1008000000 {
 228                         opp-hz = /bits/ 64 <1008000000>;
 229                         opp-microvolt = <1200000>;
 230                 };
 231                 opp@1200000000 {
 232                         opp-hz = /bits/ 64 <1200000000>;
 233                         opp-microvolt = <1200000>;
 234                 };
 235         };
 236
 237         cluster1_opp: opp_table1 {
 238                 compatible = "operating-points-v2";
 239                 opp-shared;
 240
 241                 opp@408000000 {
 242                         opp-hz = /bits/ 64 <408000000>;
 243                         opp-microvolt = <1200000>;
 244                         clock-latency-ns = <40000>;
 245                         opp-suspend;
 246                 };
 247                 opp@600000000 {
 248                         opp-hz = /bits/ 64 <600000000>;
 249                         opp-microvolt = <1200000>;
 250                 };
 251                 opp@816000000 {
 252                         opp-hz = /bits/ 64 <816000000>;
 253                         opp-microvolt = <1200000>;
 254                 };
 255                 opp@1008000000 {
 256                         opp-hz = /bits/ 64 <1008000000>;
 257                         opp-microvolt = <1200000>;
 258                 };
 259         };
 260
 261         cpu_avs: cpu-avs {
 262                 cluster0-avs {
 263                         cluster-id = <0>;
 264                         min-volt = <950000>; /* uV */
 265                         min-freq = <216000>; /* KHz */
 266                         leakage-adjust-volt = <
 267                         /*  mA        mA         uV */
 268                             0         254        0
 269                         >;
 270                         nvmem-cells = <&cpu_leakage>;
 271                         nvmem-cell-names = "cpu_leakage";
 272                 };
 273                 cluster1-avs {
 274                         cluster-id = <1>;
 275                         min-volt = <950000>; /* uV */
 276                         min-freq = <216000>; /* KHz */
 277                         leakage-adjust-volt = <
 278                         /*  mA        mA         uV */
 279                             0         254        0
 280                         >;
 281                         nvmem-cells = <&cpu_leakage>;
 282                         nvmem-cell-names = "cpu_leakage";
 283                 };
 284         };
 285
 286         arm-pmu {
 287                 compatible = "arm,armv8-pmuv3";
 288                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 294                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 295                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 296                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 297                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 298                                      <&cpu_b2>, <&cpu_b3>;
 299         };
 300
 301         amba {
 302                 compatible = "arm,amba-bus";
 303                 #address-cells = <2>;
 304                 #size-cells = <2>;
 305                 ranges;
 306
 307                 dmac_peri: dma-controller@ff250000 {
 308                         compatible = "arm,pl330", "arm,primecell";
 309                         reg = <0x0 0xff250000 0x0 0x4000>;
 310                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 311                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 312                         #dma-cells = <1>;
 313                         clocks = <&cru ACLK_DMAC_PERI>;
 314                         clock-names = "apb_pclk";
 315                         arm,pl330-broken-no-flushp;
 316                         peripherals-req-type-burst;
 317                 };
 318
 319                 dmac_bus: dma-controller@ff600000 {
 320                         compatible = "arm,pl330", "arm,primecell";
 321                         reg = <0x0 0xff600000 0x0 0x4000>;
 322                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 323                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 324                         #dma-cells = <1>;
 325                         clocks = <&cru ACLK_DMAC_BUS>;
 326                         clock-names = "apb_pclk";
 327                         arm,pl330-broken-no-flushp;
 328                         peripherals-req-type-burst;
 329                 };
 330         };
 331
 332         psci {
 333                 compatible = "arm,psci-0.2";
 334                 method = "smc";
 335         };
 336
 337         timer {
 338                 compatible = "arm,armv8-timer";
 339                 interrupts = <GIC_PPI 13
 340                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 341                              <GIC_PPI 14
 342                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 343                              <GIC_PPI 11
 344                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 345                              <GIC_PPI 10
 346                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 347         };
 348
 349         xin24m: oscillator {
 350                 compatible = "fixed-clock";
 351                 clock-frequency = <24000000>;
 352                 clock-output-names = "xin24m";
 353                 #clock-cells = <0>;
 354         };
 355
 356         sdmmc: rksdmmc@ff0c0000 {
 357                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 358                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 359                 clock-freq-min-max = <400000 150000000>;
 360                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 361                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 362                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 363                 fifo-depth = <0x100>;
 364                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 365                 status = "disabled";
 366         };
 367
 368         sdio0: dwmmc@ff0d0000 {
 369                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 370                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 371                 clock-freq-min-max = <400000 150000000>;
 372                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 373                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 374                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 375                 fifo-depth = <0x100>;
 376                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 377                 status = "disabled";
 378         };
 379
 380         emmc: rksdmmc@ff0f0000 {
 381                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 382                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 383                 clock-freq-min-max = <400000 150000000>;
 384                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 385                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 386                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 387                 fifo-depth = <0x100>;
 388                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 389                 status = "disabled";
 390         };
 391
 392         saradc: saradc@ff100000 {
 393                 compatible = "rockchip,saradc";
 394                 reg = <0x0 0xff100000 0x0 0x100>;
 395                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 396                 #io-channel-cells = <1>;
 397                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 398                 clock-names = "saradc", "apb_pclk";
 399                 resets = <&cru SRST_SARADC>;
 400                 reset-names = "saradc-apb";
 401                 status = "disabled";
 402         };
 403
 404         spi0: spi@ff110000 {
 405                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 406                 reg = <0x0 0xff110000 0x0 0x1000>;
 407                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 408                 clock-names = "spiclk", "apb_pclk";
 409                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 412                 #address-cells = <1>;
 413                 #size-cells = <0>;
 414                 status = "disabled";
 415         };
 416
 417         spi1: spi@ff120000 {
 418                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 419                 reg = <0x0 0xff120000 0x0 0x1000>;
 420                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 421                 clock-names = "spiclk", "apb_pclk";
 422                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 425                 #address-cells = <1>;
 426                 #size-cells = <0>;
 427                 status = "disabled";
 428         };
 429
 430         spi2: spi@ff130000 {
 431                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 432                 reg = <0x0 0xff130000 0x0 0x1000>;
 433                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 434                 clock-names = "spiclk", "apb_pclk";
 435                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 438                 #address-cells = <1>;
 439                 #size-cells = <0>;
 440                 status = "disabled";
 441         };
 442
 443         i2c0: i2c@ff650000 {
 444                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 445                 reg = <0x0 0xff650000 0x0 0x1000>;
 446                 clocks = <&cru PCLK_I2C0>;
 447                 clock-names = "i2c";
 448                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c0_xfer>;
 451                 #address-cells = <1>;
 452                 #size-cells = <0>;
 453                 status = "disabled";
 454         };
 455
 456         i2c2: i2c@ff140000 {
 457                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 458                 reg = <0x0 0xff140000 0x0 0x1000>;
 459                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 460                 #address-cells = <1>;
 461                 #size-cells = <0>;
 462                 clock-names = "i2c";
 463                 clocks = <&cru PCLK_I2C2>;
 464                 pinctrl-names = "default";
 465                 pinctrl-0 = <&i2c2_xfer>;
 466                 status = "disabled";
 467         };
 468
 469         i2c3: i2c@ff150000 {
 470                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 471                 reg = <0x0 0xff150000 0x0 0x1000>;
 472                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 473                 #address-cells = <1>;
 474                 #size-cells = <0>;
 475                 clock-names = "i2c";
 476                 clocks = <&cru PCLK_I2C3>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&i2c3_xfer>;
 479                 status = "disabled";
 480         };
 481
 482         i2c4: i2c@ff160000 {
 483                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 484                 reg = <0x0 0xff160000 0x0 0x1000>;
 485                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 486                 #address-cells = <1>;
 487                 #size-cells = <0>;
 488                 clock-names = "i2c";
 489                 clocks = <&cru PCLK_I2C4>;
 490                 pinctrl-names = "default";
 491                 pinctrl-0 = <&i2c4_xfer>;
 492                 status = "disabled";
 493         };
 494
 495         i2c5: i2c@ff170000 {
 496                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 497                 reg = <0x0 0xff170000 0x0 0x1000>;
 498                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 499                 #address-cells = <1>;
 500                 #size-cells = <0>;
 501                 clock-names = "i2c";
 502                 clocks = <&cru PCLK_I2C5>;
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&i2c5_xfer>;
 505                 status = "disabled";
 506         };
 507
 508         uart0: serial@ff180000 {
 509                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 510                 reg = <0x0 0xff180000 0x0 0x100>;
 511                 clock-frequency = <24000000>;
 512                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 515                 reg-shift = <2>;
 516                 reg-io-width = <4>;
 517                 status = "disabled";
 518         };
 519
 520         uart1: serial@ff190000 {
 521                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 522                 reg = <0x0 0xff190000 0x0 0x100>;
 523                 clock-frequency = <24000000>;
 524                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 525                 clock-names = "baudclk", "apb_pclk";
 526                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 527                 reg-shift = <2>;
 528                 reg-io-width = <4>;
 529                 status = "disabled";
 530         };
 531
 532         uart3: serial@ff1b0000 {
 533                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 534                 reg = <0x0 0xff1b0000 0x0 0x100>;
 535                 clock-frequency = <24000000>;
 536                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 537                 clock-names = "baudclk", "apb_pclk";
 538                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 539                 reg-shift = <2>;
 540                 reg-io-width = <4>;
 541                 status = "disabled";
 542         };
 543
 544         uart4: serial@ff1c0000 {
 545                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 546                 reg = <0x0 0xff1c0000 0x0 0x100>;
 547                 clock-frequency = <24000000>;
 548                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 549                 clock-names = "baudclk", "apb_pclk";
 550                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 551                 reg-shift = <2>;
 552                 reg-io-width = <4>;
 553                 status = "disabled";
 554         };
 555
 556         thermal-zones {
 557                 cpu {
 558                         polling-delay-passive = <100>; /* milliseconds */
 559                         polling-delay = <5000>; /* milliseconds */
 560
 561                         thermal-sensors = <&tsadc 0>;
 562
 563                         trips {
 564                                 cpu_alert0: cpu_alert0 {
 565                                         temperature = <75000>; /* millicelsius */
 566                                         hysteresis = <2000>; /* millicelsius */
 567                                         type = "passive";
 568                                 };
 569                                 cpu_alert1: cpu_alert1 {
 570                                         temperature = <80000>; /* millicelsius */
 571                                         hysteresis = <2000>; /* millicelsius */
 572                                         type = "passive";
 573                                 };
 574                                 cpu_crit: cpu_crit {
 575                                         temperature = <95000>; /* millicelsius */
 576                                         hysteresis = <2000>; /* millicelsius */
 577                                         type = "critical";
 578                                 };
 579                         };
 580
 581                         cooling-maps {
 582                                 map0 {
 583                                         trip = <&cpu_alert0>;
 584                                         cooling-device =
 585                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 586                                 };
 587                                 map1 {
 588                                         trip = <&cpu_alert1>;
 589                                         cooling-device =
 590                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 591                                 };
 592                         };
 593                 };
 594
 595                 gpu {
 596                         polling-delay-passive = <100>; /* milliseconds */
 597                         polling-delay = <5000>; /* milliseconds */
 598
 599                         thermal-sensors = <&tsadc 1>;
 600
 601                         trips {
 602                                 gpu_alert0: gpu_alert0 {
 603                                         temperature = <80000>; /* millicelsius */
 604                                         hysteresis = <2000>; /* millicelsius */
 605                                         type = "passive";
 606                                 };
 607                                 gpu_crit: gpu_crit {
 608                                         temperature = <115000>; /* millicelsius */
 609                                         hysteresis = <2000>; /* millicelsius */
 610                                         type = "critical";
 611                                 };
 612                         };
 613
 614                         cooling-maps {
 615                                 map0 {
 616                                         trip = <&gpu_alert0>;
 617                                         cooling-device =
 618                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 619                                 };
 620                         };
 621                 };
 622         };
 623
 624         tsadc: tsadc@ff280000 {
 625                 compatible = "rockchip,rk3368-tsadc";
 626                 reg = <0x0 0xff280000 0x0 0x100>;
 627                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 628                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 629                 clock-names = "tsadc", "apb_pclk";
 630                 resets = <&cru SRST_TSADC>;
 631                 reset-names = "tsadc-apb";
 632                 pinctrl-names = "init", "default", "sleep";
 633                 pinctrl-0 = <&otp_gpio>;
 634                 pinctrl-1 = <&otp_out>;
 635                 pinctrl-2 = <&otp_gpio>;
 636                 #thermal-sensor-cells = <1>;
 637                 rockchip,hw-tshut-temp = <95000>;
 638                 status = "disabled";
 639         };
 640
 641         gmac: ethernet@ff290000 {
 642                 compatible = "rockchip,rk3368-gmac";
 643                 reg = <0x0 0xff290000 0x0 0x10000>;
 644                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 645                 interrupt-names = "macirq";
 646                 rockchip,grf = <&grf>;
 647                 clocks = <&cru SCLK_MAC>,
 648                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 649                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 650                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 651                 clock-names = "stmmaceth",
 652                         "mac_clk_rx", "mac_clk_tx",
 653                         "clk_mac_ref", "clk_mac_refout",
 654                         "aclk_mac", "pclk_mac";
 655                 status = "disabled";
 656         };
 657
 658         nandc0: nandc@ff400000 {
 659                 compatible = "rockchip,rk-nandc";
 660                 reg = <0x0 0xff400000 0x0 0x4000>;
 661                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 662                 nandc_id = <0>;
 663                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 664                 clock-names = "clk_nandc", "hclk_nandc";
 665                 status = "disabled";
 666         };
 667
 668         usb_host0_ehci: usb@ff500000 {
 669                 compatible = "generic-ehci";
 670                 reg = <0x0 0xff500000 0x0 0x20000>;
 671                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 672                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 673                 clock-names = "usbhost", "utmi";
 674                 phys = <&u2phy_host>;
 675                 phy-names = "usb";
 676                 status = "disabled";
 677         };
 678
 679         usb_host0_ohci: usb@ff520000 {
 680                 compatible = "generic-ohci";
 681                 reg = <0x0 0xff520000 0x0 0x20000>;
 682                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 683                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 684                 clock-names = "usbhost", "utmi";
 685                 phys = <&u2phy_host>;
 686                 phy-names = "usb";
 687                 status = "disabled";
 688         };
 689
 690         usb_otg: usb@ff580000 {
 691                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 692                                 "snps,dwc2";
 693                 reg = <0x0 0xff580000 0x0 0x40000>;
 694                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&cru HCLK_OTG0>;
 696                 clock-names = "otg";
 697                 dr_mode = "otg";
 698                 g-np-tx-fifo-size = <16>;
 699                 g-rx-fifo-size = <275>;
 700                 g-tx-fifo-size = <256 128 128 64 64 32>;
 701                 g-use-dma;
 702                 status = "disabled";
 703         };
 704
 705         ddrpctl: syscon@ff610000 {
 706                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 707                 reg = <0x0 0xff610000 0x0 0x400>;
 708         };
 709
 710         i2c1: i2c@ff660000 {
 711                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 712                 reg = <0x0 0xff660000 0x0 0x1000>;
 713                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 714                 #address-cells = <1>;
 715                 #size-cells = <0>;
 716                 clock-names = "i2c";
 717                 clocks = <&cru PCLK_I2C1>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&i2c1_xfer>;
 720                 status = "disabled";
 721         };
 722
 723         pwm0: pwm@ff680000 {
 724                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 725                 reg = <0x0 0xff680000 0x0 0x10>;
 726                 #pwm-cells = <3>;
 727                 pinctrl-names = "default";
 728                 pinctrl-0 = <&pwm0_pin>;
 729                 clocks = <&cru PCLK_PWM1>;
 730                 clock-names = "pwm";
 731                 status = "disabled";
 732         };
 733
 734         pwm1: pwm@ff680010 {
 735                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 736                 reg = <0x0 0xff680010 0x0 0x10>;
 737                 #pwm-cells = <3>;
 738                 pinctrl-names = "default";
 739                 pinctrl-0 = <&pwm1_pin>;
 740                 clocks = <&cru PCLK_PWM1>;
 741                 clock-names = "pwm";
 742                 status = "disabled";
 743         };
 744
 745         pwm2: pwm@ff680020 {
 746                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 747                 reg = <0x0 0xff680020 0x0 0x10>;
 748                 #pwm-cells = <3>;
 749                 clocks = <&cru PCLK_PWM1>;
 750                 clock-names = "pwm";
 751                 status = "disabled";
 752         };
 753
 754         pwm3: pwm@ff680030 {
 755                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 756                 reg = <0x0 0xff680030 0x0 0x10>;
 757                 #pwm-cells = <3>;
 758                 pinctrl-names = "default";
 759                 pinctrl-0 = <&pwm3_pin>;
 760                 clocks = <&cru PCLK_PWM1>;
 761                 clock-names = "pwm";
 762                 status = "disabled";
 763         };
 764
 765         uart2: serial@ff690000 {
 766                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 767                 reg = <0x0 0xff690000 0x0 0x100>;
 768                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 769                 clock-names = "baudclk", "apb_pclk";
 770                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 771                 pinctrl-names = "default";
 772                 pinctrl-0 = <&uart2_xfer>;
 773                 reg-shift = <2>;
 774                 reg-io-width = <4>;
 775                 status = "disabled";
 776         };
 777
 778         mbox: mbox@ff6b0000 {
 779                 compatible = "rockchip,rk3368-mailbox";
 780                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 781                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 782                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 783                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 784                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru PCLK_MAILBOX>;
 786                 clock-names = "pclk_mailbox";
 787                 #mbox-cells = <1>;
 788                 status = "disabled";
 789         };
 790
 791         mailbox: mailbox@ff6b0000 {
 792                 compatible = "rockchip,rk3368-mbox-legacy";
 793                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 794                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 795                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 796                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 797                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 798                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 799                 clocks = <&cru PCLK_MAILBOX>;
 800                 clock-names = "pclk_mailbox";
 801                 #mbox-cells = <1>;
 802                 status = "disabled";
 803         };
 804
 805         mailbox_scpi: mailbox-scpi {
 806                 compatible = "rockchip,rk3368-scpi-legacy";
 807                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 808                 chan-nums = <3>;
 809                 status = "disabled";
 810         };
 811
 812         pmu: power-management@ff730000 {
 813                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 814                 reg = <0x0 0xff730000 0x0 0x1000>;
 815
 816                 power: power-controller {
 817                         status = "disabled";
 818                         compatible = "rockchip,rk3368-power-controller";
 819                         #power-domain-cells = <1>;
 820                         #address-cells = <1>;
 821                         #size-cells = <0>;
 822
 823                         /*
 824                          * Note: Although SCLK_* are the working clocks
 825                          * of device without including on the NOC, needed for
 826                          * synchronous reset.
 827                          *
 828                          * The clocks on the which NOC:
 829                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 830                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 831                          * ACLK_RGA is on ACLK_RGA_NIU.
 832                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 833                          *
 834                          * Which clock are device clocks:
 835                          *      clocks          devices
 836                          *      *_IEP           IEP:Image Enhancement Processor
 837                          *      *_ISP           ISP:Image Signal Processing
 838                          *      *_VIP           VIP:Video Input Processor
 839                          *      *_VOP*          VOP:Visual Output Processor
 840                          *      *_RGA           RGA
 841                          *      *_EDP*          EDP
 842                          *      *_DPHY*         LVDS
 843                          *      *_HDMI          HDMI
 844                          *      *_MIPI_*        MIPI
 845                          */
 846                         pd_vio {
 847                                 reg = <RK3368_PD_VIO>;
 848                                 clocks = <&cru ACLK_IEP>,
 849                                          <&cru ACLK_ISP>,
 850                                          <&cru ACLK_VIP>,
 851                                          <&cru ACLK_RGA>,
 852                                          <&cru ACLK_VOP>,
 853                                          <&cru ACLK_VOP_IEP>,
 854                                          <&cru DCLK_VOP>,
 855                                          <&cru HCLK_IEP>,
 856                                          <&cru HCLK_ISP>,
 857                                          <&cru HCLK_RGA>,
 858                                          <&cru HCLK_VIP>,
 859                                          <&cru HCLK_VOP>,
 860                                          <&cru HCLK_VIO_HDCPMMU>,
 861                                          <&cru PCLK_EDP_CTRL>,
 862                                          <&cru PCLK_HDMI_CTRL>,
 863                                          <&cru PCLK_HDCP>,
 864                                          <&cru PCLK_ISP>,
 865                                          <&cru PCLK_VIP>,
 866                                          <&cru PCLK_DPHYRX>,
 867                                          <&cru PCLK_DPHYTX0>,
 868                                          <&cru PCLK_MIPI_CSI>,
 869                                          <&cru PCLK_MIPI_DSI0>,
 870                                          <&cru SCLK_VOP0_PWM>,
 871                                          <&cru SCLK_EDP_24M>,
 872                                          <&cru SCLK_EDP>,
 873                                          <&cru SCLK_HDCP>,
 874                                          <&cru SCLK_ISP>,
 875                                          <&cru SCLK_RGA>,
 876                                          <&cru SCLK_HDMI_CEC>,
 877                                          <&cru SCLK_HDMI_HDCP>;
 878                         };
 879                         /*
 880                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 881                          * (video endecoder & decoder) clocks that on the
 882                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 883                          */
 884                         pd_video {
 885                                 reg = <RK3368_PD_VIDEO>;
 886                                 clocks = <&cru ACLK_VIDEO>,
 887                                          <&cru HCLK_VIDEO>,
 888                                          <&cru SCLK_HEVC_CABAC>,
 889                                          <&cru SCLK_HEVC_CORE>;
 890                         };
 891                         /*
 892                          * Note: ACLK_GPU is the GPU clock,
 893                          * and on the ACLK_GPU_NIU (NOC).
 894                          */
 895                         pd_gpu_1 {
 896                                 reg = <RK3368_PD_GPU_1>;
 897                                 clocks = <&cru ACLK_GPU_CFG>,
 898                                          <&cru ACLK_GPU_MEM>,
 899                                          <&cru SCLK_GPU_CORE>;
 900                         };
 901                 };
 902         };
 903
 904         pmugrf: syscon@ff738000 {
 905                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 906                 reg = <0x0 0xff738000 0x0 0x1000>;
 907
 908                 pmu_io_domains: io-domains {
 909                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 910                         status = "disabled";
 911                 };
 912
 913                 reboot-mode {
 914                         compatible = "syscon-reboot-mode";
 915                         offset = <0x200>;
 916                         mode-normal = <BOOT_NORMAL>;
 917                         mode-recovery = <BOOT_RECOVERY>;
 918                         mode-bootloader = <BOOT_FASTBOOT>;
 919                         mode-loader = <BOOT_BL_DOWNLOAD>;
 920                 };
 921         };
 922
 923         cru: clock-controller@ff760000 {
 924                 compatible = "rockchip,rk3368-cru";
 925                 reg = <0x0 0xff760000 0x0 0x1000>;
 926                 rockchip,grf = <&grf>;
 927                 #clock-cells = <1>;
 928                 #reset-cells = <1>;
 929                 assigned-clocks =
 930                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 931                         <&cru PLL_NPLL>,
 932                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
 933                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
 934                         <&cru PCLK_BUS>, <&cru PCLK_PERI>;
 935                 assigned-clock-rates =
 936                         <576000000>, <400000000>,
 937                         <1188000000>,
 938                         <300000000>, <300000000>,
 939                         <150000000>, <150000000>,
 940                         <75000000>, <75000000>;
 941         };
 942
 943         grf: syscon@ff770000 {
 944                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 945                 reg = <0x0 0xff770000 0x0 0x1000>;
 946                 #address-cells = <1>;
 947                 #size-cells = <1>;
 948
 949                 io_domains: io-domains {
 950                         compatible = "rockchip,rk3368-io-voltage-domain";
 951                         status = "disabled";
 952                 };
 953
 954                 u2phy: usb2-phy@700 {
 955                         compatible = "rockchip,rk3368-usb2phy";
 956                         reg = <0x700 0x2c>;
 957                         clocks = <&cru SCLK_OTGPHY0>;
 958                         clock-names = "phyclk";
 959                         #clock-cells = <0>;
 960                         clock-output-names = "usbotg_out";
 961                         assigned-clocks = <&cru SCLK_USBPHY480M>;
 962                         assigned-clock-parents = <&u2phy>;
 963                         status = "disabled";
 964
 965                         u2phy_host: host-port {
 966                                 #phy-cells = <0>;
 967                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 968                                 interrupt-names = "linestate";
 969                                 status = "disabled";
 970                         };
 971                 };
 972         };
 973
 974         wdt: watchdog@ff800000 {
 975                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 976                 reg = <0x0 0xff800000 0x0 0x100>;
 977                 clocks = <&cru PCLK_WDT>;
 978                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 979                 status = "disabled";
 980         };
 981
 982         timer@ff810000 {
 983                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 984                 reg = <0x0 0xff810000 0x0 0x20>;
 985                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 986         };
 987
 988         i2s_2ch: i2s-2ch@ff890000 {
 989                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 990                 reg = <0x0 0xff890000 0x0 0x1000>;
 991                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 992                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 993                 dma-names = "tx", "rx";
 994                 clock-names = "i2s_clk", "i2s_hclk";
 995                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 996                 status = "disabled";
 997         };
 998
 999         i2s_8ch: i2s-8ch@ff898000 {
1000                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1001                 reg = <0x0 0xff898000 0x0 0x1000>;
1002                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1003                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1004                 dma-names = "tx", "rx";
1005                 clock-names = "i2s_clk", "i2s_hclk";
1006                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1007                 pinctrl-names = "default";
1008                 pinctrl-0 = <&i2s_8ch_bus>;
1009                 status = "disabled";
1010         };
1011
1012         isp_mmu: iommu@ff914000 {
1013                 compatible = "rockchip,iommu";
1014                 reg = <0x0 0xff914000 0x0 0x100>,
1015                       <0x0 0xff915000 0x0 0x100>;
1016                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1017                 interrupt-names = "isp_mmu";
1018                 #iommu-cells = <0>;
1019                 status = "disabled";
1020         };
1021
1022         vop: vop@ff930000 {
1023                 compatible = "rockchip,rk3368-vop";
1024                 reg = <0x0 0xff930000 0x0 0x2fc>;
1025                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1026                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1027                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1028                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1029                 reset-names = "axi", "ahb", "dclk";
1030                 power-domains = <&power RK3368_PD_VIO>;
1031                 iommus = <&vop_mmu>;
1032                 status = "disabled";
1033
1034                 vop_out: port {
1035                         #address-cells = <1>;
1036                         #size-cells = <0>;
1037                 };
1038         };
1039
1040         display_subsystem: display-subsystem {
1041                 compatible = "rockchip,display-subsystem";
1042                 ports = <&vop_out>;
1043                 status = "disabled";
1044         };
1045
1046         vop_mmu: iommu@ff930300 {
1047                 compatible = "rockchip,iommu";
1048                 reg = <0x0 0xff930300 0x0 0x100>;
1049                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1050                 interrupt-names = "vop_mmu";
1051                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1052                 clock-names = "aclk", "hclk";
1053                 power-domains = <&power RK3368_PD_VIO>;
1054                 #iommu-cells = <0>;
1055                 status = "disabled";
1056         };
1057
1058         hevc_mmu: iommu@ff9a0440 {
1059                 compatible = "rockchip,iommu";
1060                 reg = <0x0 0xff9a0440 0x0 0x100>,
1061                       <0x0 0xff9a0480 0x0 0x100>;
1062                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1063                 interrupt-names = "hevc_mmu";
1064                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1065                 clock-names = "aclk", "hclk";
1066                 power-domains = <&power RK3368_PD_VIDEO>;
1067                 #iommu-cells = <0>;
1068                 status = "disabled";
1069         };
1070
1071         vpu_mmu: iommu@ff9a0800 {
1072                 compatible = "rockchip,iommu";
1073                 reg = <0x0 0xff9a0800 0x0 0x100>;
1074                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1075                 interrupt-names = "vpu_mmu";
1076                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1077                 clock-names = "aclk", "hclk";
1078                 power-domains = <&power RK3368_PD_VIDEO>;
1079                 #iommu-cells = <0>;
1080                 status = "disabled";
1081         };
1082
1083         gic: interrupt-controller@ffb71000 {
1084                 compatible = "arm,gic-400";
1085                 interrupt-controller;
1086                 #interrupt-cells = <3>;
1087                 #address-cells = <0>;
1088
1089                 reg = <0x0 0xffb71000 0x0 0x1000>,
1090                       <0x0 0xffb72000 0x0 0x2000>,
1091                       <0x0 0xffb74000 0x0 0x2000>,
1092                       <0x0 0xffb76000 0x0 0x2000>;
1093                 interrupts = <GIC_PPI 9
1094                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1095         };
1096
1097         gpu: rogue-g6110@ffa30000 {
1098                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1099                 reg = <0x0 0xffa30000 0x0 0x10000>;
1100                 clocks =
1101                         <&cru SCLK_GPU_CORE>,
1102                         <&cru ACLK_GPU_MEM>,
1103                         <&cru ACLK_GPU_CFG>;
1104                 clock-names =
1105                         "sclk_gpu_core",
1106                         "aclk_gpu_mem",
1107                         "aclk_gpu_cfg";
1108                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1109                 interrupt-names = "rogue-g6110-irq";
1110                 operating-points-v2 = <&gpu_opp_table>;
1111         };
1112
1113         gpu_opp_table: gpu_opp_table {
1114                 compatible = "operating-points-v2";
1115                 opp-shared;
1116
1117                 opp@200000000 {
1118                         opp-hz = /bits/ 64 <200000000>;
1119                         opp-microvolt = <950000>;
1120                 };
1121                 opp@288000000 {
1122                         opp-hz = /bits/ 64 <288000000>;
1123                         opp-microvolt = <1025000>;
1124                 };
1125                 opp@400000000 {
1126                         opp-hz = /bits/ 64 <400000000>;
1127                         opp-microvolt = <1050000>;
1128                 };
1129                 opp@576000000 {
1130                         opp-hz = /bits/ 64 <576000000>;
1131                         opp-microvolt = <1200000>;
1132                 };
1133         };
1134
1135         efuse: efuse@ffb00000 {
1136                 compatible = "rockchip,rk3368-efuse";
1137                 reg = <0x0 0xffb00000 0x0 0x20>;
1138                 #address-cells = <1>;
1139                 #size-cells = <1>;
1140                 clocks = <&cru PCLK_EFUSE256>;
1141                 clock-names = "pclk_efuse";
1142
1143                 /* Data cells */
1144                 cpu_leakage: cpu-leakage@17 {
1145                         reg = <0x17 0x1>;
1146                 };
1147                 temp_adjust: temp-adjust@1f {
1148                         reg = <0x1f 0x1>;
1149                 };
1150         };
1151
1152         pinctrl: pinctrl {
1153                 compatible = "rockchip,rk3368-pinctrl";
1154                 rockchip,grf = <&grf>;
1155                 rockchip,pmu = <&pmugrf>;
1156                 #address-cells = <0x2>;
1157                 #size-cells = <0x2>;
1158                 ranges;
1159
1160                 gpio0: gpio0@ff750000 {
1161                         compatible = "rockchip,gpio-bank";
1162                         reg = <0x0 0xff750000 0x0 0x100>;
1163                         clocks = <&cru PCLK_GPIO0>;
1164                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1165
1166                         gpio-controller;
1167                         #gpio-cells = <0x2>;
1168
1169                         interrupt-controller;
1170                         #interrupt-cells = <0x2>;
1171                 };
1172
1173                 gpio1: gpio1@ff780000 {
1174                         compatible = "rockchip,gpio-bank";
1175                         reg = <0x0 0xff780000 0x0 0x100>;
1176                         clocks = <&cru PCLK_GPIO1>;
1177                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1178
1179                         gpio-controller;
1180                         #gpio-cells = <0x2>;
1181
1182                         interrupt-controller;
1183                         #interrupt-cells = <0x2>;
1184                 };
1185
1186                 gpio2: gpio2@ff790000 {
1187                         compatible = "rockchip,gpio-bank";
1188                         reg = <0x0 0xff790000 0x0 0x100>;
1189                         clocks = <&cru PCLK_GPIO2>;
1190                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1191
1192                         gpio-controller;
1193                         #gpio-cells = <0x2>;
1194
1195                         interrupt-controller;
1196                         #interrupt-cells = <0x2>;
1197                 };
1198
1199                 gpio3: gpio3@ff7a0000 {
1200                         compatible = "rockchip,gpio-bank";
1201                         reg = <0x0 0xff7a0000 0x0 0x100>;
1202                         clocks = <&cru PCLK_GPIO3>;
1203                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1204
1205                         gpio-controller;
1206                         #gpio-cells = <0x2>;
1207
1208                         interrupt-controller;
1209                         #interrupt-cells = <0x2>;
1210                 };
1211
1212                 pcfg_pull_up: pcfg-pull-up {
1213                         bias-pull-up;
1214                 };
1215
1216                 pcfg_pull_down: pcfg-pull-down {
1217                         bias-pull-down;
1218                 };
1219
1220                 pcfg_pull_none: pcfg-pull-none {
1221                         bias-disable;
1222                 };
1223
1224                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1225                         bias-disable;
1226                         drive-strength = <12>;
1227                 };
1228
1229                 emmc {
1230                         emmc_clk: emmc-clk {
1231                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1232                         };
1233
1234                         emmc_cmd: emmc-cmd {
1235                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1236                         };
1237
1238                         emmc_pwr: emmc-pwr {
1239                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1240                         };
1241
1242                         emmc_bus1: emmc-bus1 {
1243                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1244                         };
1245
1246                         emmc_bus4: emmc-bus4 {
1247                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1248                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1249                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1250                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1251                         };
1252
1253                         emmc_bus8: emmc-bus8 {
1254                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1255                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1256                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1257                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1258                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1259                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1260                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1261                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1262                         };
1263                 };
1264
1265                 gmac {
1266                         rgmii_pins: rgmii-pins {
1267                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1268                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1269                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1270                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1271                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1273                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1274                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1275                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1276                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1277                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1278                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1279                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1280                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1281                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1282                         };
1283
1284                         rmii_pins: rmii-pins {
1285                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1286                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1287                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1288                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1289                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1290                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1291                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1292                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1293                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1294                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 i2c0 {
1299                         i2c0_xfer: i2c0-xfer {
1300                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1301                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1302                         };
1303                 };
1304
1305                 i2c1 {
1306                         i2c1_xfer: i2c1-xfer {
1307                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1308                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1309                         };
1310                 };
1311
1312                 i2c2 {
1313                         i2c2_xfer: i2c2-xfer {
1314                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1315                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1316                         };
1317                 };
1318
1319                 i2c3 {
1320                         i2c3_xfer: i2c3-xfer {
1321                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1322                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324                 };
1325
1326                 i2c4 {
1327                         i2c4_xfer: i2c4-xfer {
1328                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1329                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 i2c5 {
1334                         i2c5_xfer: i2c5-xfer {
1335                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1336                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 i2s {
1341                         i2s_8ch_bus: i2s-8ch-bus {
1342                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1343                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1344                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1345                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1346                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1347                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1348                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1349                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1350                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352                 };
1353
1354                 pwm0 {
1355                         pwm0_pin: pwm0-pin {
1356                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1357                         };
1358
1359                         vop_pwm_pin: vop-pwm {
1360                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1361                         };
1362                 };
1363
1364                 pwm1 {
1365                         pwm1_pin: pwm1-pin {
1366                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1367                         };
1368                 };
1369
1370                 pwm3 {
1371                         pwm3_pin: pwm3-pin {
1372                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1373                         };
1374                 };
1375
1376                 sdio0 {
1377                         sdio0_bus1: sdio0-bus1 {
1378                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1379                         };
1380
1381                         sdio0_bus4: sdio0-bus4 {
1382                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1383                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1384                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1385                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1386                         };
1387
1388                         sdio0_cmd: sdio0-cmd {
1389                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1390                         };
1391
1392                         sdio0_clk: sdio0-clk {
1393                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1394                         };
1395
1396                         sdio0_cd: sdio0-cd {
1397                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1398                         };
1399
1400                         sdio0_wp: sdio0-wp {
1401                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1402                         };
1403
1404                         sdio0_pwr: sdio0-pwr {
1405                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1406                         };
1407
1408                         sdio0_bkpwr: sdio0-bkpwr {
1409                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1410                         };
1411
1412                         sdio0_int: sdio0-int {
1413                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1414                         };
1415                 };
1416
1417                 sdmmc {
1418                         sdmmc_clk: sdmmc-clk {
1419                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1420                         };
1421
1422                         sdmmc_cmd: sdmmc-cmd {
1423                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1424                         };
1425
1426                         sdmmc_cd: sdmmc-cd {
1427                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1428                         };
1429
1430                         sdmmc_bus1: sdmmc-bus1 {
1431                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1432                         };
1433
1434                         sdmmc_bus4: sdmmc-bus4 {
1435                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1436                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1437                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1438                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1439                         };
1440                 };
1441
1442                 spi0 {
1443                         spi0_clk: spi0-clk {
1444                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1445                         };
1446                         spi0_cs0: spi0-cs0 {
1447                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1448                         };
1449                         spi0_cs1: spi0-cs1 {
1450                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1451                         };
1452                         spi0_tx: spi0-tx {
1453                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1454                         };
1455                         spi0_rx: spi0-rx {
1456                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1457                         };
1458                 };
1459
1460                 spi1 {
1461                         spi1_clk: spi1-clk {
1462                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1463                         };
1464                         spi1_cs0: spi1-cs0 {
1465                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1466                         };
1467                         spi1_cs1: spi1-cs1 {
1468                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1469                         };
1470                         spi1_rx: spi1-rx {
1471                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1472                         };
1473                         spi1_tx: spi1-tx {
1474                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1475                         };
1476                 };
1477
1478                 spi2 {
1479                         spi2_clk: spi2-clk {
1480                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1481                         };
1482                         spi2_cs0: spi2-cs0 {
1483                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1484                         };
1485                         spi2_rx: spi2-rx {
1486                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1487                         };
1488                         spi2_tx: spi2-tx {
1489                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1490                         };
1491                 };
1492
1493                 tsadc {
1494                         otp_gpio: otp-gpio {
1495                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1496                         };
1497
1498                         otp_out: otp-out {
1499                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1500                         };
1501                 };
1502
1503                 uart0 {
1504                         uart0_xfer: uart0-xfer {
1505                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1506                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1507                         };
1508
1509                         uart0_cts: uart0-cts {
1510                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1511                         };
1512
1513                         uart0_rts: uart0-rts {
1514                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1515                         };
1516                 };
1517
1518                 uart1 {
1519                         uart1_xfer: uart1-xfer {
1520                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1521                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1522                         };
1523
1524                         uart1_cts: uart1-cts {
1525                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1526                         };
1527
1528                         uart1_rts: uart1-rts {
1529                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1530                         };
1531                 };
1532
1533                 uart2 {
1534                         uart2_xfer: uart2-xfer {
1535                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1536                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1537                         };
1538                         /* no rts / cts for uart2 */
1539                 };
1540
1541                 uart3 {
1542                         uart3_xfer: uart3-xfer {
1543                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1544                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1545                         };
1546
1547                         uart3_cts: uart3-cts {
1548                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1549                         };
1550
1551                         uart3_rts: uart3-rts {
1552                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1553                         };
1554                 };
1555
1556                 uart4 {
1557                         uart4_xfer: uart4-xfer {
1558                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1559                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1560                         };
1561
1562                         uart4_cts: uart4-cts {
1563                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1564                         };
1565
1566                         uart4_rts: uart4-rts {
1567                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1568                         };
1569                 };
1570         };
1571 };