arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 cpu_l0: cpu@0 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x0>;
 119                         enable-method = "psci";
 120                         clocks = <&cru ARMCLKL>;
 121                         next-level-cache = <&cluster0_l2>;
 122                         operating-points-v2 = <&cluster0_opp>;
 123                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 124                         #cooling-cells = <2>; /* min followed by max */
 125                         dynamic-power-coefficient = <149>;
 126                 };
 127
 128                 cpu_l1: cpu@1 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a53", "arm,armv8";
 131                         reg = <0x0 0x1>;
 132                         enable-method = "psci";
 133                         clocks = <&cru ARMCLKL>;
 134                         next-level-cache = <&cluster0_l2>;
 135                         operating-points-v2 = <&cluster0_opp>;
 136                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 137                 };
 138
 139                 cpu_l2: cpu@2 {
 140                         device_type = "cpu";
 141                         compatible = "arm,cortex-a53", "arm,armv8";
 142                         reg = <0x0 0x2>;
 143                         enable-method = "psci";
 144                         clocks = <&cru ARMCLKL>;
 145                         next-level-cache = <&cluster0_l2>;
 146                         operating-points-v2 = <&cluster0_opp>;
 147                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 148                 };
 149
 150                 cpu_l3: cpu@3 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a53", "arm,armv8";
 153                         reg = <0x0 0x3>;
 154                         enable-method = "psci";
 155                         clocks = <&cru ARMCLKL>;
 156                         next-level-cache = <&cluster0_l2>;
 157                         operating-points-v2 = <&cluster0_opp>;
 158                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 159                 };
 160
 161                 cpu_b0: cpu@100 {
 162                         device_type = "cpu";
 163                         compatible = "arm,cortex-a53", "arm,armv8";
 164                         reg = <0x0 0x100>;
 165                         enable-method = "psci";
 166                         clocks = <&cru ARMCLKB>;
 167                         next-level-cache = <&cluster1_l2>;
 168                         operating-points-v2 = <&cluster1_opp>;
 169                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 170                         #cooling-cells = <2>; /* min followed by max */
 171                         dynamic-power-coefficient = <160>;
 172                 };
 173
 174                 cpu_b1: cpu@101 {
 175                         device_type = "cpu";
 176                         compatible = "arm,cortex-a53", "arm,armv8";
 177                         reg = <0x0 0x101>;
 178                         enable-method = "psci";
 179                         clocks = <&cru ARMCLKB>;
 180                         next-level-cache = <&cluster1_l2>;
 181                         operating-points-v2 = <&cluster1_opp>;
 182                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 183                 };
 184
 185                 cpu_b2: cpu@102 {
 186                         device_type = "cpu";
 187                         compatible = "arm,cortex-a53", "arm,armv8";
 188                         reg = <0x0 0x102>;
 189                         enable-method = "psci";
 190                         clocks = <&cru ARMCLKB>;
 191                         next-level-cache = <&cluster1_l2>;
 192                         operating-points-v2 = <&cluster1_opp>;
 193                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 194                 };
 195
 196                 cpu_b3: cpu@103 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a53", "arm,armv8";
 199                         reg = <0x0 0x103>;
 200                         enable-method = "psci";
 201                         clocks = <&cru ARMCLKB>;
 202                         next-level-cache = <&cluster1_l2>;
 203                         operating-points-v2 = <&cluster1_opp>;
 204                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 205                 };
 206
 207                 cluster0_l2: l2-cache0 {
 208                         compatible = "cache";
 209                 };
 210
 211                 cluster1_l2: l2-cache1 {
 212                         compatible = "cache";
 213                 };
 214         };
 215
 216         cluster0_opp: opp_table0 {
 217                 compatible = "operating-points-v2";
 218                 opp-shared;
 219
 220                 opp@216000000 {
 221                         opp-hz = /bits/ 64 <216000000>;
 222                         opp-microvolt = <950000 950000 1350000>;
 223                         clock-latency-ns = <40000>;
 224                         opp-suspend;
 225                 };
 226                 opp@408000000 {
 227                         opp-hz = /bits/ 64 <408000000>;
 228                         opp-microvolt = <950000 950000 1350000>;
 229                         clock-latency-ns = <40000>;
 230                 };
 231                 opp@600000000 {
 232                         opp-hz = /bits/ 64 <600000000>;
 233                         opp-microvolt = <950000 950000 1350000>;
 234                         clock-latency-ns = <40000>;
 235                 };
 236                 opp@816000000 {
 237                         opp-hz = /bits/ 64 <816000000>;
 238                         opp-microvolt = <1025000 1025000 1350000>;
 239                         clock-latency-ns = <40000>;
 240                 };
 241                 opp@1008000000 {
 242                         opp-hz = /bits/ 64 <1008000000>;
 243                         opp-microvolt = <1125000 1125000 1350000>;
 244                         clock-latency-ns = <40000>;
 245                 };
 246                 opp@1200000000 {
 247                         opp-hz = /bits/ 64 <1200000000>;
 248                         opp-microvolt = <1225000 1225000 1350000>;
 249                         clock-latency-ns = <40000>;
 250                 };
 251         };
 252
 253         cluster1_opp: opp_table1 {
 254                 compatible = "operating-points-v2";
 255                 opp-shared;
 256
 257                 opp@216000000 {
 258                         opp-hz = /bits/ 64 <216000000>;
 259                         opp-microvolt = <950000 950000 1350000>;
 260                         clock-latency-ns = <40000>;
 261                         opp-suspend;
 262                 };
 263                 opp@408000000 {
 264                         opp-hz = /bits/ 64 <408000000>;
 265                         opp-microvolt = <950000 950000 1350000>;
 266                         clock-latency-ns = <40000>;
 267                 };
 268                 opp@600000000 {
 269                         opp-hz = /bits/ 64 <600000000>;
 270                         opp-microvolt = <950000 950000 1350000>;
 271                         clock-latency-ns = <40000>;
 272                 };
 273                 opp@816000000 {
 274                         opp-hz = /bits/ 64 <816000000>;
 275                         opp-microvolt = <975000 975000 1350000>;
 276                         clock-latency-ns = <40000>;
 277                 };
 278                 opp@1008000000 {
 279                         opp-hz = /bits/ 64 <1008000000>;
 280                         opp-microvolt = <1050000 1050000 1350000>;
 281                         clock-latency-ns = <40000>;
 282                 };
 283                 opp@1200000000 {
 284                         opp-hz = /bits/ 64 <1200000000>;
 285                         opp-microvolt = <1150000 1150000 1350000>;
 286                         clock-latency-ns = <40000>;
 287                 };
 288                 opp@1296000000 {
 289                         opp-hz = /bits/ 64 <1296000000>;
 290                         opp-microvolt = <1225000 1225000 1350000>;
 291                         clock-latency-ns = <40000>;
 292                 };
 293                 opp@1416000000 {
 294                         opp-hz = /bits/ 64 <1416000000>;
 295                         opp-microvolt = <1300000 1300000 1350000>;
 296                         clock-latency-ns = <40000>;
 297                 };
 298                 opp@1512000000 {
 299                         opp-hz = /bits/ 64 <1512000000>;
 300                         opp-microvolt = <1350000 1350000 1350000>;
 301                         clock-latency-ns = <40000>;
 302                 };
 303         };
 304
 305         energy-costs {
 306                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 307                         busy-cost-data = <
 308                                 146    44       /*  216M */
 309                                 276    72       /*  408M */
 310                                 406    99       /*  600M */
 311                                 552    147      /*  816M */
 312                                 682    200      /* 1008M */
 313                                 812    255      /* 1200M */
 314                         >;
 315                         idle-cost-data = <
 316                                   6
 317                                   6
 318                                   0
 319                         >;
 320                 };
 321
 322                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 323                         busy-cost-data = <
 324                                 146    53       /*  216M */
 325                                 276    86       /*  408M */
 326                                 406    118      /*  600M */
 327                                 552    166      /*  816M */
 328                                 682    226      /* 1008M */
 329                                 812    309      /* 1200M */
 330                                 878    371      /* 1200M */
 331                                 959    446      /* 1416M */
 332                                 1024   513      /* 1512M */
 333                         >;
 334                         idle-cost-data = <
 335                                    6
 336                                    6
 337                                    0
 338                         >;
 339                 };
 340
 341                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 342                         busy-cost-data = <
 343                                 146    9        /*  216M */
 344                                 276    14       /*  408M */
 345                                 406    20       /*  600M */
 346                                 552    29       /*  816M */
 347                                 682    40       /* 1008M */
 348                                 812    51       /* 1200M */
 349                         >;
 350                         idle-cost-data = <
 351                                 56
 352                                 56
 353                                 56
 354                         >;
 355                 };
 356
 357                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 358                         busy-cost-data = <
 359                                 146    11       /*  216M */
 360                                 276    17       /*  408M */
 361                                 406    24       /*  600M */
 362                                 552    33       /*  816M */
 363                                 682    45       /* 1008M */
 364                                 812    62       /* 1200M */
 365                                 878    74       /* 1200M */
 366                                 959    89       /* 1416M */
 367                                 1024   103      /* 1512M */
 368                         >;
 369                         idle-cost-data = <
 370                                 56
 371                                 56
 372                                 56
 373                         >;
 374                 };
 375         };
 376
 377         cpu_avs: cpu-avs {
 378                 cluster0-avs {
 379                         cluster-id = <0>;
 380                         min-volt = <950000>; /* uV */
 381                         min-freq = <216000>; /* KHz */
 382                         leakage-adjust-volt = <
 383                         /*  mA        mA         uV */
 384                             0         254        0
 385                         >;
 386                         nvmem-cells = <&cpu_leakage>;
 387                         nvmem-cell-names = "cpu_leakage";
 388                 };
 389                 cluster1-avs {
 390                         cluster-id = <1>;
 391                         min-volt = <950000>; /* uV */
 392                         min-freq = <216000>; /* KHz */
 393                         leakage-adjust-volt = <
 394                         /*  mA        mA         uV */
 395                             0         254        0
 396                         >;
 397                         nvmem-cells = <&cpu_leakage>;
 398                         nvmem-cell-names = "cpu_leakage";
 399                 };
 400         };
 401
 402         arm-pmu {
 403                 compatible = "arm,armv8-pmuv3";
 404                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 405                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 406                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 407                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 408                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 409                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 410                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 411                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 412                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 413                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 414                                      <&cpu_b2>, <&cpu_b3>;
 415         };
 416
 417         amba {
 418                 compatible = "arm,amba-bus";
 419                 #address-cells = <2>;
 420                 #size-cells = <2>;
 421                 ranges;
 422
 423                 dmac_peri: dma-controller@ff250000 {
 424                         compatible = "arm,pl330", "arm,primecell";
 425                         reg = <0x0 0xff250000 0x0 0x4000>;
 426                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 427                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 428                         #dma-cells = <1>;
 429                         clocks = <&cru ACLK_DMAC_PERI>;
 430                         clock-names = "apb_pclk";
 431                         arm,pl330-broken-no-flushp;
 432                         peripherals-req-type-burst;
 433                 };
 434
 435                 dmac_bus: dma-controller@ff600000 {
 436                         compatible = "arm,pl330", "arm,primecell";
 437                         reg = <0x0 0xff600000 0x0 0x4000>;
 438                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 439                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 440                         #dma-cells = <1>;
 441                         clocks = <&cru ACLK_DMAC_BUS>;
 442                         clock-names = "apb_pclk";
 443                         arm,pl330-broken-no-flushp;
 444                         peripherals-req-type-burst;
 445                 };
 446         };
 447
 448         psci {
 449                 compatible = "arm,psci-0.2";
 450                 method = "smc";
 451         };
 452
 453         timer {
 454                 compatible = "arm,armv8-timer";
 455                 interrupts = <GIC_PPI 13
 456                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 457                              <GIC_PPI 14
 458                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 459                              <GIC_PPI 11
 460                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 461                              <GIC_PPI 10
 462                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 463         };
 464
 465         xin24m: oscillator {
 466                 compatible = "fixed-clock";
 467                 clock-frequency = <24000000>;
 468                 clock-output-names = "xin24m";
 469                 #clock-cells = <0>;
 470         };
 471
 472         sdmmc: dwmmc@ff0c0000 {
 473                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 474                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 475                 clock-freq-min-max = <400000 150000000>;
 476                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 477                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 478                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 479                 fifo-depth = <0x100>;
 480                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 481                 status = "disabled";
 482         };
 483
 484         sdio0: dwmmc@ff0d0000 {
 485                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 486                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 487                 clock-freq-min-max = <400000 150000000>;
 488                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 489                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 490                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 491                 fifo-depth = <0x100>;
 492                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 493                 status = "disabled";
 494         };
 495
 496         emmc: dwmmc@ff0f0000 {
 497                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 498                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 499                 clock-freq-min-max = <400000 150000000>;
 500                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 501                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 502                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 503                 fifo-depth = <0x100>;
 504                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 505                 status = "disabled";
 506         };
 507
 508         saradc: saradc@ff100000 {
 509                 compatible = "rockchip,saradc";
 510                 reg = <0x0 0xff100000 0x0 0x100>;
 511                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 512                 #io-channel-cells = <1>;
 513                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 514                 clock-names = "saradc", "apb_pclk";
 515                 resets = <&cru SRST_SARADC>;
 516                 reset-names = "saradc-apb";
 517                 status = "disabled";
 518         };
 519
 520         spi0: spi@ff110000 {
 521                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 522                 reg = <0x0 0xff110000 0x0 0x1000>;
 523                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 524                 clock-names = "spiclk", "apb_pclk";
 525                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 526                 pinctrl-names = "default";
 527                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 528                 #address-cells = <1>;
 529                 #size-cells = <0>;
 530                 status = "disabled";
 531         };
 532
 533         spi1: spi@ff120000 {
 534                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 535                 reg = <0x0 0xff120000 0x0 0x1000>;
 536                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 537                 clock-names = "spiclk", "apb_pclk";
 538                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 539                 pinctrl-names = "default";
 540                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 541                 #address-cells = <1>;
 542                 #size-cells = <0>;
 543                 status = "disabled";
 544         };
 545
 546         spi2: spi@ff130000 {
 547                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 548                 reg = <0x0 0xff130000 0x0 0x1000>;
 549                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 550                 clock-names = "spiclk", "apb_pclk";
 551                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 554                 #address-cells = <1>;
 555                 #size-cells = <0>;
 556                 status = "disabled";
 557         };
 558
 559         i2c0: i2c@ff650000 {
 560                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 561                 reg = <0x0 0xff650000 0x0 0x1000>;
 562                 clocks = <&cru PCLK_I2C0>;
 563                 clock-names = "i2c";
 564                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c0_xfer>;
 567                 #address-cells = <1>;
 568                 #size-cells = <0>;
 569                 status = "disabled";
 570         };
 571
 572         i2c2: i2c@ff140000 {
 573                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 574                 reg = <0x0 0xff140000 0x0 0x1000>;
 575                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 576                 #address-cells = <1>;
 577                 #size-cells = <0>;
 578                 clock-names = "i2c";
 579                 clocks = <&cru PCLK_I2C2>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&i2c2_xfer>;
 582                 status = "disabled";
 583         };
 584
 585         i2c3: i2c@ff150000 {
 586                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 587                 reg = <0x0 0xff150000 0x0 0x1000>;
 588                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 clock-names = "i2c";
 592                 clocks = <&cru PCLK_I2C3>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&i2c3_xfer>;
 595                 status = "disabled";
 596         };
 597
 598         i2c4: i2c@ff160000 {
 599                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 600                 reg = <0x0 0xff160000 0x0 0x1000>;
 601                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 602                 #address-cells = <1>;
 603                 #size-cells = <0>;
 604                 clock-names = "i2c";
 605                 clocks = <&cru PCLK_I2C4>;
 606                 pinctrl-names = "default";
 607                 pinctrl-0 = <&i2c4_xfer>;
 608                 status = "disabled";
 609         };
 610
 611         i2c5: i2c@ff170000 {
 612                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 613                 reg = <0x0 0xff170000 0x0 0x1000>;
 614                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 615                 #address-cells = <1>;
 616                 #size-cells = <0>;
 617                 clock-names = "i2c";
 618                 clocks = <&cru PCLK_I2C5>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&i2c5_xfer>;
 621                 status = "disabled";
 622         };
 623
 624         uart0: serial@ff180000 {
 625                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 626                 reg = <0x0 0xff180000 0x0 0x100>;
 627                 clock-frequency = <24000000>;
 628                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 629                 clock-names = "baudclk", "apb_pclk";
 630                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 631                 reg-shift = <2>;
 632                 reg-io-width = <4>;
 633                 status = "disabled";
 634         };
 635
 636         uart1: serial@ff190000 {
 637                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 638                 reg = <0x0 0xff190000 0x0 0x100>;
 639                 clock-frequency = <24000000>;
 640                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 641                 clock-names = "baudclk", "apb_pclk";
 642                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 643                 reg-shift = <2>;
 644                 reg-io-width = <4>;
 645                 status = "disabled";
 646         };
 647
 648         uart3: serial@ff1b0000 {
 649                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 650                 reg = <0x0 0xff1b0000 0x0 0x100>;
 651                 clock-frequency = <24000000>;
 652                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 653                 clock-names = "baudclk", "apb_pclk";
 654                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 655                 reg-shift = <2>;
 656                 reg-io-width = <4>;
 657                 status = "disabled";
 658         };
 659
 660         uart4: serial@ff1c0000 {
 661                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 662                 reg = <0x0 0xff1c0000 0x0 0x100>;
 663                 clock-frequency = <24000000>;
 664                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 665                 clock-names = "baudclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 667                 reg-shift = <2>;
 668                 reg-io-width = <4>;
 669                 status = "disabled";
 670         };
 671
 672         thermal_zones: thermal-zones {
 673                 soc_thermal: soc-thermal {
 674                         polling-delay-passive = <200>; /* milliseconds */
 675                         polling-delay = <200>; /* milliseconds */
 676                         sustainable-power = <600>; /* milliwatts */
 677
 678                         thermal-sensors = <&tsadc 0>;
 679                         trips {
 680                                 threshold: trip-point@0 {
 681                                         temperature = <70000>; /* millicelsius */
 682                                         hysteresis = <2000>; /* millicelsius */
 683                                         type = "passive";
 684                                 };
 685                                 target: trip-point@1 {
 686                                         temperature = <80000>; /* millicelsius */
 687                                         hysteresis = <2000>; /* millicelsius */
 688                                         type = "passive";
 689                                 };
 690                                 soc_crit: soc-crit {
 691                                         temperature = <95000>; /* millicelsius */
 692                                         hysteresis = <2000>; /* millicelsius */
 693                                         type = "critical";
 694                                 };
 695                         };
 696
 697                         cooling-maps {
 698                                 map0 {
 699                                         trip = <&target>;
 700                                         cooling-device =
 701                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 702                                         contribution = <1024>;
 703                                 };
 704                                 map1 {
 705                                         trip = <&target>;
 706                                         cooling-device =
 707                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 708                                         contribution = <1024>;
 709                                 };
 710                                 map2 {
 711                                         trip = <&target>;
 712                                         cooling-device =
 713                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 714                                         contribution = <1024>;
 715                                 };
 716                         };
 717                 };
 718
 719                 gpu_thermal: gpu-thermal {
 720                         polling-delay-passive = <200>; /* milliseconds */
 721                         polling-delay = <200>; /* milliseconds */
 722                         thermal-sensors = <&tsadc 1>;
 723                 };
 724         };
 725
 726         tsadc: tsadc@ff280000 {
 727                 compatible = "rockchip,rk3368-tsadc-legacy";
 728                 reg = <0x0 0xff280000 0x0 0x100>;
 729                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 731                 clock-names = "tsadc", "apb_pclk";
 732                 clock-frequency = <32768>;
 733                 resets = <&cru SRST_TSADC>;
 734                 reset-names = "tsadc-apb";
 735                 nvmem-cells = <&temp_adjust>;
 736                 nvmem-cell-names = "temp_adjust";
 737                 #thermal-sensor-cells = <1>;
 738                 hw-shut-temp = <95000>;
 739                 latency-bound = <50000>;
 740                 status = "disabled";
 741         };
 742
 743         gmac: ethernet@ff290000 {
 744                 compatible = "rockchip,rk3368-gmac";
 745                 reg = <0x0 0xff290000 0x0 0x10000>;
 746                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 747                 interrupt-names = "macirq";
 748                 rockchip,grf = <&grf>;
 749                 clocks = <&cru SCLK_MAC>,
 750                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 751                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 752                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 753                 clock-names = "stmmaceth",
 754                         "mac_clk_rx", "mac_clk_tx",
 755                         "clk_mac_ref", "clk_mac_refout",
 756                         "aclk_mac", "pclk_mac";
 757                 status = "disabled";
 758         };
 759
 760         nandc0: nandc@ff400000 {
 761                 compatible = "rockchip,rk-nandc";
 762                 reg = <0x0 0xff400000 0x0 0x4000>;
 763                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 764                 nandc_id = <0>;
 765                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 766                 clock-names = "clk_nandc", "hclk_nandc";
 767                 status = "disabled";
 768         };
 769
 770         usb_host0_ehci: usb@ff500000 {
 771                 compatible = "generic-ehci";
 772                 reg = <0x0 0xff500000 0x0 0x20000>;
 773                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 775                 clock-names = "usbhost", "utmi";
 776                 phys = <&u2phy_host>;
 777                 phy-names = "usb";
 778                 status = "disabled";
 779         };
 780
 781         usb_host0_ohci: usb@ff520000 {
 782                 compatible = "generic-ohci";
 783                 reg = <0x0 0xff520000 0x0 0x20000>;
 784                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 786                 clock-names = "usbhost", "utmi";
 787                 phys = <&u2phy_host>;
 788                 phy-names = "usb";
 789                 status = "disabled";
 790         };
 791
 792         usb_otg: usb@ff580000 {
 793                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 794                                 "snps,dwc2";
 795                 reg = <0x0 0xff580000 0x0 0x40000>;
 796                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 797                 clocks = <&cru HCLK_OTG0>;
 798                 clock-names = "otg";
 799                 dr_mode = "otg";
 800                 g-np-tx-fifo-size = <16>;
 801                 g-rx-fifo-size = <275>;
 802                 g-tx-fifo-size = <256 128 128 64 64 32>;
 803                 g-use-dma;
 804                 status = "disabled";
 805         };
 806
 807         ddrpctl: syscon@ff610000 {
 808                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 809                 reg = <0x0 0xff610000 0x0 0x400>;
 810         };
 811
 812         i2c1: i2c@ff660000 {
 813                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 814                 reg = <0x0 0xff660000 0x0 0x1000>;
 815                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 816                 #address-cells = <1>;
 817                 #size-cells = <0>;
 818                 clock-names = "i2c";
 819                 clocks = <&cru PCLK_I2C1>;
 820                 pinctrl-names = "default";
 821                 pinctrl-0 = <&i2c1_xfer>;
 822                 status = "disabled";
 823         };
 824
 825         pwm0: pwm@ff680000 {
 826                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 827                 reg = <0x0 0xff680000 0x0 0x10>;
 828                 #pwm-cells = <3>;
 829                 pinctrl-names = "default";
 830                 pinctrl-0 = <&pwm0_pin>;
 831                 clocks = <&cru PCLK_PWM1>;
 832                 clock-names = "pwm";
 833                 status = "disabled";
 834         };
 835
 836         pwm1: pwm@ff680010 {
 837                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 838                 reg = <0x0 0xff680010 0x0 0x10>;
 839                 #pwm-cells = <3>;
 840                 pinctrl-names = "default";
 841                 pinctrl-0 = <&pwm1_pin>;
 842                 clocks = <&cru PCLK_PWM1>;
 843                 clock-names = "pwm";
 844                 status = "disabled";
 845         };
 846
 847         pwm2: pwm@ff680020 {
 848                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 849                 reg = <0x0 0xff680020 0x0 0x10>;
 850                 #pwm-cells = <3>;
 851                 clocks = <&cru PCLK_PWM1>;
 852                 clock-names = "pwm";
 853                 status = "disabled";
 854         };
 855
 856         pwm3: pwm@ff680030 {
 857                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 858                 reg = <0x0 0xff680030 0x0 0x10>;
 859                 #pwm-cells = <3>;
 860                 pinctrl-names = "default";
 861                 pinctrl-0 = <&pwm3_pin>;
 862                 clocks = <&cru PCLK_PWM1>;
 863                 clock-names = "pwm";
 864                 status = "disabled";
 865         };
 866
 867         uart2: serial@ff690000 {
 868                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 869                 reg = <0x0 0xff690000 0x0 0x100>;
 870                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 871                 clock-names = "baudclk", "apb_pclk";
 872                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 873                 pinctrl-names = "default";
 874                 pinctrl-0 = <&uart2_xfer>;
 875                 reg-shift = <2>;
 876                 reg-io-width = <4>;
 877                 status = "disabled";
 878         };
 879
 880         mbox: mbox@ff6b0000 {
 881                 compatible = "rockchip,rk3368-mailbox";
 882                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 883                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 884                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 885                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 886                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 887                 clocks = <&cru PCLK_MAILBOX>;
 888                 clock-names = "pclk_mailbox";
 889                 #mbox-cells = <1>;
 890                 status = "disabled";
 891         };
 892
 893         mailbox: mailbox@ff6b0000 {
 894                 compatible = "rockchip,rk3368-mbox-legacy";
 895                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 896                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 897                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 898                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 899                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 900                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 901                 clocks = <&cru PCLK_MAILBOX>;
 902                 clock-names = "pclk_mailbox";
 903                 #mbox-cells = <1>;
 904                 status = "disabled";
 905         };
 906
 907         mailbox_scpi: mailbox-scpi {
 908                 compatible = "rockchip,rk3368-scpi-legacy";
 909                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 910                 chan-nums = <3>;
 911                 status = "disabled";
 912         };
 913
 914         qos_iep: qos@ffad0000 {
 915                 compatible = "syscon";
 916                 reg = <0x0 0xffad0000 0x0 0x20>;
 917         };
 918
 919         qos_isp_r0: qos@ffad0080 {
 920                 compatible = "syscon";
 921                 reg = <0x0 0xffad0080 0x0 0x20>;
 922         };
 923
 924         qos_isp_r1: qos@ffad0100 {
 925                 compatible = "syscon";
 926                 reg = <0x0 0xffad0100 0x0 0x20>;
 927         };
 928
 929         qos_isp_w0: qos@ffad0180 {
 930                 compatible = "syscon";
 931                 reg = <0x0 0xffad0180 0x0 0x20>;
 932         };
 933
 934         qos_isp_w1: qos@ffad0200 {
 935                 compatible = "syscon";
 936                 reg = <0x0 0xffad0200 0x0 0x20>;
 937         };
 938
 939         qos_vip: qos@ffad0280 {
 940                 compatible = "syscon";
 941                 reg = <0x0 0xffad0280 0x0 0x20>;
 942         };
 943
 944         qos_vop: qos@ffad0300 {
 945                 compatible = "syscon";
 946                 reg = <0x0 0xffad0300 0x0 0x20>;
 947         };
 948
 949         qos_rga_r: qos@ffad0380 {
 950                 compatible = "syscon";
 951                 reg = <0x0 0xffad0380 0x0 0x20>;
 952         };
 953
 954         qos_rga_w: qos@ffad0400 {
 955                 compatible = "syscon";
 956                 reg = <0x0 0xffad0400 0x0 0x20>;
 957         };
 958
 959         qos_hevc_r: qos@ffae0000 {
 960                 compatible = "syscon";
 961                 reg = <0x0 0xffae0000 0x0 0x20>;
 962         };
 963
 964         qos_vpu_r: qos@ffae0100 {
 965                 compatible = "syscon";
 966                 reg = <0x0 0xffae0100 0x0 0x20>;
 967         };
 968
 969         qos_vpu_w: qos@ffae0180 {
 970                 compatible = "syscon";
 971                 reg = <0x0 0xffae0180 0x0 0x20>;
 972         };
 973
 974         qos_gpu: qos@ffaf0000 {
 975                 compatible = "syscon";
 976                 reg = <0x0 0xffaf0000 0x0 0x20>;
 977         };
 978
 979         pmu: power-management@ff730000 {
 980                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 981                 reg = <0x0 0xff730000 0x0 0x1000>;
 982
 983                 power: power-controller {
 984                         compatible = "rockchip,rk3368-power-controller";
 985                         #power-domain-cells = <1>;
 986                         #address-cells = <1>;
 987                         #size-cells = <0>;
 988
 989                         /*
 990                          * Note: Although SCLK_* are the working clocks
 991                          * of device without including on the NOC, needed for
 992                          * synchronous reset.
 993                          *
 994                          * The clocks on the which NOC:
 995                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 996                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 997                          * ACLK_RGA is on ACLK_RGA_NIU.
 998                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 999                          *
1000                          * Which clock are device clocks:
1001                          *      clocks          devices
1002                          *      *_IEP           IEP:Image Enhancement Processor
1003                          *      *_ISP           ISP:Image Signal Processing
1004                          *      *_VIP           VIP:Video Input Processor
1005                          *      *_VOP*          VOP:Visual Output Processor
1006                          *      *_RGA           RGA
1007                          *      *_EDP*          EDP
1008                          *      *_DPHY*         LVDS
1009                          *      *_HDMI          HDMI
1010                          *      *_MIPI_*        MIPI
1011                          */
1012                         pd_vio {
1013                                 reg = <RK3368_PD_VIO>;
1014                                 clocks = <&cru ACLK_IEP>,
1015                                          <&cru ACLK_ISP>,
1016                                          <&cru ACLK_VIP>,
1017                                          <&cru ACLK_RGA>,
1018                                          <&cru ACLK_VOP>,
1019                                          <&cru ACLK_VOP_IEP>,
1020                                          <&cru DCLK_VOP>,
1021                                          <&cru HCLK_IEP>,
1022                                          <&cru HCLK_ISP>,
1023                                          <&cru HCLK_RGA>,
1024                                          <&cru HCLK_VIP>,
1025                                          <&cru HCLK_VOP>,
1026                                          <&cru HCLK_VIO_HDCPMMU>,
1027                                          <&cru PCLK_EDP_CTRL>,
1028                                          <&cru PCLK_HDMI_CTRL>,
1029                                          <&cru PCLK_HDCP>,
1030                                          <&cru PCLK_ISP>,
1031                                          <&cru PCLK_VIP>,
1032                                          <&cru PCLK_DPHYRX>,
1033                                          <&cru PCLK_DPHYTX0>,
1034                                          <&cru PCLK_MIPI_CSI>,
1035                                          <&cru PCLK_MIPI_DSI0>,
1036                                          <&cru SCLK_VOP0_PWM>,
1037                                          <&cru SCLK_EDP_24M>,
1038                                          <&cru SCLK_EDP>,
1039                                          <&cru SCLK_HDCP>,
1040                                          <&cru SCLK_ISP>,
1041                                          <&cru SCLK_RGA>,
1042                                          <&cru SCLK_HDMI_CEC>,
1043                                          <&cru SCLK_HDMI_HDCP>;
1044                                 pm_qos = <&qos_iep>,
1045                                          <&qos_isp_r0>,
1046                                          <&qos_isp_r1>,
1047                                          <&qos_isp_w0>,
1048                                          <&qos_isp_w1>,
1049                                          <&qos_vip>,
1050                                          <&qos_vop>,
1051                                          <&qos_rga_r>,
1052                                          <&qos_rga_w>;
1053                         };
1054                         /*
1055                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1056                          * (video endecoder & decoder) clocks that on the
1057                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1058                          */
1059                         pd_video {
1060                                 reg = <RK3368_PD_VIDEO>;
1061                                 clocks = <&cru ACLK_VIDEO>,
1062                                          <&cru HCLK_VIDEO>,
1063                                          <&cru SCLK_HEVC_CABAC>,
1064                                          <&cru SCLK_HEVC_CORE>;
1065                                 pm_qos = <&qos_hevc_r>,
1066                                          <&qos_vpu_r>,
1067                                          <&qos_vpu_w>;
1068                         };
1069                         /*
1070                          * Note: ACLK_GPU is the GPU clock,
1071                          * and on the ACLK_GPU_NIU (NOC).
1072                          */
1073                         pd_gpu_1 {
1074                                 reg = <RK3368_PD_GPU_1>;
1075                                 clocks = <&cru ACLK_GPU_CFG>,
1076                                          <&cru ACLK_GPU_MEM>,
1077                                          <&cru SCLK_GPU_CORE>;
1078                                 pm_qos = <&qos_gpu>;
1079                         };
1080                 };
1081         };
1082
1083         pmugrf: syscon@ff738000 {
1084                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1085                 reg = <0x0 0xff738000 0x0 0x1000>;
1086
1087                 pmu_io_domains: io-domains {
1088                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1089                         status = "disabled";
1090                 };
1091
1092                 reboot-mode {
1093                         compatible = "syscon-reboot-mode";
1094                         offset = <0x200>;
1095                         mode-normal = <BOOT_NORMAL>;
1096                         mode-recovery = <BOOT_RECOVERY>;
1097                         mode-bootloader = <BOOT_FASTBOOT>;
1098                         mode-loader = <BOOT_BL_DOWNLOAD>;
1099                 };
1100         };
1101
1102         cru: clock-controller@ff760000 {
1103                 compatible = "rockchip,rk3368-cru";
1104                 reg = <0x0 0xff760000 0x0 0x1000>;
1105                 rockchip,grf = <&grf>;
1106                 #clock-cells = <1>;
1107                 #reset-cells = <1>;
1108                 assigned-clocks =
1109                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1110                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1111                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1112                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1113                         <&cru ACLK_CCI_PRE>;
1114                 assigned-clock-rates =
1115                         <576000000>, <400000000>,
1116                         <300000000>, <300000000>,
1117                         <150000000>, <150000000>,
1118                         <75000000>, <75000000>,
1119                         <576000000>;
1120         };
1121
1122         grf: syscon@ff770000 {
1123                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1124                 reg = <0x0 0xff770000 0x0 0x1000>;
1125                 #address-cells = <1>;
1126                 #size-cells = <1>;
1127
1128                 edp_phy: edp-phy {
1129                         compatible = "rockchip,rk3368-dp-phy";
1130                         clocks = <&cru SCLK_EDP_24M>;
1131                         clock-names = "24m";
1132                         resets = <&cru SRST_EDP_24M>;
1133                         reset-names = "edp_24m";
1134                         #phy-cells = <0>;
1135                         status = "disabled";
1136                 };
1137
1138                 io_domains: io-domains {
1139                         compatible = "rockchip,rk3368-io-voltage-domain";
1140                         status = "disabled";
1141                 };
1142
1143                 u2phy: usb2-phy@700 {
1144                         compatible = "rockchip,rk3368-usb2phy";
1145                         reg = <0x700 0x2c>;
1146                         clocks = <&cru SCLK_OTGPHY0>;
1147                         clock-names = "phyclk";
1148                         #clock-cells = <0>;
1149                         clock-output-names = "usbotg_out";
1150                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1151                         assigned-clock-parents = <&u2phy>;
1152                         status = "disabled";
1153
1154                         u2phy_host: host-port {
1155                                 #phy-cells = <0>;
1156                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1157                                 interrupt-names = "linestate";
1158                                 status = "disabled";
1159                         };
1160                 };
1161         };
1162
1163         wdt: watchdog@ff800000 {
1164                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1165                 reg = <0x0 0xff800000 0x0 0x100>;
1166                 clocks = <&cru PCLK_WDT>;
1167                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1168                 status = "disabled";
1169         };
1170
1171         timer@ff810000 {
1172                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1173                 reg = <0x0 0xff810000 0x0 0x20>;
1174                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1175         };
1176
1177         i2s_2ch: i2s-2ch@ff890000 {
1178                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1179                 reg = <0x0 0xff890000 0x0 0x1000>;
1180                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1181                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1182                 dma-names = "tx", "rx";
1183                 clock-names = "i2s_clk", "i2s_hclk";
1184                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1185                 status = "disabled";
1186         };
1187
1188         i2s_8ch: i2s-8ch@ff898000 {
1189                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1190                 reg = <0x0 0xff898000 0x0 0x1000>;
1191                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1192                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1193                 dma-names = "tx", "rx";
1194                 clock-names = "i2s_clk", "i2s_hclk";
1195                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1196                 pinctrl-names = "default";
1197                 pinctrl-0 = <&i2s_8ch_bus>;
1198                 status = "disabled";
1199         };
1200
1201         iep: iep@ff900000 {
1202                 compatible = "rockchip,iep";
1203                 iommu_enabled = <1>;
1204                 iommus = <&iep_mmu>;
1205                 reg = <0x0 0xff900000 0x0 0x800>;
1206                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1207                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1208                 clock-names = "aclk_iep", "hclk_iep";
1209                 power-domains = <&power RK3368_PD_VIO>;
1210                 allocator = <1>;
1211                 version = <2>;
1212                 status = "disabled";
1213         };
1214
1215         iep_mmu: iommu@ff900800 {
1216                 compatible = "rockchip,iommu";
1217                 reg = <0x0 0xff900800 0x0 0x100>;
1218                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1219                 interrupt-names = "iep_mmu";
1220                 power-domains = <&power RK3368_PD_VIO>;
1221                 #iommu-cells = <0>;
1222                 status = "disabled";
1223         };
1224
1225         isp: isp@ff910000 {
1226                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1227                 reg = <0x0 0xff910000 0x0 0x4000>;
1228                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1229                 power-domains = <&power RK3368_PD_VIO>;
1230                 clocks =
1231                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1232                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1233                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1234                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1235                 clock-names =
1236                         "aclk_isp", "hclk_isp", "clk_isp",
1237                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1238                         "clk_cif_pll", "hclk_mipiphy1",
1239                         "pclk_dphyrx", "clk_vio0_noc";
1240
1241                 pinctrl-names =
1242                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1243                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1244                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1245                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1246                 pinctrl-0 = <&cif_clkout>;
1247                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1248                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1249                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1250                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1251                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1252                 pinctrl-6 = <&cif_clkout>;
1253                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1254                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1255                 pinctrl-9 = <&isp_flash_trigger>;
1256                 rockchip,isp,mipiphy = <2>;
1257                 rockchip,isp,cifphy = <1>;
1258                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1259                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1260                 rockchip,grf = <&grf>;
1261                 rockchip,cru = <&cru>;
1262                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1263                 rockchip,isp,iommu-enable = <1>;
1264                 iommus = <&isp_mmu>;
1265                 status = "disabled";
1266         };
1267
1268         isp_mmu: iommu@ff914000 {
1269                 compatible = "rockchip,iommu";
1270                 reg = <0x0 0xff914000 0x0 0x100>,
1271                       <0x0 0xff915000 0x0 0x100>;
1272                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1273                 interrupt-names = "isp_mmu";
1274                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1275                 clock-names = "aclk", "hclk";
1276                 rk_iommu,disable_reset_quirk;
1277                 #iommu-cells = <0>;
1278                 power-domains = <&power RK3368_PD_VIO>;
1279                 status = "disabled";
1280         };
1281
1282         vop: vop@ff930000 {
1283                 compatible = "rockchip,rk3368-vop";
1284                 reg = <0x0 0xff930000 0x0 0x2fc>;
1285                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1286                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1287                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1288                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1289                 assigned-clock-rates = <400000000>, <200000000>;
1290                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1291                 reset-names = "axi", "ahb", "dclk";
1292                 power-domains = <&power RK3368_PD_VIO>;
1293                 iommus = <&vop_mmu>;
1294                 status = "disabled";
1295
1296                 vop_out: port {
1297                         #address-cells = <1>;
1298                         #size-cells = <0>;
1299
1300                         vop_out_mipi: endpoint@0 {
1301                                 reg = <0>;
1302                                 remote-endpoint = <&mipi_in_vop>;
1303                         };
1304
1305                         vop_out_edp: endpoint@1 {
1306                                 reg = <1>;
1307                                 remote-endpoint = <&edp_in_vop>;
1308                         };
1309                 };
1310         };
1311
1312         display_subsystem: display-subsystem {
1313                 compatible = "rockchip,display-subsystem";
1314                 ports = <&vop_out>;
1315                 status = "disabled";
1316         };
1317
1318         vop_mmu: iommu@ff930300 {
1319                 compatible = "rockchip,iommu";
1320                 reg = <0x0 0xff930300 0x0 0x100>;
1321                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1322                 interrupt-names = "vop_mmu";
1323                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1324                 clock-names = "aclk", "hclk";
1325                 power-domains = <&power RK3368_PD_VIO>;
1326                 #iommu-cells = <0>;
1327                 status = "disabled";
1328         };
1329
1330         mipi_dsi_host: mipi-dsi-host@ff960000 {
1331                 compatible = "rockchip,rk3368-mipi-dsi";
1332                 reg = <0x0 0xff960000 0x0 0x4000>;
1333                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1334                 clocks = <&cru PCLK_MIPI_DSI0>;
1335                 clock-names = "pclk";
1336                 resets = <&cru SRST_MIPIDSI0>;
1337                 reset-names = "apb";
1338                 phys = <&mipi_dphy>;
1339                 phy-names = "mipi_dphy";
1340                 rockchip,grf = <&grf>;
1341                 power-domains = <&power RK3368_PD_VIO>;
1342                 #address-cells = <1>;
1343                 #size-cells = <0>;
1344                 status = "disabled";
1345
1346                 ports {
1347                         port {
1348                                 mipi_in_vop: endpoint {
1349                                         remote-endpoint = <&vop_out_mipi>;
1350                                 };
1351                         };
1352                 };
1353         };
1354
1355         mipi_dphy: mipi-dphy@ff968000 {
1356                 compatible = "rockchip,rk3368-mipi-dphy";
1357                 reg = <0x0 0xff968000 0x0 0x4000>;
1358                 #phy-cells = <0>;
1359                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1360                 clock-names = "ref", "pclk";
1361                 resets = <&cru SRST_MIPIDPHYTX>;
1362                 reset-names = "apb";
1363                 status = "disabled";
1364         };
1365
1366         edp: edp@ff970000 {
1367                 compatible = "rockchip,rk3368-edp";
1368                 reg = <0x0 0xff970000 0x0 0x8000>;
1369                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1370                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1371                 clock-names = "dp", "pclk";
1372                 resets = <&cru SRST_EDP>;
1373                 reset-names = "dp";
1374                 power-domains = <&power RK3368_PD_VIO>;
1375                 rockchip,grf = <&grf>;
1376                 phys = <&edp_phy>;
1377                 phy-names = "dp";
1378                 pinctrl-names = "default";
1379                 pinctrl-0 = <&edp_hpd>;
1380                 status = "disabled";
1381
1382                 ports {
1383                         #address-cells = <1>;
1384                         #size-cells = <0>;
1385
1386                         edp_in: port@0 {
1387                                 reg = <0>;
1388
1389                                 edp_in_vop: endpoint {
1390                                         remote-endpoint = <&vop_out_edp>;
1391                                 };
1392                         };
1393                 };
1394         };
1395
1396         hevc_mmu: iommu@ff9a0440 {
1397                 compatible = "rockchip,iommu";
1398                 reg = <0x0 0xff9a0440 0x0 0x40>,
1399                       <0x0 0xff9a0480 0x0 0x40>;
1400                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1401                 interrupt-names = "hevc_mmu";
1402                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1403                 clock-names = "aclk", "hclk";
1404                 power-domains = <&power RK3368_PD_VIDEO>;
1405                 #iommu-cells = <0>;
1406                 status = "disabled";
1407         };
1408
1409         vpu_mmu: iommu@ff9a0800 {
1410                 compatible = "rockchip,iommu";
1411                 reg = <0x0 0xff9a0800 0x0 0x100>;
1412                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1413                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1414                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1415                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1416                 clock-names = "aclk", "hclk";
1417                 power-domains = <&power RK3368_PD_VIDEO>;
1418                 #iommu-cells = <0>;
1419                 status = "disabled";
1420         };
1421
1422         vpu: vpu_service {
1423                 compatible = "rockchip,vpu_sub";
1424                 iommu_enabled = <1>;
1425                 iommus = <&vpu_mmu>;
1426                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1427                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1428                 interrupt-names = "irq_enc","irq_dec";
1429                 dev_mode = <0>;
1430                 name = "vpu_service";
1431                 allocator = <1>;
1432         };
1433
1434         hevc: hevc_service {
1435                 compatible = "rockchip,hevc_sub";
1436                 iommu_enabled = <1>;
1437                 iommus = <&hevc_mmu>;
1438                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1439                 interrupt-names = "irq_dec";
1440                 dev_mode = <1>;
1441                 name = "hevc_service";
1442                 allocator = <1>;
1443         };
1444
1445         vpu_combo: vpu_combo@ff9a0000 {
1446                 compatible = "rockchip,vpu_combo";
1447                 reg = <0x0 0xff9a0000 0x0 0x440>;
1448                 rockchip,grf = <&grf>;
1449                 subcnt = <2>;
1450                 rockchip,sub = <&vpu>, <&hevc>;
1451                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1452                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1453                 clock-names = "aclk_vcodec", "hclk_vcodec",
1454                               "clk_core", "clk_cabac";
1455                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1456                          <&cru SRST_VIDEO>;
1457                 reset-names = "video_a", "video_h", "video";
1458                 mode_bit = <12>;
1459                 mode_ctrl = <0x418>;
1460                 name = "vpu_combo";
1461                 power-domains = <&power RK3368_PD_VIDEO>;
1462                 status = "disabled";
1463         };
1464
1465         gic: interrupt-controller@ffb71000 {
1466                 compatible = "arm,gic-400";
1467                 interrupt-controller;
1468                 #interrupt-cells = <3>;
1469                 #address-cells = <0>;
1470
1471                 reg = <0x0 0xffb71000 0x0 0x1000>,
1472                       <0x0 0xffb72000 0x0 0x2000>,
1473                       <0x0 0xffb74000 0x0 0x2000>,
1474                       <0x0 0xffb76000 0x0 0x2000>;
1475                 interrupts = <GIC_PPI 9
1476                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1477         };
1478
1479         gpu: rogue-g6110@ffa30000 {
1480                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1481                 reg = <0x0 0xffa30000 0x0 0x10000>;
1482                 clocks =
1483                         <&cru SCLK_GPU_CORE>,
1484                         <&cru ACLK_GPU_MEM>,
1485                         <&cru ACLK_GPU_CFG>;
1486                 clock-names =
1487                         "sclk_gpu_core",
1488                         "aclk_gpu_mem",
1489                         "aclk_gpu_cfg";
1490                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1491                 interrupt-names = "rogue-g6110-irq";
1492                 power-domains = <&power RK3368_PD_GPU_1>;
1493                 operating-points-v2 = <&gpu_opp_table>;
1494                 #cooling-cells = <2>; /* min followed by max */
1495                 gpu_power_model: power_model {
1496                         compatible = "arm,mali-simple-power-model";
1497                         voltage = <900>;
1498                         frequency = <500>;
1499                         static-power = <300>;
1500                         dynamic-power = <396>;
1501                         ts = <32000 4700 (-80) 2>;
1502                         thermal-zone = "gpu-thermal";
1503                 };
1504         };
1505
1506         gpu_opp_table: gpu_opp_table {
1507                 compatible = "operating-points-v2";
1508                 opp-shared;
1509
1510                 opp@200000000 {
1511                         opp-hz = /bits/ 64 <200000000>;
1512                         opp-microvolt = <1100000>;
1513                 };
1514                 opp@288000000 {
1515                         opp-hz = /bits/ 64 <288000000>;
1516                         opp-microvolt = <1100000>;
1517                 };
1518                 opp@400000000 {
1519                         opp-hz = /bits/ 64 <400000000>;
1520                         opp-microvolt = <1100000>;
1521                 };
1522                 opp@576000000 {
1523                         opp-hz = /bits/ 64 <576000000>;
1524                         opp-microvolt = <1200000>;
1525                 };
1526         };
1527
1528         efuse: efuse@ffb00000 {
1529                 compatible = "rockchip,rk3368-efuse";
1530                 reg = <0x0 0xffb00000 0x0 0x20>;
1531                 #address-cells = <1>;
1532                 #size-cells = <1>;
1533                 clocks = <&cru PCLK_EFUSE256>;
1534                 clock-names = "pclk_efuse";
1535
1536                 /* Data cells */
1537                 cpu_leakage: cpu-leakage@17 {
1538                         reg = <0x17 0x1>;
1539                 };
1540                 temp_adjust: temp-adjust@1f {
1541                         reg = <0x1f 0x1>;
1542                 };
1543         };
1544
1545         pinctrl: pinctrl {
1546                 compatible = "rockchip,rk3368-pinctrl";
1547                 rockchip,grf = <&grf>;
1548                 rockchip,pmu = <&pmugrf>;
1549                 #address-cells = <0x2>;
1550                 #size-cells = <0x2>;
1551                 ranges;
1552
1553                 gpio0: gpio0@ff750000 {
1554                         compatible = "rockchip,gpio-bank";
1555                         reg = <0x0 0xff750000 0x0 0x100>;
1556                         clocks = <&cru PCLK_GPIO0>;
1557                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1558
1559                         gpio-controller;
1560                         #gpio-cells = <0x2>;
1561
1562                         interrupt-controller;
1563                         #interrupt-cells = <0x2>;
1564                 };
1565
1566                 gpio1: gpio1@ff780000 {
1567                         compatible = "rockchip,gpio-bank";
1568                         reg = <0x0 0xff780000 0x0 0x100>;
1569                         clocks = <&cru PCLK_GPIO1>;
1570                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1571
1572                         gpio-controller;
1573                         #gpio-cells = <0x2>;
1574
1575                         interrupt-controller;
1576                         #interrupt-cells = <0x2>;
1577                 };
1578
1579                 gpio2: gpio2@ff790000 {
1580                         compatible = "rockchip,gpio-bank";
1581                         reg = <0x0 0xff790000 0x0 0x100>;
1582                         clocks = <&cru PCLK_GPIO2>;
1583                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1584
1585                         gpio-controller;
1586                         #gpio-cells = <0x2>;
1587
1588                         interrupt-controller;
1589                         #interrupt-cells = <0x2>;
1590                 };
1591
1592                 gpio3: gpio3@ff7a0000 {
1593                         compatible = "rockchip,gpio-bank";
1594                         reg = <0x0 0xff7a0000 0x0 0x100>;
1595                         clocks = <&cru PCLK_GPIO3>;
1596                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1597
1598                         gpio-controller;
1599                         #gpio-cells = <0x2>;
1600
1601                         interrupt-controller;
1602                         #interrupt-cells = <0x2>;
1603                 };
1604
1605                 pcfg_pull_up: pcfg-pull-up {
1606                         bias-pull-up;
1607                 };
1608
1609                 pcfg_pull_down: pcfg-pull-down {
1610                         bias-pull-down;
1611                 };
1612
1613                 pcfg_pull_none: pcfg-pull-none {
1614                         bias-disable;
1615                 };
1616
1617                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1618                         bias-disable;
1619                         drive-strength = <12>;
1620                 };
1621
1622                 edp {
1623                         edp_hpd: edp-hpd {
1624                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1625                         };
1626                 };
1627
1628                 emmc {
1629                         emmc_clk: emmc-clk {
1630                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1631                         };
1632
1633                         emmc_cmd: emmc-cmd {
1634                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1635                         };
1636
1637                         emmc_pwr: emmc-pwr {
1638                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1639                         };
1640
1641                         emmc_bus1: emmc-bus1 {
1642                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1643                         };
1644
1645                         emmc_bus4: emmc-bus4 {
1646                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1647                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1648                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1649                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1650                         };
1651
1652                         emmc_bus8: emmc-bus8 {
1653                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1654                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1655                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1656                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1657                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1658                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1659                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1660                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1661                         };
1662                 };
1663
1664                 gmac {
1665                         rgmii_pins: rgmii-pins {
1666                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1667                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1668                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1669                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1670                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1671                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1672                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1673                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1674                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1675                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1676                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1677                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1678                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1679                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1680                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1681                         };
1682
1683                         rmii_pins: rmii-pins {
1684                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1685                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1686                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1687                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1688                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1689                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1690                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1691                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1692                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1693                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1694                         };
1695                 };
1696
1697                 i2c0 {
1698                         i2c0_xfer: i2c0-xfer {
1699                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1700                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1701                         };
1702                 };
1703
1704                 i2c1 {
1705                         i2c1_xfer: i2c1-xfer {
1706                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1707                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1708                         };
1709                 };
1710
1711                 i2c2 {
1712                         i2c2_xfer: i2c2-xfer {
1713                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1714                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1715                         };
1716                 };
1717
1718                 i2c3 {
1719                         i2c3_xfer: i2c3-xfer {
1720                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1721                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1722                         };
1723                 };
1724
1725                 i2c4 {
1726                         i2c4_xfer: i2c4-xfer {
1727                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1728                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1729                         };
1730                 };
1731
1732                 i2c5 {
1733                         i2c5_xfer: i2c5-xfer {
1734                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1735                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1736                         };
1737                 };
1738
1739                 i2s {
1740                         i2s_8ch_bus: i2s-8ch-bus {
1741                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1742                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1743                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1744                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1745                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1746                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1747                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1748                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1749                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1750                         };
1751                 };
1752
1753                 pwm0 {
1754                         pwm0_pin: pwm0-pin {
1755                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1756                         };
1757
1758                         vop_pwm_pin: vop-pwm {
1759                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1760                         };
1761                 };
1762
1763                 pwm1 {
1764                         pwm1_pin: pwm1-pin {
1765                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1766                         };
1767                 };
1768
1769                 pwm3 {
1770                         pwm3_pin: pwm3-pin {
1771                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1772                         };
1773                 };
1774
1775                 sdio0 {
1776                         sdio0_bus1: sdio0-bus1 {
1777                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1778                         };
1779
1780                         sdio0_bus4: sdio0-bus4 {
1781                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1782                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1783                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1784                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1785                         };
1786
1787                         sdio0_cmd: sdio0-cmd {
1788                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1789                         };
1790
1791                         sdio0_clk: sdio0-clk {
1792                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1793                         };
1794
1795                         sdio0_cd: sdio0-cd {
1796                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798
1799                         sdio0_wp: sdio0-wp {
1800                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1801                         };
1802
1803                         sdio0_pwr: sdio0-pwr {
1804                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1805                         };
1806
1807                         sdio0_bkpwr: sdio0-bkpwr {
1808                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810
1811                         sdio0_int: sdio0-int {
1812                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814                 };
1815
1816                 sdmmc {
1817                         sdmmc_clk: sdmmc-clk {
1818                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1819                         };
1820
1821                         sdmmc_cmd: sdmmc-cmd {
1822                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1823                         };
1824
1825                         sdmmc_cd: sdmmc-cd {
1826                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1827                         };
1828
1829                         sdmmc_bus1: sdmmc-bus1 {
1830                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1831                         };
1832
1833                         sdmmc_bus4: sdmmc-bus4 {
1834                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1835                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1836                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1837                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839                 };
1840
1841                 spi0 {
1842                         spi0_clk: spi0-clk {
1843                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1844                         };
1845                         spi0_cs0: spi0-cs0 {
1846                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1847                         };
1848                         spi0_cs1: spi0-cs1 {
1849                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1850                         };
1851                         spi0_tx: spi0-tx {
1852                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1853                         };
1854                         spi0_rx: spi0-rx {
1855                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1856                         };
1857                 };
1858
1859                 spi1 {
1860                         spi1_clk: spi1-clk {
1861                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1862                         };
1863                         spi1_cs0: spi1-cs0 {
1864                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1865                         };
1866                         spi1_cs1: spi1-cs1 {
1867                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1868                         };
1869                         spi1_rx: spi1-rx {
1870                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1871                         };
1872                         spi1_tx: spi1-tx {
1873                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1874                         };
1875                 };
1876
1877                 spi2 {
1878                         spi2_clk: spi2-clk {
1879                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1880                         };
1881                         spi2_cs0: spi2-cs0 {
1882                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1883                         };
1884                         spi2_rx: spi2-rx {
1885                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1886                         };
1887                         spi2_tx: spi2-tx {
1888                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1889                         };
1890                 };
1891
1892                 uart0 {
1893                         uart0_xfer: uart0-xfer {
1894                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1895                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1896                         };
1897
1898                         uart0_cts: uart0-cts {
1899                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1900                         };
1901
1902                         uart0_rts: uart0-rts {
1903                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1904                         };
1905                 };
1906
1907                 uart1 {
1908                         uart1_xfer: uart1-xfer {
1909                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1910                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1911                         };
1912
1913                         uart1_cts: uart1-cts {
1914                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1915                         };
1916
1917                         uart1_rts: uart1-rts {
1918                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1919                         };
1920                 };
1921
1922                 uart2 {
1923                         uart2_xfer: uart2-xfer {
1924                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1925                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1926                         };
1927                         /* no rts / cts for uart2 */
1928                 };
1929
1930                 uart3 {
1931                         uart3_xfer: uart3-xfer {
1932                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1933                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1934                         };
1935
1936                         uart3_cts: uart3-cts {
1937                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1938                         };
1939
1940                         uart3_rts: uart3-rts {
1941                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1942                         };
1943                 };
1944
1945                 uart4 {
1946                         uart4_xfer: uart4-xfer {
1947                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1948                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1949                         };
1950
1951                         uart4_cts: uart4-cts {
1952                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1953                         };
1954
1955                         uart4_rts: uart4-rts {
1956                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1957                         };
1958                 };
1959
1960                 isp {
1961                         cif_clkout: cif-clkout {
1962                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1963                         };
1964
1965                         isp_dvp_d2d9: isp-dvp-d2d9 {
1966                                 rockchip,pins =
1967                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1968                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1969                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1970                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1971                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1972                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1973                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1974                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1975                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1976                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1977                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1978                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1979                         };
1980
1981                         isp_dvp_d0d1: isp-dvp-d0d1 {
1982                                 rockchip,pins =
1983                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1984                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1985                         };
1986
1987                         isp_dvp_d10d11:isp_d10d11 {
1988                                 rockchip,pins =
1989                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1990                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1991                         };
1992
1993                         isp_dvp_d0d7: isp-dvp-d0d7 {
1994                                 rockchip,pins =
1995                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1996                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1997                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1998                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1999                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2000                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2001                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2002                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
2003                         };
2004
2005                         isp_dvp_d4d11: isp-dvp-d4d11 {
2006                                 rockchip,pins =
2007                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
2008                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
2009                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
2010                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
2011                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
2012                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
2013                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
2014                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2015                         };
2016
2017                         isp_shutter: isp-shutter {
2018                                 rockchip,pins =
2019                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2020                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2021                         };
2022
2023                         isp_flash_trigger: isp-flash-trigger {
2024                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2025                         };
2026
2027                         isp_prelight: isp-prelight {
2028                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2029                         };
2030
2031                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2032                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2033                         };
2034                 };
2035         };
2036 };