arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/power/rk3368-power.h>
  49 #include <dt-bindings/soc/rockchip,boot-mode.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51 #include <dt-bindings/display/mipi_dsi.h>
  52 #include <dt-bindings/display/drm_mipi_dsi.h>
  53 #include <dt-bindings/display/media-bus-format.h>
  54
  55 / {
  56         compatible = "rockchip,rk3368";
  57         interrupt-parent = <&gic>;
  58         #address-cells = <2>;
  59         #size-cells = <2>;
  60
  61         aliases {
  62                 ethernet0 = &gmac;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67                 i2c4 = &i2c4;
  68                 i2c5 = &i2c5;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         cpus {
  80                 #address-cells = <0x2>;
  81                 #size-cells = <0x0>;
  82
  83                 cpu-map {
  84                         cluster0 {
  85                                 core0 {
  86                                         cpu = <&cpu_l0>;
  87                                 };
  88                                 core1 {
  89                                         cpu = <&cpu_l1>;
  90                                 };
  91                                 core2 {
  92                                         cpu = <&cpu_l2>;
  93                                 };
  94                                 core3 {
  95                                         cpu = <&cpu_l3>;
  96                                 };
  97                         };
  98
  99                         cluster1 {
 100                                 core0 {
 101                                         cpu = <&cpu_b0>;
 102                                 };
 103                                 core1 {
 104                                         cpu = <&cpu_b1>;
 105                                 };
 106                                 core2 {
 107                                         cpu = <&cpu_b2>;
 108                                 };
 109                                 core3 {
 110                                         cpu = <&cpu_b3>;
 111                                 };
 112                         };
 113                 };
 114
 115                 cpu_l0: cpu@0 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a53", "arm,armv8";
 118                         reg = <0x0 0x0>;
 119                         enable-method = "psci";
 120                         clocks = <&cru ARMCLKL>;
 121                         operating-points-v2 = <&cluster0_opp>;
 122                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 123                         #cooling-cells = <2>; /* min followed by max */
 124                         dynamic-power-coefficient = <149>;
 125                 };
 126
 127                 cpu_l1: cpu@1 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x1>;
 131                         enable-method = "psci";
 132                         clocks = <&cru ARMCLKL>;
 133                         operating-points-v2 = <&cluster0_opp>;
 134                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 135                 };
 136
 137                 cpu_l2: cpu@2 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a53", "arm,armv8";
 140                         reg = <0x0 0x2>;
 141                         enable-method = "psci";
 142                         clocks = <&cru ARMCLKL>;
 143                         operating-points-v2 = <&cluster0_opp>;
 144                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 145                 };
 146
 147                 cpu_l3: cpu@3 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a53", "arm,armv8";
 150                         reg = <0x0 0x3>;
 151                         enable-method = "psci";
 152                         clocks = <&cru ARMCLKL>;
 153                         operating-points-v2 = <&cluster0_opp>;
 154                         sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
 155                 };
 156
 157                 cpu_b0: cpu@100 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a53", "arm,armv8";
 160                         reg = <0x0 0x100>;
 161                         enable-method = "psci";
 162                         clocks = <&cru ARMCLKB>;
 163                         operating-points-v2 = <&cluster1_opp>;
 164                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 165                         #cooling-cells = <2>; /* min followed by max */
 166                         dynamic-power-coefficient = <160>;
 167                 };
 168
 169                 cpu_b1: cpu@101 {
 170                         device_type = "cpu";
 171                         compatible = "arm,cortex-a53", "arm,armv8";
 172                         reg = <0x0 0x101>;
 173                         enable-method = "psci";
 174                         clocks = <&cru ARMCLKB>;
 175                         operating-points-v2 = <&cluster1_opp>;
 176                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 177                 };
 178
 179                 cpu_b2: cpu@102 {
 180                         device_type = "cpu";
 181                         compatible = "arm,cortex-a53", "arm,armv8";
 182                         reg = <0x0 0x102>;
 183                         enable-method = "psci";
 184                         clocks = <&cru ARMCLKB>;
 185                         operating-points-v2 = <&cluster1_opp>;
 186                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 187                 };
 188
 189                 cpu_b3: cpu@103 {
 190                         device_type = "cpu";
 191                         compatible = "arm,cortex-a53", "arm,armv8";
 192                         reg = <0x0 0x103>;
 193                         enable-method = "psci";
 194                         clocks = <&cru ARMCLKB>;
 195                         operating-points-v2 = <&cluster1_opp>;
 196                         sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
 197                 };
 198         };
 199
 200         cluster0_opp: opp_table0 {
 201                 compatible = "operating-points-v2";
 202                 opp-shared;
 203
 204                 opp@216000000 {
 205                         opp-hz = /bits/ 64 <216000000>;
 206                         opp-microvolt = <950000 950000 1350000>;
 207                         clock-latency-ns = <40000>;
 208                         opp-suspend;
 209                 };
 210                 opp@408000000 {
 211                         opp-hz = /bits/ 64 <408000000>;
 212                         opp-microvolt = <950000 950000 1350000>;
 213                         clock-latency-ns = <40000>;
 214                 };
 215                 opp@600000000 {
 216                         opp-hz = /bits/ 64 <600000000>;
 217                         opp-microvolt = <950000 950000 1350000>;
 218                         clock-latency-ns = <40000>;
 219                 };
 220                 opp@816000000 {
 221                         opp-hz = /bits/ 64 <816000000>;
 222                         opp-microvolt = <1025000 1025000 1350000>;
 223                         clock-latency-ns = <40000>;
 224                 };
 225                 opp@1008000000 {
 226                         opp-hz = /bits/ 64 <1008000000>;
 227                         opp-microvolt = <1125000 1125000 1350000>;
 228                         clock-latency-ns = <40000>;
 229                 };
 230                 opp@1200000000 {
 231                         opp-hz = /bits/ 64 <1200000000>;
 232                         opp-microvolt = <1225000 1225000 1350000>;
 233                         clock-latency-ns = <40000>;
 234                 };
 235         };
 236
 237         cluster1_opp: opp_table1 {
 238                 compatible = "operating-points-v2";
 239                 opp-shared;
 240
 241                 opp@216000000 {
 242                         opp-hz = /bits/ 64 <216000000>;
 243                         opp-microvolt = <950000 950000 1350000>;
 244                         clock-latency-ns = <40000>;
 245                         opp-suspend;
 246                 };
 247                 opp@408000000 {
 248                         opp-hz = /bits/ 64 <408000000>;
 249                         opp-microvolt = <950000 950000 1350000>;
 250                         clock-latency-ns = <40000>;
 251                 };
 252                 opp@600000000 {
 253                         opp-hz = /bits/ 64 <600000000>;
 254                         opp-microvolt = <950000 950000 1350000>;
 255                         clock-latency-ns = <40000>;
 256                 };
 257                 opp@816000000 {
 258                         opp-hz = /bits/ 64 <816000000>;
 259                         opp-microvolt = <975000 975000 1350000>;
 260                         clock-latency-ns = <40000>;
 261                 };
 262                 opp@1008000000 {
 263                         opp-hz = /bits/ 64 <1008000000>;
 264                         opp-microvolt = <1050000 1050000 1350000>;
 265                         clock-latency-ns = <40000>;
 266                 };
 267                 opp@1200000000 {
 268                         opp-hz = /bits/ 64 <1200000000>;
 269                         opp-microvolt = <1150000 1150000 1350000>;
 270                         clock-latency-ns = <40000>;
 271                 };
 272                 opp@1296000000 {
 273                         opp-hz = /bits/ 64 <1296000000>;
 274                         opp-microvolt = <1225000 1225000 1350000>;
 275                         clock-latency-ns = <40000>;
 276                 };
 277                 opp@1416000000 {
 278                         opp-hz = /bits/ 64 <1416000000>;
 279                         opp-microvolt = <1300000 1300000 1350000>;
 280                         clock-latency-ns = <40000>;
 281                 };
 282                 opp@1512000000 {
 283                         opp-hz = /bits/ 64 <1512000000>;
 284                         opp-microvolt = <1350000 1350000 1350000>;
 285                         clock-latency-ns = <40000>;
 286                 };
 287         };
 288
 289         energy-costs {
 290                 RK3368_CPU_COST_0: rk3368-core-cost0 {
 291                         busy-cost-data = <
 292                                 146    44       /*  216M */
 293                                 276    72       /*  408M */
 294                                 406    99       /*  600M */
 295                                 552    147      /*  816M */
 296                                 682    200      /* 1008M */
 297                                 812    255      /* 1200M */
 298                         >;
 299                         idle-cost-data = <
 300                                   6
 301                                   6
 302                                   0
 303                         >;
 304                 };
 305
 306                 RK3368_CPU_COST_1: rk3368-core-cost1 {
 307                         busy-cost-data = <
 308                                 146    53       /*  216M */
 309                                 276    86       /*  408M */
 310                                 406    118      /*  600M */
 311                                 552    166      /*  816M */
 312                                 682    226      /* 1008M */
 313                                 812    309      /* 1200M */
 314                                 878    371      /* 1200M */
 315                                 959    446      /* 1416M */
 316                                 1024   513      /* 1512M */
 317                         >;
 318                         idle-cost-data = <
 319                                    6
 320                                    6
 321                                    0
 322                         >;
 323                 };
 324
 325                 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
 326                         busy-cost-data = <
 327                                 146    9        /*  216M */
 328                                 276    14       /*  408M */
 329                                 406    20       /*  600M */
 330                                 552    29       /*  816M */
 331                                 682    40       /* 1008M */
 332                                 812    51       /* 1200M */
 333                         >;
 334                         idle-cost-data = <
 335                                 56
 336                                 56
 337                                 56
 338                         >;
 339                 };
 340
 341                 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
 342                         busy-cost-data = <
 343                                 146    11       /*  216M */
 344                                 276    17       /*  408M */
 345                                 406    24       /*  600M */
 346                                 552    33       /*  816M */
 347                                 682    45       /* 1008M */
 348                                 812    62       /* 1200M */
 349                                 878    74       /* 1200M */
 350                                 959    89       /* 1416M */
 351                                 1024   103      /* 1512M */
 352                         >;
 353                         idle-cost-data = <
 354                                 56
 355                                 56
 356                                 56
 357                         >;
 358                 };
 359         };
 360
 361         cpu_avs: cpu-avs {
 362                 cluster0-avs {
 363                         cluster-id = <0>;
 364                         min-volt = <950000>; /* uV */
 365                         min-freq = <216000>; /* KHz */
 366                         leakage-adjust-volt = <
 367                         /*  mA        mA         uV */
 368                             0         254        0
 369                         >;
 370                         nvmem-cells = <&cpu_leakage>;
 371                         nvmem-cell-names = "cpu_leakage";
 372                 };
 373                 cluster1-avs {
 374                         cluster-id = <1>;
 375                         min-volt = <950000>; /* uV */
 376                         min-freq = <216000>; /* KHz */
 377                         leakage-adjust-volt = <
 378                         /*  mA        mA         uV */
 379                             0         254        0
 380                         >;
 381                         nvmem-cells = <&cpu_leakage>;
 382                         nvmem-cell-names = "cpu_leakage";
 383                 };
 384         };
 385
 386         arm-pmu {
 387                 compatible = "arm,armv8-pmuv3";
 388                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 389                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 390                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 391                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 392                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 393                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 394                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 395                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 396                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 397                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 398                                      <&cpu_b2>, <&cpu_b3>;
 399         };
 400
 401         amba {
 402                 compatible = "arm,amba-bus";
 403                 #address-cells = <2>;
 404                 #size-cells = <2>;
 405                 ranges;
 406
 407                 dmac_peri: dma-controller@ff250000 {
 408                         compatible = "arm,pl330", "arm,primecell";
 409                         reg = <0x0 0xff250000 0x0 0x4000>;
 410                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 411                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 412                         #dma-cells = <1>;
 413                         clocks = <&cru ACLK_DMAC_PERI>;
 414                         clock-names = "apb_pclk";
 415                         arm,pl330-broken-no-flushp;
 416                         peripherals-req-type-burst;
 417                 };
 418
 419                 dmac_bus: dma-controller@ff600000 {
 420                         compatible = "arm,pl330", "arm,primecell";
 421                         reg = <0x0 0xff600000 0x0 0x4000>;
 422                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 423                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 424                         #dma-cells = <1>;
 425                         clocks = <&cru ACLK_DMAC_BUS>;
 426                         clock-names = "apb_pclk";
 427                         arm,pl330-broken-no-flushp;
 428                         peripherals-req-type-burst;
 429                 };
 430         };
 431
 432         psci {
 433                 compatible = "arm,psci-0.2";
 434                 method = "smc";
 435         };
 436
 437         timer {
 438                 compatible = "arm,armv8-timer";
 439                 interrupts = <GIC_PPI 13
 440                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 441                              <GIC_PPI 14
 442                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 443                              <GIC_PPI 11
 444                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 445                              <GIC_PPI 10
 446                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 447         };
 448
 449         xin24m: oscillator {
 450                 compatible = "fixed-clock";
 451                 clock-frequency = <24000000>;
 452                 clock-output-names = "xin24m";
 453                 #clock-cells = <0>;
 454         };
 455
 456         sdmmc: dwmmc@ff0c0000 {
 457                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 458                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 459                 clock-freq-min-max = <400000 150000000>;
 460                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 461                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 462                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 463                 fifo-depth = <0x100>;
 464                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 465                 status = "disabled";
 466         };
 467
 468         sdio0: dwmmc@ff0d0000 {
 469                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 470                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 471                 clock-freq-min-max = <400000 150000000>;
 472                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 473                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 474                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 475                 fifo-depth = <0x100>;
 476                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 477                 status = "disabled";
 478         };
 479
 480         emmc: dwmmc@ff0f0000 {
 481                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 482                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 483                 clock-freq-min-max = <400000 150000000>;
 484                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 485                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 486                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 487                 fifo-depth = <0x100>;
 488                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 489                 status = "disabled";
 490         };
 491
 492         saradc: saradc@ff100000 {
 493                 compatible = "rockchip,saradc";
 494                 reg = <0x0 0xff100000 0x0 0x100>;
 495                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 496                 #io-channel-cells = <1>;
 497                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 498                 clock-names = "saradc", "apb_pclk";
 499                 resets = <&cru SRST_SARADC>;
 500                 reset-names = "saradc-apb";
 501                 status = "disabled";
 502         };
 503
 504         spi0: spi@ff110000 {
 505                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 506                 reg = <0x0 0xff110000 0x0 0x1000>;
 507                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 508                 clock-names = "spiclk", "apb_pclk";
 509                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 512                 #address-cells = <1>;
 513                 #size-cells = <0>;
 514                 status = "disabled";
 515         };
 516
 517         spi1: spi@ff120000 {
 518                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 519                 reg = <0x0 0xff120000 0x0 0x1000>;
 520                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 521                 clock-names = "spiclk", "apb_pclk";
 522                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 523                 pinctrl-names = "default";
 524                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 525                 #address-cells = <1>;
 526                 #size-cells = <0>;
 527                 status = "disabled";
 528         };
 529
 530         spi2: spi@ff130000 {
 531                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 532                 reg = <0x0 0xff130000 0x0 0x1000>;
 533                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 534                 clock-names = "spiclk", "apb_pclk";
 535                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 536                 pinctrl-names = "default";
 537                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 538                 #address-cells = <1>;
 539                 #size-cells = <0>;
 540                 status = "disabled";
 541         };
 542
 543         i2c0: i2c@ff650000 {
 544                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 545                 reg = <0x0 0xff650000 0x0 0x1000>;
 546                 clocks = <&cru PCLK_I2C0>;
 547                 clock-names = "i2c";
 548                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&i2c0_xfer>;
 551                 #address-cells = <1>;
 552                 #size-cells = <0>;
 553                 status = "disabled";
 554         };
 555
 556         i2c2: i2c@ff140000 {
 557                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 558                 reg = <0x0 0xff140000 0x0 0x1000>;
 559                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 560                 #address-cells = <1>;
 561                 #size-cells = <0>;
 562                 clock-names = "i2c";
 563                 clocks = <&cru PCLK_I2C2>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c2_xfer>;
 566                 status = "disabled";
 567         };
 568
 569         i2c3: i2c@ff150000 {
 570                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 571                 reg = <0x0 0xff150000 0x0 0x1000>;
 572                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 573                 #address-cells = <1>;
 574                 #size-cells = <0>;
 575                 clock-names = "i2c";
 576                 clocks = <&cru PCLK_I2C3>;
 577                 pinctrl-names = "default";
 578                 pinctrl-0 = <&i2c3_xfer>;
 579                 status = "disabled";
 580         };
 581
 582         i2c4: i2c@ff160000 {
 583                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 584                 reg = <0x0 0xff160000 0x0 0x1000>;
 585                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 586                 #address-cells = <1>;
 587                 #size-cells = <0>;
 588                 clock-names = "i2c";
 589                 clocks = <&cru PCLK_I2C4>;
 590                 pinctrl-names = "default";
 591                 pinctrl-0 = <&i2c4_xfer>;
 592                 status = "disabled";
 593         };
 594
 595         i2c5: i2c@ff170000 {
 596                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 597                 reg = <0x0 0xff170000 0x0 0x1000>;
 598                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 599                 #address-cells = <1>;
 600                 #size-cells = <0>;
 601                 clock-names = "i2c";
 602                 clocks = <&cru PCLK_I2C5>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&i2c5_xfer>;
 605                 status = "disabled";
 606         };
 607
 608         uart0: serial@ff180000 {
 609                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 610                 reg = <0x0 0xff180000 0x0 0x100>;
 611                 clock-frequency = <24000000>;
 612                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 status = "disabled";
 618         };
 619
 620         uart1: serial@ff190000 {
 621                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 622                 reg = <0x0 0xff190000 0x0 0x100>;
 623                 clock-frequency = <24000000>;
 624                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 625                 clock-names = "baudclk", "apb_pclk";
 626                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 627                 reg-shift = <2>;
 628                 reg-io-width = <4>;
 629                 status = "disabled";
 630         };
 631
 632         uart3: serial@ff1b0000 {
 633                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 634                 reg = <0x0 0xff1b0000 0x0 0x100>;
 635                 clock-frequency = <24000000>;
 636                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 637                 clock-names = "baudclk", "apb_pclk";
 638                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 639                 reg-shift = <2>;
 640                 reg-io-width = <4>;
 641                 status = "disabled";
 642         };
 643
 644         uart4: serial@ff1c0000 {
 645                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 646                 reg = <0x0 0xff1c0000 0x0 0x100>;
 647                 clock-frequency = <24000000>;
 648                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 649                 clock-names = "baudclk", "apb_pclk";
 650                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 651                 reg-shift = <2>;
 652                 reg-io-width = <4>;
 653                 status = "disabled";
 654         };
 655
 656         thermal_zones: thermal-zones {
 657                 soc_thermal: soc-thermal {
 658                         polling-delay-passive = <200>; /* milliseconds */
 659                         polling-delay = <200>; /* milliseconds */
 660                         sustainable-power = <600>; /* milliwatts */
 661
 662                         thermal-sensors = <&tsadc 0>;
 663                         trips {
 664                                 threshold: trip-point@0 {
 665                                         temperature = <70000>; /* millicelsius */
 666                                         hysteresis = <2000>; /* millicelsius */
 667                                         type = "passive";
 668                                 };
 669                                 target: trip-point@1 {
 670                                         temperature = <80000>; /* millicelsius */
 671                                         hysteresis = <2000>; /* millicelsius */
 672                                         type = "passive";
 673                                 };
 674                                 soc_crit: soc-crit {
 675                                         temperature = <95000>; /* millicelsius */
 676                                         hysteresis = <2000>; /* millicelsius */
 677                                         type = "critical";
 678                                 };
 679                         };
 680
 681                         cooling-maps {
 682                                 map0 {
 683                                         trip = <&target>;
 684                                         cooling-device =
 685                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 686                                         contribution = <1024>;
 687                                 };
 688                                 map1 {
 689                                         trip = <&target>;
 690                                         cooling-device =
 691                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 692                                         contribution = <1024>;
 693                                 };
 694                                 map2 {
 695                                         trip = <&target>;
 696                                         cooling-device =
 697                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 698                                         contribution = <1024>;
 699                                 };
 700                         };
 701                 };
 702
 703                 gpu_thermal: gpu-thermal {
 704                         polling-delay-passive = <200>; /* milliseconds */
 705                         polling-delay = <200>; /* milliseconds */
 706                         thermal-sensors = <&tsadc 1>;
 707                 };
 708         };
 709
 710         tsadc: tsadc@ff280000 {
 711                 compatible = "rockchip,rk3368-tsadc-legacy";
 712                 reg = <0x0 0xff280000 0x0 0x100>;
 713                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 715                 clock-names = "tsadc", "apb_pclk";
 716                 clock-frequency = <32768>;
 717                 resets = <&cru SRST_TSADC>;
 718                 reset-names = "tsadc-apb";
 719                 nvmem-cells = <&temp_adjust>;
 720                 nvmem-cell-names = "temp_adjust";
 721                 #thermal-sensor-cells = <1>;
 722                 hw-shut-temp = <95000>;
 723                 latency-bound = <50000>;
 724                 status = "disabled";
 725         };
 726
 727         gmac: ethernet@ff290000 {
 728                 compatible = "rockchip,rk3368-gmac";
 729                 reg = <0x0 0xff290000 0x0 0x10000>;
 730                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 731                 interrupt-names = "macirq";
 732                 rockchip,grf = <&grf>;
 733                 clocks = <&cru SCLK_MAC>,
 734                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 735                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 736                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 737                 clock-names = "stmmaceth",
 738                         "mac_clk_rx", "mac_clk_tx",
 739                         "clk_mac_ref", "clk_mac_refout",
 740                         "aclk_mac", "pclk_mac";
 741                 status = "disabled";
 742         };
 743
 744         nandc0: nandc@ff400000 {
 745                 compatible = "rockchip,rk-nandc";
 746                 reg = <0x0 0xff400000 0x0 0x4000>;
 747                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 748                 nandc_id = <0>;
 749                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 750                 clock-names = "clk_nandc", "hclk_nandc";
 751                 status = "disabled";
 752         };
 753
 754         usb_host0_ehci: usb@ff500000 {
 755                 compatible = "generic-ehci";
 756                 reg = <0x0 0xff500000 0x0 0x20000>;
 757                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 758                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 759                 clock-names = "usbhost", "utmi";
 760                 phys = <&u2phy_host>;
 761                 phy-names = "usb";
 762                 status = "disabled";
 763         };
 764
 765         usb_host0_ohci: usb@ff520000 {
 766                 compatible = "generic-ohci";
 767                 reg = <0x0 0xff520000 0x0 0x20000>;
 768                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&cru HCLK_HOST0>, <&u2phy>;
 770                 clock-names = "usbhost", "utmi";
 771                 phys = <&u2phy_host>;
 772                 phy-names = "usb";
 773                 status = "disabled";
 774         };
 775
 776         usb_otg: usb@ff580000 {
 777                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 778                                 "snps,dwc2";
 779                 reg = <0x0 0xff580000 0x0 0x40000>;
 780                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 781                 clocks = <&cru HCLK_OTG0>;
 782                 clock-names = "otg";
 783                 dr_mode = "otg";
 784                 g-np-tx-fifo-size = <16>;
 785                 g-rx-fifo-size = <275>;
 786                 g-tx-fifo-size = <256 128 128 64 64 32>;
 787                 g-use-dma;
 788                 status = "disabled";
 789         };
 790
 791         ddrpctl: syscon@ff610000 {
 792                 compatible = "rockchip,rk3368-ddrpctl", "syscon";
 793                 reg = <0x0 0xff610000 0x0 0x400>;
 794         };
 795
 796         i2c1: i2c@ff660000 {
 797                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 798                 reg = <0x0 0xff660000 0x0 0x1000>;
 799                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 800                 #address-cells = <1>;
 801                 #size-cells = <0>;
 802                 clock-names = "i2c";
 803                 clocks = <&cru PCLK_I2C1>;
 804                 pinctrl-names = "default";
 805                 pinctrl-0 = <&i2c1_xfer>;
 806                 status = "disabled";
 807         };
 808
 809         pwm0: pwm@ff680000 {
 810                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 811                 reg = <0x0 0xff680000 0x0 0x10>;
 812                 #pwm-cells = <3>;
 813                 pinctrl-names = "default";
 814                 pinctrl-0 = <&pwm0_pin>;
 815                 clocks = <&cru PCLK_PWM1>;
 816                 clock-names = "pwm";
 817                 status = "disabled";
 818         };
 819
 820         pwm1: pwm@ff680010 {
 821                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 822                 reg = <0x0 0xff680010 0x0 0x10>;
 823                 #pwm-cells = <3>;
 824                 pinctrl-names = "default";
 825                 pinctrl-0 = <&pwm1_pin>;
 826                 clocks = <&cru PCLK_PWM1>;
 827                 clock-names = "pwm";
 828                 status = "disabled";
 829         };
 830
 831         pwm2: pwm@ff680020 {
 832                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 833                 reg = <0x0 0xff680020 0x0 0x10>;
 834                 #pwm-cells = <3>;
 835                 clocks = <&cru PCLK_PWM1>;
 836                 clock-names = "pwm";
 837                 status = "disabled";
 838         };
 839
 840         pwm3: pwm@ff680030 {
 841                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 842                 reg = <0x0 0xff680030 0x0 0x10>;
 843                 #pwm-cells = <3>;
 844                 pinctrl-names = "default";
 845                 pinctrl-0 = <&pwm3_pin>;
 846                 clocks = <&cru PCLK_PWM1>;
 847                 clock-names = "pwm";
 848                 status = "disabled";
 849         };
 850
 851         uart2: serial@ff690000 {
 852                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 853                 reg = <0x0 0xff690000 0x0 0x100>;
 854                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 855                 clock-names = "baudclk", "apb_pclk";
 856                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&uart2_xfer>;
 859                 reg-shift = <2>;
 860                 reg-io-width = <4>;
 861                 status = "disabled";
 862         };
 863
 864         mbox: mbox@ff6b0000 {
 865                 compatible = "rockchip,rk3368-mailbox";
 866                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 867                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 868                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 869                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 870                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 871                 clocks = <&cru PCLK_MAILBOX>;
 872                 clock-names = "pclk_mailbox";
 873                 #mbox-cells = <1>;
 874                 status = "disabled";
 875         };
 876
 877         mailbox: mailbox@ff6b0000 {
 878                 compatible = "rockchip,rk3368-mbox-legacy";
 879                 reg = <0x0 0xff6b0000 0x0 0x1000>,
 880                       <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
 881                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 882                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 883                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 884                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 885                 clocks = <&cru PCLK_MAILBOX>;
 886                 clock-names = "pclk_mailbox";
 887                 #mbox-cells = <1>;
 888                 status = "disabled";
 889         };
 890
 891         mailbox_scpi: mailbox-scpi {
 892                 compatible = "rockchip,rk3368-scpi-legacy";
 893                 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
 894                 chan-nums = <3>;
 895                 status = "disabled";
 896         };
 897
 898         qos_iep: qos@ffad0000 {
 899                 compatible = "syscon";
 900                 reg = <0x0 0xffad0000 0x0 0x20>;
 901         };
 902
 903         qos_isp_r0: qos@ffad0080 {
 904                 compatible = "syscon";
 905                 reg = <0x0 0xffad0080 0x0 0x20>;
 906         };
 907
 908         qos_isp_r1: qos@ffad0100 {
 909                 compatible = "syscon";
 910                 reg = <0x0 0xffad0100 0x0 0x20>;
 911         };
 912
 913         qos_isp_w0: qos@ffad0180 {
 914                 compatible = "syscon";
 915                 reg = <0x0 0xffad0180 0x0 0x20>;
 916         };
 917
 918         qos_isp_w1: qos@ffad0200 {
 919                 compatible = "syscon";
 920                 reg = <0x0 0xffad0200 0x0 0x20>;
 921         };
 922
 923         qos_vip: qos@ffad0280 {
 924                 compatible = "syscon";
 925                 reg = <0x0 0xffad0280 0x0 0x20>;
 926         };
 927
 928         qos_vop: qos@ffad0300 {
 929                 compatible = "syscon";
 930                 reg = <0x0 0xffad0300 0x0 0x20>;
 931         };
 932
 933         qos_rga_r: qos@ffad0380 {
 934                 compatible = "syscon";
 935                 reg = <0x0 0xffad0380 0x0 0x20>;
 936         };
 937
 938         qos_rga_w: qos@ffad0400 {
 939                 compatible = "syscon";
 940                 reg = <0x0 0xffad0400 0x0 0x20>;
 941         };
 942
 943         qos_hevc_r: qos@ffae0000 {
 944                 compatible = "syscon";
 945                 reg = <0x0 0xffae0000 0x0 0x20>;
 946         };
 947
 948         qos_vpu_r: qos@ffae0100 {
 949                 compatible = "syscon";
 950                 reg = <0x0 0xffae0100 0x0 0x20>;
 951         };
 952
 953         qos_vpu_w: qos@ffae0180 {
 954                 compatible = "syscon";
 955                 reg = <0x0 0xffae0180 0x0 0x20>;
 956         };
 957
 958         qos_gpu: qos@ffaf0000 {
 959                 compatible = "syscon";
 960                 reg = <0x0 0xffaf0000 0x0 0x20>;
 961         };
 962
 963         pmu: power-management@ff730000 {
 964                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
 965                 reg = <0x0 0xff730000 0x0 0x1000>;
 966
 967                 power: power-controller {
 968                         compatible = "rockchip,rk3368-power-controller";
 969                         #power-domain-cells = <1>;
 970                         #address-cells = <1>;
 971                         #size-cells = <0>;
 972
 973                         /*
 974                          * Note: Although SCLK_* are the working clocks
 975                          * of device without including on the NOC, needed for
 976                          * synchronous reset.
 977                          *
 978                          * The clocks on the which NOC:
 979                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 980                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 981                          * ACLK_RGA is on ACLK_RGA_NIU.
 982                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 983                          *
 984                          * Which clock are device clocks:
 985                          *      clocks          devices
 986                          *      *_IEP           IEP:Image Enhancement Processor
 987                          *      *_ISP           ISP:Image Signal Processing
 988                          *      *_VIP           VIP:Video Input Processor
 989                          *      *_VOP*          VOP:Visual Output Processor
 990                          *      *_RGA           RGA
 991                          *      *_EDP*          EDP
 992                          *      *_DPHY*         LVDS
 993                          *      *_HDMI          HDMI
 994                          *      *_MIPI_*        MIPI
 995                          */
 996                         pd_vio {
 997                                 reg = <RK3368_PD_VIO>;
 998                                 clocks = <&cru ACLK_IEP>,
 999                                          <&cru ACLK_ISP>,
1000                                          <&cru ACLK_VIP>,
1001                                          <&cru ACLK_RGA>,
1002                                          <&cru ACLK_VOP>,
1003                                          <&cru ACLK_VOP_IEP>,
1004                                          <&cru DCLK_VOP>,
1005                                          <&cru HCLK_IEP>,
1006                                          <&cru HCLK_ISP>,
1007                                          <&cru HCLK_RGA>,
1008                                          <&cru HCLK_VIP>,
1009                                          <&cru HCLK_VOP>,
1010                                          <&cru HCLK_VIO_HDCPMMU>,
1011                                          <&cru PCLK_EDP_CTRL>,
1012                                          <&cru PCLK_HDMI_CTRL>,
1013                                          <&cru PCLK_HDCP>,
1014                                          <&cru PCLK_ISP>,
1015                                          <&cru PCLK_VIP>,
1016                                          <&cru PCLK_DPHYRX>,
1017                                          <&cru PCLK_DPHYTX0>,
1018                                          <&cru PCLK_MIPI_CSI>,
1019                                          <&cru PCLK_MIPI_DSI0>,
1020                                          <&cru SCLK_VOP0_PWM>,
1021                                          <&cru SCLK_EDP_24M>,
1022                                          <&cru SCLK_EDP>,
1023                                          <&cru SCLK_HDCP>,
1024                                          <&cru SCLK_ISP>,
1025                                          <&cru SCLK_RGA>,
1026                                          <&cru SCLK_HDMI_CEC>,
1027                                          <&cru SCLK_HDMI_HDCP>;
1028                                 pm_qos = <&qos_iep>,
1029                                          <&qos_isp_r0>,
1030                                          <&qos_isp_r1>,
1031                                          <&qos_isp_w0>,
1032                                          <&qos_isp_w1>,
1033                                          <&qos_vip>,
1034                                          <&qos_vop>,
1035                                          <&qos_rga_r>,
1036                                          <&qos_rga_w>;
1037                         };
1038                         /*
1039                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1040                          * (video endecoder & decoder) clocks that on the
1041                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1042                          */
1043                         pd_video {
1044                                 reg = <RK3368_PD_VIDEO>;
1045                                 clocks = <&cru ACLK_VIDEO>,
1046                                          <&cru HCLK_VIDEO>,
1047                                          <&cru SCLK_HEVC_CABAC>,
1048                                          <&cru SCLK_HEVC_CORE>;
1049                                 pm_qos = <&qos_hevc_r>,
1050                                          <&qos_vpu_r>,
1051                                          <&qos_vpu_w>;
1052                         };
1053                         /*
1054                          * Note: ACLK_GPU is the GPU clock,
1055                          * and on the ACLK_GPU_NIU (NOC).
1056                          */
1057                         pd_gpu_1 {
1058                                 reg = <RK3368_PD_GPU_1>;
1059                                 clocks = <&cru ACLK_GPU_CFG>,
1060                                          <&cru ACLK_GPU_MEM>,
1061                                          <&cru SCLK_GPU_CORE>;
1062                                 pm_qos = <&qos_gpu>;
1063                         };
1064                 };
1065         };
1066
1067         pmugrf: syscon@ff738000 {
1068                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1069                 reg = <0x0 0xff738000 0x0 0x1000>;
1070
1071                 pmu_io_domains: io-domains {
1072                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1073                         status = "disabled";
1074                 };
1075
1076                 reboot-mode {
1077                         compatible = "syscon-reboot-mode";
1078                         offset = <0x200>;
1079                         mode-normal = <BOOT_NORMAL>;
1080                         mode-recovery = <BOOT_RECOVERY>;
1081                         mode-bootloader = <BOOT_FASTBOOT>;
1082                         mode-loader = <BOOT_BL_DOWNLOAD>;
1083                 };
1084         };
1085
1086         cru: clock-controller@ff760000 {
1087                 compatible = "rockchip,rk3368-cru";
1088                 reg = <0x0 0xff760000 0x0 0x1000>;
1089                 rockchip,grf = <&grf>;
1090                 #clock-cells = <1>;
1091                 #reset-cells = <1>;
1092                 assigned-clocks =
1093                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1094                         <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1095                         <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1096                         <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1097                         <&cru ACLK_CCI_PRE>;
1098                 assigned-clock-rates =
1099                         <576000000>, <400000000>,
1100                         <300000000>, <300000000>,
1101                         <150000000>, <150000000>,
1102                         <75000000>, <75000000>,
1103                         <576000000>;
1104         };
1105
1106         grf: syscon@ff770000 {
1107                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1108                 reg = <0x0 0xff770000 0x0 0x1000>;
1109                 #address-cells = <1>;
1110                 #size-cells = <1>;
1111
1112                 edp_phy: edp-phy {
1113                         compatible = "rockchip,rk3368-dp-phy";
1114                         clocks = <&cru SCLK_EDP_24M>;
1115                         clock-names = "24m";
1116                         resets = <&cru SRST_EDP_24M>;
1117                         reset-names = "edp_24m";
1118                         #phy-cells = <0>;
1119                         status = "disabled";
1120                 };
1121
1122                 io_domains: io-domains {
1123                         compatible = "rockchip,rk3368-io-voltage-domain";
1124                         status = "disabled";
1125                 };
1126
1127                 u2phy: usb2-phy@700 {
1128                         compatible = "rockchip,rk3368-usb2phy";
1129                         reg = <0x700 0x2c>;
1130                         clocks = <&cru SCLK_OTGPHY0>;
1131                         clock-names = "phyclk";
1132                         #clock-cells = <0>;
1133                         clock-output-names = "usbotg_out";
1134                         assigned-clocks = <&cru SCLK_USBPHY480M>;
1135                         assigned-clock-parents = <&u2phy>;
1136                         status = "disabled";
1137
1138                         u2phy_host: host-port {
1139                                 #phy-cells = <0>;
1140                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1141                                 interrupt-names = "linestate";
1142                                 status = "disabled";
1143                         };
1144                 };
1145         };
1146
1147         wdt: watchdog@ff800000 {
1148                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1149                 reg = <0x0 0xff800000 0x0 0x100>;
1150                 clocks = <&cru PCLK_WDT>;
1151                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1152                 status = "disabled";
1153         };
1154
1155         timer@ff810000 {
1156                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1157                 reg = <0x0 0xff810000 0x0 0x20>;
1158                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1159         };
1160
1161         i2s_2ch: i2s-2ch@ff890000 {
1162                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1163                 reg = <0x0 0xff890000 0x0 0x1000>;
1164                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1165                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1166                 dma-names = "tx", "rx";
1167                 clock-names = "i2s_clk", "i2s_hclk";
1168                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1169                 status = "disabled";
1170         };
1171
1172         i2s_8ch: i2s-8ch@ff898000 {
1173                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1174                 reg = <0x0 0xff898000 0x0 0x1000>;
1175                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1176                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1177                 dma-names = "tx", "rx";
1178                 clock-names = "i2s_clk", "i2s_hclk";
1179                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1180                 pinctrl-names = "default";
1181                 pinctrl-0 = <&i2s_8ch_bus>;
1182                 status = "disabled";
1183         };
1184
1185         iep: iep@ff900000 {
1186                 compatible = "rockchip,iep";
1187                 iommu_enabled = <1>;
1188                 iommus = <&iep_mmu>;
1189                 reg = <0x0 0xff900000 0x0 0x800>;
1190                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1191                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1192                 clock-names = "aclk_iep", "hclk_iep";
1193                 power-domains = <&power RK3368_PD_VIO>;
1194                 allocator = <1>;
1195                 version = <2>;
1196                 status = "disabled";
1197         };
1198
1199         iep_mmu: iommu@ff900800 {
1200                 compatible = "rockchip,iommu";
1201                 reg = <0x0 0xff900800 0x0 0x100>;
1202                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1203                 interrupt-names = "iep_mmu";
1204                 power-domains = <&power RK3368_PD_VIO>;
1205                 #iommu-cells = <0>;
1206                 status = "disabled";
1207         };
1208
1209         isp: isp@ff910000 {
1210                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1211                 reg = <0x0 0xff910000 0x0 0x4000>;
1212                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1213                 power-domains = <&power RK3368_PD_VIO>;
1214                 clocks =
1215                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1216                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1217                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1218                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1219                 clock-names =
1220                         "aclk_isp", "hclk_isp", "clk_isp",
1221                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1222                         "clk_cif_pll", "hclk_mipiphy1",
1223                         "pclk_dphyrx", "clk_vio0_noc";
1224
1225                 pinctrl-names =
1226                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1227                         "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1228                         "isp_mipi_fl", "isp_mipi_fl_prefl",
1229                         "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1230                 pinctrl-0 = <&cif_clkout>;
1231                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1232                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1233                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1234                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1235                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1236                 pinctrl-6 = <&cif_clkout>;
1237                 pinctrl-7 = <&cif_clkout &isp_prelight>;
1238                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1239                 pinctrl-9 = <&isp_flash_trigger>;
1240                 rockchip,isp,mipiphy = <2>;
1241                 rockchip,isp,cifphy = <1>;
1242                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1243                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1244                 rockchip,grf = <&grf>;
1245                 rockchip,cru = <&cru>;
1246                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1247                 rockchip,isp,iommu-enable = <1>;
1248                 iommus = <&isp_mmu>;
1249                 status = "disabled";
1250         };
1251
1252         isp_mmu: iommu@ff914000 {
1253                 compatible = "rockchip,iommu";
1254                 reg = <0x0 0xff914000 0x0 0x100>,
1255                       <0x0 0xff915000 0x0 0x100>;
1256                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1257                 interrupt-names = "isp_mmu";
1258                 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1259                 clock-names = "aclk", "hclk";
1260                 rk_iommu,disable_reset_quirk;
1261                 #iommu-cells = <0>;
1262                 power-domains = <&power RK3368_PD_VIO>;
1263                 status = "disabled";
1264         };
1265
1266         vop: vop@ff930000 {
1267                 compatible = "rockchip,rk3368-vop";
1268                 reg = <0x0 0xff930000 0x0 0x2fc>;
1269                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1270                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1271                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1272                 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1273                 assigned-clock-rates = <400000000>, <200000000>;
1274                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1275                 reset-names = "axi", "ahb", "dclk";
1276                 power-domains = <&power RK3368_PD_VIO>;
1277                 iommus = <&vop_mmu>;
1278                 status = "disabled";
1279
1280                 vop_out: port {
1281                         #address-cells = <1>;
1282                         #size-cells = <0>;
1283
1284                         vop_out_mipi: endpoint@0 {
1285                                 reg = <0>;
1286                                 remote-endpoint = <&mipi_in_vop>;
1287                         };
1288
1289                         vop_out_edp: endpoint@1 {
1290                                 reg = <1>;
1291                                 remote-endpoint = <&edp_in_vop>;
1292                         };
1293                 };
1294         };
1295
1296         display_subsystem: display-subsystem {
1297                 compatible = "rockchip,display-subsystem";
1298                 ports = <&vop_out>;
1299                 status = "disabled";
1300         };
1301
1302         vop_mmu: iommu@ff930300 {
1303                 compatible = "rockchip,iommu";
1304                 reg = <0x0 0xff930300 0x0 0x100>;
1305                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1306                 interrupt-names = "vop_mmu";
1307                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1308                 clock-names = "aclk", "hclk";
1309                 power-domains = <&power RK3368_PD_VIO>;
1310                 #iommu-cells = <0>;
1311                 status = "disabled";
1312         };
1313
1314         mipi_dsi_host: mipi-dsi-host@ff960000 {
1315                 compatible = "rockchip,rk3368-mipi-dsi";
1316                 reg = <0x0 0xff960000 0x0 0x4000>;
1317                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1318                 clocks = <&cru PCLK_MIPI_DSI0>;
1319                 clock-names = "pclk";
1320                 resets = <&cru SRST_MIPIDSI0>;
1321                 reset-names = "apb";
1322                 phys = <&mipi_dphy>;
1323                 phy-names = "mipi_dphy";
1324                 rockchip,grf = <&grf>;
1325                 power-domains = <&power RK3368_PD_VIO>;
1326                 #address-cells = <1>;
1327                 #size-cells = <0>;
1328                 status = "disabled";
1329
1330                 ports {
1331                         port {
1332                                 mipi_in_vop: endpoint {
1333                                         remote-endpoint = <&vop_out_mipi>;
1334                                 };
1335                         };
1336                 };
1337         };
1338
1339         mipi_dphy: mipi-dphy@ff968000 {
1340                 compatible = "rockchip,rk3368-mipi-dphy";
1341                 reg = <0x0 0xff968000 0x0 0x4000>;
1342                 #phy-cells = <0>;
1343                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1344                 clock-names = "ref", "pclk";
1345                 resets = <&cru SRST_MIPIDPHYTX>;
1346                 reset-names = "apb";
1347                 status = "disabled";
1348         };
1349
1350         edp: edp@ff970000 {
1351                 compatible = "rockchip,rk3368-edp";
1352                 reg = <0x0 0xff970000 0x0 0x8000>;
1353                 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1354                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1355                 clock-names = "dp", "pclk";
1356                 resets = <&cru SRST_EDP>;
1357                 reset-names = "dp";
1358                 power-domains = <&power RK3368_PD_VIO>;
1359                 rockchip,grf = <&grf>;
1360                 phys = <&edp_phy>;
1361                 phy-names = "dp";
1362                 pinctrl-names = "default";
1363                 pinctrl-0 = <&edp_hpd>;
1364                 status = "disabled";
1365
1366                 ports {
1367                         #address-cells = <1>;
1368                         #size-cells = <0>;
1369
1370                         edp_in: port@0 {
1371                                 reg = <0>;
1372
1373                                 edp_in_vop: endpoint {
1374                                         remote-endpoint = <&vop_out_edp>;
1375                                 };
1376                         };
1377                 };
1378         };
1379
1380         hevc_mmu: iommu@ff9a0440 {
1381                 compatible = "rockchip,iommu";
1382                 reg = <0x0 0xff9a0440 0x0 0x40>,
1383                       <0x0 0xff9a0480 0x0 0x40>;
1384                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1385                 interrupt-names = "hevc_mmu";
1386                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1387                 clock-names = "aclk", "hclk";
1388                 power-domains = <&power RK3368_PD_VIDEO>;
1389                 #iommu-cells = <0>;
1390                 status = "disabled";
1391         };
1392
1393         vpu_mmu: iommu@ff9a0800 {
1394                 compatible = "rockchip,iommu";
1395                 reg = <0x0 0xff9a0800 0x0 0x100>;
1396                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1397                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1398                 interrupt-names = "vepu_mmu", "vdpu_mmu";
1399                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1400                 clock-names = "aclk", "hclk";
1401                 power-domains = <&power RK3368_PD_VIDEO>;
1402                 #iommu-cells = <0>;
1403                 status = "disabled";
1404         };
1405
1406         vpu: vpu_service {
1407                 compatible = "rockchip,vpu_sub";
1408                 iommu_enabled = <1>;
1409                 iommus = <&vpu_mmu>;
1410                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1411                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1412                 interrupt-names = "irq_enc","irq_dec";
1413                 dev_mode = <0>;
1414                 name = "vpu_service";
1415                 allocator = <1>;
1416         };
1417
1418         hevc: hevc_service {
1419                 compatible = "rockchip,hevc_sub";
1420                 iommu_enabled = <1>;
1421                 iommus = <&hevc_mmu>;
1422                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1423                 interrupt-names = "irq_dec";
1424                 dev_mode = <1>;
1425                 name = "hevc_service";
1426                 allocator = <1>;
1427         };
1428
1429         vpu_combo: vpu_combo@ff9a0000 {
1430                 compatible = "rockchip,vpu_combo";
1431                 reg = <0x0 0xff9a0000 0x0 0x440>;
1432                 rockchip,grf = <&grf>;
1433                 subcnt = <2>;
1434                 rockchip,sub = <&vpu>, <&hevc>;
1435                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1436                          <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1437                 clock-names = "aclk_vcodec", "hclk_vcodec",
1438                               "clk_core", "clk_cabac";
1439                 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1440                          <&cru SRST_VIDEO>;
1441                 reset-names = "video_a", "video_h", "video";
1442                 mode_bit = <12>;
1443                 mode_ctrl = <0x418>;
1444                 name = "vpu_combo";
1445                 power-domains = <&power RK3368_PD_VIDEO>;
1446                 status = "disabled";
1447         };
1448
1449         gic: interrupt-controller@ffb71000 {
1450                 compatible = "arm,gic-400";
1451                 interrupt-controller;
1452                 #interrupt-cells = <3>;
1453                 #address-cells = <0>;
1454
1455                 reg = <0x0 0xffb71000 0x0 0x1000>,
1456                       <0x0 0xffb72000 0x0 0x2000>,
1457                       <0x0 0xffb74000 0x0 0x2000>,
1458                       <0x0 0xffb76000 0x0 0x2000>;
1459                 interrupts = <GIC_PPI 9
1460                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1461         };
1462
1463         gpu: rogue-g6110@ffa30000 {
1464                 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1465                 reg = <0x0 0xffa30000 0x0 0x10000>;
1466                 clocks =
1467                         <&cru SCLK_GPU_CORE>,
1468                         <&cru ACLK_GPU_MEM>,
1469                         <&cru ACLK_GPU_CFG>;
1470                 clock-names =
1471                         "sclk_gpu_core",
1472                         "aclk_gpu_mem",
1473                         "aclk_gpu_cfg";
1474                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1475                 interrupt-names = "rogue-g6110-irq";
1476                 power-domains = <&power RK3368_PD_GPU_1>;
1477                 operating-points-v2 = <&gpu_opp_table>;
1478                 #cooling-cells = <2>; /* min followed by max */
1479                 gpu_power_model: power_model {
1480                         compatible = "arm,mali-simple-power-model";
1481                         voltage = <900>;
1482                         frequency = <500>;
1483                         static-power = <300>;
1484                         dynamic-power = <396>;
1485                         ts = <32000 4700 (-80) 2>;
1486                         thermal-zone = "gpu-thermal";
1487                 };
1488         };
1489
1490         gpu_opp_table: gpu_opp_table {
1491                 compatible = "operating-points-v2";
1492                 opp-shared;
1493
1494                 opp@200000000 {
1495                         opp-hz = /bits/ 64 <200000000>;
1496                         opp-microvolt = <1100000>;
1497                 };
1498                 opp@288000000 {
1499                         opp-hz = /bits/ 64 <288000000>;
1500                         opp-microvolt = <1100000>;
1501                 };
1502                 opp@400000000 {
1503                         opp-hz = /bits/ 64 <400000000>;
1504                         opp-microvolt = <1100000>;
1505                 };
1506                 opp@576000000 {
1507                         opp-hz = /bits/ 64 <576000000>;
1508                         opp-microvolt = <1200000>;
1509                 };
1510         };
1511
1512         efuse: efuse@ffb00000 {
1513                 compatible = "rockchip,rk3368-efuse";
1514                 reg = <0x0 0xffb00000 0x0 0x20>;
1515                 #address-cells = <1>;
1516                 #size-cells = <1>;
1517                 clocks = <&cru PCLK_EFUSE256>;
1518                 clock-names = "pclk_efuse";
1519
1520                 /* Data cells */
1521                 cpu_leakage: cpu-leakage@17 {
1522                         reg = <0x17 0x1>;
1523                 };
1524                 temp_adjust: temp-adjust@1f {
1525                         reg = <0x1f 0x1>;
1526                 };
1527         };
1528
1529         pinctrl: pinctrl {
1530                 compatible = "rockchip,rk3368-pinctrl";
1531                 rockchip,grf = <&grf>;
1532                 rockchip,pmu = <&pmugrf>;
1533                 #address-cells = <0x2>;
1534                 #size-cells = <0x2>;
1535                 ranges;
1536
1537                 gpio0: gpio0@ff750000 {
1538                         compatible = "rockchip,gpio-bank";
1539                         reg = <0x0 0xff750000 0x0 0x100>;
1540                         clocks = <&cru PCLK_GPIO0>;
1541                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1542
1543                         gpio-controller;
1544                         #gpio-cells = <0x2>;
1545
1546                         interrupt-controller;
1547                         #interrupt-cells = <0x2>;
1548                 };
1549
1550                 gpio1: gpio1@ff780000 {
1551                         compatible = "rockchip,gpio-bank";
1552                         reg = <0x0 0xff780000 0x0 0x100>;
1553                         clocks = <&cru PCLK_GPIO1>;
1554                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1555
1556                         gpio-controller;
1557                         #gpio-cells = <0x2>;
1558
1559                         interrupt-controller;
1560                         #interrupt-cells = <0x2>;
1561                 };
1562
1563                 gpio2: gpio2@ff790000 {
1564                         compatible = "rockchip,gpio-bank";
1565                         reg = <0x0 0xff790000 0x0 0x100>;
1566                         clocks = <&cru PCLK_GPIO2>;
1567                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1568
1569                         gpio-controller;
1570                         #gpio-cells = <0x2>;
1571
1572                         interrupt-controller;
1573                         #interrupt-cells = <0x2>;
1574                 };
1575
1576                 gpio3: gpio3@ff7a0000 {
1577                         compatible = "rockchip,gpio-bank";
1578                         reg = <0x0 0xff7a0000 0x0 0x100>;
1579                         clocks = <&cru PCLK_GPIO3>;
1580                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1581
1582                         gpio-controller;
1583                         #gpio-cells = <0x2>;
1584
1585                         interrupt-controller;
1586                         #interrupt-cells = <0x2>;
1587                 };
1588
1589                 pcfg_pull_up: pcfg-pull-up {
1590                         bias-pull-up;
1591                 };
1592
1593                 pcfg_pull_down: pcfg-pull-down {
1594                         bias-pull-down;
1595                 };
1596
1597                 pcfg_pull_none: pcfg-pull-none {
1598                         bias-disable;
1599                 };
1600
1601                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1602                         bias-disable;
1603                         drive-strength = <12>;
1604                 };
1605
1606                 edp {
1607                         edp_hpd: edp-hpd {
1608                                 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1609                         };
1610                 };
1611
1612                 emmc {
1613                         emmc_clk: emmc-clk {
1614                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1615                         };
1616
1617                         emmc_cmd: emmc-cmd {
1618                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1619                         };
1620
1621                         emmc_pwr: emmc-pwr {
1622                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1623                         };
1624
1625                         emmc_bus1: emmc-bus1 {
1626                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1627                         };
1628
1629                         emmc_bus4: emmc-bus4 {
1630                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1631                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1632                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1633                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1634                         };
1635
1636                         emmc_bus8: emmc-bus8 {
1637                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1638                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1639                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1640                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1641                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1642                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1643                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1644                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1645                         };
1646                 };
1647
1648                 gmac {
1649                         rgmii_pins: rgmii-pins {
1650                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1651                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1652                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1653                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1654                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1655                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1656                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1657                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1658                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1659                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1660                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1661                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1662                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1663                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1664                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1665                         };
1666
1667                         rmii_pins: rmii-pins {
1668                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1669                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1670                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1671                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1672                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1673                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1674                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1675                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1676                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1677                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1678                         };
1679                 };
1680
1681                 i2c0 {
1682                         i2c0_xfer: i2c0-xfer {
1683                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1684                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1685                         };
1686                 };
1687
1688                 i2c1 {
1689                         i2c1_xfer: i2c1-xfer {
1690                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1691                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1692                         };
1693                 };
1694
1695                 i2c2 {
1696                         i2c2_xfer: i2c2-xfer {
1697                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1698                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1699                         };
1700                 };
1701
1702                 i2c3 {
1703                         i2c3_xfer: i2c3-xfer {
1704                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1705                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707                 };
1708
1709                 i2c4 {
1710                         i2c4_xfer: i2c4-xfer {
1711                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1712                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1713                         };
1714                 };
1715
1716                 i2c5 {
1717                         i2c5_xfer: i2c5-xfer {
1718                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1719                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1720                         };
1721                 };
1722
1723                 i2s {
1724                         i2s_8ch_bus: i2s-8ch-bus {
1725                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1726                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1727                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1728                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1729                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1730                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1731                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1732                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1733                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 pwm0 {
1738                         pwm0_pin: pwm0-pin {
1739                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1740                         };
1741
1742                         vop_pwm_pin: vop-pwm {
1743                                 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1744                         };
1745                 };
1746
1747                 pwm1 {
1748                         pwm1_pin: pwm1-pin {
1749                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1750                         };
1751                 };
1752
1753                 pwm3 {
1754                         pwm3_pin: pwm3-pin {
1755                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1756                         };
1757                 };
1758
1759                 sdio0 {
1760                         sdio0_bus1: sdio0-bus1 {
1761                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1762                         };
1763
1764                         sdio0_bus4: sdio0-bus4 {
1765                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1766                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1767                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1768                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1769                         };
1770
1771                         sdio0_cmd: sdio0-cmd {
1772                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1773                         };
1774
1775                         sdio0_clk: sdio0-clk {
1776                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778
1779                         sdio0_cd: sdio0-cd {
1780                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1781                         };
1782
1783                         sdio0_wp: sdio0-wp {
1784                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1785                         };
1786
1787                         sdio0_pwr: sdio0-pwr {
1788                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1789                         };
1790
1791                         sdio0_bkpwr: sdio0-bkpwr {
1792                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1793                         };
1794
1795                         sdio0_int: sdio0-int {
1796                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1797                         };
1798                 };
1799
1800                 sdmmc {
1801                         sdmmc_clk: sdmmc-clk {
1802                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1803                         };
1804
1805                         sdmmc_cmd: sdmmc-cmd {
1806                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1807                         };
1808
1809                         sdmmc_cd: sdmmc-cd {
1810                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1811                         };
1812
1813                         sdmmc_bus1: sdmmc-bus1 {
1814                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1815                         };
1816
1817                         sdmmc_bus4: sdmmc-bus4 {
1818                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1819                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1820                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1821                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1822                         };
1823                 };
1824
1825                 spi0 {
1826                         spi0_clk: spi0-clk {
1827                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1828                         };
1829                         spi0_cs0: spi0-cs0 {
1830                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1831                         };
1832                         spi0_cs1: spi0-cs1 {
1833                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1834                         };
1835                         spi0_tx: spi0-tx {
1836                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1837                         };
1838                         spi0_rx: spi0-rx {
1839                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1840                         };
1841                 };
1842
1843                 spi1 {
1844                         spi1_clk: spi1-clk {
1845                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1846                         };
1847                         spi1_cs0: spi1-cs0 {
1848                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1849                         };
1850                         spi1_cs1: spi1-cs1 {
1851                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1852                         };
1853                         spi1_rx: spi1-rx {
1854                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1855                         };
1856                         spi1_tx: spi1-tx {
1857                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1858                         };
1859                 };
1860
1861                 spi2 {
1862                         spi2_clk: spi2-clk {
1863                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1864                         };
1865                         spi2_cs0: spi2-cs0 {
1866                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1867                         };
1868                         spi2_rx: spi2-rx {
1869                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1870                         };
1871                         spi2_tx: spi2-tx {
1872                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1873                         };
1874                 };
1875
1876                 uart0 {
1877                         uart0_xfer: uart0-xfer {
1878                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1879                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1880                         };
1881
1882                         uart0_cts: uart0-cts {
1883                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1884                         };
1885
1886                         uart0_rts: uart0-rts {
1887                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1888                         };
1889                 };
1890
1891                 uart1 {
1892                         uart1_xfer: uart1-xfer {
1893                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1894                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1895                         };
1896
1897                         uart1_cts: uart1-cts {
1898                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1899                         };
1900
1901                         uart1_rts: uart1-rts {
1902                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1903                         };
1904                 };
1905
1906                 uart2 {
1907                         uart2_xfer: uart2-xfer {
1908                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1909                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1910                         };
1911                         /* no rts / cts for uart2 */
1912                 };
1913
1914                 uart3 {
1915                         uart3_xfer: uart3-xfer {
1916                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1917                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1918                         };
1919
1920                         uart3_cts: uart3-cts {
1921                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1922                         };
1923
1924                         uart3_rts: uart3-rts {
1925                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1926                         };
1927                 };
1928
1929                 uart4 {
1930                         uart4_xfer: uart4-xfer {
1931                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1932                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1933                         };
1934
1935                         uart4_cts: uart4-cts {
1936                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1937                         };
1938
1939                         uart4_rts: uart4-rts {
1940                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1941                         };
1942                 };
1943
1944                 isp {
1945                         cif_clkout: cif-clkout {
1946                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1947                         };
1948
1949                         isp_dvp_d2d9: isp-dvp-d2d9 {
1950                                 rockchip,pins =
1951                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1952                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1953                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1954                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1955                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1956                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1957                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1958                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1959                                                 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1960                                                 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1961                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1962                                                 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1963                         };
1964
1965                         isp_dvp_d0d1: isp-dvp-d0d1 {
1966                                 rockchip,pins =
1967                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1968                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1969                         };
1970
1971                         isp_dvp_d10d11:isp_d10d11 {
1972                                 rockchip,pins =
1973                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1974                                                 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1975                         };
1976
1977                         isp_dvp_d0d7: isp-dvp-d0d7 {
1978                                 rockchip,pins =
1979                                                 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1980                                                 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1981                                                 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1982                                                 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1983                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1984                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1985                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1986                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1987                         };
1988
1989                         isp_dvp_d4d11: isp-dvp-d4d11 {
1990                                 rockchip,pins =
1991                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1992                                                 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1993                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1994                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1995                                                 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1996                                                 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1997                                                 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1998                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1999                         };
2000
2001                         isp_shutter: isp-shutter {
2002                                 rockchip,pins =
2003                                                 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2004                                                 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2005                         };
2006
2007                         isp_flash_trigger: isp-flash-trigger {
2008                                 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2009                         };
2010
2011                         isp_prelight: isp-prelight {
2012                                 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2013                         };
2014
2015                         isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2016                                 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2017                         };
2018                 };
2019         };
2020 };