2 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3368-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/power/rk3368-power.h>
49 #include <dt-bindings/soc/rockchip,boot-mode.h>
50 #include <dt-bindings/thermal/thermal.h>
51 #include <dt-bindings/display/mipi_dsi.h>
52 #include <dt-bindings/display/drm_mipi_dsi.h>
53 #include <dt-bindings/display/media-bus-format.h>
56 compatible = "rockchip,rk3368";
57 interrupt-parent = <&gic>;
80 #address-cells = <0x2>;
117 compatible = "arm,cortex-a53", "arm,armv8";
119 enable-method = "psci";
120 clocks = <&cru ARMCLKL>;
121 operating-points-v2 = <&cluster0_opp>;
122 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
123 #cooling-cells = <2>; /* min followed by max */
124 dynamic-power-coefficient = <149>;
129 compatible = "arm,cortex-a53", "arm,armv8";
131 enable-method = "psci";
132 clocks = <&cru ARMCLKL>;
133 operating-points-v2 = <&cluster0_opp>;
134 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
139 compatible = "arm,cortex-a53", "arm,armv8";
141 enable-method = "psci";
142 clocks = <&cru ARMCLKL>;
143 operating-points-v2 = <&cluster0_opp>;
144 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
149 compatible = "arm,cortex-a53", "arm,armv8";
151 enable-method = "psci";
152 clocks = <&cru ARMCLKL>;
153 operating-points-v2 = <&cluster0_opp>;
154 sched-energy-costs = <&RK3368_CPU_COST_0 &RK3368_CLUSTER_COST_0>;
159 compatible = "arm,cortex-a53", "arm,armv8";
161 enable-method = "psci";
162 clocks = <&cru ARMCLKB>;
163 operating-points-v2 = <&cluster1_opp>;
164 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
165 #cooling-cells = <2>; /* min followed by max */
166 dynamic-power-coefficient = <160>;
171 compatible = "arm,cortex-a53", "arm,armv8";
173 enable-method = "psci";
174 clocks = <&cru ARMCLKB>;
175 operating-points-v2 = <&cluster1_opp>;
176 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
181 compatible = "arm,cortex-a53", "arm,armv8";
183 enable-method = "psci";
184 clocks = <&cru ARMCLKB>;
185 operating-points-v2 = <&cluster1_opp>;
186 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
191 compatible = "arm,cortex-a53", "arm,armv8";
193 enable-method = "psci";
194 clocks = <&cru ARMCLKB>;
195 operating-points-v2 = <&cluster1_opp>;
196 sched-energy-costs = <&RK3368_CPU_COST_1 &RK3368_CLUSTER_COST_1>;
200 cluster0_opp: opp_table0 {
201 compatible = "operating-points-v2";
205 opp-hz = /bits/ 64 <216000000>;
206 opp-microvolt = <950000 950000 1350000>;
207 clock-latency-ns = <40000>;
211 opp-hz = /bits/ 64 <408000000>;
212 opp-microvolt = <950000 950000 1350000>;
213 clock-latency-ns = <40000>;
216 opp-hz = /bits/ 64 <600000000>;
217 opp-microvolt = <950000 950000 1350000>;
218 clock-latency-ns = <40000>;
221 opp-hz = /bits/ 64 <816000000>;
222 opp-microvolt = <1025000 1025000 1350000>;
223 clock-latency-ns = <40000>;
226 opp-hz = /bits/ 64 <1008000000>;
227 opp-microvolt = <1125000 1125000 1350000>;
228 clock-latency-ns = <40000>;
231 opp-hz = /bits/ 64 <1200000000>;
232 opp-microvolt = <1225000 1225000 1350000>;
233 clock-latency-ns = <40000>;
237 cluster1_opp: opp_table1 {
238 compatible = "operating-points-v2";
242 opp-hz = /bits/ 64 <216000000>;
243 opp-microvolt = <950000 950000 1350000>;
244 clock-latency-ns = <40000>;
248 opp-hz = /bits/ 64 <408000000>;
249 opp-microvolt = <950000 950000 1350000>;
250 clock-latency-ns = <40000>;
253 opp-hz = /bits/ 64 <600000000>;
254 opp-microvolt = <950000 950000 1350000>;
255 clock-latency-ns = <40000>;
258 opp-hz = /bits/ 64 <816000000>;
259 opp-microvolt = <975000 975000 1350000>;
260 clock-latency-ns = <40000>;
263 opp-hz = /bits/ 64 <1008000000>;
264 opp-microvolt = <1050000 1050000 1350000>;
265 clock-latency-ns = <40000>;
268 opp-hz = /bits/ 64 <1200000000>;
269 opp-microvolt = <1150000 1150000 1350000>;
270 clock-latency-ns = <40000>;
273 opp-hz = /bits/ 64 <1296000000>;
274 opp-microvolt = <1225000 1225000 1350000>;
275 clock-latency-ns = <40000>;
278 opp-hz = /bits/ 64 <1416000000>;
279 opp-microvolt = <1300000 1300000 1350000>;
280 clock-latency-ns = <40000>;
283 opp-hz = /bits/ 64 <1512000000>;
284 opp-microvolt = <1350000 1350000 1350000>;
285 clock-latency-ns = <40000>;
290 RK3368_CPU_COST_0: rk3368-core-cost0 {
306 RK3368_CPU_COST_1: rk3368-core-cost1 {
325 RK3368_CLUSTER_COST_0: rk3368-cluster-cost0 {
341 RK3368_CLUSTER_COST_1: rk3368-cluster-cost1 {
364 min-volt = <950000>; /* uV */
365 min-freq = <216000>; /* KHz */
366 leakage-adjust-volt = <
370 nvmem-cells = <&cpu_leakage>;
371 nvmem-cell-names = "cpu_leakage";
375 min-volt = <950000>; /* uV */
376 min-freq = <216000>; /* KHz */
377 leakage-adjust-volt = <
381 nvmem-cells = <&cpu_leakage>;
382 nvmem-cell-names = "cpu_leakage";
387 compatible = "arm,armv8-pmuv3";
388 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
393 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
395 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
396 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
397 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
398 <&cpu_b2>, <&cpu_b3>;
402 compatible = "arm,amba-bus";
403 #address-cells = <2>;
407 dmac_peri: dma-controller@ff250000 {
408 compatible = "arm,pl330", "arm,primecell";
409 reg = <0x0 0xff250000 0x0 0x4000>;
410 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru ACLK_DMAC_PERI>;
414 clock-names = "apb_pclk";
415 arm,pl330-broken-no-flushp;
416 peripherals-req-type-burst;
419 dmac_bus: dma-controller@ff600000 {
420 compatible = "arm,pl330", "arm,primecell";
421 reg = <0x0 0xff600000 0x0 0x4000>;
422 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&cru ACLK_DMAC_BUS>;
426 clock-names = "apb_pclk";
427 arm,pl330-broken-no-flushp;
428 peripherals-req-type-burst;
433 compatible = "arm,psci-0.2";
438 compatible = "arm,armv8-timer";
439 interrupts = <GIC_PPI 13
440 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
442 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
444 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
446 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
450 compatible = "fixed-clock";
451 clock-frequency = <24000000>;
452 clock-output-names = "xin24m";
456 sdmmc: dwmmc@ff0c0000 {
457 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
458 reg = <0x0 0xff0c0000 0x0 0x4000>;
459 clock-freq-min-max = <400000 150000000>;
460 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
461 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
462 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
463 fifo-depth = <0x100>;
464 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
468 sdio0: dwmmc@ff0d0000 {
469 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
470 reg = <0x0 0xff0d0000 0x0 0x4000>;
471 clock-freq-min-max = <400000 150000000>;
472 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
473 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
474 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
475 fifo-depth = <0x100>;
476 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
480 emmc: dwmmc@ff0f0000 {
481 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
482 reg = <0x0 0xff0f0000 0x0 0x4000>;
483 clock-freq-min-max = <400000 150000000>;
484 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
485 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
486 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
487 fifo-depth = <0x100>;
488 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
492 saradc: saradc@ff100000 {
493 compatible = "rockchip,saradc";
494 reg = <0x0 0xff100000 0x0 0x100>;
495 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
496 #io-channel-cells = <1>;
497 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
498 clock-names = "saradc", "apb_pclk";
499 resets = <&cru SRST_SARADC>;
500 reset-names = "saradc-apb";
505 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
506 reg = <0x0 0xff110000 0x0 0x1000>;
507 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
508 clock-names = "spiclk", "apb_pclk";
509 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
510 pinctrl-names = "default";
511 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
512 #address-cells = <1>;
518 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
519 reg = <0x0 0xff120000 0x0 0x1000>;
520 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
521 clock-names = "spiclk", "apb_pclk";
522 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
523 pinctrl-names = "default";
524 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
525 #address-cells = <1>;
531 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
532 reg = <0x0 0xff130000 0x0 0x1000>;
533 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
534 clock-names = "spiclk", "apb_pclk";
535 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
536 pinctrl-names = "default";
537 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
538 #address-cells = <1>;
544 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
545 reg = <0x0 0xff650000 0x0 0x1000>;
546 clocks = <&cru PCLK_I2C0>;
548 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
549 pinctrl-names = "default";
550 pinctrl-0 = <&i2c0_xfer>;
551 #address-cells = <1>;
557 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
558 reg = <0x0 0xff140000 0x0 0x1000>;
559 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
560 #address-cells = <1>;
563 clocks = <&cru PCLK_I2C2>;
564 pinctrl-names = "default";
565 pinctrl-0 = <&i2c2_xfer>;
570 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
571 reg = <0x0 0xff150000 0x0 0x1000>;
572 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
573 #address-cells = <1>;
576 clocks = <&cru PCLK_I2C3>;
577 pinctrl-names = "default";
578 pinctrl-0 = <&i2c3_xfer>;
583 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
584 reg = <0x0 0xff160000 0x0 0x1000>;
585 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
586 #address-cells = <1>;
589 clocks = <&cru PCLK_I2C4>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&i2c4_xfer>;
596 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
597 reg = <0x0 0xff170000 0x0 0x1000>;
598 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
599 #address-cells = <1>;
602 clocks = <&cru PCLK_I2C5>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&i2c5_xfer>;
608 uart0: serial@ff180000 {
609 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
610 reg = <0x0 0xff180000 0x0 0x100>;
611 clock-frequency = <24000000>;
612 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
613 clock-names = "baudclk", "apb_pclk";
614 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
620 uart1: serial@ff190000 {
621 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
622 reg = <0x0 0xff190000 0x0 0x100>;
623 clock-frequency = <24000000>;
624 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
625 clock-names = "baudclk", "apb_pclk";
626 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
632 uart3: serial@ff1b0000 {
633 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
634 reg = <0x0 0xff1b0000 0x0 0x100>;
635 clock-frequency = <24000000>;
636 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
637 clock-names = "baudclk", "apb_pclk";
638 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
644 uart4: serial@ff1c0000 {
645 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
646 reg = <0x0 0xff1c0000 0x0 0x100>;
647 clock-frequency = <24000000>;
648 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
649 clock-names = "baudclk", "apb_pclk";
650 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
656 thermal_zones: thermal-zones {
657 soc_thermal: soc-thermal {
658 polling-delay-passive = <200>; /* milliseconds */
659 polling-delay = <200>; /* milliseconds */
660 sustainable-power = <600>; /* milliwatts */
662 thermal-sensors = <&tsadc 0>;
664 threshold: trip-point@0 {
665 temperature = <70000>; /* millicelsius */
666 hysteresis = <2000>; /* millicelsius */
669 target: trip-point@1 {
670 temperature = <80000>; /* millicelsius */
671 hysteresis = <2000>; /* millicelsius */
675 temperature = <95000>; /* millicelsius */
676 hysteresis = <2000>; /* millicelsius */
685 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
686 contribution = <1024>;
691 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
692 contribution = <1024>;
697 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
698 contribution = <1024>;
703 gpu_thermal: gpu-thermal {
704 polling-delay-passive = <200>; /* milliseconds */
705 polling-delay = <200>; /* milliseconds */
706 thermal-sensors = <&tsadc 1>;
710 tsadc: tsadc@ff280000 {
711 compatible = "rockchip,rk3368-tsadc-legacy";
712 reg = <0x0 0xff280000 0x0 0x100>;
713 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
715 clock-names = "tsadc", "apb_pclk";
716 clock-frequency = <32768>;
717 resets = <&cru SRST_TSADC>;
718 reset-names = "tsadc-apb";
719 nvmem-cells = <&temp_adjust>;
720 nvmem-cell-names = "temp_adjust";
721 #thermal-sensor-cells = <1>;
722 hw-shut-temp = <95000>;
723 latency-bound = <50000>;
727 gmac: ethernet@ff290000 {
728 compatible = "rockchip,rk3368-gmac";
729 reg = <0x0 0xff290000 0x0 0x10000>;
730 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
731 interrupt-names = "macirq";
732 rockchip,grf = <&grf>;
733 clocks = <&cru SCLK_MAC>,
734 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
735 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
736 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
737 clock-names = "stmmaceth",
738 "mac_clk_rx", "mac_clk_tx",
739 "clk_mac_ref", "clk_mac_refout",
740 "aclk_mac", "pclk_mac";
744 nandc0: nandc@ff400000 {
745 compatible = "rockchip,rk-nandc";
746 reg = <0x0 0xff400000 0x0 0x4000>;
747 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
749 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
750 clock-names = "clk_nandc", "hclk_nandc";
754 usb_host0_ehci: usb@ff500000 {
755 compatible = "generic-ehci";
756 reg = <0x0 0xff500000 0x0 0x20000>;
757 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru HCLK_HOST0>, <&u2phy>;
759 clock-names = "usbhost", "utmi";
760 phys = <&u2phy_host>;
765 usb_host0_ohci: usb@ff520000 {
766 compatible = "generic-ohci";
767 reg = <0x0 0xff520000 0x0 0x20000>;
768 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&cru HCLK_HOST0>, <&u2phy>;
770 clock-names = "usbhost", "utmi";
771 phys = <&u2phy_host>;
776 usb_otg: usb@ff580000 {
777 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
779 reg = <0x0 0xff580000 0x0 0x40000>;
780 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&cru HCLK_OTG0>;
784 g-np-tx-fifo-size = <16>;
785 g-rx-fifo-size = <275>;
786 g-tx-fifo-size = <256 128 128 64 64 32>;
791 ddrpctl: syscon@ff610000 {
792 compatible = "rockchip,rk3368-ddrpctl", "syscon";
793 reg = <0x0 0xff610000 0x0 0x400>;
797 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
798 reg = <0x0 0xff660000 0x0 0x1000>;
799 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
800 #address-cells = <1>;
803 clocks = <&cru PCLK_I2C1>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&i2c1_xfer>;
810 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
811 reg = <0x0 0xff680000 0x0 0x10>;
813 pinctrl-names = "default";
814 pinctrl-0 = <&pwm0_pin>;
815 clocks = <&cru PCLK_PWM1>;
821 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
822 reg = <0x0 0xff680010 0x0 0x10>;
824 pinctrl-names = "default";
825 pinctrl-0 = <&pwm1_pin>;
826 clocks = <&cru PCLK_PWM1>;
832 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
833 reg = <0x0 0xff680020 0x0 0x10>;
835 clocks = <&cru PCLK_PWM1>;
841 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
842 reg = <0x0 0xff680030 0x0 0x10>;
844 pinctrl-names = "default";
845 pinctrl-0 = <&pwm3_pin>;
846 clocks = <&cru PCLK_PWM1>;
851 uart2: serial@ff690000 {
852 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
853 reg = <0x0 0xff690000 0x0 0x100>;
854 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
855 clock-names = "baudclk", "apb_pclk";
856 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
857 pinctrl-names = "default";
858 pinctrl-0 = <&uart2_xfer>;
864 mbox: mbox@ff6b0000 {
865 compatible = "rockchip,rk3368-mailbox";
866 reg = <0x0 0xff6b0000 0x0 0x1000>;
867 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
868 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
871 clocks = <&cru PCLK_MAILBOX>;
872 clock-names = "pclk_mailbox";
877 mailbox: mailbox@ff6b0000 {
878 compatible = "rockchip,rk3368-mbox-legacy";
879 reg = <0x0 0xff6b0000 0x0 0x1000>,
880 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
881 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&cru PCLK_MAILBOX>;
886 clock-names = "pclk_mailbox";
891 mailbox_scpi: mailbox-scpi {
892 compatible = "rockchip,rk3368-scpi-legacy";
893 mboxes = <&mailbox 0>, <&mailbox 1>, <&mailbox 2>;
898 qos_iep: qos@ffad0000 {
899 compatible = "syscon";
900 reg = <0x0 0xffad0000 0x0 0x20>;
903 qos_isp_r0: qos@ffad0080 {
904 compatible = "syscon";
905 reg = <0x0 0xffad0080 0x0 0x20>;
908 qos_isp_r1: qos@ffad0100 {
909 compatible = "syscon";
910 reg = <0x0 0xffad0100 0x0 0x20>;
913 qos_isp_w0: qos@ffad0180 {
914 compatible = "syscon";
915 reg = <0x0 0xffad0180 0x0 0x20>;
918 qos_isp_w1: qos@ffad0200 {
919 compatible = "syscon";
920 reg = <0x0 0xffad0200 0x0 0x20>;
923 qos_vip: qos@ffad0280 {
924 compatible = "syscon";
925 reg = <0x0 0xffad0280 0x0 0x20>;
928 qos_vop: qos@ffad0300 {
929 compatible = "syscon";
930 reg = <0x0 0xffad0300 0x0 0x20>;
933 qos_rga_r: qos@ffad0380 {
934 compatible = "syscon";
935 reg = <0x0 0xffad0380 0x0 0x20>;
938 qos_rga_w: qos@ffad0400 {
939 compatible = "syscon";
940 reg = <0x0 0xffad0400 0x0 0x20>;
943 qos_hevc_r: qos@ffae0000 {
944 compatible = "syscon";
945 reg = <0x0 0xffae0000 0x0 0x20>;
948 qos_vpu_r: qos@ffae0100 {
949 compatible = "syscon";
950 reg = <0x0 0xffae0100 0x0 0x20>;
953 qos_vpu_w: qos@ffae0180 {
954 compatible = "syscon";
955 reg = <0x0 0xffae0180 0x0 0x20>;
958 qos_gpu: qos@ffaf0000 {
959 compatible = "syscon";
960 reg = <0x0 0xffaf0000 0x0 0x20>;
963 pmu: power-management@ff730000 {
964 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
965 reg = <0x0 0xff730000 0x0 0x1000>;
967 power: power-controller {
968 compatible = "rockchip,rk3368-power-controller";
969 #power-domain-cells = <1>;
970 #address-cells = <1>;
974 * Note: Although SCLK_* are the working clocks
975 * of device without including on the NOC, needed for
978 * The clocks on the which NOC:
979 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
980 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
981 * ACLK_RGA is on ACLK_RGA_NIU.
982 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
984 * Which clock are device clocks:
986 * *_IEP IEP:Image Enhancement Processor
987 * *_ISP ISP:Image Signal Processing
988 * *_VIP VIP:Video Input Processor
989 * *_VOP* VOP:Visual Output Processor
997 reg = <RK3368_PD_VIO>;
998 clocks = <&cru ACLK_IEP>,
1003 <&cru ACLK_VOP_IEP>,
1010 <&cru HCLK_VIO_HDCPMMU>,
1011 <&cru PCLK_EDP_CTRL>,
1012 <&cru PCLK_HDMI_CTRL>,
1017 <&cru PCLK_DPHYTX0>,
1018 <&cru PCLK_MIPI_CSI>,
1019 <&cru PCLK_MIPI_DSI0>,
1020 <&cru SCLK_VOP0_PWM>,
1021 <&cru SCLK_EDP_24M>,
1026 <&cru SCLK_HDMI_CEC>,
1027 <&cru SCLK_HDMI_HDCP>;
1028 pm_qos = <&qos_iep>,
1039 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
1040 * (video endecoder & decoder) clocks that on the
1041 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
1044 reg = <RK3368_PD_VIDEO>;
1045 clocks = <&cru ACLK_VIDEO>,
1047 <&cru SCLK_HEVC_CABAC>,
1048 <&cru SCLK_HEVC_CORE>;
1049 pm_qos = <&qos_hevc_r>,
1054 * Note: ACLK_GPU is the GPU clock,
1055 * and on the ACLK_GPU_NIU (NOC).
1058 reg = <RK3368_PD_GPU_1>;
1059 clocks = <&cru ACLK_GPU_CFG>,
1060 <&cru ACLK_GPU_MEM>,
1061 <&cru SCLK_GPU_CORE>;
1062 pm_qos = <&qos_gpu>;
1067 pmugrf: syscon@ff738000 {
1068 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
1069 reg = <0x0 0xff738000 0x0 0x1000>;
1071 pmu_io_domains: io-domains {
1072 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
1073 status = "disabled";
1077 compatible = "syscon-reboot-mode";
1079 mode-normal = <BOOT_NORMAL>;
1080 mode-recovery = <BOOT_RECOVERY>;
1081 mode-bootloader = <BOOT_FASTBOOT>;
1082 mode-loader = <BOOT_BL_DOWNLOAD>;
1086 cru: clock-controller@ff760000 {
1087 compatible = "rockchip,rk3368-cru";
1088 reg = <0x0 0xff760000 0x0 0x1000>;
1089 rockchip,grf = <&grf>;
1093 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1094 <&cru ACLK_BUS>, <&cru ACLK_PERI>,
1095 <&cru HCLK_BUS>, <&cru HCLK_PERI>,
1096 <&cru PCLK_BUS>, <&cru PCLK_PERI>,
1097 <&cru ACLK_CCI_PRE>;
1098 assigned-clock-rates =
1099 <576000000>, <400000000>,
1100 <300000000>, <300000000>,
1101 <150000000>, <150000000>,
1102 <75000000>, <75000000>,
1106 grf: syscon@ff770000 {
1107 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
1108 reg = <0x0 0xff770000 0x0 0x1000>;
1109 #address-cells = <1>;
1113 compatible = "rockchip,rk3368-dp-phy";
1114 clocks = <&cru SCLK_EDP_24M>;
1115 clock-names = "24m";
1116 resets = <&cru SRST_EDP_24M>;
1117 reset-names = "edp_24m";
1119 status = "disabled";
1122 io_domains: io-domains {
1123 compatible = "rockchip,rk3368-io-voltage-domain";
1124 status = "disabled";
1127 u2phy: usb2-phy@700 {
1128 compatible = "rockchip,rk3368-usb2phy";
1130 clocks = <&cru SCLK_OTGPHY0>;
1131 clock-names = "phyclk";
1133 clock-output-names = "usbotg_out";
1134 assigned-clocks = <&cru SCLK_USBPHY480M>;
1135 assigned-clock-parents = <&u2phy>;
1136 status = "disabled";
1138 u2phy_host: host-port {
1140 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1141 interrupt-names = "linestate";
1142 status = "disabled";
1147 wdt: watchdog@ff800000 {
1148 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
1149 reg = <0x0 0xff800000 0x0 0x100>;
1150 clocks = <&cru PCLK_WDT>;
1151 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1152 status = "disabled";
1156 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
1157 reg = <0x0 0xff810000 0x0 0x20>;
1158 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
1161 i2s_2ch: i2s-2ch@ff890000 {
1162 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1163 reg = <0x0 0xff890000 0x0 0x1000>;
1164 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1165 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
1166 dma-names = "tx", "rx";
1167 clock-names = "i2s_clk", "i2s_hclk";
1168 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
1169 status = "disabled";
1172 i2s_8ch: i2s-8ch@ff898000 {
1173 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
1174 reg = <0x0 0xff898000 0x0 0x1000>;
1175 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1176 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1177 dma-names = "tx", "rx";
1178 clock-names = "i2s_clk", "i2s_hclk";
1179 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
1180 pinctrl-names = "default";
1181 pinctrl-0 = <&i2s_8ch_bus>;
1182 status = "disabled";
1186 compatible = "rockchip,iep";
1187 iommu_enabled = <1>;
1188 iommus = <&iep_mmu>;
1189 reg = <0x0 0xff900000 0x0 0x800>;
1190 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1191 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1192 clock-names = "aclk_iep", "hclk_iep";
1193 power-domains = <&power RK3368_PD_VIO>;
1196 status = "disabled";
1199 iep_mmu: iommu@ff900800 {
1200 compatible = "rockchip,iommu";
1201 reg = <0x0 0xff900800 0x0 0x100>;
1202 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1203 interrupt-names = "iep_mmu";
1204 power-domains = <&power RK3368_PD_VIO>;
1206 status = "disabled";
1210 compatible = "rockchip,rk3368-isp", "rockchip,isp";
1211 reg = <0x0 0xff910000 0x0 0x4000>;
1212 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1213 power-domains = <&power RK3368_PD_VIO>;
1215 <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1216 <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
1217 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
1218 <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
1220 "aclk_isp", "hclk_isp", "clk_isp",
1221 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1222 "clk_cif_pll", "hclk_mipiphy1",
1223 "pclk_dphyrx", "clk_vio0_noc";
1226 "default", "isp_dvp8bit2", "isp_dvp10bit",
1227 "isp_dvp12bit", "isp_dvp8bit0", "isp_dvp8bit4",
1228 "isp_mipi_fl", "isp_mipi_fl_prefl",
1229 "isp_flash_as_gpio", "isp_flash_as_trigger_out";
1230 pinctrl-0 = <&cif_clkout>;
1231 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1232 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1233 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1234 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1235 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
1236 pinctrl-6 = <&cif_clkout>;
1237 pinctrl-7 = <&cif_clkout &isp_prelight>;
1238 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
1239 pinctrl-9 = <&isp_flash_trigger>;
1240 rockchip,isp,mipiphy = <2>;
1241 rockchip,isp,cifphy = <1>;
1242 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1243 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1244 rockchip,grf = <&grf>;
1245 rockchip,cru = <&cru>;
1246 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
1247 rockchip,isp,iommu-enable = <1>;
1248 iommus = <&isp_mmu>;
1249 status = "disabled";
1252 isp_mmu: iommu@ff914000 {
1253 compatible = "rockchip,iommu";
1254 reg = <0x0 0xff914000 0x0 0x100>,
1255 <0x0 0xff915000 0x0 0x100>;
1256 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1257 interrupt-names = "isp_mmu";
1258 clocks = <&cru ACLK_RGA>, <&cru HCLK_ISP>;
1259 clock-names = "aclk", "hclk";
1260 rk_iommu,disable_reset_quirk;
1262 power-domains = <&power RK3368_PD_VIO>;
1263 status = "disabled";
1267 compatible = "rockchip,rk3368-vop";
1268 reg = <0x0 0xff930000 0x0 0x2fc>;
1269 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1270 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
1271 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1272 assigned-clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1273 assigned-clock-rates = <400000000>, <200000000>;
1274 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1275 reset-names = "axi", "ahb", "dclk";
1276 power-domains = <&power RK3368_PD_VIO>;
1277 iommus = <&vop_mmu>;
1278 status = "disabled";
1281 #address-cells = <1>;
1284 vop_out_mipi: endpoint@0 {
1286 remote-endpoint = <&mipi_in_vop>;
1289 vop_out_edp: endpoint@1 {
1291 remote-endpoint = <&edp_in_vop>;
1296 display_subsystem: display-subsystem {
1297 compatible = "rockchip,display-subsystem";
1299 status = "disabled";
1302 vop_mmu: iommu@ff930300 {
1303 compatible = "rockchip,iommu";
1304 reg = <0x0 0xff930300 0x0 0x100>;
1305 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1306 interrupt-names = "vop_mmu";
1307 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
1308 clock-names = "aclk", "hclk";
1309 power-domains = <&power RK3368_PD_VIO>;
1311 status = "disabled";
1314 mipi_dsi_host: mipi-dsi-host@ff960000 {
1315 compatible = "rockchip,rk3368-mipi-dsi";
1316 reg = <0x0 0xff960000 0x0 0x4000>;
1317 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1318 clocks = <&cru PCLK_MIPI_DSI0>;
1319 clock-names = "pclk";
1320 resets = <&cru SRST_MIPIDSI0>;
1321 reset-names = "apb";
1322 phys = <&mipi_dphy>;
1323 phy-names = "mipi_dphy";
1324 rockchip,grf = <&grf>;
1325 power-domains = <&power RK3368_PD_VIO>;
1326 #address-cells = <1>;
1328 status = "disabled";
1332 mipi_in_vop: endpoint {
1333 remote-endpoint = <&vop_out_mipi>;
1339 mipi_dphy: mipi-dphy@ff968000 {
1340 compatible = "rockchip,rk3368-mipi-dphy";
1341 reg = <0x0 0xff968000 0x0 0x4000>;
1343 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX0>;
1344 clock-names = "ref", "pclk";
1345 resets = <&cru SRST_MIPIDPHYTX>;
1346 reset-names = "apb";
1347 status = "disabled";
1351 compatible = "rockchip,rk3368-edp";
1352 reg = <0x0 0xff970000 0x0 0x8000>;
1353 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1355 clock-names = "dp", "pclk";
1356 resets = <&cru SRST_EDP>;
1358 power-domains = <&power RK3368_PD_VIO>;
1359 rockchip,grf = <&grf>;
1362 pinctrl-names = "default";
1363 pinctrl-0 = <&edp_hpd>;
1364 status = "disabled";
1367 #address-cells = <1>;
1373 edp_in_vop: endpoint {
1374 remote-endpoint = <&vop_out_edp>;
1380 hevc_mmu: iommu@ff9a0440 {
1381 compatible = "rockchip,iommu";
1382 reg = <0x0 0xff9a0440 0x0 0x40>,
1383 <0x0 0xff9a0480 0x0 0x40>;
1384 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1385 interrupt-names = "hevc_mmu";
1386 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1387 clock-names = "aclk", "hclk";
1388 power-domains = <&power RK3368_PD_VIDEO>;
1390 status = "disabled";
1393 vpu_mmu: iommu@ff9a0800 {
1394 compatible = "rockchip,iommu";
1395 reg = <0x0 0xff9a0800 0x0 0x100>;
1396 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1398 interrupt-names = "vepu_mmu", "vdpu_mmu";
1399 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1400 clock-names = "aclk", "hclk";
1401 power-domains = <&power RK3368_PD_VIDEO>;
1403 status = "disabled";
1407 compatible = "rockchip,vpu_sub";
1408 iommu_enabled = <1>;
1409 iommus = <&vpu_mmu>;
1410 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1412 interrupt-names = "irq_enc","irq_dec";
1414 name = "vpu_service";
1418 hevc: hevc_service {
1419 compatible = "rockchip,hevc_sub";
1420 iommu_enabled = <1>;
1421 iommus = <&hevc_mmu>;
1422 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1423 interrupt-names = "irq_dec";
1425 name = "hevc_service";
1429 vpu_combo: vpu_combo@ff9a0000 {
1430 compatible = "rockchip,vpu_combo";
1431 reg = <0x0 0xff9a0000 0x0 0x440>;
1432 rockchip,grf = <&grf>;
1434 rockchip,sub = <&vpu>, <&hevc>;
1435 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>,
1436 <&cru SCLK_HEVC_CORE>, <&cru SCLK_HEVC_CABAC>;
1437 clock-names = "aclk_vcodec", "hclk_vcodec",
1438 "clk_core", "clk_cabac";
1439 resets = <&cru SRST_VIDEO_AXI>, <&cru SRST_VIDEO_AHB>,
1441 reset-names = "video_a", "video_h", "video";
1443 mode_ctrl = <0x418>;
1445 power-domains = <&power RK3368_PD_VIDEO>;
1446 status = "disabled";
1449 gic: interrupt-controller@ffb71000 {
1450 compatible = "arm,gic-400";
1451 interrupt-controller;
1452 #interrupt-cells = <3>;
1453 #address-cells = <0>;
1455 reg = <0x0 0xffb71000 0x0 0x1000>,
1456 <0x0 0xffb72000 0x0 0x2000>,
1457 <0x0 0xffb74000 0x0 0x2000>,
1458 <0x0 0xffb76000 0x0 0x2000>;
1459 interrupts = <GIC_PPI 9
1460 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1463 gpu: rogue-g6110@ffa30000 {
1464 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1465 reg = <0x0 0xffa30000 0x0 0x10000>;
1467 <&cru SCLK_GPU_CORE>,
1468 <&cru ACLK_GPU_MEM>,
1469 <&cru ACLK_GPU_CFG>;
1474 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1475 interrupt-names = "rogue-g6110-irq";
1476 power-domains = <&power RK3368_PD_GPU_1>;
1477 operating-points-v2 = <&gpu_opp_table>;
1478 #cooling-cells = <2>; /* min followed by max */
1479 gpu_power_model: power_model {
1480 compatible = "arm,mali-simple-power-model";
1483 static-power = <300>;
1484 dynamic-power = <396>;
1485 ts = <32000 4700 (-80) 2>;
1486 thermal-zone = "gpu-thermal";
1490 gpu_opp_table: gpu_opp_table {
1491 compatible = "operating-points-v2";
1495 opp-hz = /bits/ 64 <200000000>;
1496 opp-microvolt = <1100000>;
1499 opp-hz = /bits/ 64 <288000000>;
1500 opp-microvolt = <1100000>;
1503 opp-hz = /bits/ 64 <400000000>;
1504 opp-microvolt = <1100000>;
1507 opp-hz = /bits/ 64 <576000000>;
1508 opp-microvolt = <1200000>;
1512 efuse: efuse@ffb00000 {
1513 compatible = "rockchip,rk3368-efuse";
1514 reg = <0x0 0xffb00000 0x0 0x20>;
1515 #address-cells = <1>;
1517 clocks = <&cru PCLK_EFUSE256>;
1518 clock-names = "pclk_efuse";
1521 cpu_leakage: cpu-leakage@17 {
1524 temp_adjust: temp-adjust@1f {
1530 compatible = "rockchip,rk3368-pinctrl";
1531 rockchip,grf = <&grf>;
1532 rockchip,pmu = <&pmugrf>;
1533 #address-cells = <0x2>;
1534 #size-cells = <0x2>;
1537 gpio0: gpio0@ff750000 {
1538 compatible = "rockchip,gpio-bank";
1539 reg = <0x0 0xff750000 0x0 0x100>;
1540 clocks = <&cru PCLK_GPIO0>;
1541 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
1544 #gpio-cells = <0x2>;
1546 interrupt-controller;
1547 #interrupt-cells = <0x2>;
1550 gpio1: gpio1@ff780000 {
1551 compatible = "rockchip,gpio-bank";
1552 reg = <0x0 0xff780000 0x0 0x100>;
1553 clocks = <&cru PCLK_GPIO1>;
1554 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1557 #gpio-cells = <0x2>;
1559 interrupt-controller;
1560 #interrupt-cells = <0x2>;
1563 gpio2: gpio2@ff790000 {
1564 compatible = "rockchip,gpio-bank";
1565 reg = <0x0 0xff790000 0x0 0x100>;
1566 clocks = <&cru PCLK_GPIO2>;
1567 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1570 #gpio-cells = <0x2>;
1572 interrupt-controller;
1573 #interrupt-cells = <0x2>;
1576 gpio3: gpio3@ff7a0000 {
1577 compatible = "rockchip,gpio-bank";
1578 reg = <0x0 0xff7a0000 0x0 0x100>;
1579 clocks = <&cru PCLK_GPIO3>;
1580 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1583 #gpio-cells = <0x2>;
1585 interrupt-controller;
1586 #interrupt-cells = <0x2>;
1589 pcfg_pull_up: pcfg-pull-up {
1593 pcfg_pull_down: pcfg-pull-down {
1597 pcfg_pull_none: pcfg-pull-none {
1601 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1603 drive-strength = <12>;
1608 rockchip,pins = <2 23 RK_FUNC_2 &pcfg_pull_none>;
1613 emmc_clk: emmc-clk {
1614 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1617 emmc_cmd: emmc-cmd {
1618 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1621 emmc_pwr: emmc-pwr {
1622 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1625 emmc_bus1: emmc-bus1 {
1626 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1629 emmc_bus4: emmc-bus4 {
1630 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1631 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1632 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1633 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1636 emmc_bus8: emmc-bus8 {
1637 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1638 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1639 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1640 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1641 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1642 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1643 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1644 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1649 rgmii_pins: rgmii-pins {
1650 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1651 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1652 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1653 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1654 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1655 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1656 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1657 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1658 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1659 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1660 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1661 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1662 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1663 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1664 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1667 rmii_pins: rmii-pins {
1668 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1669 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1670 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1671 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1672 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1673 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1674 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1675 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1676 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1677 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1682 i2c0_xfer: i2c0-xfer {
1683 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1684 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1689 i2c1_xfer: i2c1-xfer {
1690 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1691 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1696 i2c2_xfer: i2c2-xfer {
1697 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1698 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1703 i2c3_xfer: i2c3-xfer {
1704 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1705 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1710 i2c4_xfer: i2c4-xfer {
1711 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1712 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1717 i2c5_xfer: i2c5-xfer {
1718 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1719 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1724 i2s_8ch_bus: i2s-8ch-bus {
1725 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1726 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1727 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1728 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1729 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1730 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1731 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1732 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1733 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1738 pwm0_pin: pwm0-pin {
1739 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1742 vop_pwm_pin: vop-pwm {
1743 rockchip,pins = <3 8 RK_FUNC_3 &pcfg_pull_none>;
1748 pwm1_pin: pwm1-pin {
1749 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1754 pwm3_pin: pwm3-pin {
1755 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1760 sdio0_bus1: sdio0-bus1 {
1761 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1764 sdio0_bus4: sdio0-bus4 {
1765 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1766 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1767 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1768 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1771 sdio0_cmd: sdio0-cmd {
1772 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1775 sdio0_clk: sdio0-clk {
1776 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1779 sdio0_cd: sdio0-cd {
1780 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1783 sdio0_wp: sdio0-wp {
1784 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1787 sdio0_pwr: sdio0-pwr {
1788 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1791 sdio0_bkpwr: sdio0-bkpwr {
1792 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1795 sdio0_int: sdio0-int {
1796 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1801 sdmmc_clk: sdmmc-clk {
1802 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1805 sdmmc_cmd: sdmmc-cmd {
1806 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1809 sdmmc_cd: sdmmc-cd {
1810 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1813 sdmmc_bus1: sdmmc-bus1 {
1814 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1817 sdmmc_bus4: sdmmc-bus4 {
1818 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1819 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1820 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1821 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1826 spi0_clk: spi0-clk {
1827 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1829 spi0_cs0: spi0-cs0 {
1830 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1832 spi0_cs1: spi0-cs1 {
1833 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1836 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1839 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1844 spi1_clk: spi1-clk {
1845 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1847 spi1_cs0: spi1-cs0 {
1848 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1850 spi1_cs1: spi1-cs1 {
1851 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1854 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1857 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1862 spi2_clk: spi2-clk {
1863 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1865 spi2_cs0: spi2-cs0 {
1866 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1869 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1872 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1877 uart0_xfer: uart0-xfer {
1878 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1879 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1882 uart0_cts: uart0-cts {
1883 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1886 uart0_rts: uart0-rts {
1887 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1892 uart1_xfer: uart1-xfer {
1893 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1894 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1897 uart1_cts: uart1-cts {
1898 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1901 uart1_rts: uart1-rts {
1902 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1907 uart2_xfer: uart2-xfer {
1908 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1909 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1911 /* no rts / cts for uart2 */
1915 uart3_xfer: uart3-xfer {
1916 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1917 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1920 uart3_cts: uart3-cts {
1921 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1924 uart3_rts: uart3-rts {
1925 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1930 uart4_xfer: uart4-xfer {
1931 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1932 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1935 uart4_cts: uart4-cts {
1936 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1939 uart4_rts: uart4-rts {
1940 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1945 cif_clkout: cif-clkout {
1946 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1949 isp_dvp_d2d9: isp-dvp-d2d9 {
1951 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1952 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1953 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1954 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1955 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1956 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1957 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1958 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1959 <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1960 <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1961 <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1962 <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1965 isp_dvp_d0d1: isp-dvp-d0d1 {
1967 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1968 <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1971 isp_dvp_d10d11:isp_d10d11 {
1973 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1974 <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1977 isp_dvp_d0d7: isp-dvp-d0d7 {
1979 <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1980 <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1981 <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1982 <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1983 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1984 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1985 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1986 <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1989 isp_dvp_d4d11: isp-dvp-d4d11 {
1991 <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1992 <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1993 <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1994 <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1995 <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1996 <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1997 <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1998 <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
2001 isp_shutter: isp-shutter {
2003 <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
2004 <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
2007 isp_flash_trigger: isp-flash-trigger {
2008 rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
2011 isp_prelight: isp-prelight {
2012 rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
2015 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
2016 rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU