arch/arm64/boot/dts/rockchip/rk3368-android.dtsi

   1 /*
   2  * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 / {
  44         chosen {
  45                 bootargs = "earlycon=uart8250,mmio32,0xff690000 swiotlb=1 firmware_class.path=/system/vendor/firmware";
  46         };
  47
  48         fiq_debugger: fiq-debugger {
  49                 compatible = "rockchip,fiq-debugger";
  50                 rockchip,serial-id = <2>;
  51                 rockchip,signal-irq = <186>;
  52                 rockchip,wake-irq = <0>;
  53                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  54                 rockchip,baudrate = <115200>;  /* Only 115200 and 1500000 */
  55                 pinctrl-names = "default";
  56                 pinctrl-0 = <&uart2_xfer>;
  57         };
  58
  59         reserved-memory {
  60                 #address-cells = <2>;
  61                 #size-cells = <2>;
  62                 ranges;
  63
  64                 drm_logo: drm-logo@00000000 {
  65                         compatible = "rockchip,drm-logo";
  66                         reg = <0x0 0x0 0x0 0x0>;
  67                 };
  68
  69                 /* global autoconfigured region for contiguous allocations */
  70                 linux,cma {
  71                         compatible = "shared-dma-pool";
  72                         reusable;
  73                         size = <0x0 0x8000000>;
  74                         linux,cma-default;
  75                 };
  76
  77                 /* reg = <0x0 0x0 0x0 0x0> will be updated by uboot */
  78                 rockchip_logo: rockchip-logo@00000000 {
  79                         compatible = "rockchip,drm-logo";
  80                         reg = <0x0 0x0 0x0 0x0>;
  81                 };
  82         };
  83
  84         ion {
  85                 compatible = "rockchip,ion";
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88
  89                 cma-heap {
  90                         reg = <0x00000000 0x02000000>;
  91                 };
  92
  93                 system-heap {
  94                 };
  95         };
  96
  97         isp: isp@ff910000 {
  98                 compatible = "rockchip,rk3368-isp", "rockchip,isp";
  99                 reg = <0x0 0xff910000 0x0 0x10000>;
 100                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 101                 power-domains = <&power RK3368_PD_VIO>;
 102                 clocks =
 103                         <&cru ACLK_RGA>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
 104                         <&cru SCLK_ISP>, <&cru PCLK_ISP>, <&cru SCLK_VIP_OUT>,
 105                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>,
 106                         <&cru PCLK_DPHYRX>, <&cru ACLK_VIO0_NOC>;
 107                 clock-names =
 108                         "aclk_isp", "hclk_isp", "clk_isp",
 109                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
 110                         "clk_cif_pll", "hclk_mipiphy1",
 111                         "pclk_dphyrx", "clk_vio0_noc";
 112                 pinctrl-names =
 113                         "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit",
 114                         "isp_dvp8bit0", "isp_dvp8bit4", "isp_mipi_fl",
 115                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
 116                         "isp_flash_as_trigger_out";
 117                 pinctrl-0 = <&cif_clkout>;
 118                 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
 119                 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
 120                 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
 121                 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
 122                 pinctrl-5 = <&cif_clkout &isp_dvp_d4d11>;
 123                 pinctrl-6 = <&cif_clkout>;
 124                 pinctrl-7 = <&cif_clkout &isp_prelight>;
 125                 pinctrl-8 = <&isp_flash_trigger_as_gpio>;
 126                 pinctrl-9 = <&isp_flash_trigger>;
 127                 rockchip,isp,mipiphy = <2>;
 128                 rockchip,isp,cifphy = <1>;
 129                 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
 130                 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
 131                 rockchip,grf = <&grf>;
 132                 rockchip,cru = <&cru>;
 133                 rockchip,gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>;
 134                 rockchip,isp,iommu_enable = <1>;
 135                 status = "disabled";
 136         };
 137
 138         rga@ff920000 {
 139                 compatible = "rockchip,rga2";
 140                 dev_mode = <1>;
 141                 reg = <0x0 0xff920000 0x0 0x1000>;
 142                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 143                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 144                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 145                 status = "disabled";
 146         };
 147
 148         hdmi: hdmi@ff980000 {
 149                 compatible = "rockchip,rk3368-hdmi";
 150                 reg = <0x0 0xff980000 0x0 0x20000>;
 151                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 152                 clocks = <&cru PCLK_HDMI_CTRL>,
 153                          <&cru SCLK_HDMI_HDCP>,
 154                          <&cru SCLK_HDMI_CEC>;
 155                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 156                 power-domains = <&power RK3368_PD_VIO>;
 157                 resets = <&cru SRST_HDMI>;
 158                 reset-names = "hdmi";
 159                 pinctrl-names = "default", "gpio";
 160                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 161                 pinctrl-1 = <&i2c5_gpio>;
 162                 status = "okay";
 163         };
 164
 165         dwc_control_usb: dwc-control-usb {
 166                 compatible = "rockchip,rk3368-dwc-control-usb";
 167                 status = "okay";
 168
 169                 rockchip,grf = <&grf>;
 170                 grf-offset = <0x04bc>; /* GRF_SOC_STATUS for USB2.0 OTG */
 171                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 175                 interrupt-names = "otg_id", "otg_bvalid",
 176                                   "otg_linestate", "host0_linestate";
 177                 clocks = <&cru HCLK_USB_PERI>;
 178                 clock-names = "hclk_usb_peri";
 179
 180                 otg_drv_gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
 181                 rockchip,remote_wakeup;
 182                 rockchip,usb_irq_wakeup;
 183
 184                 usb_bc {
 185                         compatible = "inno,phy";
 186                         regbase = &dwc_control_usb;
 187                         rk_usb,bvalid     = <0x4bc 23 1>;
 188                         rk_usb,iddig      = <0x4bc 26 1>;
 189                         rk_usb,vdmsrcen   = <0x718 12 1>;
 190                         rk_usb,vdpsrcen   = <0x718 11 1>;
 191                         rk_usb,rdmpden    = <0x718 10 1>;
 192                         rk_usb,idpsrcen   = <0x718  9 1>;
 193                         rk_usb,idmsinken  = <0x718  8 1>;
 194                         rk_usb,idpsinken  = <0x718  7 1>;
 195                         rk_usb,dpattach   = <0x4b8 31 1>;
 196                         rk_usb,cpdet      = <0x4b8 30 1>;
 197                         rk_usb,dcpattach  = <0x4b8 29 1>;
 198                 };
 199         };
 200 };
 201
 202 &display_subsystem {
 203         status = "okay";
 204
 205         memory-region = <&drm_logo>;
 206         route {
 207                 route_mipi: route-mipi {
 208                         status = "okay";
 209                         logo,uboot = "logo.bmp";
 210                         logo,kernel = "logo_kernel.bmp";
 211                         logo,mode = "center";
 212                         charge_logo,mode = "center";
 213                         connect = <&vop_out_mipi>;
 214                 };
 215         };
 216 };
 217
 218 &vop {
 219         status = "okay";
 220 };
 221
 222 &vop_mmu {
 223         status = "okay";
 224 };
 225
 226 &usb_otg {
 227         status = "okay";
 228         clocks = <&cru SCLK_OTGPHY0>, <&cru HCLK_OTG0>;
 229         clock-names = "sclk_otgphy0", "otg";
 230         resets = <&cru SRST_USBOTG_AHB>,
 231                  <&cru SRST_USBOTG_PHY>,
 232                  <&cru SRST_USBOTG_CON>;
 233         reset-names = "otg_ahb", "otg_phy", "otg_controller";
 234         /* 0 - Normal, 1 - Force Host, 2 - Force Device */
 235         rockchip,usb-mode = <0>;
 236 };
 237
 238 &pinctrl {
 239         hdmi_i2c {
 240                 hdmii2c_xfer: hdmii2c-xfer {
 241                         rockchip,pins = <3 26 RK_FUNC_1 &pcfg_pull_none>,
 242                                         <3 27 RK_FUNC_1 &pcfg_pull_none>;
 243                 };
 244         };
 245
 246         hdmi_pin {
 247                 hdmi_cec: hdmi-cec {
 248                         rockchip,pins = <3 23 RK_FUNC_1 &pcfg_pull_none>;
 249                 };
 250         };
 251
 252         i2c5 {
 253                 i2c5_gpio: i2c5-gpio {
 254                         rockchip,pins = <3 26 RK_FUNC_GPIO &pcfg_pull_none>,
 255                                         <3 27 RK_FUNC_GPIO &pcfg_pull_none>;
 256                 };
 257         };
 258
 259         isp {
 260                 cif_clkout: cif-clkout {
 261                         rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 262                 };
 263
 264                 isp_dvp_d2d9: isp-dvp-d2d9 {
 265                         rockchip,pins =
 266                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 267                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 268                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 269                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 270                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 271                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 272                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 273                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 274                                         <1 8 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
 275                                         <1 9 RK_FUNC_1 &pcfg_pull_none>,//cif_href
 276                                         <1 10 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
 277                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
 278                 };
 279
 280                 isp_dvp_d0d1: isp-dvp-d0d1 {
 281                         rockchip,pins =
 282                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 283                                         <1 13 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
 284                 };
 285
 286                 isp_dvp_d10d11:isp_d10d11 {
 287                         rockchip,pins =
 288                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 289                                         <1 15 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 290                 };
 291
 292                 isp_dvp_d0d7: isp-dvp-d0d7 {
 293                         rockchip,pins =
 294                                         <1 12 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
 295                                         <1 13 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
 296                                         <1 0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
 297                                         <1 1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
 298                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 299                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 300                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 301                                         <1 5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
 302                 };
 303
 304                 isp_dvp_d4d11: isp-dvp-d4d11 {
 305                         rockchip,pins =
 306                                         <1 2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
 307                                         <1 3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
 308                                         <1 4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
 309                                         <1 5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
 310                                         <1 6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
 311                                         <1 7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
 312                                         <1 14 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
 313                                         <1 17 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
 314                 };
 315
 316                 isp_shutter: isp-shutter {
 317                         rockchip,pins =
 318                                         <3 19 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
 319                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
 320                 };
 321
 322                 isp_flash_trigger: isp-flash-trigger {
 323                         rockchip,pins = <3 20 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
 324                 };
 325
 326                 isp_prelight: isp-prelight {
 327                         rockchip,pins = <3 21 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
 328                 };
 329
 330                 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
 331                         rockchip,pins = <3 20 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
 332                 };
 333         };
 334 };