arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48
  49 / {
  50         compatible = "rockchip,rk3366";
  51         interrupt-parent = <&gic>;
  52         #address-cells = <2>;
  53         #size-cells = <2>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 serial0 = &uart0;
  63                 serial2 = &uart2;
  64                 serial3 = &uart3;
  65                 spi0 = &spi0;
  66                 spi1 = &spi1;
  67         };
  68
  69         cpus {
  70                 #address-cells = <0x2>;
  71                 #size-cells = <0x0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53","arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                 };
  79
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53","arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86
  87                 cpu2: cpu@2 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a53","arm,armv8";
  90                         reg = <0x0 0x2>;
  91                         enable-method = "psci";
  92                 };
  93
  94                 cpu3: cpu@3 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a53","arm,armv8";
  97                         reg = <0x0 0x3>;
  98                         enable-method = "psci";
  99                 };
 100         };
 101
 102         psci {
 103                 compatible = "arm,psci-1.0";
 104                 method = "smc";
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv8-timer";
 109                 interrupts = <
 110                                 GIC_PPI 13
 111                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 112                                 <GIC_PPI 14
 113                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                                 <GIC_PPI 11
 115                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 116                                 <GIC_PPI 10
 117                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 118                 clock-frequency = <24000000>;
 119         };
 120
 121         xin24m: xin24m {
 122                 compatible = "fixed-clock";
 123                 #clock-cells = <0>;
 124                 clock-frequency = <24000000>;
 125                 clock-output-names = "xin24m";
 126         };
 127
 128         gic: interrupt-controller@ffb71000 {
 129                 compatible = "arm,gic-400";
 130                 interrupt-controller;
 131                 #interrupt-cells = <3>;
 132                 #address-cells = <0>;
 133
 134                 reg = <0x0 0xffb71000 0x0 0x1000>,
 135                       <0x0 0xffb72000 0x0 0x1000>,
 136                       <0x0 0xffb74000 0x0 0x2000>,
 137                       <0x0 0xffb76000 0x0 0x2000>;
 138                 interrupts = <GIC_PPI 9
 139                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 140         };
 141
 142         nandc0: nandc@ff0c0000 {
 143                 compatible = "rockchip,rk-nandc";
 144                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 145                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 146                 nandc_id = <0>;
 147                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 148                 clock-names = "clk_nandc", "hclk_nandc";
 149                 status = "disabled";
 150         };
 151
 152         saradc: saradc@ff100000 {
 153                 compatible = "rockchip,saradc";
 154                 reg = <0x0 0xff100000 0x0 0x100>;
 155                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 156                 #io-channel-cells = <1>;
 157                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 158                 clock-names = "saradc", "apb_pclk";
 159                 status = "disabled";
 160         };
 161
 162         spi0: spi@ff110000 {
 163                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 164                 reg = <0x0 0xff110000 0x0 0x1000>;
 165                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 166                 clock-names = "spiclk", "apb_pclk";
 167                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 168                 pinctrl-names = "default";
 169                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 170                 #address-cells = <1>;
 171                 #size-cells = <0>;
 172                 status = "disabled";
 173         };
 174
 175         spi1: spi@ff120000 {
 176                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 177                 reg = <0x0 0xff120000 0x0 0x1000>;
 178                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 179                 clock-names = "spiclk", "apb_pclk";
 180                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 181                 pinctrl-names = "default";
 182                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 183                 #address-cells = <1>;
 184                 #size-cells = <0>;
 185                 status = "disabled";
 186         };
 187
 188         i2c0: i2c@ff650000 {
 189                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 190                 reg = <0x0 0xff728000 0x0 0x1000>;
 191                 clocks = <&cru PCLK_I2C0>;
 192                 clock-names = "i2c";
 193                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 194                 pinctrl-names = "default";
 195                 pinctrl-0 = <&i2c0_xfer>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 status = "disabled";
 199         };
 200
 201         i2c2: i2c@ff140000 {
 202                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 203                 reg = <0x0 0xff140000 0x0 0x1000>;
 204                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 205                 #address-cells = <1>;
 206                 #size-cells = <0>;
 207                 clock-names = "i2c";
 208                 clocks = <&cru PCLK_I2C2>;
 209                 pinctrl-names = "default";
 210                 pinctrl-0 = <&i2c2_xfer>;
 211                 status = "disabled";
 212         };
 213
 214         i2c3: i2c@ff150000 {
 215                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 216                 reg = <0x0 0xff150000 0x0 0x1000>;
 217                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 218                 #address-cells = <1>;
 219                 #size-cells = <0>;
 220                 clock-names = "i2c";
 221                 clocks = <&cru PCLK_I2C3>;
 222                 pinctrl-names = "default";
 223                 pinctrl-0 = <&i2c3_xfer>;
 224                 status = "disabled";
 225         };
 226
 227         i2c4: i2c@ff160000 {
 228                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 229                 reg = <0x0 0xff160000 0x0 0x1000>;
 230                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 231                 #address-cells = <1>;
 232                 #size-cells = <0>;
 233                 clock-names = "i2c";
 234                 clocks = <&cru PCLK_I2C4>;
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&i2c4_xfer>;
 237                 status = "disabled";
 238         };
 239
 240         i2c5: i2c@ff170000 {
 241                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 242                 reg = <0x0 0xff170000 0x0 0x1000>;
 243                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 244                 #address-cells = <1>;
 245                 #size-cells = <0>;
 246                 clock-names = "i2c";
 247                 clocks = <&cru PCLK_I2C5>;
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&i2c5_xfer>;
 250                 status = "disabled";
 251         };
 252
 253         uart0: serial@ff180000 {
 254                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 255                 reg = <0x0 0xff180000 0x0 0x100>;
 256                 clock-frequency = <24000000>;
 257                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 258                 clock-names = "baudclk", "apb_pclk";
 259                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 260                 reg-shift = <2>;
 261                 reg-io-width = <4>;
 262                 pinctrl-names = "default";
 263                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 264                 status = "disabled";
 265         };
 266
 267         uart3: serial@ff1b0000 {
 268                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 269                 reg = <0x0 0xff1b0000 0x0 0x100>;
 270                 clock-frequency = <24000000>;
 271                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 272                 clock-names = "baudclk", "apb_pclk";
 273                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg-shift = <2>;
 275                 reg-io-width = <4>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 278                 status = "disabled";
 279         };
 280
 281         i2c1: i2c@ff660000 {
 282                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 283                 reg = <0x0 0xff660000 0x0 0x1000>;
 284                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 clock-names = "i2c";
 288                 clocks = <&cru PCLK_I2C1>;
 289                 pinctrl-names = "default";
 290                 pinctrl-0 = <&i2c1_xfer>;
 291                 status = "disabled";
 292         };
 293
 294         pwm0: pwm@ff680000 {
 295                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 296                 reg = <0x0 0xff680000 0x0 0x10>;
 297                 #pwm-cells = <3>;
 298                 pinctrl-names = "default";
 299                 pinctrl-0 = <&pwm0_pin>;
 300                 clocks = <&cru PCLK_RKPWM>;
 301                 clock-names = "pwm";
 302                 status = "disabled";
 303         };
 304
 305         pwm1: pwm@ff680010 {
 306                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 307                 reg = <0x0 0xff680010 0x0 0x10>;
 308                 #pwm-cells = <3>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&pwm1_pin>;
 311                 clocks = <&cru PCLK_RKPWM>;
 312                 clock-names = "pwm";
 313                 status = "disabled";
 314         };
 315
 316         pwm2: pwm@ff680020 {
 317                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 318                 reg = <0x0 0xff680020 0x0 0x10>;
 319                 #pwm-cells = <3>;
 320                 clocks = <&cru PCLK_RKPWM>;
 321                 clock-names = "pwm";
 322                 status = "disabled";
 323         };
 324
 325         pwm3: pwm@ff680030 {
 326                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 327                 reg = <0x0 0xff680030 0x0 0x10>;
 328                 #pwm-cells = <3>;
 329                 pinctrl-names = "default";
 330                 pinctrl-0 = <&pwm3_t2_pin>;
 331                 clocks = <&cru PCLK_RKPWM>;
 332                 clock-names = "pwm";
 333                 status = "disabled";
 334         };
 335
 336         uart2: serial@ff690000 {
 337                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 338                 reg = <0x0 0xff690000 0x0 0x100>;
 339                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 341                 clock-names = "baudclk", "apb_pclk";
 342                 reg-shift = <2>;
 343                 reg-io-width = <4>;
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&uart2_t1_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         pmugrf: syscon@ff738000 {
 350                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 351                 reg = <0x0 0xff738000 0x0 0x1000>;
 352         };
 353
 354         amba {
 355                 compatible = "arm,amba-bus";
 356                 #address-cells = <2>;
 357                 #size-cells = <2>;
 358                 ranges;
 359
 360                 dmac_peri: dma-controller@ff250000 {
 361                         compatible = "arm,pl330", "arm,primecell";
 362                         reg = <0x0 0xff250000 0x0 0x4000>;
 363                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 364                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 365                         #dma-cells = <1>;
 366                         clocks = <&cru ACLK_DMAC_PERI>;
 367                         clock-names = "apb_pclk";
 368                 };
 369
 370                 dmac_bus: dma-controller@ff600000 {
 371                         compatible = "arm,pl330", "arm,primecell";
 372                         reg = <0x0 0xff600000 0x0 0x4000>;
 373                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 374                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 375                         #dma-cells = <1>;
 376                         clocks = <&cru ACLK_DMAC_BUS>;
 377                         clock-names = "apb_pclk";
 378                 };
 379         };
 380
 381         cru: clock-controller@ff760000 {
 382                 compatible = "rockchip,rk3366-cru";
 383                 reg = <0x0 0xff760000 0x0 0x1000>;
 384                 rockchip,grf = <&grf>;
 385                 #clock-cells = <1>;
 386                 #reset-cells = <1>;
 387         };
 388
 389         grf: syscon@ff770000 {
 390                 compatible = "rockchip,rk3366-grf", "syscon";
 391                 reg = <0x0 0xff770000 0x0 0x1000>;
 392         };
 393
 394         dsihost0: mipi@ff960000 {
 395                 compatible = "rockchip,rk3368-dsi";
 396                 rockchip,prop = <0>;
 397                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 398                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 399                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 400                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 401                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 402                 status = "disabled";
 403         };
 404
 405         pinctrl: pinctrl {
 406                 compatible = "rockchip,rk3366-pinctrl";
 407                 rockchip,grf = <&grf>;
 408                 rockchip,pmu = <&pmugrf>;
 409                 #address-cells = <0x2>;
 410                 #size-cells = <0x2>;
 411                 ranges;
 412
 413                 gpio0: gpio0@ff750000 {
 414                         compatible = "rockchip,gpio-bank";
 415                         reg = <0x0 0xff750000 0x0 0x100>;
 416                         clocks = <&cru PCLK_GPIO0>;
 417                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 418
 419                         gpio-controller;
 420                         #gpio-cells = <0x2>;
 421
 422                         interrupt-controller;
 423                         #interrupt-cells = <0x2>;
 424                 };
 425
 426                 gpio1: gpio1@ff780000 {
 427                         compatible = "rockchip,gpio-bank";
 428                         reg = <0x0 0xff758000 0x0 0x100>;
 429                         clocks = <&cru PCLK_GPIO1>;
 430                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 431
 432                         gpio-controller;
 433                         #gpio-cells = <0x2>;
 434
 435                         interrupt-controller;
 436                         #interrupt-cells = <0x2>;
 437                 };
 438
 439                 gpio2: gpio2@ff790000 {
 440                         compatible = "rockchip,gpio-bank";
 441                         reg = <0x0 0xff790000 0x0 0x100>;
 442                         clocks = <&cru PCLK_GPIO2>;
 443                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 444
 445                         gpio-controller;
 446                         #gpio-cells = <0x2>;
 447
 448                         interrupt-controller;
 449                         #interrupt-cells = <0x2>;
 450                 };
 451
 452                 gpio3: gpio3@ff7a0000 {
 453                         compatible = "rockchip,gpio-bank";
 454                         reg = <0x0 0xff7a0000 0x0 0x100>;
 455                         clocks = <&cru PCLK_GPIO3>;
 456                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 457
 458                         gpio-controller;
 459                         #gpio-cells = <0x2>;
 460
 461                         interrupt-controller;
 462                         #interrupt-cells = <0x2>;
 463                 };
 464
 465                 gpio4: gpio4@ff7b0000 {
 466                         compatible = "rockchip,gpio-bank";
 467                         reg = <0x0 0xff7b0000 0x0 0x100>;
 468                         clocks = <&cru PCLK_GPIO4>;
 469                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 470
 471                         gpio-controller;
 472                         #gpio-cells = <0x2>;
 473
 474                         interrupt-controller;
 475                         #interrupt-cells = <0x2>;
 476                 };
 477
 478                 gpio5: gpio5@ff7c0000 {
 479                         compatible = "rockchip,gpio-bank";
 480                         reg = <0x0 0xff7c0000 0x0 0x100>;
 481                         clocks = <&cru PCLK_GPIO5>;
 482                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 483
 484                         gpio-controller;
 485                         #gpio-cells = <0x2>;
 486
 487                         interrupt-controller;
 488                         #interrupt-cells = <0x2>;
 489                 };
 490
 491                 pcfg_pull_up: pcfg-pull-up {
 492                         bias-pull-up;
 493                 };
 494
 495                 pcfg_pull_down: pcfg-pull-down {
 496                         bias-pull-down;
 497                 };
 498
 499                 pcfg_pull_none: pcfg-pull-none {
 500                         bias-disable;
 501                 };
 502
 503                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 504                         bias-disable;
 505                         drive-strength = <12>;
 506                 };
 507
 508                 emmc {
 509                         emmc_clk: emmc-clk {
 510                                 rockchip,pins =
 511                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 512                         };
 513
 514                         emmc_cmd: emmc-cmd {
 515                                 rockchip,pins =
 516                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 517                         };
 518
 519                         emmc_pwr: emmc-pwr {
 520                                 rockchip,pins =
 521                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 522                         };
 523
 524                         emmc_bus1: emmc-bus1 {
 525                                 rockchip,pins =
 526                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 527                         };
 528
 529                         emmc_bus4: emmc-bus4 {
 530                                 rockchip,pins =
 531                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 532                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 533                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 534                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 535                         };
 536
 537                         emmc_bus8: emmc-bus8 {
 538                                 rockchip,pins =
 539                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 540                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 541                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 542                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 543                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 544                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 545                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 546                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 547                         };
 548                 };
 549
 550                 i2c0 {
 551                         i2c0_xfer: i2c0-xfer {
 552                                 rockchip,pins =
 553                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 554                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 555                         };
 556                 };
 557
 558                 i2c1 {
 559                         i2c1_xfer: i2c1-xfer {
 560                                 rockchip,pins =
 561                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 562                                         <4 20 RK_FUNC_1 &pcfg_pull_none>;
 563                         };
 564                 };
 565
 566                 i2c2 {
 567                         i2c2_xfer: i2c2-xfer {
 568                                 rockchip,pins =
 569                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 570                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 571                         };
 572                 };
 573
 574                 i2c3 {
 575                         i2c3_xfer: i2c3-xfer {
 576                                 rockchip,pins =
 577                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 578                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 579                         };
 580                 };
 581
 582                 i2c4 {
 583                         i2c4_xfer: i2c4-xfer {
 584                                 rockchip,pins =
 585                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 586                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 587                         };
 588                 };
 589
 590                 i2c5 {
 591                         i2c5_xfer: i2c5-xfer {
 592                                 rockchip,pins =
 593                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 594                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 595                         };
 596                 };
 597
 598                 i2s {
 599                         i2s_8ch_bus: i2s-8ch-bus {
 600                                 rockchip,pins =
 601                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 602                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 603                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 604                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 605                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 606                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
 607                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
 608                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
 609                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
 610                         };
 611                 };
 612
 613                 spi0 {
 614                         spi0_clk: spi0-clk {
 615                                 rockchip,pins =
 616                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
 617                         };
 618                         spi0_cs0: spi0-cs0 {
 619                                 rockchip,pins =
 620                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
 621                         };
 622                         spi0_cs1: spi0-cs1 {
 623                                 rockchip,pins =
 624                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
 625                         };
 626                         spi0_tx: spi0-tx {
 627                                 rockchip,pins =
 628                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
 629                         };
 630                         spi0_rx: spi0-rx {
 631                                 rockchip,pins =
 632                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
 633                         };
 634                 };
 635
 636                 spi1 {
 637                         spi1_clk: spi1-clk {
 638                                 rockchip,pins =
 639                                         <2 4 RK_FUNC_2 &pcfg_pull_up>;
 640                         };
 641                         spi1_cs0: spi1-cs0 {
 642                                 rockchip,pins =
 643                                         <2 5 RK_FUNC_2 &pcfg_pull_up>;
 644                         };
 645                         spi1_rx: spi1-rx {
 646                                 rockchip,pins =
 647                                         <2 6 RK_FUNC_2 &pcfg_pull_up>;
 648                         };
 649                         spi1_tx: spi1-tx {
 650                                 rockchip,pins =
 651                                         <2 7 RK_FUNC_2 &pcfg_pull_up>;
 652                         };
 653                 };
 654
 655                 uart0 {
 656                         uart0_xfer: uart0-xfer {
 657                                 rockchip,pins =
 658                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
 659                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
 660                         };
 661
 662                         uart0_cts: uart0-cts {
 663                                 rockchip,pins =
 664                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
 665                         };
 666
 667                         uart0_rts: uart0-rts {
 668                                 rockchip,pins =
 669                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
 670                         };
 671                 };
 672
 673                 uart2_t0 {
 674                         uart2_t0_xfer: uart2_t0-xfer {
 675                                 rockchip,pins =
 676                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
 677                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
 678                         };
 679                         /* no rts / cts for uart2 */
 680                 };
 681
 682                 uart2_t1 {
 683                         uart2_t1_xfer: uart2_t1-xfer {
 684                                 rockchip,pins =
 685                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
 686                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
 687                         };
 688                         /* no rts / cts for uart2 */
 689                 };
 690
 691                 uart2_t2 {
 692                         uart2_t2_xfer: uart2_t2-xfer {
 693                                 rockchip,pins =
 694                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
 695                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
 696                         };
 697                         /* no rts / cts for uart2 */
 698                 };
 699
 700                 uart3 {
 701                         uart3_xfer: uart3-xfer {
 702                                 rockchip,pins =
 703                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
 704                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
 705                         };
 706
 707                         uart3_cts: uart3-cts {
 708                                 rockchip,pins =
 709                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
 710                         };
 711
 712                         uart3_rts: uart3-rts {
 713                                 rockchip,pins =
 714                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
 715                         };
 716                 };
 717
 718                 pwm0 {
 719                         pwm0_pin: pwm0-pin {
 720                                 rockchip,pins =
 721                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
 722                         };
 723                 };
 724
 725                 pwm1 {
 726                         pwm1_pin: pwm1-pin {
 727                                 rockchip,pins =
 728                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
 729                         };
 730                 };
 731
 732                 pwm2_t0 {
 733                         pwm2_t0_pin: pwm2_t0-pin {
 734                                 rockchip,pins =
 735                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
 736                         };
 737                 };
 738
 739                 pwm2_t1 {
 740                         pwm2_t1_pin: pwm2_t1-pin {
 741                                 rockchip,pins =
 742                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
 743                         };
 744                 };
 745
 746                 pwm3_t0 {
 747                         pwm3_t0_pin: pwm3_t0-pin {
 748                                 rockchip,pins =
 749                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
 750                         };
 751                 };
 752
 753                 pwm3_t1 {
 754                         pwm3_t1_pin: pwm3_t1-pin {
 755                                 rockchip,pins =
 756                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
 757                         };
 758                 };
 759
 760                 pwm3_t2 {
 761                         pwm3_t2_pin: pwm3_t2-pin {
 762                                 rockchip,pins =
 763                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
 764                         };
 765                 };
 766         };
 767 };