arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3366";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 i2c0 = &i2c0;
  59                 i2c1 = &i2c1;
  60                 i2c2 = &i2c2;
  61                 i2c3 = &i2c3;
  62                 i2c4 = &i2c4;
  63                 i2c5 = &i2c5;
  64                 serial0 = &uart0;
  65                 serial2 = &uart2;
  66                 serial3 = &uart3;
  67                 spi0 = &spi0;
  68                 spi1 = &spi1;
  69         };
  70
  71         cpus {
  72                 #address-cells = <0x2>;
  73                 #size-cells = <0x0>;
  74
  75                 cpu0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,cortex-a53","arm,armv8";
  78                         reg = <0x0 0x0>;
  79                         enable-method = "psci";
  80                 };
  81
  82                 cpu1: cpu@1 {
  83                         device_type = "cpu";
  84                         compatible = "arm,cortex-a53","arm,armv8";
  85                         reg = <0x0 0x1>;
  86                         enable-method = "psci";
  87                 };
  88
  89                 cpu2: cpu@2 {
  90                         device_type = "cpu";
  91                         compatible = "arm,cortex-a53","arm,armv8";
  92                         reg = <0x0 0x2>;
  93                         enable-method = "psci";
  94                 };
  95
  96                 cpu3: cpu@3 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53","arm,armv8";
  99                         reg = <0x0 0x3>;
 100                         enable-method = "psci";
 101                 };
 102         };
 103
 104         psci {
 105                 compatible = "arm,psci-1.0";
 106                 method = "smc";
 107         };
 108
 109         timer {
 110                 compatible = "arm,armv8-timer";
 111                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 112                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 113                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 114                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 115         };
 116
 117         xin24m: xin24m {
 118                 compatible = "fixed-clock";
 119                 #clock-cells = <0>;
 120                 clock-frequency = <24000000>;
 121                 clock-output-names = "xin24m";
 122         };
 123
 124         gic: interrupt-controller@ffb71000 {
 125                 compatible = "arm,gic-400";
 126                 interrupt-controller;
 127                 #interrupt-cells = <3>;
 128                 #address-cells = <0>;
 129
 130                 reg = <0x0 0xffb71000 0x0 0x1000>,
 131                       <0x0 0xffb72000 0x0 0x1000>,
 132                       <0x0 0xffb74000 0x0 0x2000>,
 133                       <0x0 0xffb76000 0x0 0x2000>;
 134                 interrupts = <GIC_PPI 9
 135                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 136         };
 137
 138         nandc0: nandc@ff0c0000 {
 139                 compatible = "rockchip,rk-nandc";
 140                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 141                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 142                 nandc_id = <0>;
 143                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 144                 clock-names = "clk_nandc", "hclk_nandc";
 145                 status = "disabled";
 146         };
 147
 148         saradc: saradc@ff100000 {
 149                 compatible = "rockchip,saradc";
 150                 reg = <0x0 0xff100000 0x0 0x100>;
 151                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 152                 #io-channel-cells = <1>;
 153                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 154                 clock-names = "saradc", "apb_pclk";
 155                 status = "disabled";
 156         };
 157
 158         spi0: spi@ff110000 {
 159                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 160                 reg = <0x0 0xff110000 0x0 0x1000>;
 161                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 162                 clock-names = "spiclk", "apb_pclk";
 163                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 164                 pinctrl-names = "default";
 165                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 166                 #address-cells = <1>;
 167                 #size-cells = <0>;
 168                 status = "disabled";
 169         };
 170
 171         spi1: spi@ff120000 {
 172                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 173                 reg = <0x0 0xff120000 0x0 0x1000>;
 174                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 175                 clock-names = "spiclk", "apb_pclk";
 176                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 177                 pinctrl-names = "default";
 178                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 179                 #address-cells = <1>;
 180                 #size-cells = <0>;
 181                 status = "disabled";
 182         };
 183
 184         sdmmc: rksdmmc@ff400000 {
 185                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 186                 clock-freq-min-max = <400000 150000000>;
 187                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 188                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 189                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 190                 fifo-depth = <0x100>;
 191                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 192                 reg = <0x0 0xff400000 0x0 0x4000>;
 193                 status = "disabled";
 194         };
 195
 196         sdio: rksdmmc@ff410000 {
 197                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 198                 clock-freq-min-max = <400000 150000000>;
 199                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 200                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 201                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 202                 fifo-depth = <0x100>;
 203                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 204                 reg = <0x0 0xff410000 0x0 0x4000>;
 205                 status = "disabled";
 206         };
 207
 208         emmc: rksdmmc@ff420000 {
 209                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 210                 clock-freq-min-max = <400000 150000000>;
 211                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 212                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 214                 fifo-depth = <0x100>;
 215                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 216                 reg = <0x0 0xff420000 0x0 0x4000>;
 217                 status = "disabled";
 218         };
 219
 220         gmac: eth@ff440000 {
 221                 compatible = "rockchip,rk3366-gmac";
 222                 reg = <0x0 0xff440000 0x0 0x10000>;
 223                 rockchip,grf = <&grf>;
 224                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 225                 interrupt-names = "macirq";
 226                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 227                          <&cru SCLK_MAC_RX>, <&cru SCLK_MACREF>,
 228                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 229                          <&cru PCLK_GMAC>;
 230                 clock-names = "stmmaceth", "mac_clk_rx",
 231                               "mac_clk_tx", "clk_mac_ref",
 232                               "clk_mac_refout", "aclk_mac",
 233                               "pclk_mac";
 234                 resets = <&cru SRST_MAC>;
 235                 reset-names = "stmmaceth";
 236                 status = "disabled";
 237         };
 238
 239         i2c0: i2c@ff650000 {
 240                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 241                 reg = <0x0 0xff728000 0x0 0x1000>;
 242                 clocks = <&cru PCLK_I2C0>;
 243                 clock-names = "i2c";
 244                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 245                 pinctrl-names = "default";
 246                 pinctrl-0 = <&i2c0_xfer>;
 247                 #address-cells = <1>;
 248                 #size-cells = <0>;
 249                 status = "disabled";
 250         };
 251
 252         i2c2: i2c@ff140000 {
 253                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 254                 reg = <0x0 0xff140000 0x0 0x1000>;
 255                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 256                 #address-cells = <1>;
 257                 #size-cells = <0>;
 258                 clock-names = "i2c";
 259                 clocks = <&cru PCLK_I2C2>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&i2c2_xfer>;
 262                 status = "disabled";
 263         };
 264
 265         i2c3: i2c@ff150000 {
 266                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 267                 reg = <0x0 0xff150000 0x0 0x1000>;
 268                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 269                 #address-cells = <1>;
 270                 #size-cells = <0>;
 271                 clock-names = "i2c";
 272                 clocks = <&cru PCLK_I2C3>;
 273                 pinctrl-names = "default";
 274                 pinctrl-0 = <&i2c3_xfer>;
 275                 status = "disabled";
 276         };
 277
 278         i2c4: i2c@ff160000 {
 279                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 280                 reg = <0x0 0xff160000 0x0 0x1000>;
 281                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 282                 #address-cells = <1>;
 283                 #size-cells = <0>;
 284                 clock-names = "i2c";
 285                 clocks = <&cru PCLK_I2C4>;
 286                 pinctrl-names = "default";
 287                 pinctrl-0 = <&i2c4_xfer>;
 288                 status = "disabled";
 289         };
 290
 291         i2c5: i2c@ff170000 {
 292                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 293                 reg = <0x0 0xff170000 0x0 0x1000>;
 294                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 295                 #address-cells = <1>;
 296                 #size-cells = <0>;
 297                 clock-names = "i2c";
 298                 clocks = <&cru PCLK_I2C5>;
 299                 pinctrl-names = "default";
 300                 pinctrl-0 = <&i2c5_xfer>;
 301                 status = "disabled";
 302         };
 303
 304         uart0: serial@ff180000 {
 305                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 306                 reg = <0x0 0xff180000 0x0 0x100>;
 307                 clock-frequency = <24000000>;
 308                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 309                 clock-names = "baudclk", "apb_pclk";
 310                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 311                 reg-shift = <2>;
 312                 reg-io-width = <4>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 315                 status = "disabled";
 316         };
 317
 318         uart3: serial@ff1b0000 {
 319                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 320                 reg = <0x0 0xff1b0000 0x0 0x100>;
 321                 clock-frequency = <24000000>;
 322                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 323                 clock-names = "baudclk", "apb_pclk";
 324                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg-shift = <2>;
 326                 reg-io-width = <4>;
 327                 pinctrl-names = "default";
 328                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 329                 status = "disabled";
 330         };
 331
 332         usb_otg: usb@ff4c0000 {
 333                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 334                              "snps,dwc2";
 335                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 336                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 337                 clocks = <&cru HCLK_OTG>;
 338                 clock-names = "otg";
 339                 dr_mode = "otg";
 340                 g-np-tx-fifo-size = <16>;
 341                 g-rx-fifo-size = <275>;
 342                 g-tx-fifo-size = <256 128 128 64 64 32>;
 343                 g-use-dma;
 344                 status = "disabled";
 345         };
 346
 347         i2c1: i2c@ff660000 {
 348                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 349                 reg = <0x0 0xff660000 0x0 0x1000>;
 350                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C1>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c1_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         pwm0: pwm@ff680000 {
 361                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 362                 reg = <0x0 0xff680000 0x0 0x10>;
 363                 #pwm-cells = <3>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&pwm0_pin>;
 366                 clocks = <&cru PCLK_RKPWM>;
 367                 clock-names = "pwm";
 368                 status = "disabled";
 369         };
 370
 371         pwm1: pwm@ff680010 {
 372                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 373                 reg = <0x0 0xff680010 0x0 0x10>;
 374                 #pwm-cells = <3>;
 375                 pinctrl-names = "default";
 376                 pinctrl-0 = <&pwm1_pin>;
 377                 clocks = <&cru PCLK_RKPWM>;
 378                 clock-names = "pwm";
 379                 status = "disabled";
 380         };
 381
 382         pwm2: pwm@ff680020 {
 383                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 384                 reg = <0x0 0xff680020 0x0 0x10>;
 385                 #pwm-cells = <3>;
 386                 clocks = <&cru PCLK_RKPWM>;
 387                 clock-names = "pwm";
 388                 status = "disabled";
 389         };
 390
 391         pwm3: pwm@ff680030 {
 392                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 393                 reg = <0x0 0xff680030 0x0 0x10>;
 394                 #pwm-cells = <3>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pwm3_t2_pin>;
 397                 clocks = <&cru PCLK_RKPWM>;
 398                 clock-names = "pwm";
 399                 status = "disabled";
 400         };
 401
 402         uart2: serial@ff690000 {
 403                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 404                 reg = <0x0 0xff690000 0x0 0x100>;
 405                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 406                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 407                 clock-names = "baudclk", "apb_pclk";
 408                 reg-shift = <2>;
 409                 reg-io-width = <4>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&uart2_t1_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         pmu: power-management@ff730000 {
 416                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 417                 reg = <0x0 0xff730000 0x0 0x1000>;
 418
 419                 power: power-controller {
 420                         status = "disabled";
 421                         compatible = "rockchip,rk3366-power-controller";
 422                         #power-domain-cells = <1>;
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425
 426                         /*
 427                          * Note: Although SCLK_* are the working clocks
 428                          * of device without including on the NOC, needed for
 429                          * synchronous reset.
 430                          *
 431                          * The clocks on the which NOC:
 432                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 433                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 434                          * ACLK_ISP is on ACLK_ISP_NIU.
 435                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 436                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 437                          *
 438                          * Which clock are device clocks:
 439                          *      clocks          devices
 440                          *      *_IEP           IEP:Image Enhancement Processor
 441                          *      *_ISP           ISP:Image Signal Processing
 442                          *      *_VOP*          VOP:Visual Output Processor
 443                          *      *_RGA           RGA
 444                          *      *_DPHY*         LVDS
 445                          *      *_HDMI          HDMI
 446                          *      *_MIPI_*        MIPI
 447                          */
 448                         pd_vio {
 449                                 reg = <RK3366_PD_VIO>;
 450                                 clocks = <&cru ACLK_IEP>,
 451                                          <&cru ACLK_ISP>,
 452                                          <&cru ACLK_RGA>,
 453                                          <&cru ACLK_HDCP>,
 454                                          <&cru ACLK_VOP_FULL>,
 455                                          <&cru ACLK_VOP_LITE>,
 456                                          <&cru ACLK_VOP_IEP>,
 457                                          <&cru DCLK_VOP_FULL>,
 458                                          <&cru DCLK_VOP_LITE>,
 459                                          <&cru HCLK_IEP>,
 460                                          <&cru HCLK_ISP>,
 461                                          <&cru HCLK_RGA>,
 462                                          <&cru HCLK_VOP_FULL>,
 463                                          <&cru HCLK_VOP_LITE>,
 464                                          <&cru HCLK_VIO_HDCPMMU>,
 465                                          <&cru PCLK_HDMI_CTRL>,
 466                                          <&cru PCLK_HDCP>,
 467                                          <&cru PCLK_MIPI_DSI0>,
 468                                          <&cru SCLK_VOP_FULL_PWM>,
 469                                          <&cru SCLK_HDCP>,
 470                                          <&cru SCLK_ISP>,
 471                                          <&cru SCLK_RGA>,
 472                                          <&cru SCLK_HDMI_CEC>,
 473                                          <&cru SCLK_HDMI_HDCP>;
 474                         };
 475
 476                         /*
 477                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 478                          * (video endecoder & decoder) clocks that on the
 479                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 480                          */
 481                         pd_vpu {
 482                                 reg = <RK3366_PD_VPU>;
 483                                 clocks = <&cru ACLK_VIDEO>,
 484                                          <&cru HCLK_VIDEO>;
 485                         };
 486
 487                         /*
 488                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 489                          * (video decoder) clocks that on the
 490                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 491                          */
 492                         pd_rkvdec {
 493                                 reg = <RK3366_PD_RKVDEC>;
 494                                 clocks = <&cru ACLK_RKVDEC>,
 495                                          <&cru HCLK_RKVDEC>;
 496                         };
 497
 498                         pd_video {
 499                                 reg = <RK3366_PD_VIDEO>;
 500                                 clocks = <&cru ACLK_VIDEO>,
 501                                          <&cru ACLK_RKVDEC>,
 502                                          <&cru HCLK_VIDEO>,
 503                                          <&cru HCLK_RKVDEC>,
 504                                          <&cru SCLK_HEVC_CABAC>,
 505                                          <&cru SCLK_HEVC_CORE>;
 506                         };
 507
 508                         /*
 509                          * Note: ACLK_GPU is the GPU clock,
 510                          * and on the ACLK_GPU_NIU (NOC).
 511                          */
 512                         pd_gpu {
 513                                 reg = <RK3366_PD_GPU>;
 514                                 clocks = <&cru ACLK_GPU>;
 515                         };
 516                 };
 517         };
 518
 519         pmugrf: syscon@ff738000 {
 520                 compatible = "rockchip,rk3366-pmugrf", "syscon";
 521                 reg = <0x0 0xff738000 0x0 0x1000>;
 522         };
 523
 524         amba {
 525                 compatible = "arm,amba-bus";
 526                 #address-cells = <2>;
 527                 #size-cells = <2>;
 528                 ranges;
 529
 530                 dmac_peri: dma-controller@ff250000 {
 531                         compatible = "arm,pl330", "arm,primecell";
 532                         reg = <0x0 0xff250000 0x0 0x4000>;
 533                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 534                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 535                         #dma-cells = <1>;
 536                         clocks = <&cru ACLK_DMAC_PERI>;
 537                         clock-names = "apb_pclk";
 538                 };
 539
 540                 dmac_bus: dma-controller@ff600000 {
 541                         compatible = "arm,pl330", "arm,primecell";
 542                         reg = <0x0 0xff600000 0x0 0x4000>;
 543                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 544                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 545                         #dma-cells = <1>;
 546                         clocks = <&cru ACLK_DMAC_BUS>;
 547                         clock-names = "apb_pclk";
 548                 };
 549         };
 550
 551         cru: clock-controller@ff760000 {
 552                 compatible = "rockchip,rk3366-cru";
 553                 reg = <0x0 0xff760000 0x0 0x1000>;
 554                 rockchip,grf = <&grf>;
 555                 #clock-cells = <1>;
 556                 #reset-cells = <1>;
 557                 assigned-clocks =
 558                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 559                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 560                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 561                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 562                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 563                 assigned-clock-rates =
 564                         <750000000>, <576000000>,
 565                         <594000000>, <594000000>,
 566                         <480000000>, <520000000>,
 567                         <375000000>, <288000000>,
 568                         <100000000>, <100000000>;
 569         };
 570
 571         grf: syscon@ff770000 {
 572                 compatible = "rockchip,rk3366-grf", "syscon";
 573                 reg = <0x0 0xff770000 0x0 0x1000>;
 574         };
 575
 576         i2s_2ch: i2s-2ch@ff890000 {
 577                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 578                 reg = <0x0 0xff890000 0x0 0x1000>;
 579                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 580                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 581                 dma-names = "tx", "rx";
 582                 clock-names = "i2s_hclk", "i2s_clk";
 583                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 584                 status = "disabled";
 585         };
 586
 587         i2s_8ch: i2s-8ch@ff898000 {
 588                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 589                 reg = <0x0 0xff898000 0x0 0x1000>;
 590                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 591                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 592                 dma-names = "tx", "rx";
 593                 clock-names = "i2s_hclk", "i2s_clk";
 594                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&i2s_8ch_bus>;
 597                 status = "disabled";
 598         };
 599
 600         fb: fb {
 601                 compatible = "rockchip,rk-fb";
 602                 rockchip,disp-mode = <DUAL>;
 603                 status = "disabled";
 604         };
 605
 606         rk_screen: screen {
 607                 compatible = "rockchip,screen";
 608                 status = "disabled";
 609         };
 610
 611         vop_lite: vop@ff8f0000 {
 612                 compatible = "rockchip,rk3366-lcdc-lite";
 613                 rockchip,grf = <&grf>;
 614                 rockchip,pwr18 = <0>;
 615                 rockchip,iommu-enabled = <1>;
 616                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 617                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 618                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 619                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 620                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 621                 reset-names = "axi", "ahb", "dclk";
 622                 status = "disabled";
 623         };
 624
 625         vopl_mmu: vopl-mmu {
 626                 dbgname = "vop";
 627                 compatible = "rockchip,vopl_mmu";
 628                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 629                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 630                 interrupt-names = "vopl_mmu";
 631                 status = "disabled";
 632         };
 633
 634         rga: rga@ff920000 {
 635                 compatible = "rockchip,rga2";
 636                 dev_mode = <1>;
 637                 reg = <0x0 0xff920000 0x0 0x1000>;
 638                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 639                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 640                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 641                 status = "disabled";
 642         };
 643
 644         vop_big: vop@ff930000 {
 645                 compatible = "rockchip,rk3366-lcdc-big";
 646                 rockchip,grf = <&grf>;
 647                 rockchip,prop = <PRMRY>;
 648                 rockchip,pwr18 = <0>;
 649                 rockchip,iommu-enabled = <1>;
 650                 reg = <0x0 0xff930000 0x0 0x23f0>;
 651                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 653                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 654                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 655                 reset-names = "axi", "ahb", "dclk";
 656                 status = "disabled";
 657         };
 658
 659         vopb_mmu: vopb-mmu {
 660                 dbgname = "vop";
 661                 compatible = "rockchip,vopb_mmu";
 662                 reg = <0x0 0xff932400 0x0 0x100>;
 663                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 664                 interrupt-names = "vop_mmu";
 665                 status = "disabled";
 666         };
 667
 668         dsihost0: mipi@ff960000 {
 669                 compatible = "rockchip,rk3368-dsi";
 670                 rockchip,prop = <0>;
 671                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 672                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 673                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 674                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 675                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 676                 status = "disabled";
 677         };
 678
 679         lvds: lvds@ff968000 {
 680                 compatible = "rockchip,rk3366-lvds";
 681                 rockchip,grf = <&grf>;
 682                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 683                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 684                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 685                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 686                 status = "disabled";
 687         };
 688
 689         hdmi: hdmi@ff980000 {
 690                 compatible = "rockchip,rk3366-hdmi";
 691                 reg = <0x0 0xff980000 0x0 0x20000>;
 692                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 693                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 694                 clocks = <&cru PCLK_HDMI_CTRL>,
 695                          <&cru SCLK_HDMI_HDCP>,
 696                          <&cru SCLK_HDMI_CEC>,
 697                          <&cru DCLK_HDMIPHY>;
 698                 clock-names = "pclk_hdmi",
 699                               "hdcp_clk_hdmi",
 700                               "cec_clk_hdmi",
 701                               "dclk_hdmi_phy";
 702                 resets = <&cru SRST_HDMI>;
 703                 reset-names = "hdmi";
 704                 pinctrl-names = "default", "gpio";
 705                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 706                 pinctrl-1 = <&i2c5_gpio>;
 707                 status = "disabled";
 708         };
 709
 710         pinctrl: pinctrl {
 711                 compatible = "rockchip,rk3366-pinctrl";
 712                 rockchip,grf = <&grf>;
 713                 rockchip,pmu = <&pmugrf>;
 714                 #address-cells = <0x2>;
 715                 #size-cells = <0x2>;
 716                 ranges;
 717
 718                 gpio0: gpio0@ff750000 {
 719                         compatible = "rockchip,gpio-bank";
 720                         reg = <0x0 0xff750000 0x0 0x100>;
 721                         clocks = <&cru PCLK_GPIO0>;
 722                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 723
 724                         gpio-controller;
 725                         #gpio-cells = <0x2>;
 726
 727                         interrupt-controller;
 728                         #interrupt-cells = <0x2>;
 729                 };
 730
 731                 gpio1: gpio1@ff780000 {
 732                         compatible = "rockchip,gpio-bank";
 733                         reg = <0x0 0xff758000 0x0 0x100>;
 734                         clocks = <&cru PCLK_GPIO1>;
 735                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 736
 737                         gpio-controller;
 738                         #gpio-cells = <0x2>;
 739
 740                         interrupt-controller;
 741                         #interrupt-cells = <0x2>;
 742                 };
 743
 744                 gpio2: gpio2@ff790000 {
 745                         compatible = "rockchip,gpio-bank";
 746                         reg = <0x0 0xff790000 0x0 0x100>;
 747                         clocks = <&cru PCLK_GPIO2>;
 748                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 749
 750                         gpio-controller;
 751                         #gpio-cells = <0x2>;
 752
 753                         interrupt-controller;
 754                         #interrupt-cells = <0x2>;
 755                 };
 756
 757                 gpio3: gpio3@ff7a0000 {
 758                         compatible = "rockchip,gpio-bank";
 759                         reg = <0x0 0xff7a0000 0x0 0x100>;
 760                         clocks = <&cru PCLK_GPIO3>;
 761                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 762
 763                         gpio-controller;
 764                         #gpio-cells = <0x2>;
 765
 766                         interrupt-controller;
 767                         #interrupt-cells = <0x2>;
 768                 };
 769
 770                 gpio4: gpio4@ff7b0000 {
 771                         compatible = "rockchip,gpio-bank";
 772                         reg = <0x0 0xff7b0000 0x0 0x100>;
 773                         clocks = <&cru PCLK_GPIO4>;
 774                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 775
 776                         gpio-controller;
 777                         #gpio-cells = <0x2>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <0x2>;
 781                 };
 782
 783                 gpio5: gpio5@ff7c0000 {
 784                         compatible = "rockchip,gpio-bank";
 785                         reg = <0x0 0xff7c0000 0x0 0x100>;
 786                         clocks = <&cru PCLK_GPIO5>;
 787                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 788
 789                         gpio-controller;
 790                         #gpio-cells = <0x2>;
 791
 792                         interrupt-controller;
 793                         #interrupt-cells = <0x2>;
 794                 };
 795
 796                 pcfg_pull_up: pcfg-pull-up {
 797                         bias-pull-up;
 798                 };
 799
 800                 pcfg_pull_down: pcfg-pull-down {
 801                         bias-pull-down;
 802                 };
 803
 804                 pcfg_pull_none: pcfg-pull-none {
 805                         bias-disable;
 806                 };
 807
 808                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 809                         bias-disable;
 810                         drive-strength = <12>;
 811                 };
 812
 813                 emmc {
 814                         emmc_clk: emmc-clk {
 815                                 rockchip,pins =
 816                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 817                         };
 818
 819                         emmc_cmd: emmc-cmd {
 820                                 rockchip,pins =
 821                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 822                         };
 823
 824                         emmc_pwr: emmc-pwr {
 825                                 rockchip,pins =
 826                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 827                         };
 828
 829                         emmc_bus1: emmc-bus1 {
 830                                 rockchip,pins =
 831                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 832                         };
 833
 834                         emmc_bus4: emmc-bus4 {
 835                                 rockchip,pins =
 836                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 837                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 838                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 839                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 840                         };
 841
 842                         emmc_bus8: emmc-bus8 {
 843                                 rockchip,pins =
 844                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 845                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 846                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 847                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 848                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 849                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 850                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 851                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 852                         };
 853                 };
 854
 855                 sdmmc {
 856                         sdmmc_cd: sdmmc-cd {
 857                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 858                         };
 859
 860                         sdmmc_bus1: sdmmc-bus1 {
 861                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 862                         };
 863
 864                         sdmmc_bus4: sdmmc-bus4 {
 865                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 866                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 867                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 868                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 869                         };
 870
 871                         sdmmc_clk: sdmmc-clk {
 872                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 873                         };
 874
 875                         sdmmc_cmd: sdmmc-cmd {
 876                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 877                         };
 878                 };
 879
 880                 sdio {
 881                         sdio_bus1: sdio-bus1 {
 882                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 883                         };
 884
 885                         sdio_bus4: sdio-bus4 {
 886                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 887                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 888                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 889                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 890                         };
 891
 892                         sdio_cmd: sdio-cmd {
 893                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 894                         };
 895
 896                         sdio_clk: sdio-clk {
 897                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 898                         };
 899
 900                         sdio_cd: sdio-cd {
 901                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 902                         };
 903
 904                         sdio_wp: sdio-wp {
 905                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 906                         };
 907
 908                         sdio_int: sdio-int {
 909                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 910                         };
 911
 912                         sdio_pwr: sdio-pwr {
 913                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 914                         };
 915                 };
 916
 917                 hdmi_i2c {
 918                         hdmii2c_xfer: hdmii2c-xfer {
 919                                 rockchip,pins =
 920                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 921                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 922                         };
 923                 };
 924
 925                 hdmi_pin {
 926                         hdmi_cec: hdmi-cec {
 927                                 rockchip,pins =
 928                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930                 };
 931
 932                 i2c0 {
 933                         i2c0_xfer: i2c0-xfer {
 934                                 rockchip,pins =
 935                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 936                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 937                         };
 938                 };
 939
 940                 i2c1 {
 941                         i2c1_xfer: i2c1-xfer {
 942                                 rockchip,pins =
 943                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
 944                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
 945                         };
 946                 };
 947
 948                 i2c2 {
 949                         i2c2_xfer: i2c2-xfer {
 950                                 rockchip,pins =
 951                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
 952                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 i2c3 {
 957                         i2c3_xfer: i2c3-xfer {
 958                                 rockchip,pins =
 959                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
 960                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 961                         };
 962                 };
 963
 964                 i2c4 {
 965                         i2c4_xfer: i2c4-xfer {
 966                                 rockchip,pins =
 967                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
 968                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
 969                         };
 970                 };
 971
 972                 i2c5 {
 973                         i2c5_xfer: i2c5-xfer {
 974                                 rockchip,pins =
 975                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
 976                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
 977                         };
 978                         i2c5_gpio: i2c5-gpio {
 979                                 rockchip,pins =
 980                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
 981                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
 982                         };
 983                 };
 984
 985                 i2s {
 986                         i2s_8ch_bus: i2s-8ch-bus {
 987                                 rockchip,pins =
 988                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
 989                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
 990                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
 991                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
 992                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
 993                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
 994                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
 995                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
 996                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
 997                         };
 998                 };
 999
1000                 spi0 {
1001                         spi0_clk: spi0-clk {
1002                                 rockchip,pins =
1003                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1004                         };
1005                         spi0_cs0: spi0-cs0 {
1006                                 rockchip,pins =
1007                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1008                         };
1009                         spi0_cs1: spi0-cs1 {
1010                                 rockchip,pins =
1011                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1012                         };
1013                         spi0_tx: spi0-tx {
1014                                 rockchip,pins =
1015                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1016                         };
1017                         spi0_rx: spi0-rx {
1018                                 rockchip,pins =
1019                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1020                         };
1021                 };
1022
1023                 spi1 {
1024                         spi1_clk: spi1-clk {
1025                                 rockchip,pins =
1026                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1027                         };
1028                         spi1_cs0: spi1-cs0 {
1029                                 rockchip,pins =
1030                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1031                         };
1032                         spi1_tx: spi1-tx {
1033                                 rockchip,pins =
1034                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1035                         };
1036                         spi1_rx: spi1-rx {
1037                                 rockchip,pins =
1038                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1039                         };
1040                 };
1041
1042                 uart0 {
1043                         uart0_xfer: uart0-xfer {
1044                                 rockchip,pins =
1045                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1046                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1047                         };
1048
1049                         uart0_cts: uart0-cts {
1050                                 rockchip,pins =
1051                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1052                         };
1053
1054                         uart0_rts: uart0-rts {
1055                                 rockchip,pins =
1056                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 uart2_t0 {
1061                         uart2_t0_xfer: uart2_t0-xfer {
1062                                 rockchip,pins =
1063                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1064                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1065                         };
1066                         /* no rts / cts for uart2 */
1067                 };
1068
1069                 uart2_t1 {
1070                         uart2_t1_xfer: uart2_t1-xfer {
1071                                 rockchip,pins =
1072                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1073                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1074                         };
1075                         /* no rts / cts for uart2 */
1076                 };
1077
1078                 uart2_t2 {
1079                         uart2_t2_xfer: uart2_t2-xfer {
1080                                 rockchip,pins =
1081                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1082                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1083                         };
1084                         /* no rts / cts for uart2 */
1085                 };
1086
1087                 uart3 {
1088                         uart3_xfer: uart3-xfer {
1089                                 rockchip,pins =
1090                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1091                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1092                         };
1093
1094                         uart3_cts: uart3-cts {
1095                                 rockchip,pins =
1096                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1097                         };
1098
1099                         uart3_rts: uart3-rts {
1100                                 rockchip,pins =
1101                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1102                         };
1103                 };
1104
1105                 pwm0 {
1106                         pwm0_pin: pwm0-pin {
1107                                 rockchip,pins =
1108                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1109                         };
1110                 };
1111
1112                 pwm1 {
1113                         pwm1_pin: pwm1-pin {
1114                                 rockchip,pins =
1115                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1116                         };
1117                 };
1118
1119                 pwm2_t0 {
1120                         pwm2_t0_pin: pwm2_t0-pin {
1121                                 rockchip,pins =
1122                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1123                         };
1124                 };
1125
1126                 pwm2_t1 {
1127                         pwm2_t1_pin: pwm2_t1-pin {
1128                                 rockchip,pins =
1129                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1130                         };
1131                 };
1132
1133                 pwm3_t0 {
1134                         pwm3_t0_pin: pwm3_t0-pin {
1135                                 rockchip,pins =
1136                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1137                         };
1138                 };
1139
1140                 pwm3_t1 {
1141                         pwm3_t1_pin: pwm3_t1-pin {
1142                                 rockchip,pins =
1143                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1144                         };
1145                 };
1146
1147                 pwm3_t2 {
1148                         pwm3_t2_pin: pwm3_t2-pin {
1149                                 rockchip,pins =
1150                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1151                         };
1152                 };
1153
1154                 lcdc {
1155                         lcdc_lcdc: lcdc-lcdc {
1156                                 rockchip,pins =
1157                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1158                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1159                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1160                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1161                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1162                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1163                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1164                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1165                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1166                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1167                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1168                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1169                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1170                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1171                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1172                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1173                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1174                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1175                         };
1176
1177                         lcdc_gpio: lcdc-gpio {
1178                                 rockchip,pins =
1179                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1180                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1181                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1182                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1183                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1184                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1185                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1186                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1187                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1188                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1189                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1190                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1191                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1192                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1193                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1194                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1195                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1196                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1197                         };
1198                 };
1199
1200                 gmac {
1201                         rgmii_pins: rgmii-pins {
1202                                 rockchip,pins =
1203                                         /* mac_rxd3 */
1204                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1205                                         /* mac_rxd2 */
1206                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1207                                         /* mac_txd3 */
1208                                         <2 5  RK_FUNC_1 &pcfg_pull_none>,
1209                                         /* mac_txd2 */
1210                                         <2 4  RK_FUNC_1 &pcfg_pull_none>,
1211                                         /* mac_rxd1 */
1212                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1213                                         /* mac_rxd0 */
1214                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1215                                         /* mac_txd1 */
1216                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1217                                         /* mac_txd0 */
1218                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1219                                         /* mac_crs */
1220                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1221                                         /* mac_rxclkin */
1222                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1223                                         /* mac_mdio */
1224                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1225                                         /* mac_txen */
1226                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1227                                         /* mac_clk */
1228                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1229                                         /* mac_rxer */
1230                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1231                                         /* mac_rxdv */
1232                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1233                                         /* mac_mdc */
1234                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236
1237                         rmii_pins: rmii-pins {
1238                                 rockchip,pins =
1239                                         /* mac_rxd1 */
1240                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1241                                         /* mac_rxd0 */
1242                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1243                                         /* mac_txd1 */
1244                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1245                                         /* mac_txd0 */
1246                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1247                                         /* mac_crs */
1248                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1249                                         /* mac_rxclkin */
1250                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1251                                         /* mac_mdio */
1252                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1253                                         /* mac_txen */
1254                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1255                                         /* mac_clk */
1256                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1257                                         /* mac_rxer */
1258                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1259                                         /* mac_rxdv */
1260                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1261                                         /* mac_mdc */
1262                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1263                         };
1264                 };
1265
1266                 eth_phy {
1267                         eth_phy_pwr: eth-phy-pwr {
1268                                 rockchip,pins =
1269                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1270                         };
1271                 };
1272         };
1273 };