arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLK>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53","arm,armv8";
  88                         reg = <0x0 0x1>;
  89                         enable-method = "psci";
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                 };
  92
  93                 cpu2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53","arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53","arm,armv8";
 104                         reg = <0x0 0x3>;
 105                         enable-method = "psci";
 106                         operating-points-v2 = <&cpu0_opp_table>;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp_table0 {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp00 {
 115                         opp-hz = /bits/ 64 <408000000>;
 116                         opp-microvolt = <1200000>;
 117                         clock-latency-ns = <40000>;
 118                         opp-suspend;
 119                 };
 120                 opp01 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <1200000>;
 123                 };
 124                 opp02 {
 125                         opp-hz = /bits/ 64 <816000000>;
 126                         opp-microvolt = <1200000>;
 127                 };
 128                 opp03 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1200000>;
 131                 };
 132                 opp04 {
 133                         opp-hz = /bits/ 64 <1200000000>;
 134                         opp-microvolt = <1200000>;
 135                 };
 136         };
 137
 138         psci {
 139                 compatible = "arm,psci-1.0";
 140                 method = "smc";
 141         };
 142
 143         timer {
 144                 compatible = "arm,armv8-timer";
 145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 149         };
 150
 151         xin24m: xin24m {
 152                 compatible = "fixed-clock";
 153                 #clock-cells = <0>;
 154                 clock-frequency = <24000000>;
 155                 clock-output-names = "xin24m";
 156         };
 157
 158         gic: interrupt-controller@ffb71000 {
 159                 compatible = "arm,gic-400";
 160                 interrupt-controller;
 161                 #interrupt-cells = <3>;
 162                 #address-cells = <0>;
 163
 164                 reg = <0x0 0xffb71000 0x0 0x1000>,
 165                       <0x0 0xffb72000 0x0 0x1000>,
 166                       <0x0 0xffb74000 0x0 0x2000>,
 167                       <0x0 0xffb76000 0x0 0x2000>;
 168                 interrupts = <GIC_PPI 9
 169                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 170         };
 171
 172         nandc0: nandc@ff0c0000 {
 173                 compatible = "rockchip,rk-nandc";
 174                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 175                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 176                 nandc_id = <0>;
 177                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 178                 clock-names = "clk_nandc", "hclk_nandc";
 179                 status = "disabled";
 180         };
 181
 182         saradc: saradc@ff100000 {
 183                 compatible = "rockchip,saradc";
 184                 reg = <0x0 0xff100000 0x0 0x100>;
 185                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 186                 #io-channel-cells = <1>;
 187                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 188                 clock-names = "saradc", "apb_pclk";
 189                 status = "disabled";
 190         };
 191
 192         spi0: spi@ff110000 {
 193                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 194                 reg = <0x0 0xff110000 0x0 0x1000>;
 195                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 196                 clock-names = "spiclk", "apb_pclk";
 197                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 198                 pinctrl-names = "default";
 199                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 200                 #address-cells = <1>;
 201                 #size-cells = <0>;
 202                 status = "disabled";
 203         };
 204
 205         spi1: spi@ff120000 {
 206                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 207                 reg = <0x0 0xff120000 0x0 0x1000>;
 208                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 209                 clock-names = "spiclk", "apb_pclk";
 210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 211                 pinctrl-names = "default";
 212                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 213                 #address-cells = <1>;
 214                 #size-cells = <0>;
 215                 status = "disabled";
 216         };
 217
 218         sdmmc: rksdmmc@ff400000 {
 219                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 220                 clock-freq-min-max = <400000 150000000>;
 221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 222                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 223                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 224                 fifo-depth = <0x100>;
 225                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 226                 reg = <0x0 0xff400000 0x0 0x4000>;
 227                 status = "disabled";
 228         };
 229
 230         sdio: rksdmmc@ff410000 {
 231                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 234                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0x0 0xff410000 0x0 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         emmc: rksdmmc@ff420000 {
 243                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 246                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0x0 0xff420000 0x0 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         gmac: eth@ff440000 {
 255                 compatible = "rockchip,rk3366-gmac";
 256                 reg = <0x0 0xff440000 0x0 0x10000>;
 257                 rockchip,grf = <&grf>;
 258                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 259                 interrupt-names = "macirq";
 260                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 261                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 262                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 263                          <&cru PCLK_GMAC>;
 264                 clock-names = "stmmaceth", "mac_clk_rx",
 265                               "mac_clk_tx", "clk_mac_ref",
 266                               "clk_mac_refout", "aclk_mac",
 267                               "pclk_mac";
 268                 resets = <&cru SRST_MAC>;
 269                 reset-names = "stmmaceth";
 270                 status = "disabled";
 271         };
 272
 273         i2c0: i2c@ff650000 {
 274                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 275                 reg = <0x0 0xff728000 0x0 0x1000>;
 276                 clocks = <&cru PCLK_I2C0>;
 277                 clock-names = "i2c";
 278                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&i2c0_xfer>;
 281                 #address-cells = <1>;
 282                 #size-cells = <0>;
 283                 status = "disabled";
 284         };
 285
 286         i2c2: i2c@ff140000 {
 287                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 288                 reg = <0x0 0xff140000 0x0 0x1000>;
 289                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 clock-names = "i2c";
 293                 clocks = <&cru PCLK_I2C2>;
 294                 pinctrl-names = "default";
 295                 pinctrl-0 = <&i2c2_xfer>;
 296                 status = "disabled";
 297         };
 298
 299         i2c3: i2c@ff150000 {
 300                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 301                 reg = <0x0 0xff150000 0x0 0x1000>;
 302                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 clock-names = "i2c";
 306                 clocks = <&cru PCLK_I2C3>;
 307                 pinctrl-names = "default";
 308                 pinctrl-0 = <&i2c3_xfer>;
 309                 status = "disabled";
 310         };
 311
 312         i2c4: i2c@ff160000 {
 313                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 314                 reg = <0x0 0xff160000 0x0 0x1000>;
 315                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 316                 #address-cells = <1>;
 317                 #size-cells = <0>;
 318                 clock-names = "i2c";
 319                 clocks = <&cru PCLK_I2C4>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&i2c4_xfer>;
 322                 status = "disabled";
 323         };
 324
 325         i2c5: i2c@ff170000 {
 326                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 327                 reg = <0x0 0xff170000 0x0 0x1000>;
 328                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 clock-names = "i2c";
 332                 clocks = <&cru PCLK_I2C5>;
 333                 pinctrl-names = "default";
 334                 pinctrl-0 = <&i2c5_xfer>;
 335                 status = "disabled";
 336         };
 337
 338         uart0: serial@ff180000 {
 339                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 340                 reg = <0x0 0xff180000 0x0 0x100>;
 341                 clock-frequency = <24000000>;
 342                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 343                 clock-names = "baudclk", "apb_pclk";
 344                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 345                 reg-shift = <2>;
 346                 reg-io-width = <4>;
 347                 pinctrl-names = "default";
 348                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 349                 status = "disabled";
 350         };
 351
 352         uart3: serial@ff1b0000 {
 353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 354                 reg = <0x0 0xff1b0000 0x0 0x100>;
 355                 clock-frequency = <24000000>;
 356                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 357                 clock-names = "baudclk", "apb_pclk";
 358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 359                 reg-shift = <2>;
 360                 reg-io-width = <4>;
 361                 pinctrl-names = "default";
 362                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 363                 status = "disabled";
 364         };
 365
 366         usb_otg: usb@ff4c0000 {
 367                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 368                              "snps,dwc2";
 369                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 370                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 371                 clocks = <&cru HCLK_OTG>;
 372                 clock-names = "otg";
 373                 dr_mode = "otg";
 374                 g-np-tx-fifo-size = <16>;
 375                 g-rx-fifo-size = <275>;
 376                 g-tx-fifo-size = <256 128 128 64 64 32>;
 377                 g-use-dma;
 378                 status = "disabled";
 379         };
 380
 381         i2c1: i2c@ff660000 {
 382                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 383                 reg = <0x0 0xff660000 0x0 0x1000>;
 384                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clock-names = "i2c";
 388                 clocks = <&cru PCLK_I2C1>;
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c1_xfer>;
 391                 status = "disabled";
 392         };
 393
 394         pwm0: pwm@ff680000 {
 395                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 396                 reg = <0x0 0xff680000 0x0 0x10>;
 397                 #pwm-cells = <3>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&pwm0_pin>;
 400                 clocks = <&cru PCLK_RKPWM>;
 401                 clock-names = "pwm";
 402                 status = "disabled";
 403         };
 404
 405         pwm1: pwm@ff680010 {
 406                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 407                 reg = <0x0 0xff680010 0x0 0x10>;
 408                 #pwm-cells = <3>;
 409                 pinctrl-names = "default";
 410                 pinctrl-0 = <&pwm1_pin>;
 411                 clocks = <&cru PCLK_RKPWM>;
 412                 clock-names = "pwm";
 413                 status = "disabled";
 414         };
 415
 416         pwm2: pwm@ff680020 {
 417                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 418                 reg = <0x0 0xff680020 0x0 0x10>;
 419                 #pwm-cells = <3>;
 420                 clocks = <&cru PCLK_RKPWM>;
 421                 clock-names = "pwm";
 422                 status = "disabled";
 423         };
 424
 425         pwm3: pwm@ff680030 {
 426                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 427                 reg = <0x0 0xff680030 0x0 0x10>;
 428                 #pwm-cells = <3>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&pwm3_t2_pin>;
 431                 clocks = <&cru PCLK_RKPWM>;
 432                 clock-names = "pwm";
 433                 status = "disabled";
 434         };
 435
 436         uart2: serial@ff690000 {
 437                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 438                 reg = <0x0 0xff690000 0x0 0x100>;
 439                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 440                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 reg-shift = <2>;
 443                 reg-io-width = <4>;
 444                 pinctrl-names = "default";
 445                 pinctrl-0 = <&uart2_t1_xfer>;
 446                 status = "disabled";
 447         };
 448
 449         pmu: power-management@ff730000 {
 450                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 451                 reg = <0x0 0xff730000 0x0 0x1000>;
 452
 453                 power: power-controller {
 454                         status = "disabled";
 455                         compatible = "rockchip,rk3366-power-controller";
 456                         #power-domain-cells = <1>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459
 460                         /*
 461                          * Note: Although SCLK_* are the working clocks
 462                          * of device without including on the NOC, needed for
 463                          * synchronous reset.
 464                          *
 465                          * The clocks on the which NOC:
 466                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 467                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 468                          * ACLK_ISP is on ACLK_ISP_NIU.
 469                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 470                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 471                          *
 472                          * Which clock are device clocks:
 473                          *      clocks          devices
 474                          *      *_IEP           IEP:Image Enhancement Processor
 475                          *      *_ISP           ISP:Image Signal Processing
 476                          *      *_VOP*          VOP:Visual Output Processor
 477                          *      *_RGA           RGA
 478                          *      *_DPHY*         LVDS
 479                          *      *_HDMI          HDMI
 480                          *      *_MIPI_*        MIPI
 481                          */
 482                         pd_vio {
 483                                 reg = <RK3366_PD_VIO>;
 484                                 clocks = <&cru ACLK_IEP>,
 485                                          <&cru ACLK_ISP>,
 486                                          <&cru ACLK_RGA>,
 487                                          <&cru ACLK_HDCP>,
 488                                          <&cru ACLK_VOP_FULL>,
 489                                          <&cru ACLK_VOP_LITE>,
 490                                          <&cru ACLK_VOP_IEP>,
 491                                          <&cru DCLK_VOP_FULL>,
 492                                          <&cru DCLK_VOP_LITE>,
 493                                          <&cru HCLK_IEP>,
 494                                          <&cru HCLK_ISP>,
 495                                          <&cru HCLK_RGA>,
 496                                          <&cru HCLK_VOP_FULL>,
 497                                          <&cru HCLK_VOP_LITE>,
 498                                          <&cru HCLK_VIO_HDCPMMU>,
 499                                          <&cru PCLK_HDMI_CTRL>,
 500                                          <&cru PCLK_HDCP>,
 501                                          <&cru PCLK_MIPI_DSI0>,
 502                                          <&cru SCLK_VOP_FULL_PWM>,
 503                                          <&cru SCLK_HDCP>,
 504                                          <&cru SCLK_ISP>,
 505                                          <&cru SCLK_RGA>,
 506                                          <&cru SCLK_HDMI_CEC>,
 507                                          <&cru SCLK_HDMI_HDCP>;
 508                         };
 509
 510                         /*
 511                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 512                          * (video endecoder & decoder) clocks that on the
 513                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 514                          */
 515                         pd_vpu {
 516                                 reg = <RK3366_PD_VPU>;
 517                                 clocks = <&cru ACLK_VIDEO>,
 518                                          <&cru HCLK_VIDEO>;
 519                         };
 520
 521                         /*
 522                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 523                          * (video decoder) clocks that on the
 524                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 525                          */
 526                         pd_rkvdec {
 527                                 reg = <RK3366_PD_RKVDEC>;
 528                                 clocks = <&cru ACLK_RKVDEC>,
 529                                          <&cru HCLK_RKVDEC>;
 530                         };
 531
 532                         pd_video {
 533                                 reg = <RK3366_PD_VIDEO>;
 534                                 clocks = <&cru ACLK_VIDEO>,
 535                                          <&cru ACLK_RKVDEC>,
 536                                          <&cru HCLK_VIDEO>,
 537                                          <&cru HCLK_RKVDEC>,
 538                                          <&cru SCLK_HEVC_CABAC>,
 539                                          <&cru SCLK_HEVC_CORE>;
 540                         };
 541
 542                         /*
 543                          * Note: ACLK_GPU is the GPU clock,
 544                          * and on the ACLK_GPU_NIU (NOC).
 545                          */
 546                         pd_gpu {
 547                                 reg = <RK3366_PD_GPU>;
 548                                 clocks = <&cru ACLK_GPU>;
 549                         };
 550                 };
 551         };
 552
 553         pmugrf: syscon@ff738000 {
 554                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 555                 reg = <0x0 0xff738000 0x0 0x1000>;
 556
 557                 reboot-mode {
 558                         compatible = "syscon-reboot-mode";
 559                         offset = <0x200>;
 560                         mode-normal = <BOOT_NORMAL>;
 561                         mode-recovery = <BOOT_RECOVERY>;
 562                         mode-fastboot = <BOOT_FASTBOOT>;
 563                         mode-loader = <BOOT_LOADER>;
 564                 };
 565         };
 566
 567         amba {
 568                 compatible = "arm,amba-bus";
 569                 #address-cells = <2>;
 570                 #size-cells = <2>;
 571                 ranges;
 572
 573                 dmac_peri: dma-controller@ff250000 {
 574                         compatible = "arm,pl330", "arm,primecell";
 575                         reg = <0x0 0xff250000 0x0 0x4000>;
 576                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 577                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 578                         #dma-cells = <1>;
 579                         clocks = <&cru ACLK_DMAC_PERI>;
 580                         clock-names = "apb_pclk";
 581                 };
 582
 583                 dmac_bus: dma-controller@ff600000 {
 584                         compatible = "arm,pl330", "arm,primecell";
 585                         reg = <0x0 0xff600000 0x0 0x4000>;
 586                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 588                         #dma-cells = <1>;
 589                         clocks = <&cru ACLK_DMAC_BUS>;
 590                         clock-names = "apb_pclk";
 591                 };
 592         };
 593
 594         cru: clock-controller@ff760000 {
 595                 compatible = "rockchip,rk3366-cru";
 596                 reg = <0x0 0xff760000 0x0 0x1000>;
 597                 rockchip,grf = <&grf>;
 598                 #clock-cells = <1>;
 599                 #reset-cells = <1>;
 600                 assigned-clocks =
 601                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 602                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 603                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 604                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 605                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
 606                 assigned-clock-rates =
 607                         <750000000>, <576000000>,
 608                         <594000000>, <594000000>,
 609                         <480000000>, <520000000>,
 610                         <375000000>, <288000000>,
 611                         <100000000>, <100000000>;
 612         };
 613
 614         grf: syscon@ff770000 {
 615                 compatible = "rockchip,rk3366-grf", "syscon";
 616                 reg = <0x0 0xff770000 0x0 0x1000>;
 617         };
 618
 619         spdif: spdif@ff880000 {
 620                 compatible = "rockchip,rk3366-spdif";
 621                 reg = <0x0 0xff880000 0x0 0x1000>;
 622                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 623                 dmas = <&dmac_bus 3>;
 624                 dma-names = "tx";
 625                 clock-names = "hclk", "mclk";
 626                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 627                 pinctrl-names = "default";
 628                 pinctrl-0 = <&spdif_bus>;
 629                 status = "disabled";
 630         };
 631
 632         i2s_2ch: i2s-2ch@ff890000 {
 633                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 634                 reg = <0x0 0xff890000 0x0 0x1000>;
 635                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 636                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 637                 dma-names = "tx", "rx";
 638                 clock-names = "i2s_hclk", "i2s_clk";
 639                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 640                 status = "disabled";
 641         };
 642
 643         i2s_8ch: i2s-8ch@ff898000 {
 644                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 645                 reg = <0x0 0xff898000 0x0 0x1000>;
 646                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 647                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 648                 dma-names = "tx", "rx";
 649                 clock-names = "i2s_hclk", "i2s_clk";
 650                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 651                 pinctrl-names = "default";
 652                 pinctrl-0 = <&i2s_8ch_bus>;
 653                 status = "disabled";
 654         };
 655
 656         fb: fb {
 657                 compatible = "rockchip,rk-fb";
 658                 rockchip,disp-mode = <DUAL>;
 659                 status = "disabled";
 660         };
 661
 662         rk_screen: screen {
 663                 compatible = "rockchip,screen";
 664                 status = "disabled";
 665         };
 666
 667         vop_lite: vop@ff8f0000 {
 668                 compatible = "rockchip,rk3366-lcdc-lite";
 669                 rockchip,grf = <&grf>;
 670                 rockchip,pwr18 = <0>;
 671                 rockchip,iommu-enabled = <1>;
 672                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 673                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 674                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 675                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 676                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 677                 reset-names = "axi", "ahb", "dclk";
 678                 status = "disabled";
 679         };
 680
 681         vopl_mmu: vopl-mmu {
 682                 dbgname = "vop";
 683                 compatible = "rockchip,vopl_mmu";
 684                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 685                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 686                 interrupt-names = "vopl_mmu";
 687                 status = "disabled";
 688         };
 689
 690         rga: rga@ff920000 {
 691                 compatible = "rockchip,rga2";
 692                 dev_mode = <1>;
 693                 reg = <0x0 0xff920000 0x0 0x1000>;
 694                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 695                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 696                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 697                 status = "disabled";
 698         };
 699
 700         vop_big: vop@ff930000 {
 701                 compatible = "rockchip,rk3366-lcdc-big";
 702                 rockchip,grf = <&grf>;
 703                 rockchip,prop = <PRMRY>;
 704                 rockchip,pwr18 = <0>;
 705                 rockchip,iommu-enabled = <1>;
 706                 reg = <0x0 0xff930000 0x0 0x23f0>;
 707                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 708                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 709                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 710                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 711                 reset-names = "axi", "ahb", "dclk";
 712                 status = "disabled";
 713         };
 714
 715         vopb_mmu: vopb-mmu {
 716                 dbgname = "vop";
 717                 compatible = "rockchip,vopb_mmu";
 718                 reg = <0x0 0xff932400 0x0 0x100>;
 719                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 720                 interrupt-names = "vop_mmu";
 721                 status = "disabled";
 722         };
 723
 724         dsihost0: mipi@ff960000 {
 725                 compatible = "rockchip,rk3368-dsi";
 726                 rockchip,prop = <0>;
 727                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 728                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 729                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 730                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 731                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 732                 status = "disabled";
 733         };
 734
 735         lvds: lvds@ff968000 {
 736                 compatible = "rockchip,rk3366-lvds";
 737                 rockchip,grf = <&grf>;
 738                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 739                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 740                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 741                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 742                 status = "disabled";
 743         };
 744
 745         hdmi: hdmi@ff980000 {
 746                 compatible = "rockchip,rk3366-hdmi";
 747                 reg = <0x0 0xff980000 0x0 0x20000>;
 748                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 749                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 750                 clocks = <&cru PCLK_HDMI_CTRL>,
 751                          <&cru SCLK_HDMI_HDCP>,
 752                          <&cru SCLK_HDMI_CEC>,
 753                          <&cru DCLK_HDMIPHY>;
 754                 clock-names = "pclk_hdmi",
 755                               "hdcp_clk_hdmi",
 756                               "cec_clk_hdmi",
 757                               "dclk_hdmi_phy";
 758                 resets = <&cru SRST_HDMI>;
 759                 reset-names = "hdmi";
 760                 pinctrl-names = "default", "gpio";
 761                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 762                 pinctrl-1 = <&i2c5_gpio>;
 763                 status = "disabled";
 764         };
 765
 766         pinctrl: pinctrl {
 767                 compatible = "rockchip,rk3366-pinctrl";
 768                 rockchip,grf = <&grf>;
 769                 rockchip,pmu = <&pmugrf>;
 770                 #address-cells = <0x2>;
 771                 #size-cells = <0x2>;
 772                 ranges;
 773
 774                 gpio0: gpio0@ff750000 {
 775                         compatible = "rockchip,gpio-bank";
 776                         reg = <0x0 0xff750000 0x0 0x100>;
 777                         clocks = <&cru PCLK_GPIO0>;
 778                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 779
 780                         gpio-controller;
 781                         #gpio-cells = <0x2>;
 782
 783                         interrupt-controller;
 784                         #interrupt-cells = <0x2>;
 785                 };
 786
 787                 gpio1: gpio1@ff780000 {
 788                         compatible = "rockchip,gpio-bank";
 789                         reg = <0x0 0xff758000 0x0 0x100>;
 790                         clocks = <&cru PCLK_GPIO1>;
 791                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 792
 793                         gpio-controller;
 794                         #gpio-cells = <0x2>;
 795
 796                         interrupt-controller;
 797                         #interrupt-cells = <0x2>;
 798                 };
 799
 800                 gpio2: gpio2@ff790000 {
 801                         compatible = "rockchip,gpio-bank";
 802                         reg = <0x0 0xff790000 0x0 0x100>;
 803                         clocks = <&cru PCLK_GPIO2>;
 804                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 805
 806                         gpio-controller;
 807                         #gpio-cells = <0x2>;
 808
 809                         interrupt-controller;
 810                         #interrupt-cells = <0x2>;
 811                 };
 812
 813                 gpio3: gpio3@ff7a0000 {
 814                         compatible = "rockchip,gpio-bank";
 815                         reg = <0x0 0xff7a0000 0x0 0x100>;
 816                         clocks = <&cru PCLK_GPIO3>;
 817                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 818
 819                         gpio-controller;
 820                         #gpio-cells = <0x2>;
 821
 822                         interrupt-controller;
 823                         #interrupt-cells = <0x2>;
 824                 };
 825
 826                 gpio4: gpio4@ff7b0000 {
 827                         compatible = "rockchip,gpio-bank";
 828                         reg = <0x0 0xff7b0000 0x0 0x100>;
 829                         clocks = <&cru PCLK_GPIO4>;
 830                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 831
 832                         gpio-controller;
 833                         #gpio-cells = <0x2>;
 834
 835                         interrupt-controller;
 836                         #interrupt-cells = <0x2>;
 837                 };
 838
 839                 gpio5: gpio5@ff7c0000 {
 840                         compatible = "rockchip,gpio-bank";
 841                         reg = <0x0 0xff7c0000 0x0 0x100>;
 842                         clocks = <&cru PCLK_GPIO5>;
 843                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
 844
 845                         gpio-controller;
 846                         #gpio-cells = <0x2>;
 847
 848                         interrupt-controller;
 849                         #interrupt-cells = <0x2>;
 850                 };
 851
 852                 pcfg_pull_up: pcfg-pull-up {
 853                         bias-pull-up;
 854                 };
 855
 856                 pcfg_pull_down: pcfg-pull-down {
 857                         bias-pull-down;
 858                 };
 859
 860                 pcfg_pull_none: pcfg-pull-none {
 861                         bias-disable;
 862                 };
 863
 864                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 865                         bias-disable;
 866                         drive-strength = <12>;
 867                 };
 868
 869                 emmc {
 870                         emmc_clk: emmc-clk {
 871                                 rockchip,pins =
 872                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
 873                         };
 874
 875                         emmc_cmd: emmc-cmd {
 876                                 rockchip,pins =
 877                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
 878                         };
 879
 880                         emmc_pwr: emmc-pwr {
 881                                 rockchip,pins =
 882                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
 883                         };
 884
 885                         emmc_bus1: emmc-bus1 {
 886                                 rockchip,pins =
 887                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
 888                         };
 889
 890                         emmc_bus4: emmc-bus4 {
 891                                 rockchip,pins =
 892                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 893                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 894                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 895                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
 896                         };
 897
 898                         emmc_bus8: emmc-bus8 {
 899                                 rockchip,pins =
 900                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
 901                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
 902                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
 903                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
 904                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
 905                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
 906                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
 907                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
 908                         };
 909                 };
 910
 911                 sdmmc {
 912                         sdmmc_cd: sdmmc-cd {
 913                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
 914                         };
 915
 916                         sdmmc_bus1: sdmmc-bus1 {
 917                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
 918                         };
 919
 920                         sdmmc_bus4: sdmmc-bus4 {
 921                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
 922                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
 923                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
 924                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
 925                         };
 926
 927                         sdmmc_clk: sdmmc-clk {
 928                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930
 931                         sdmmc_cmd: sdmmc-cmd {
 932                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
 933                         };
 934                 };
 935
 936                 sdio {
 937                         sdio_bus1: sdio-bus1 {
 938                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
 939                         };
 940
 941                         sdio_bus4: sdio-bus4 {
 942                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
 943                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
 944                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
 945                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
 946                         };
 947
 948                         sdio_cmd: sdio-cmd {
 949                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
 950                         };
 951
 952                         sdio_clk: sdio-clk {
 953                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
 954                         };
 955
 956                         sdio_cd: sdio-cd {
 957                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
 958                         };
 959
 960                         sdio_wp: sdio-wp {
 961                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
 962                         };
 963
 964                         sdio_int: sdio-int {
 965                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
 966                         };
 967
 968                         sdio_pwr: sdio-pwr {
 969                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
 970                         };
 971                 };
 972
 973                 hdmi_i2c {
 974                         hdmii2c_xfer: hdmii2c-xfer {
 975                                 rockchip,pins =
 976                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
 977                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
 978                         };
 979                 };
 980
 981                 hdmi_pin {
 982                         hdmi_cec: hdmi-cec {
 983                                 rockchip,pins =
 984                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
 985                         };
 986                 };
 987
 988                 i2c0 {
 989                         i2c0_xfer: i2c0-xfer {
 990                                 rockchip,pins =
 991                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
 992                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
 993                         };
 994                 };
 995
 996                 i2c1 {
 997                         i2c1_xfer: i2c1-xfer {
 998                                 rockchip,pins =
 999                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 i2c2 {
1005                         i2c2_xfer: i2c2-xfer {
1006                                 rockchip,pins =
1007                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1008                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1009                         };
1010                 };
1011
1012                 i2c3 {
1013                         i2c3_xfer: i2c3-xfer {
1014                                 rockchip,pins =
1015                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1016                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1017                         };
1018                 };
1019
1020                 i2c4 {
1021                         i2c4_xfer: i2c4-xfer {
1022                                 rockchip,pins =
1023                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1024                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1025                         };
1026                 };
1027
1028                 i2c5 {
1029                         i2c5_xfer: i2c5-xfer {
1030                                 rockchip,pins =
1031                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1032                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1033                         };
1034                         i2c5_gpio: i2c5-gpio {
1035                                 rockchip,pins =
1036                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1037                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1038                         };
1039                 };
1040
1041                 i2s {
1042                         i2s_8ch_bus: i2s-8ch-bus {
1043                                 rockchip,pins =
1044                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1045                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1046                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1047                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1048                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1049                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1050                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1051                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1052                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 spdif {
1057                         spdif_bus: spdif-bus {
1058                                 rockchip,pins =
1059                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1060                         };
1061                 };
1062
1063                 spi0 {
1064                         spi0_clk: spi0-clk {
1065                                 rockchip,pins =
1066                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1067                         };
1068                         spi0_cs0: spi0-cs0 {
1069                                 rockchip,pins =
1070                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1071                         };
1072                         spi0_cs1: spi0-cs1 {
1073                                 rockchip,pins =
1074                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1075                         };
1076                         spi0_tx: spi0-tx {
1077                                 rockchip,pins =
1078                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1079                         };
1080                         spi0_rx: spi0-rx {
1081                                 rockchip,pins =
1082                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1083                         };
1084                 };
1085
1086                 spi1 {
1087                         spi1_clk: spi1-clk {
1088                                 rockchip,pins =
1089                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1090                         };
1091                         spi1_cs0: spi1-cs0 {
1092                                 rockchip,pins =
1093                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1094                         };
1095                         spi1_tx: spi1-tx {
1096                                 rockchip,pins =
1097                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1098                         };
1099                         spi1_rx: spi1-rx {
1100                                 rockchip,pins =
1101                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1102                         };
1103                 };
1104
1105                 uart0 {
1106                         uart0_xfer: uart0-xfer {
1107                                 rockchip,pins =
1108                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1109                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1110                         };
1111
1112                         uart0_cts: uart0-cts {
1113                                 rockchip,pins =
1114                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116
1117                         uart0_rts: uart0-rts {
1118                                 rockchip,pins =
1119                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 uart2_t0 {
1124                         uart2_t0_xfer: uart2_t0-xfer {
1125                                 rockchip,pins =
1126                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1127                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129                         /* no rts / cts for uart2 */
1130                 };
1131
1132                 uart2_t1 {
1133                         uart2_t1_xfer: uart2_t1-xfer {
1134                                 rockchip,pins =
1135                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1136                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1137                         };
1138                         /* no rts / cts for uart2 */
1139                 };
1140
1141                 uart2_t2 {
1142                         uart2_t2_xfer: uart2_t2-xfer {
1143                                 rockchip,pins =
1144                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1145                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1146                         };
1147                         /* no rts / cts for uart2 */
1148                 };
1149
1150                 uart3 {
1151                         uart3_xfer: uart3-xfer {
1152                                 rockchip,pins =
1153                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1154                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156
1157                         uart3_cts: uart3-cts {
1158                                 rockchip,pins =
1159                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         uart3_rts: uart3-rts {
1163                                 rockchip,pins =
1164                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1165                         };
1166                 };
1167
1168                 pwm0 {
1169                         pwm0_pin: pwm0-pin {
1170                                 rockchip,pins =
1171                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1172                         };
1173                 };
1174
1175                 pwm1 {
1176                         pwm1_pin: pwm1-pin {
1177                                 rockchip,pins =
1178                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1179                         };
1180                 };
1181
1182                 pwm2_t0 {
1183                         pwm2_t0_pin: pwm2_t0-pin {
1184                                 rockchip,pins =
1185                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1186                         };
1187                 };
1188
1189                 pwm2_t1 {
1190                         pwm2_t1_pin: pwm2_t1-pin {
1191                                 rockchip,pins =
1192                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1193                         };
1194                 };
1195
1196                 pwm3_t0 {
1197                         pwm3_t0_pin: pwm3_t0-pin {
1198                                 rockchip,pins =
1199                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1200                         };
1201                 };
1202
1203                 pwm3_t1 {
1204                         pwm3_t1_pin: pwm3_t1-pin {
1205                                 rockchip,pins =
1206                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1207                         };
1208                 };
1209
1210                 pwm3_t2 {
1211                         pwm3_t2_pin: pwm3_t2-pin {
1212                                 rockchip,pins =
1213                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1214                         };
1215                 };
1216
1217                 lcdc {
1218                         lcdc_lcdc: lcdc-lcdc {
1219                                 rockchip,pins =
1220                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1221                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1222                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1223                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1224                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1225                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1226                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1227                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1228                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1229                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1230                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1231                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1232                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1233                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1234                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1235                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1236                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1237                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1238                         };
1239
1240                         lcdc_gpio: lcdc-gpio {
1241                                 rockchip,pins =
1242                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1243                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1244                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1245                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1246                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1247                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1248                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1249                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1250                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1251                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1252                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1253                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1254                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1255                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1256                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1257                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1258                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1259                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1260                         };
1261                 };
1262
1263                 gmac {
1264                         rgmii_pins: rgmii-pins {
1265                                 rockchip,pins =
1266                                         /* mac_rxd3 */
1267                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1268                                         /* mac_rxd2 */
1269                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1270                                         /* mac_txd3 */
1271                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1272                                         /* mac_txd2 */
1273                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1274                                         /* mac_rxd1 */
1275                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1276                                         /* mac_rxd0 */
1277                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1278                                         /* mac_txd1 */
1279                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1280                                         /* mac_txd0 */
1281                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1282                                         /* mac_txclkout */
1283                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1284                                         /* mac_crs */
1285                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1286                                         /* mac_rxclkin */
1287                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1288                                         /* mac_mdio */
1289                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1290                                         /* mac_txen */
1291                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1292                                         /* mac_clk */
1293                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1294                                         /* mac_rxer */
1295                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1296                                         /* mac_rxdv */
1297                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1298                                         /* mac_mdc */
1299                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1300                         };
1301
1302                         rmii_pins: rmii-pins {
1303                                 rockchip,pins =
1304                                         /* mac_rxd1 */
1305                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1306                                         /* mac_rxd0 */
1307                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1308                                         /* mac_txd1 */
1309                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1310                                         /* mac_txd0 */
1311                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1312                                         /* mac_crs */
1313                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1314                                         /* mac_rxclkin */
1315                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1316                                         /* mac_mdio */
1317                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1318                                         /* mac_txen */
1319                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1320                                         /* mac_clk */
1321                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1322                                         /* mac_rxer */
1323                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1324                                         /* mac_rxdv */
1325                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1326                                         /* mac_mdc */
1327                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1328                         };
1329                 };
1330
1331                 eth_phy {
1332                         eth_phy_pwr: eth-phy-pwr {
1333                                 rockchip,pins =
1334                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1335                         };
1336                 };
1337         };
1338 };