arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip,boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3366";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x0>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&cpu_sleep>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <166>;
  88                 };
  89
  90                 cpu1: cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x1>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cpu-idle-states = <&cpu_sleep>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53","arm,armv8";
 102                         reg = <0x0 0x2>;
 103                         enable-method = "psci";
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                 };
 107
 108                 cpu3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         operating-points-v2 = <&cpu0_opp_table>;
 114                         cpu-idle-states = <&cpu_sleep>;
 115                 };
 116
 117                 idle-states {
 118                         entry-method = "psci";
 119                         cpu_sleep: cpu-sleep-0 {
 120                                 compatible = "arm,idle-state";
 121                                 local-timer-stop;
 122                                 arm,psci-suspend-param = <0x0010000>;
 123                                 entry-latency-us = <350>;
 124                                 exit-latency-us = <600>;
 125                                 min-residency-us = <1150>;
 126                         };
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp@408000000 {
 135                         opp-hz = /bits/ 64 <408000000>;
 136                         opp-microvolt = <950000>;
 137                         clock-latency-ns = <40000>;
 138                         opp-suspend;
 139                 };
 140                 opp@600000000 {
 141                         opp-hz = /bits/ 64 <600000000>;
 142                         opp-microvolt = <950000>;
 143                 };
 144                 opp@816000000 {
 145                         opp-hz = /bits/ 64 <816000000>;
 146                         opp-microvolt = <1000000>;
 147                 };
 148                 opp@1008000000 {
 149                         opp-hz = /bits/ 64 <1008000000>;
 150                         opp-microvolt = <1075000>;
 151                 };
 152                 opp@1200000000 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <1175000>;
 155                 };
 156                 opp@1296000000 {
 157                         opp-hz = /bits/ 64 <1296000000>;
 158                         opp-microvolt = <1250000>;
 159                 };
 160         };
 161
 162         cpu_avs: cpu-avs {
 163                 cluster0-avs {
 164                         cluster-id = <0>;
 165                         min-volt = <950000>; /* uV */
 166                         min-freq = <408000>; /* KHz */
 167                         leakage-adjust-volt = <
 168                         /*  mA        mA         uV */
 169                             0         254        0
 170                         >;
 171                         nvmem-cells = <&cpu_leakage>;
 172                         nvmem-cell-names = "cpu_leakage";
 173                 };
 174         };
 175
 176         psci {
 177                 compatible = "arm,psci-1.0";
 178                 method = "smc";
 179         };
 180
 181         timer {
 182                 compatible = "arm,armv8-timer";
 183                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 184                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 185                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 186                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 187         };
 188
 189         arm-pmu {
 190                 compatible = "arm,cortex-a53-pmu";
 191                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 192                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 193                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 194                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 195                 interrupt-affinity = <&cpu0>,
 196                                      <&cpu1>,
 197                                      <&cpu2>,
 198                                      <&cpu3>;
 199         };
 200
 201         xin24m: xin24m {
 202                 compatible = "fixed-clock";
 203                 #clock-cells = <0>;
 204                 clock-frequency = <24000000>;
 205                 clock-output-names = "xin24m";
 206         };
 207
 208         gic: interrupt-controller@ffb71000 {
 209                 compatible = "arm,gic-400";
 210                 interrupt-controller;
 211                 #interrupt-cells = <3>;
 212                 #address-cells = <0>;
 213
 214                 reg = <0x0 0xffb71000 0x0 0x1000>,
 215                       <0x0 0xffb72000 0x0 0x1000>,
 216                       <0x0 0xffb74000 0x0 0x2000>,
 217                       <0x0 0xffb76000 0x0 0x2000>;
 218                 interrupts = <GIC_PPI 9
 219                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 220         };
 221
 222         nandc0: nandc@ff0c0000 {
 223                 compatible = "rockchip,rk-nandc";
 224                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 225                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 226                 nandc_id = <0>;
 227                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 228                 clock-names = "clk_nandc", "hclk_nandc";
 229                 status = "disabled";
 230         };
 231
 232         saradc: saradc@ff100000 {
 233                 compatible = "rockchip,saradc";
 234                 reg = <0x0 0xff100000 0x0 0x100>;
 235                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 236                 #io-channel-cells = <1>;
 237                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 238                 clock-names = "saradc", "apb_pclk";
 239                 status = "disabled";
 240         };
 241
 242         spi0: spi@ff110000 {
 243                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 244                 reg = <0x0 0xff110000 0x0 0x1000>;
 245                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 246                 clock-names = "spiclk", "apb_pclk";
 247                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 status = "disabled";
 253         };
 254
 255         spi1: spi@ff120000 {
 256                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 257                 reg = <0x0 0xff120000 0x0 0x1000>;
 258                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 259                 clock-names = "spiclk", "apb_pclk";
 260                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 261                 pinctrl-names = "default";
 262                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 263                 #address-cells = <1>;
 264                 #size-cells = <0>;
 265                 status = "disabled";
 266         };
 267
 268         scr: rkscr@ff1d0000 {
 269                 compatible = "rockchip-scr";
 270                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 271                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 272                 #address-cells = <1>;
 273                 #size-cells = <0>;
 274                 pinctrl-names = "default";
 275                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 276                 clocks = <&cru PCLK_SIM>;
 277                 clock-names = "g_pclk_sim_card";
 278                 status = "disabled";
 279         };
 280
 281         thermal-zones {
 282                 soc_thermal: soc-thermal {
 283                         polling-delay-passive = <100>; /* milliseconds */
 284                         polling-delay = <1000>; /* milliseconds */
 285                         sustainable-power = <1600>; /* milliwatts */
 286
 287                         thermal-sensors = <&tsadc 0>;
 288
 289                         trips {
 290                                 threshold: trip-point@0 {
 291                                         temperature = <70000>; /* millicelsius */
 292                                         hysteresis = <2000>; /* millicelsius */
 293                                         type = "passive";
 294                                 };
 295                                 target: trip-point@1 {
 296                                         temperature = <85000>; /* millicelsius */
 297                                         hysteresis = <2000>; /* millicelsius */
 298                                         type = "passive";
 299                                 };
 300                                 soc_crit: soc-crit {
 301                                         temperature = <95000>; /* millicelsius */
 302                                         hysteresis = <2000>; /* millicelsius */
 303                                         type = "critical";
 304                                 };
 305                         };
 306
 307                         cooling-maps {
 308                                 map0 {
 309                                         trip = <&target>;
 310                                         cooling-device =
 311                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 312                                 };
 313                                 map1 {
 314                                         trip = <&target>;
 315                                         cooling-device =
 316                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 317                                 };
 318                         };
 319                 };
 320
 321                 gpu_thermal: gpu-thermal {
 322                         polling-delay-passive = <100>; /* milliseconds */
 323                         polling-delay = <1000>; /* milliseconds */
 324
 325                         thermal-sensors = <&tsadc 1>;
 326                 };
 327         };
 328
 329         tsadc: tsadc@ff260000 {
 330                 compatible = "rockchip,rk3366-tsadc";
 331                 reg = <0x0 0xff260000 0x0 0x100>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 334                 clock-names = "tsadc", "apb_pclk";
 335                 resets = <&cru SRST_TSADC>;
 336                 reset-names = "tsadc-apb";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&tsadc_gpio>;
 339                 #thermal-sensor-cells = <1>;
 340                 rockchip,hw-tshut-temp = <95000>;
 341                 status = "disabled";
 342         };
 343
 344         sdmmc: rksdmmc@ff400000 {
 345                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 346                 clock-freq-min-max = <400000 150000000>;
 347                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 348                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 349                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 350                 fifo-depth = <0x100>;
 351                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 352                 reg = <0x0 0xff400000 0x0 0x4000>;
 353                 status = "disabled";
 354         };
 355
 356         sdio: rksdmmc@ff410000 {
 357                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 358                 clock-freq-min-max = <400000 150000000>;
 359                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 360                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 361                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 362                 fifo-depth = <0x100>;
 363                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 364                 reg = <0x0 0xff410000 0x0 0x4000>;
 365                 status = "disabled";
 366         };
 367
 368         emmc: rksdmmc@ff420000 {
 369                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 370                 clock-freq-min-max = <400000 150000000>;
 371                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 372                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 373                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 374                 fifo-depth = <0x100>;
 375                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 376                 reg = <0x0 0xff420000 0x0 0x4000>;
 377                 status = "disabled";
 378         };
 379
 380         gmac: eth@ff440000 {
 381                 compatible = "rockchip,rk3366-gmac";
 382                 reg = <0x0 0xff440000 0x0 0x10000>;
 383                 rockchip,grf = <&grf>;
 384                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 385                 interrupt-names = "macirq";
 386                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 387                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 388                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 389                          <&cru PCLK_GMAC>;
 390                 clock-names = "stmmaceth", "mac_clk_rx",
 391                               "mac_clk_tx", "clk_mac_ref",
 392                               "clk_mac_refout", "aclk_mac",
 393                               "pclk_mac";
 394                 resets = <&cru SRST_MAC>;
 395                 reset-names = "stmmaceth";
 396                 status = "disabled";
 397         };
 398
 399         i2c0: i2c@ff650000 {
 400                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 401                 reg = <0x0 0xff728000 0x0 0x1000>;
 402                 clocks = <&cru PCLK_I2C0>;
 403                 clock-names = "i2c";
 404                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 405                 pinctrl-names = "default";
 406                 pinctrl-0 = <&i2c0_xfer>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 status = "disabled";
 410         };
 411
 412         i2c2: i2c@ff140000 {
 413                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 414                 reg = <0x0 0xff140000 0x0 0x1000>;
 415                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 416                 #address-cells = <1>;
 417                 #size-cells = <0>;
 418                 clock-names = "i2c";
 419                 clocks = <&cru PCLK_I2C2>;
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&i2c2_xfer>;
 422                 status = "disabled";
 423         };
 424
 425         i2c3: i2c@ff150000 {
 426                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 427                 reg = <0x0 0xff150000 0x0 0x1000>;
 428                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clock-names = "i2c";
 432                 clocks = <&cru PCLK_I2C3>;
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&i2c3_xfer>;
 435                 status = "disabled";
 436         };
 437
 438         i2c4: i2c@ff160000 {
 439                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 440                 reg = <0x0 0xff160000 0x0 0x1000>;
 441                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 442                 #address-cells = <1>;
 443                 #size-cells = <0>;
 444                 clock-names = "i2c";
 445                 clocks = <&cru PCLK_I2C4>;
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&i2c4_xfer>;
 448                 status = "disabled";
 449         };
 450
 451         i2c5: i2c@ff170000 {
 452                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 453                 reg = <0x0 0xff170000 0x0 0x1000>;
 454                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 455                 #address-cells = <1>;
 456                 #size-cells = <0>;
 457                 clock-names = "i2c";
 458                 clocks = <&cru PCLK_I2C5>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&i2c5_xfer>;
 461                 status = "disabled";
 462         };
 463
 464         uart0: serial@ff180000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff180000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 475                 status = "disabled";
 476         };
 477
 478         uart3: serial@ff1b0000 {
 479                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 480                 reg = <0x0 0xff1b0000 0x0 0x100>;
 481                 clock-frequency = <24000000>;
 482                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 483                 clock-names = "baudclk", "apb_pclk";
 484                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 485                 reg-shift = <2>;
 486                 reg-io-width = <4>;
 487                 pinctrl-names = "default";
 488                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 489                 status = "disabled";
 490         };
 491
 492         usb_host0_ehci: usb@ff480000 {
 493                 compatible = "generic-ehci";
 494                 reg = <0x0 0xff480000 0x0 0x20000>;
 495                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 497                 clock-names = "usbphy_480m", "hclk_host0";
 498                 phys = <&u2phy_host>;
 499                 phy-names = "usb";
 500                 status = "disabled";
 501         };
 502
 503         usb_host0_ohci: usb@ff4a0000 {
 504                 compatible = "generic-ohci";
 505                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 506                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 507                 clocks = <&cru SCLK_USBPHY480M>, <&cru HCLK_HOST>;
 508                 clock-names = "usbphy_480m", "hclk_host0";
 509                 phys = <&u2phy_host>;
 510                 phy-names = "usb";
 511                 status = "disabled";
 512         };
 513
 514         usb_otg: usb@ff4c0000 {
 515                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 516                              "snps,dwc2";
 517                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 518                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 519                 clocks = <&cru HCLK_OTG>;
 520                 clock-names = "otg";
 521                 dr_mode = "otg";
 522                 g-np-tx-fifo-size = <16>;
 523                 g-rx-fifo-size = <275>;
 524                 g-tx-fifo-size = <256 128 128 64 64 32>;
 525                 g-use-dma;
 526                 status = "disabled";
 527         };
 528
 529         i2c1: i2c@ff660000 {
 530                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 531                 reg = <0x0 0xff660000 0x0 0x1000>;
 532                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 533                 #address-cells = <1>;
 534                 #size-cells = <0>;
 535                 clock-names = "i2c";
 536                 clocks = <&cru PCLK_I2C1>;
 537                 pinctrl-names = "default";
 538                 pinctrl-0 = <&i2c1_xfer>;
 539                 status = "disabled";
 540         };
 541
 542         efuse: efuse@ff670000 {
 543                 compatible = "rockchip,rk3366-efuse";
 544                 reg = <0x0 0xff670000 0x0 0x20>;
 545                 #address-cells = <1>;
 546                 #size-cells = <1>;
 547                 clocks = <&cru PCLK_EFUSE_256>;
 548                 clock-names = "pclk_efuse";
 549
 550                 /* Data cells */
 551                 cpu_leakage: cpu-leakage {
 552                         reg = <0x17 0x1>;
 553                 };
 554                 gpu_leakage: gpu-leakage {
 555                         reg = <0x18 0x1>;
 556                 };
 557                 logic_leakage: logic-leakage {
 558                         reg = <0x19 0x1>;
 559                 };
 560                 wafer_info: wafer-info {
 561                         reg = <0x1c 0x1>;
 562                 };
 563         };
 564
 565         pwm0: pwm@ff680000 {
 566                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 567                 reg = <0x0 0xff680000 0x0 0x10>;
 568                 #pwm-cells = <3>;
 569                 pinctrl-names = "default";
 570                 pinctrl-0 = <&pwm0_pin>;
 571                 clocks = <&cru PCLK_RKPWM>;
 572                 clock-names = "pwm";
 573                 status = "disabled";
 574         };
 575
 576         pwm1: pwm@ff680010 {
 577                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 578                 reg = <0x0 0xff680010 0x0 0x10>;
 579                 #pwm-cells = <3>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm1_pin>;
 582                 clocks = <&cru PCLK_RKPWM>;
 583                 clock-names = "pwm";
 584                 status = "disabled";
 585         };
 586
 587         pwm2: pwm@ff680020 {
 588                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 589                 reg = <0x0 0xff680020 0x0 0x10>;
 590                 #pwm-cells = <3>;
 591                 clocks = <&cru PCLK_RKPWM>;
 592                 clock-names = "pwm";
 593                 status = "disabled";
 594         };
 595
 596         pwm3: pwm@ff680030 {
 597                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 598                 reg = <0x0 0xff680030 0x0 0x10>;
 599                 #pwm-cells = <3>;
 600                 pinctrl-names = "default";
 601                 pinctrl-0 = <&pwm3_t2_pin>;
 602                 clocks = <&cru PCLK_RKPWM>;
 603                 clock-names = "pwm";
 604                 status = "disabled";
 605         };
 606
 607         uart2: serial@ff690000 {
 608                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 609                 reg = <0x0 0xff690000 0x0 0x100>;
 610                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 612                 clock-names = "baudclk", "apb_pclk";
 613                 reg-shift = <2>;
 614                 reg-io-width = <4>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&uart2_t1_xfer>;
 617                 status = "disabled";
 618         };
 619
 620         pmu: power-management@ff730000 {
 621                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 622                 reg = <0x0 0xff730000 0x0 0x1000>;
 623
 624                 power: power-controller {
 625                         status = "disabled";
 626                         compatible = "rockchip,rk3366-power-controller";
 627                         #power-domain-cells = <1>;
 628                         #address-cells = <1>;
 629                         #size-cells = <0>;
 630
 631                         /*
 632                          * Note: Although SCLK_* are the working clocks
 633                          * of device without including on the NOC, needed for
 634                          * synchronous reset.
 635                          *
 636                          * The clocks on the which NOC:
 637                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 638                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 639                          * ACLK_ISP is on ACLK_ISP_NIU.
 640                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 641                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 642                          *
 643                          * Which clock are device clocks:
 644                          *      clocks          devices
 645                          *      *_IEP           IEP:Image Enhancement Processor
 646                          *      *_ISP           ISP:Image Signal Processing
 647                          *      *_VOP*          VOP:Visual Output Processor
 648                          *      *_RGA           RGA
 649                          *      *_DPHY*         LVDS
 650                          *      *_HDMI          HDMI
 651                          *      *_MIPI_*        MIPI
 652                          */
 653                         pd_vio {
 654                                 reg = <RK3366_PD_VIO>;
 655                                 clocks = <&cru ACLK_IEP>,
 656                                          <&cru ACLK_ISP>,
 657                                          <&cru ACLK_RGA>,
 658                                          <&cru ACLK_HDCP>,
 659                                          <&cru ACLK_VOP_FULL>,
 660                                          <&cru ACLK_VOP_LITE>,
 661                                          <&cru ACLK_VOP_IEP>,
 662                                          <&cru DCLK_VOP_FULL>,
 663                                          <&cru DCLK_VOP_LITE>,
 664                                          <&cru HCLK_IEP>,
 665                                          <&cru HCLK_ISP>,
 666                                          <&cru HCLK_RGA>,
 667                                          <&cru HCLK_VOP_FULL>,
 668                                          <&cru HCLK_VOP_LITE>,
 669                                          <&cru HCLK_VIO_HDCPMMU>,
 670                                          <&cru PCLK_HDMI_CTRL>,
 671                                          <&cru PCLK_HDCP>,
 672                                          <&cru PCLK_MIPI_DSI0>,
 673                                          <&cru SCLK_VOP_FULL_PWM>,
 674                                          <&cru SCLK_HDCP>,
 675                                          <&cru SCLK_ISP>,
 676                                          <&cru SCLK_RGA>,
 677                                          <&cru SCLK_HDMI_CEC>,
 678                                          <&cru SCLK_HDMI_HDCP>;
 679                         };
 680
 681                         /*
 682                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 683                          * (video endecoder & decoder) clocks that on the
 684                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 685                          */
 686                         pd_vpu {
 687                                 reg = <RK3366_PD_VPU>;
 688                                 clocks = <&cru ACLK_VIDEO>,
 689                                          <&cru HCLK_VIDEO>;
 690                         };
 691
 692                         /*
 693                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 694                          * (video decoder) clocks that on the
 695                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 696                          */
 697                         pd_rkvdec {
 698                                 reg = <RK3366_PD_RKVDEC>;
 699                                 clocks = <&cru ACLK_RKVDEC>,
 700                                          <&cru HCLK_RKVDEC>;
 701                         };
 702
 703                         pd_video {
 704                                 reg = <RK3366_PD_VIDEO>;
 705                                 clocks = <&cru ACLK_VIDEO>,
 706                                          <&cru ACLK_RKVDEC>,
 707                                          <&cru HCLK_VIDEO>,
 708                                          <&cru HCLK_RKVDEC>,
 709                                          <&cru SCLK_HEVC_CABAC>,
 710                                          <&cru SCLK_HEVC_CORE>;
 711                         };
 712
 713                         /*
 714                          * Note: ACLK_GPU is the GPU clock,
 715                          * and on the ACLK_GPU_NIU (NOC).
 716                          */
 717                         pd_gpu {
 718                                 reg = <RK3366_PD_GPU>;
 719                                 clocks = <&cru ACLK_GPU>;
 720                         };
 721                 };
 722         };
 723
 724         pmugrf: syscon@ff738000 {
 725                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 726                 reg = <0x0 0xff738000 0x0 0x1000>;
 727
 728                 reboot-mode {
 729                         compatible = "syscon-reboot-mode";
 730                         offset = <0x200>;
 731                         mode-normal = <BOOT_NORMAL>;
 732                         mode-recovery = <BOOT_RECOVERY>;
 733                         mode-fastboot = <BOOT_FASTBOOT>;
 734                         mode-loader = <BOOT_BL_DOWNLOAD>;
 735                 };
 736
 737                 pmu_pvtm: pmu-pvtm {
 738                         compatible = "rockchip,rk3366-pmu-pvtm";
 739                         clocks = <&cru SCLK_PVTM_PMU>;
 740                         clock-names = "pmu";
 741                         status = "disabled";
 742                 };
 743         };
 744
 745         amba {
 746                 compatible = "arm,amba-bus";
 747                 #address-cells = <2>;
 748                 #size-cells = <2>;
 749                 ranges;
 750
 751                 dmac_peri: dma-controller@ff250000 {
 752                         compatible = "arm,pl330", "arm,primecell";
 753                         reg = <0x0 0xff250000 0x0 0x4000>;
 754                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 755                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 756                         #dma-cells = <1>;
 757                         clocks = <&cru ACLK_DMAC_PERI>;
 758                         clock-names = "apb_pclk";
 759                         peripherals-req-type-burst;
 760                 };
 761
 762                 dmac_bus: dma-controller@ff600000 {
 763                         compatible = "arm,pl330", "arm,primecell";
 764                         reg = <0x0 0xff600000 0x0 0x4000>;
 765                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 766                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 767                         #dma-cells = <1>;
 768                         clocks = <&cru ACLK_DMAC_BUS>;
 769                         clock-names = "apb_pclk";
 770                         peripherals-req-type-burst;
 771                 };
 772         };
 773
 774         cru: clock-controller@ff760000 {
 775                 compatible = "rockchip,rk3366-cru";
 776                 reg = <0x0 0xff760000 0x0 0x1000>;
 777                 rockchip,grf = <&grf>;
 778                 #clock-cells = <1>;
 779                 #reset-cells = <1>;
 780                 assigned-clocks =
 781                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 782                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 783                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 784                         <&cru SCLK_SPDIF_8CH_SRC>,
 785                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 786                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 787                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 788                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 789                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 790                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 791                         <&cru ACLK_PERI1>;
 792                 assigned-clock-rates =
 793                         <0>, <0>,
 794                         <0>, <0>,
 795                         <0>, <0>,
 796                         <0>,
 797                         <750000000>, <576000000>,
 798                         <594000000>, <594000000>,
 799                         <960000000>, <520000000>,
 800                         <375000000>, <288000000>,
 801                         <100000000>, <100000000>,
 802                         <288000000>, <288000000>,
 803                         <144000000>;
 804                 assigned-clock-parents =
 805                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 806                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 807                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 808                         <&cru PLL_GPLL>;
 809         };
 810
 811         grf: syscon@ff770000 {
 812                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 813                 reg = <0x0 0xff770000 0x0 0x1000>;
 814                 #address-cells = <1>;
 815                 #size-cells = <1>;
 816
 817                 u2phy: usb2-phy@700 {
 818                         compatible = "rockchip,rk3366-usb2phy";
 819                         reg = <0x700 0x2c>;
 820                         clocks = <&cru SCLK_OTG_PHY0>;
 821                         clock-names = "phyclk";
 822                         #clock-cells = <0>;
 823                         clock-output-names = "sclk_otgphy0_480m";
 824
 825                         u2phy_host: host-port {
 826                                 #phy-cells = <0>;
 827                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 828                                 interrupt-names = "linestate";
 829                                 status = "okay";
 830                         };
 831                 };
 832
 833                 pvtm: pvtm {
 834                         compatible = "rockchip,rk3366-pvtm";
 835                         clocks = <&cru SCLK_PVTM_CORE>, <&cru SCLK_PVTM_GPU>;
 836                         clock-names = "core", "gpu";
 837                         status = "disabled";
 838                 };
 839         };
 840
 841         wdt: watchdog@ff800000 {
 842                 compatible = "snps,dw-wdt";
 843                 reg = <0x0 0xff800000 0x0 0x100>;
 844                 clocks = <&cru PCLK_WDT>;
 845                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 846                 status = "disabled";
 847         };
 848
 849         spdif: spdif@ff880000 {
 850                 compatible = "rockchip,rk3366-spdif";
 851                 reg = <0x0 0xff880000 0x0 0x1000>;
 852                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 853                 dmas = <&dmac_bus 3>;
 854                 dma-names = "tx";
 855                 clock-names = "mclk", "hclk";
 856                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 857                 pinctrl-names = "default";
 858                 pinctrl-0 = <&spdif_bus>;
 859                 status = "disabled";
 860         };
 861
 862         i2s_2ch: i2s-2ch@ff890000 {
 863                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 864                 reg = <0x0 0xff890000 0x0 0x1000>;
 865                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 866                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 867                 dma-names = "tx", "rx";
 868                 clock-names = "i2s_clk", "i2s_hclk";
 869                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 870                 status = "disabled";
 871         };
 872
 873         i2s_8ch: i2s-8ch@ff898000 {
 874                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 875                 reg = <0x0 0xff898000 0x0 0x1000>;
 876                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 877                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 878                 dma-names = "tx", "rx";
 879                 clock-names = "i2s_clk", "i2s_hclk";
 880                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 881                 pinctrl-names = "default";
 882                 pinctrl-0 = <&i2s_8ch_bus>;
 883                 status = "disabled";
 884         };
 885
 886         fb: fb {
 887                 compatible = "rockchip,rk-fb";
 888                 rockchip,disp-mode = <DUAL>;
 889                 status = "disabled";
 890         };
 891
 892         rk_screen: screen {
 893                 compatible = "rockchip,screen";
 894                 status = "disabled";
 895         };
 896
 897         vop_lite: vop@ff8f0000 {
 898                 compatible = "rockchip,rk3366-lcdc-lite";
 899                 rockchip,grf = <&grf>;
 900                 rockchip,pwr18 = <0>;
 901                 rockchip,iommu-enabled = <1>;
 902                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 903                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 904                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 905                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 906                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 907                 reset-names = "axi", "ahb", "dclk";
 908                 status = "disabled";
 909         };
 910
 911         vopl_mmu: vopl-mmu {
 912                 dbgname = "vop";
 913                 compatible = "rockchip,vopl_mmu";
 914                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 915                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 916                 interrupt-names = "vopl_mmu";
 917                 status = "disabled";
 918         };
 919
 920         iep: iep@ff900000 {
 921                 compatible = "rockchip,iep";
 922                 iommu_enabled = <1>;
 923                 reg = <0x0 0xff900000 0x0 0x800>;
 924                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 925                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 926                 clock-names = "aclk_iep", "hclk_iep";
 927                 version = <2>;
 928                 status = "disabled";
 929         };
 930
 931         rga: rga@ff920000 {
 932                 compatible = "rockchip,rga2";
 933                 dev_mode = <1>;
 934                 reg = <0x0 0xff920000 0x0 0x1000>;
 935                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 936                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 937                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 938                 status = "disabled";
 939         };
 940
 941         vop_big: vop@ff930000 {
 942                 compatible = "rockchip,rk3366-lcdc-big";
 943                 rockchip,grf = <&grf>;
 944                 rockchip,prop = <PRMRY>;
 945                 rockchip,pwr18 = <0>;
 946                 rockchip,iommu-enabled = <1>;
 947                 reg = <0x0 0xff930000 0x0 0x23f0>;
 948                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 949                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 950                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 951                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 952                 reset-names = "axi", "ahb", "dclk";
 953                 status = "disabled";
 954         };
 955
 956         vopb_mmu: vopb-mmu {
 957                 dbgname = "vop";
 958                 compatible = "rockchip,vopb_mmu";
 959                 reg = <0x0 0xff932400 0x0 0x100>;
 960                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 961                 interrupt-names = "vop_mmu";
 962                 status = "disabled";
 963         };
 964
 965         iep_mmu: iep-mmu {
 966                 dbgname = "iep";
 967                 compatible = "rockchip,iep_mmu";
 968                 reg = <0x0 0xff900800 0x0 0x100>;
 969                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 970                 interrupt-names = "iep_mmu";
 971                 status = "disabled";
 972         };
 973
 974         vpu_mmu: vpu_mmu {
 975                 dbgname = "vpu";
 976                 compatible = "rockchip,vpu_mmu";
 977                 reg = <0x0 0xff9a0800 0x0 0x100>;
 978                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 979                 interrupt-names = "vpu_mmu";
 980                 status = "disabled";
 981         };
 982
 983         vdec_mmu: vdec_mmu {
 984                 dbgname = "vdec";
 985                 compatible = "rockchip,vdec_mmu";
 986                 reg = <0x0 0xff9b0480 0x0 0x40>,
 987                       <0x0 0xff9b04c0 0x0 0x40>;
 988                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 989                 interrupt-names = "vdec_mmu";
 990                 status = "disabled";
 991         };
 992
 993         dsihost0: mipi@ff960000 {
 994                 compatible = "rockchip,rk3366-dsi";
 995                 rockchip,prop = <0>;
 996                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 997                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 998                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 999                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
1000                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
1001                 status = "disabled";
1002         };
1003
1004         lvds: lvds@ff968000 {
1005                 compatible = "rockchip,rk3366-lvds";
1006                 rockchip,grf = <&grf>;
1007                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
1008                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
1009                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
1010                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
1011                 status = "disabled";
1012         };
1013
1014         hdmi: hdmi@ff980000 {
1015                 compatible = "rockchip,rk3366-hdmi";
1016                 reg = <0x0 0xff980000 0x0 0x20000>;
1017                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1018                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1019                 clocks = <&cru PCLK_HDMI_CTRL>,
1020                          <&cru SCLK_HDMI_HDCP>,
1021                          <&cru SCLK_HDMI_CEC>,
1022                          <&cru DCLK_HDMIPHY>;
1023                 clock-names = "pclk_hdmi",
1024                               "hdcp_clk_hdmi",
1025                               "cec_clk_hdmi",
1026                               "dclk_hdmi_phy";
1027                 resets = <&cru SRST_HDMI>;
1028                 reset-names = "hdmi";
1029                 pinctrl-names = "default", "gpio";
1030                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
1031                 pinctrl-1 = <&i2c5_gpio>;
1032                 status = "disabled";
1033         };
1034
1035         vpu: vpu_service@ff9a0000 {
1036                 compatible = "rockchip,vpu_service";
1037                 rockchip,grf = <&grf>;
1038                 iommu_enabled = <1>;
1039                 reg = <0x0 0xff9a0000 0x0 0x800>;
1040                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1041                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1042                 interrupt-names = "irq_dec", "irq_enc";
1043                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
1044                 clock-names = "aclk_vcodec", "hclk_vcodec";
1045                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
1046                 reset-names = "video_h", "video_a";
1047                 name = "vpu_service";
1048                 dev_mode = <0>;
1049                 status = "disabled";
1050         };
1051
1052         rkvdec: rkvdec@ff9b0000 {
1053                 compatible = "rockchip,rkvdec";
1054                 rockchip,grf = <&grf>;
1055                 iommu_enabled = <1>;
1056                 reg = <0x0 0xff9b0000 0x0 0x400>;
1057                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1058                 interrupt-names = "irq_dec";
1059                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1060                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1061                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1062                 reset-names = "video_h", "video_a";
1063                 dev_mode = <2>;
1064                 name = "rkvdec";
1065                 status = "disabled";
1066         };
1067
1068         pinctrl: pinctrl {
1069                 compatible = "rockchip,rk3366-pinctrl";
1070                 rockchip,grf = <&grf>;
1071                 rockchip,pmu = <&pmugrf>;
1072                 #address-cells = <0x2>;
1073                 #size-cells = <0x2>;
1074                 ranges;
1075
1076                 gpio0: gpio0@ff750000 {
1077                         compatible = "rockchip,gpio-bank";
1078                         reg = <0x0 0xff750000 0x0 0x100>;
1079                         clocks = <&cru PCLK_GPIO0>;
1080                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1081
1082                         gpio-controller;
1083                         #gpio-cells = <0x2>;
1084
1085                         interrupt-controller;
1086                         #interrupt-cells = <0x2>;
1087                 };
1088
1089                 gpio1: gpio1@ff780000 {
1090                         compatible = "rockchip,gpio-bank";
1091                         reg = <0x0 0xff758000 0x0 0x100>;
1092                         clocks = <&cru PCLK_GPIO1>;
1093                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1094
1095                         gpio-controller;
1096                         #gpio-cells = <0x2>;
1097
1098                         interrupt-controller;
1099                         #interrupt-cells = <0x2>;
1100                 };
1101
1102                 gpio2: gpio2@ff790000 {
1103                         compatible = "rockchip,gpio-bank";
1104                         reg = <0x0 0xff790000 0x0 0x100>;
1105                         clocks = <&cru PCLK_GPIO2>;
1106                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1107
1108                         gpio-controller;
1109                         #gpio-cells = <0x2>;
1110
1111                         interrupt-controller;
1112                         #interrupt-cells = <0x2>;
1113                 };
1114
1115                 gpio3: gpio3@ff7a0000 {
1116                         compatible = "rockchip,gpio-bank";
1117                         reg = <0x0 0xff7a0000 0x0 0x100>;
1118                         clocks = <&cru PCLK_GPIO3>;
1119                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1120
1121                         gpio-controller;
1122                         #gpio-cells = <0x2>;
1123
1124                         interrupt-controller;
1125                         #interrupt-cells = <0x2>;
1126                 };
1127
1128                 gpio4: gpio4@ff7b0000 {
1129                         compatible = "rockchip,gpio-bank";
1130                         reg = <0x0 0xff7b0000 0x0 0x100>;
1131                         clocks = <&cru PCLK_GPIO4>;
1132                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1133
1134                         gpio-controller;
1135                         #gpio-cells = <0x2>;
1136
1137                         interrupt-controller;
1138                         #interrupt-cells = <0x2>;
1139                 };
1140
1141                 gpio5: gpio5@ff7c0000 {
1142                         compatible = "rockchip,gpio-bank";
1143                         reg = <0x0 0xff7c0000 0x0 0x100>;
1144                         clocks = <&cru PCLK_GPIO5>;
1145                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1146
1147                         gpio-controller;
1148                         #gpio-cells = <0x2>;
1149
1150                         interrupt-controller;
1151                         #interrupt-cells = <0x2>;
1152                 };
1153
1154                 pcfg_pull_up: pcfg-pull-up {
1155                         bias-pull-up;
1156                 };
1157
1158                 pcfg_pull_down: pcfg-pull-down {
1159                         bias-pull-down;
1160                 };
1161
1162                 pcfg_pull_none: pcfg-pull-none {
1163                         bias-disable;
1164                 };
1165
1166                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1167                         bias-disable;
1168                         drive-strength = <12>;
1169                 };
1170
1171                 emmc {
1172                         emmc_clk: emmc-clk {
1173                                 rockchip,pins =
1174                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1175                         };
1176
1177                         emmc_cmd: emmc-cmd {
1178                                 rockchip,pins =
1179                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1180                         };
1181
1182                         emmc_pwr: emmc-pwr {
1183                                 rockchip,pins =
1184                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1185                         };
1186
1187                         emmc_bus1: emmc-bus1 {
1188                                 rockchip,pins =
1189                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1190                         };
1191
1192                         emmc_bus4: emmc-bus4 {
1193                                 rockchip,pins =
1194                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1195                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1196                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1197                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1198                         };
1199
1200                         emmc_bus8: emmc-bus8 {
1201                                 rockchip,pins =
1202                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1203                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1204                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1205                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1206                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1207                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1208                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1209                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1210                         };
1211                 };
1212
1213                 sdmmc {
1214                         sdmmc_cd: sdmmc-cd {
1215                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1216                         };
1217
1218                         sdmmc_bus1: sdmmc-bus1 {
1219                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1220                         };
1221
1222                         sdmmc_bus4: sdmmc-bus4 {
1223                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1224                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1225                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1226                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1227                         };
1228
1229                         sdmmc_clk: sdmmc-clk {
1230                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1231                         };
1232
1233                         sdmmc_cmd: sdmmc-cmd {
1234                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1235                         };
1236                 };
1237
1238                 sdio {
1239                         sdio_bus1: sdio-bus1 {
1240                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1241                         };
1242
1243                         sdio_bus4: sdio-bus4 {
1244                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1245                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1246                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1247                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1248                         };
1249
1250                         sdio_cmd: sdio-cmd {
1251                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1252                         };
1253
1254                         sdio_clk: sdio-clk {
1255                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1256                         };
1257
1258                         sdio_cd: sdio-cd {
1259                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1260                         };
1261
1262                         sdio_wp: sdio-wp {
1263                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1264                         };
1265
1266                         sdio_int: sdio-int {
1267                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1268                         };
1269
1270                         sdio_pwr: sdio-pwr {
1271                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1272                         };
1273                 };
1274
1275                 hdmi_i2c {
1276                         hdmii2c_xfer: hdmii2c-xfer {
1277                                 rockchip,pins =
1278                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1279                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1280                         };
1281                 };
1282
1283                 hdmi_pin {
1284                         hdmi_cec: hdmi-cec {
1285                                 rockchip,pins =
1286                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1287                         };
1288                 };
1289
1290                 i2c0 {
1291                         i2c0_xfer: i2c0-xfer {
1292                                 rockchip,pins =
1293                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1294                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 i2c1 {
1299                         i2c1_xfer: i2c1-xfer {
1300                                 rockchip,pins =
1301                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1302                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 i2c2 {
1307                         i2c2_xfer: i2c2-xfer {
1308                                 rockchip,pins =
1309                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1310                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1311                         };
1312
1313                         i2c2_gpio: i2c2-gpio {
1314                                 rockchip,pins =
1315                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1316                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1317                         };
1318                 };
1319
1320                 i2c3 {
1321                         i2c3_xfer: i2c3-xfer {
1322                                 rockchip,pins =
1323                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1324                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1325                         };
1326                 };
1327
1328                 i2c4 {
1329                         i2c4_xfer: i2c4-xfer {
1330                                 rockchip,pins =
1331                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1332                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1333                         };
1334
1335                         i2c4_gpio: i2c4-gpio {
1336                                 rockchip,pins =
1337                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1338                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1339                         };
1340                 };
1341
1342                 i2c5 {
1343                         i2c5_xfer: i2c5-xfer {
1344                                 rockchip,pins =
1345                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1346                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1347                         };
1348                         i2c5_gpio: i2c5-gpio {
1349                                 rockchip,pins =
1350                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1351                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1352                         };
1353                 };
1354
1355                 i2s {
1356                         i2s_8ch_bus: i2s-8ch-bus {
1357                                 rockchip,pins =
1358                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1359                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1360                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1361                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1362                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1363                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1364                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1365                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1366                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1367                         };
1368                 };
1369
1370                 spdif {
1371                         spdif_bus: spdif-bus {
1372                                 rockchip,pins =
1373                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1374                         };
1375                 };
1376
1377                 spi0 {
1378                         spi0_clk: spi0-clk {
1379                                 rockchip,pins =
1380                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1381                         };
1382                         spi0_cs0: spi0-cs0 {
1383                                 rockchip,pins =
1384                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1385                         };
1386                         spi0_cs1: spi0-cs1 {
1387                                 rockchip,pins =
1388                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1389                         };
1390                         spi0_tx: spi0-tx {
1391                                 rockchip,pins =
1392                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1393                         };
1394                         spi0_rx: spi0-rx {
1395                                 rockchip,pins =
1396                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1397                         };
1398                 };
1399
1400                 spi1 {
1401                         spi1_clk: spi1-clk {
1402                                 rockchip,pins =
1403                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1404                         };
1405                         spi1_cs0: spi1-cs0 {
1406                                 rockchip,pins =
1407                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1408                         };
1409                         spi1_tx: spi1-tx {
1410                                 rockchip,pins =
1411                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1412                         };
1413                         spi1_rx: spi1-rx {
1414                                 rockchip,pins =
1415                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1416                         };
1417                 };
1418
1419                 scr {
1420                         scr_clk: scr-clk {
1421                                 rockchip,pins =
1422                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1423                         };
1424
1425                         scr_io: scr-io {
1426                                 rockchip,pins =
1427                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1428                         };
1429
1430                         scr_rst: scr-rst {
1431                                 rockchip,pins =
1432                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1433                         };
1434
1435                         scr_detect: scr-detect {
1436                                 rockchip,pins =
1437                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1438                         };
1439                 };
1440
1441                 uart0 {
1442                         uart0_xfer: uart0-xfer {
1443                                 rockchip,pins =
1444                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1445                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1446                         };
1447
1448                         uart0_cts: uart0-cts {
1449                                 rockchip,pins =
1450                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1451                         };
1452
1453                         uart0_rts: uart0-rts {
1454                                 rockchip,pins =
1455                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1456                         };
1457                 };
1458
1459                 uart2_t0 {
1460                         uart2_t0_xfer: uart2_t0-xfer {
1461                                 rockchip,pins =
1462                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1463                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1464                         };
1465                         /* no rts / cts for uart2 */
1466                 };
1467
1468                 uart2_t1 {
1469                         uart2_t1_xfer: uart2_t1-xfer {
1470                                 rockchip,pins =
1471                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1472                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1473                         };
1474                         /* no rts / cts for uart2 */
1475                 };
1476
1477                 uart2_t2 {
1478                         uart2_t2_xfer: uart2_t2-xfer {
1479                                 rockchip,pins =
1480                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1481                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1482                         };
1483                         /* no rts / cts for uart2 */
1484                 };
1485
1486                 uart3 {
1487                         uart3_xfer: uart3-xfer {
1488                                 rockchip,pins =
1489                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1490                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1491                         };
1492
1493                         uart3_cts: uart3-cts {
1494                                 rockchip,pins =
1495                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1496                         };
1497
1498                         uart3_rts: uart3-rts {
1499                                 rockchip,pins =
1500                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1501                         };
1502                 };
1503
1504                 pwm0 {
1505                         pwm0_pin: pwm0-pin {
1506                                 rockchip,pins =
1507                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1508                         };
1509                 };
1510
1511                 pwm1 {
1512                         pwm1_pin: pwm1-pin {
1513                                 rockchip,pins =
1514                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1515                         };
1516                 };
1517
1518                 pwm2_t0 {
1519                         pwm2_t0_pin: pwm2_t0-pin {
1520                                 rockchip,pins =
1521                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1522                         };
1523                 };
1524
1525                 pwm2_t1 {
1526                         pwm2_t1_pin: pwm2_t1-pin {
1527                                 rockchip,pins =
1528                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 pwm3_t0 {
1533                         pwm3_t0_pin: pwm3_t0-pin {
1534                                 rockchip,pins =
1535                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1536                         };
1537                 };
1538
1539                 pwm3_t1 {
1540                         pwm3_t1_pin: pwm3_t1-pin {
1541                                 rockchip,pins =
1542                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1543                         };
1544                 };
1545
1546                 pwm3_t2 {
1547                         pwm3_t2_pin: pwm3_t2-pin {
1548                                 rockchip,pins =
1549                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1550                         };
1551                 };
1552
1553                 lcdc {
1554                         lcdc_lcdc: lcdc-lcdc {
1555                                 rockchip,pins =
1556                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1557                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1558                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1559                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1560                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1561                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1562                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1563                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1564                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1565                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1566                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1567                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1568                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1569                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1570                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1571                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1572                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1573                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1574                         };
1575
1576                         lcdc_gpio: lcdc-gpio {
1577                                 rockchip,pins =
1578                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1579                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1580                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1581                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1582                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1583                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1584                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1585                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1586                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1587                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1588                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1589                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1590                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1591                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1592                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1593                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1594                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1595                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1596                         };
1597                 };
1598
1599                 gmac {
1600                         rgmii_pins: rgmii-pins {
1601                                 rockchip,pins =
1602                                         /* mac_rxd3 */
1603                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1604                                         /* mac_rxd2 */
1605                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1606                                         /* mac_txd3 */
1607                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1608                                         /* mac_txd2 */
1609                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1610                                         /* mac_rxd1 */
1611                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1612                                         /* mac_rxd0 */
1613                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1614                                         /* mac_txd1 */
1615                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1616                                         /* mac_txd0 */
1617                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1618                                         /* mac_txclkout */
1619                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1620                                         /* mac_crs */
1621                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1622                                         /* mac_rxclkin */
1623                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1624                                         /* mac_mdio */
1625                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1626                                         /* mac_txen */
1627                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1628                                         /* mac_clk */
1629                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1630                                         /* mac_rxer */
1631                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1632                                         /* mac_rxdv */
1633                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1634                                         /* mac_mdc */
1635                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1636                         };
1637
1638                         rmii_pins: rmii-pins {
1639                                 rockchip,pins =
1640                                         /* mac_rxd1 */
1641                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1642                                         /* mac_rxd0 */
1643                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1644                                         /* mac_txd1 */
1645                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1646                                         /* mac_txd0 */
1647                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1648                                         /* mac_crs */
1649                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1650                                         /* mac_rxclkin */
1651                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1652                                         /* mac_mdio */
1653                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1654                                         /* mac_txen */
1655                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1656                                         /* mac_clk */
1657                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1658                                         /* mac_rxer */
1659                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1660                                         /* mac_rxdv */
1661                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1662                                         /* mac_mdc */
1663                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1664                         };
1665                 };
1666
1667                 eth_phy {
1668                         eth_phy_pwr: eth-phy-pwr {
1669                                 rockchip,pins =
1670                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1671                         };
1672                 };
1673
1674                 tsadc_pin {
1675                         tsadc_gpio: tsadc-gpio {
1676                                 rockchip,pins =
1677                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1678                         };
1679
1680                         tsadc_int: tsadc-int {
1681                                 rockchip,pins =
1682                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 usb2 {
1687                         host_vbus_drv: host-vbus-drv {
1688                                 rockchip,pins =
1689                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1690                         };
1691                 };
1692
1693         };
1694
1695         gpu: gpu@ffa30000 {
1696                 compatible = "arm,malit764",
1697                              "arm,malit76x",
1698                              "arm,malit7xx",
1699                              "arm,mali-midgard";
1700
1701                 reg = <0x0 0xffa30000 0 0x10000>;
1702
1703                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1704                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1705                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1706                 interrupt-names = "GPU", "MMU", "JOB";
1707
1708                 clocks = <&cru ACLK_GPU>;
1709                 clock-names = "clk_mali";
1710                 #cooling-cells = <2>; /* min followed by max */
1711                 operating-points-v2 = <&gpu_opp_table>;
1712                 status = "disabled";
1713
1714                 power_model {
1715                         compatible = "arm,mali-simple-power-model";
1716                         voltage = <900>;
1717                         frequency = <500>;
1718                         static-power = <300>;
1719                         dynamic-power = <1780>;
1720                         ts = <32000 4700 (-80) 2>;
1721                         thermal-zone = "gpu-thermal";
1722                 };
1723         };
1724
1725         gpu_opp_table: gpu_opp_table {
1726                 compatible = "operating-points-v2";
1727                 opp-shared;
1728
1729                 opp@96000000 {
1730                         opp-hz = /bits/ 64 <96000000>;
1731                         opp-microvolt = <1100000>;
1732                 };
1733                 opp@192000000 {
1734                         opp-hz = /bits/ 64 <192000000>;
1735                         opp-microvolt = <1100000>;
1736                 };
1737                 opp@288000000 {
1738                         opp-hz = /bits/ 64 <288000000>;
1739                         opp-microvolt = <1100000>;
1740                 };
1741                 opp@375000000 {
1742                         opp-hz = /bits/ 64 <375000000>;
1743                         opp-microvolt = <1125000>;
1744                 };
1745                 opp@480000000 {
1746                         opp-hz = /bits/ 64 <480000000>;
1747                         opp-microvolt = <1200000>;
1748                 };
1749         };
1750 };