a8cfeed37d804a7b9841ee5afcd270b518ff4012
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3366.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
51
52 / {
53         compatible = "rockchip,rk3366";
54         interrupt-parent = <&gic>;
55         #address-cells = <2>;
56         #size-cells = <2>;
57
58         aliases {
59                 i2c0 = &i2c0;
60                 i2c1 = &i2c1;
61                 i2c2 = &i2c2;
62                 i2c3 = &i2c3;
63                 i2c4 = &i2c4;
64                 i2c5 = &i2c5;
65                 serial0 = &uart0;
66                 serial2 = &uart2;
67                 serial3 = &uart3;
68                 spi0 = &spi0;
69                 spi1 = &spi1;
70         };
71
72         cpus {
73                 #address-cells = <0x2>;
74                 #size-cells = <0x0>;
75
76                 cpu0: cpu@0 {
77                         device_type = "cpu";
78                         compatible = "arm,cortex-a53","arm,armv8";
79                         reg = <0x0 0x0>;
80                         enable-method = "psci";
81                         clocks = <&cru ARMCLK>;
82                         operating-points-v2 = <&cpu0_opp_table>;
83                 };
84
85                 cpu1: cpu@1 {
86                         device_type = "cpu";
87                         compatible = "arm,cortex-a53","arm,armv8";
88                         reg = <0x0 0x1>;
89                         enable-method = "psci";
90                         operating-points-v2 = <&cpu0_opp_table>;
91                 };
92
93                 cpu2: cpu@2 {
94                         device_type = "cpu";
95                         compatible = "arm,cortex-a53","arm,armv8";
96                         reg = <0x0 0x2>;
97                         enable-method = "psci";
98                         operating-points-v2 = <&cpu0_opp_table>;
99                 };
100
101                 cpu3: cpu@3 {
102                         device_type = "cpu";
103                         compatible = "arm,cortex-a53","arm,armv8";
104                         reg = <0x0 0x3>;
105                         enable-method = "psci";
106                         operating-points-v2 = <&cpu0_opp_table>;
107                 };
108         };
109
110         cpu0_opp_table: opp_table0 {
111                 compatible = "operating-points-v2";
112                 opp-shared;
113
114                 opp00 {
115                         opp-hz = /bits/ 64 <408000000>;
116                         opp-microvolt = <1200000>;
117                         clock-latency-ns = <40000>;
118                         opp-suspend;
119                 };
120                 opp01 {
121                         opp-hz = /bits/ 64 <600000000>;
122                         opp-microvolt = <1200000>;
123                 };
124                 opp02 {
125                         opp-hz = /bits/ 64 <816000000>;
126                         opp-microvolt = <1200000>;
127                 };
128                 opp03 {
129                         opp-hz = /bits/ 64 <1008000000>;
130                         opp-microvolt = <1200000>;
131                 };
132                 opp04 {
133                         opp-hz = /bits/ 64 <1200000000>;
134                         opp-microvolt = <1200000>;
135                 };
136         };
137
138         psci {
139                 compatible = "arm,psci-1.0";
140                 method = "smc";
141         };
142
143         timer {
144                 compatible = "arm,armv8-timer";
145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149         };
150
151         xin24m: xin24m {
152                 compatible = "fixed-clock";
153                 #clock-cells = <0>;
154                 clock-frequency = <24000000>;
155                 clock-output-names = "xin24m";
156         };
157
158         gic: interrupt-controller@ffb71000 {
159                 compatible = "arm,gic-400";
160                 interrupt-controller;
161                 #interrupt-cells = <3>;
162                 #address-cells = <0>;
163
164                 reg = <0x0 0xffb71000 0x0 0x1000>,
165                       <0x0 0xffb72000 0x0 0x1000>,
166                       <0x0 0xffb74000 0x0 0x2000>,
167                       <0x0 0xffb76000 0x0 0x2000>;
168                 interrupts = <GIC_PPI 9
169                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
170         };
171
172         nandc0: nandc@ff0c0000 {
173                 compatible = "rockchip,rk-nandc";
174                 reg = <0x0 0xff0c0000 0x0 0x4000>;
175                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
176                 nandc_id = <0>;
177                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
178                 clock-names = "clk_nandc", "hclk_nandc";
179                 status = "disabled";
180         };
181
182         saradc: saradc@ff100000 {
183                 compatible = "rockchip,saradc";
184                 reg = <0x0 0xff100000 0x0 0x100>;
185                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
186                 #io-channel-cells = <1>;
187                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
188                 clock-names = "saradc", "apb_pclk";
189                 status = "disabled";
190         };
191
192         spi0: spi@ff110000 {
193                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
194                 reg = <0x0 0xff110000 0x0 0x1000>;
195                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
196                 clock-names = "spiclk", "apb_pclk";
197                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198                 pinctrl-names = "default";
199                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
200                 #address-cells = <1>;
201                 #size-cells = <0>;
202                 status = "disabled";
203         };
204
205         spi1: spi@ff120000 {
206                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
207                 reg = <0x0 0xff120000 0x0 0x1000>;
208                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
209                 clock-names = "spiclk", "apb_pclk";
210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
211                 pinctrl-names = "default";
212                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
213                 #address-cells = <1>;
214                 #size-cells = <0>;
215                 status = "disabled";
216         };
217
218         sdmmc: rksdmmc@ff400000 {
219                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
220                 clock-freq-min-max = <400000 150000000>;
221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224                 fifo-depth = <0x100>;
225                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
226                 reg = <0x0 0xff400000 0x0 0x4000>;
227                 status = "disabled";
228         };
229
230         sdio: rksdmmc@ff410000 {
231                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
232                 clock-freq-min-max = <400000 150000000>;
233                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
234                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236                 fifo-depth = <0x100>;
237                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
238                 reg = <0x0 0xff410000 0x0 0x4000>;
239                 status = "disabled";
240         };
241
242         emmc: rksdmmc@ff420000 {
243                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
244                 clock-freq-min-max = <400000 150000000>;
245                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248                 fifo-depth = <0x100>;
249                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
250                 reg = <0x0 0xff420000 0x0 0x4000>;
251                 status = "disabled";
252         };
253
254         gmac: eth@ff440000 {
255                 compatible = "rockchip,rk3366-gmac";
256                 reg = <0x0 0xff440000 0x0 0x10000>;
257                 rockchip,grf = <&grf>;
258                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
259                 interrupt-names = "macirq";
260                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
261                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
262                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
263                          <&cru PCLK_GMAC>;
264                 clock-names = "stmmaceth", "mac_clk_rx",
265                               "mac_clk_tx", "clk_mac_ref",
266                               "clk_mac_refout", "aclk_mac",
267                               "pclk_mac";
268                 resets = <&cru SRST_MAC>;
269                 reset-names = "stmmaceth";
270                 status = "disabled";
271         };
272
273         i2c0: i2c@ff650000 {
274                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
275                 reg = <0x0 0xff728000 0x0 0x1000>;
276                 clocks = <&cru PCLK_I2C0>;
277                 clock-names = "i2c";
278                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
279                 pinctrl-names = "default";
280                 pinctrl-0 = <&i2c0_xfer>;
281                 #address-cells = <1>;
282                 #size-cells = <0>;
283                 status = "disabled";
284         };
285
286         i2c2: i2c@ff140000 {
287                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
288                 reg = <0x0 0xff140000 0x0 0x1000>;
289                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
290                 #address-cells = <1>;
291                 #size-cells = <0>;
292                 clock-names = "i2c";
293                 clocks = <&cru PCLK_I2C2>;
294                 pinctrl-names = "default";
295                 pinctrl-0 = <&i2c2_xfer>;
296                 status = "disabled";
297         };
298
299         i2c3: i2c@ff150000 {
300                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
301                 reg = <0x0 0xff150000 0x0 0x1000>;
302                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
303                 #address-cells = <1>;
304                 #size-cells = <0>;
305                 clock-names = "i2c";
306                 clocks = <&cru PCLK_I2C3>;
307                 pinctrl-names = "default";
308                 pinctrl-0 = <&i2c3_xfer>;
309                 status = "disabled";
310         };
311
312         i2c4: i2c@ff160000 {
313                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
314                 reg = <0x0 0xff160000 0x0 0x1000>;
315                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
316                 #address-cells = <1>;
317                 #size-cells = <0>;
318                 clock-names = "i2c";
319                 clocks = <&cru PCLK_I2C4>;
320                 pinctrl-names = "default";
321                 pinctrl-0 = <&i2c4_xfer>;
322                 status = "disabled";
323         };
324
325         i2c5: i2c@ff170000 {
326                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
327                 reg = <0x0 0xff170000 0x0 0x1000>;
328                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
329                 #address-cells = <1>;
330                 #size-cells = <0>;
331                 clock-names = "i2c";
332                 clocks = <&cru PCLK_I2C5>;
333                 pinctrl-names = "default";
334                 pinctrl-0 = <&i2c5_xfer>;
335                 status = "disabled";
336         };
337
338         uart0: serial@ff180000 {
339                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
340                 reg = <0x0 0xff180000 0x0 0x100>;
341                 clock-frequency = <24000000>;
342                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
343                 clock-names = "baudclk", "apb_pclk";
344                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
345                 reg-shift = <2>;
346                 reg-io-width = <4>;
347                 pinctrl-names = "default";
348                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
349                 status = "disabled";
350         };
351
352         uart3: serial@ff1b0000 {
353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354                 reg = <0x0 0xff1b0000 0x0 0x100>;
355                 clock-frequency = <24000000>;
356                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
357                 clock-names = "baudclk", "apb_pclk";
358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
359                 reg-shift = <2>;
360                 reg-io-width = <4>;
361                 pinctrl-names = "default";
362                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
363                 status = "disabled";
364         };
365
366         usb_host0_echi: usb@ff480000 {
367                 compatible = "generic-ehci";
368                 reg = <0x0 0xff480000 0x0 0x20000>;
369                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
370                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
371                 clock-names = "sclk_otgphy0", "hclk_host0";
372                 status = "disabled";
373         };
374
375         usb_host0_ohci: usb@ff4a0000 {
376                 compatible = "generic-ohci";
377                 reg = <0x0 0xff4a0000 0x0 0x20000>;
378                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
379                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
380                 clock-names = "sclk_otgphy0", "hclk_host0";
381                 status = "disabled";
382         };
383
384         usb_otg: usb@ff4c0000 {
385                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
386                              "snps,dwc2";
387                 reg = <0x0 0xff4c0000 0x0 0x40000>;
388                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
389                 clocks = <&cru HCLK_OTG>;
390                 clock-names = "otg";
391                 dr_mode = "otg";
392                 g-np-tx-fifo-size = <16>;
393                 g-rx-fifo-size = <275>;
394                 g-tx-fifo-size = <256 128 128 64 64 32>;
395                 g-use-dma;
396                 status = "disabled";
397         };
398
399         i2c1: i2c@ff660000 {
400                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
401                 reg = <0x0 0xff660000 0x0 0x1000>;
402                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
403                 #address-cells = <1>;
404                 #size-cells = <0>;
405                 clock-names = "i2c";
406                 clocks = <&cru PCLK_I2C1>;
407                 pinctrl-names = "default";
408                 pinctrl-0 = <&i2c1_xfer>;
409                 status = "disabled";
410         };
411
412         pwm0: pwm@ff680000 {
413                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
414                 reg = <0x0 0xff680000 0x0 0x10>;
415                 #pwm-cells = <3>;
416                 pinctrl-names = "default";
417                 pinctrl-0 = <&pwm0_pin>;
418                 clocks = <&cru PCLK_RKPWM>;
419                 clock-names = "pwm";
420                 status = "disabled";
421         };
422
423         pwm1: pwm@ff680010 {
424                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
425                 reg = <0x0 0xff680010 0x0 0x10>;
426                 #pwm-cells = <3>;
427                 pinctrl-names = "default";
428                 pinctrl-0 = <&pwm1_pin>;
429                 clocks = <&cru PCLK_RKPWM>;
430                 clock-names = "pwm";
431                 status = "disabled";
432         };
433
434         pwm2: pwm@ff680020 {
435                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
436                 reg = <0x0 0xff680020 0x0 0x10>;
437                 #pwm-cells = <3>;
438                 clocks = <&cru PCLK_RKPWM>;
439                 clock-names = "pwm";
440                 status = "disabled";
441         };
442
443         pwm3: pwm@ff680030 {
444                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
445                 reg = <0x0 0xff680030 0x0 0x10>;
446                 #pwm-cells = <3>;
447                 pinctrl-names = "default";
448                 pinctrl-0 = <&pwm3_t2_pin>;
449                 clocks = <&cru PCLK_RKPWM>;
450                 clock-names = "pwm";
451                 status = "disabled";
452         };
453
454         uart2: serial@ff690000 {
455                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
456                 reg = <0x0 0xff690000 0x0 0x100>;
457                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
458                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
459                 clock-names = "baudclk", "apb_pclk";
460                 reg-shift = <2>;
461                 reg-io-width = <4>;
462                 pinctrl-names = "default";
463                 pinctrl-0 = <&uart2_t1_xfer>;
464                 status = "disabled";
465         };
466
467         pmu: power-management@ff730000 {
468                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
469                 reg = <0x0 0xff730000 0x0 0x1000>;
470
471                 power: power-controller {
472                         status = "disabled";
473                         compatible = "rockchip,rk3366-power-controller";
474                         #power-domain-cells = <1>;
475                         #address-cells = <1>;
476                         #size-cells = <0>;
477
478                         /*
479                          * Note: Although SCLK_* are the working clocks
480                          * of device without including on the NOC, needed for
481                          * synchronous reset.
482                          *
483                          * The clocks on the which NOC:
484                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
485                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
486                          * ACLK_ISP is on ACLK_ISP_NIU.
487                          * ACLK_HDCP is on ACLK_HDCP_NIU.
488                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
489                          *
490                          * Which clock are device clocks:
491                          *      clocks          devices
492                          *      *_IEP           IEP:Image Enhancement Processor
493                          *      *_ISP           ISP:Image Signal Processing
494                          *      *_VOP*          VOP:Visual Output Processor
495                          *      *_RGA           RGA
496                          *      *_DPHY*         LVDS
497                          *      *_HDMI          HDMI
498                          *      *_MIPI_*        MIPI
499                          */
500                         pd_vio {
501                                 reg = <RK3366_PD_VIO>;
502                                 clocks = <&cru ACLK_IEP>,
503                                          <&cru ACLK_ISP>,
504                                          <&cru ACLK_RGA>,
505                                          <&cru ACLK_HDCP>,
506                                          <&cru ACLK_VOP_FULL>,
507                                          <&cru ACLK_VOP_LITE>,
508                                          <&cru ACLK_VOP_IEP>,
509                                          <&cru DCLK_VOP_FULL>,
510                                          <&cru DCLK_VOP_LITE>,
511                                          <&cru HCLK_IEP>,
512                                          <&cru HCLK_ISP>,
513                                          <&cru HCLK_RGA>,
514                                          <&cru HCLK_VOP_FULL>,
515                                          <&cru HCLK_VOP_LITE>,
516                                          <&cru HCLK_VIO_HDCPMMU>,
517                                          <&cru PCLK_HDMI_CTRL>,
518                                          <&cru PCLK_HDCP>,
519                                          <&cru PCLK_MIPI_DSI0>,
520                                          <&cru SCLK_VOP_FULL_PWM>,
521                                          <&cru SCLK_HDCP>,
522                                          <&cru SCLK_ISP>,
523                                          <&cru SCLK_RGA>,
524                                          <&cru SCLK_HDMI_CEC>,
525                                          <&cru SCLK_HDMI_HDCP>;
526                         };
527
528                         /*
529                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
530                          * (video endecoder & decoder) clocks that on the
531                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
532                          */
533                         pd_vpu {
534                                 reg = <RK3366_PD_VPU>;
535                                 clocks = <&cru ACLK_VIDEO>,
536                                          <&cru HCLK_VIDEO>;
537                         };
538
539                         /*
540                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
541                          * (video decoder) clocks that on the
542                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
543                          */
544                         pd_rkvdec {
545                                 reg = <RK3366_PD_RKVDEC>;
546                                 clocks = <&cru ACLK_RKVDEC>,
547                                          <&cru HCLK_RKVDEC>;
548                         };
549
550                         pd_video {
551                                 reg = <RK3366_PD_VIDEO>;
552                                 clocks = <&cru ACLK_VIDEO>,
553                                          <&cru ACLK_RKVDEC>,
554                                          <&cru HCLK_VIDEO>,
555                                          <&cru HCLK_RKVDEC>,
556                                          <&cru SCLK_HEVC_CABAC>,
557                                          <&cru SCLK_HEVC_CORE>;
558                         };
559
560                         /*
561                          * Note: ACLK_GPU is the GPU clock,
562                          * and on the ACLK_GPU_NIU (NOC).
563                          */
564                         pd_gpu {
565                                 reg = <RK3366_PD_GPU>;
566                                 clocks = <&cru ACLK_GPU>;
567                         };
568                 };
569         };
570
571         pmugrf: syscon@ff738000 {
572                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
573                 reg = <0x0 0xff738000 0x0 0x1000>;
574
575                 reboot-mode {
576                         compatible = "syscon-reboot-mode";
577                         offset = <0x200>;
578                         mode-normal = <BOOT_NORMAL>;
579                         mode-recovery = <BOOT_RECOVERY>;
580                         mode-fastboot = <BOOT_FASTBOOT>;
581                         mode-loader = <BOOT_LOADER>;
582                 };
583         };
584
585         amba {
586                 compatible = "arm,amba-bus";
587                 #address-cells = <2>;
588                 #size-cells = <2>;
589                 ranges;
590
591                 dmac_peri: dma-controller@ff250000 {
592                         compatible = "arm,pl330", "arm,primecell";
593                         reg = <0x0 0xff250000 0x0 0x4000>;
594                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
595                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
596                         #dma-cells = <1>;
597                         clocks = <&cru ACLK_DMAC_PERI>;
598                         clock-names = "apb_pclk";
599                 };
600
601                 dmac_bus: dma-controller@ff600000 {
602                         compatible = "arm,pl330", "arm,primecell";
603                         reg = <0x0 0xff600000 0x0 0x4000>;
604                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
605                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
606                         #dma-cells = <1>;
607                         clocks = <&cru ACLK_DMAC_BUS>;
608                         clock-names = "apb_pclk";
609                 };
610         };
611
612         cru: clock-controller@ff760000 {
613                 compatible = "rockchip,rk3366-cru";
614                 reg = <0x0 0xff760000 0x0 0x1000>;
615                 rockchip,grf = <&grf>;
616                 #clock-cells = <1>;
617                 #reset-cells = <1>;
618                 assigned-clocks =
619                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
620                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
621                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
622                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
623                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
624                 assigned-clock-rates =
625                         <750000000>, <576000000>,
626                         <594000000>, <594000000>,
627                         <480000000>, <520000000>,
628                         <375000000>, <288000000>,
629                         <100000000>, <100000000>;
630         };
631
632         grf: syscon@ff770000 {
633                 compatible = "rockchip,rk3366-grf", "syscon";
634                 reg = <0x0 0xff770000 0x0 0x1000>;
635         };
636
637         spdif: spdif@ff880000 {
638                 compatible = "rockchip,rk3366-spdif";
639                 reg = <0x0 0xff880000 0x0 0x1000>;
640                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
641                 dmas = <&dmac_bus 3>;
642                 dma-names = "tx";
643                 clock-names = "hclk", "mclk";
644                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
645                 pinctrl-names = "default";
646                 pinctrl-0 = <&spdif_bus>;
647                 status = "disabled";
648         };
649
650         i2s_2ch: i2s-2ch@ff890000 {
651                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
652                 reg = <0x0 0xff890000 0x0 0x1000>;
653                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
654                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
655                 dma-names = "tx", "rx";
656                 clock-names = "i2s_hclk", "i2s_clk";
657                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
658                 status = "disabled";
659         };
660
661         i2s_8ch: i2s-8ch@ff898000 {
662                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
663                 reg = <0x0 0xff898000 0x0 0x1000>;
664                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
665                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
666                 dma-names = "tx", "rx";
667                 clock-names = "i2s_hclk", "i2s_clk";
668                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
669                 pinctrl-names = "default";
670                 pinctrl-0 = <&i2s_8ch_bus>;
671                 status = "disabled";
672         };
673
674         fb: fb {
675                 compatible = "rockchip,rk-fb";
676                 rockchip,disp-mode = <DUAL>;
677                 status = "disabled";
678         };
679
680         rk_screen: screen {
681                 compatible = "rockchip,screen";
682                 status = "disabled";
683         };
684
685         vop_lite: vop@ff8f0000 {
686                 compatible = "rockchip,rk3366-lcdc-lite";
687                 rockchip,grf = <&grf>;
688                 rockchip,pwr18 = <0>;
689                 rockchip,iommu-enabled = <1>;
690                 reg = <0x0 0xff8f0000 0x0 0x1000>;
691                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
692                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
693                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
694                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
695                 reset-names = "axi", "ahb", "dclk";
696                 status = "disabled";
697         };
698
699         vopl_mmu: vopl-mmu {
700                 dbgname = "vop";
701                 compatible = "rockchip,vopl_mmu";
702                 reg = <0x0 0xff8f0f00 0x0 0x100>;
703                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
704                 interrupt-names = "vopl_mmu";
705                 status = "disabled";
706         };
707
708         rga: rga@ff920000 {
709                 compatible = "rockchip,rga2";
710                 dev_mode = <1>;
711                 reg = <0x0 0xff920000 0x0 0x1000>;
712                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
713                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
714                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
715                 status = "disabled";
716         };
717
718         vop_big: vop@ff930000 {
719                 compatible = "rockchip,rk3366-lcdc-big";
720                 rockchip,grf = <&grf>;
721                 rockchip,prop = <PRMRY>;
722                 rockchip,pwr18 = <0>;
723                 rockchip,iommu-enabled = <1>;
724                 reg = <0x0 0xff930000 0x0 0x23f0>;
725                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
726                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
727                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
728                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
729                 reset-names = "axi", "ahb", "dclk";
730                 status = "disabled";
731         };
732
733         vopb_mmu: vopb-mmu {
734                 dbgname = "vop";
735                 compatible = "rockchip,vopb_mmu";
736                 reg = <0x0 0xff932400 0x0 0x100>;
737                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
738                 interrupt-names = "vop_mmu";
739                 status = "disabled";
740         };
741
742         dsihost0: mipi@ff960000 {
743                 compatible = "rockchip,rk3368-dsi";
744                 rockchip,prop = <0>;
745                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
746                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
747                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
748                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
749                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
750                 status = "disabled";
751         };
752
753         lvds: lvds@ff968000 {
754                 compatible = "rockchip,rk3366-lvds";
755                 rockchip,grf = <&grf>;
756                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
757                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
758                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
759                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
760                 status = "disabled";
761         };
762
763         hdmi: hdmi@ff980000 {
764                 compatible = "rockchip,rk3366-hdmi";
765                 reg = <0x0 0xff980000 0x0 0x20000>;
766                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
767                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
768                 clocks = <&cru PCLK_HDMI_CTRL>,
769                          <&cru SCLK_HDMI_HDCP>,
770                          <&cru SCLK_HDMI_CEC>,
771                          <&cru DCLK_HDMIPHY>;
772                 clock-names = "pclk_hdmi",
773                               "hdcp_clk_hdmi",
774                               "cec_clk_hdmi",
775                               "dclk_hdmi_phy";
776                 resets = <&cru SRST_HDMI>;
777                 reset-names = "hdmi";
778                 pinctrl-names = "default", "gpio";
779                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
780                 pinctrl-1 = <&i2c5_gpio>;
781                 status = "disabled";
782         };
783
784         pinctrl: pinctrl {
785                 compatible = "rockchip,rk3366-pinctrl";
786                 rockchip,grf = <&grf>;
787                 rockchip,pmu = <&pmugrf>;
788                 #address-cells = <0x2>;
789                 #size-cells = <0x2>;
790                 ranges;
791
792                 gpio0: gpio0@ff750000 {
793                         compatible = "rockchip,gpio-bank";
794                         reg = <0x0 0xff750000 0x0 0x100>;
795                         clocks = <&cru PCLK_GPIO0>;
796                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
797
798                         gpio-controller;
799                         #gpio-cells = <0x2>;
800
801                         interrupt-controller;
802                         #interrupt-cells = <0x2>;
803                 };
804
805                 gpio1: gpio1@ff780000 {
806                         compatible = "rockchip,gpio-bank";
807                         reg = <0x0 0xff758000 0x0 0x100>;
808                         clocks = <&cru PCLK_GPIO1>;
809                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
810
811                         gpio-controller;
812                         #gpio-cells = <0x2>;
813
814                         interrupt-controller;
815                         #interrupt-cells = <0x2>;
816                 };
817
818                 gpio2: gpio2@ff790000 {
819                         compatible = "rockchip,gpio-bank";
820                         reg = <0x0 0xff790000 0x0 0x100>;
821                         clocks = <&cru PCLK_GPIO2>;
822                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
823
824                         gpio-controller;
825                         #gpio-cells = <0x2>;
826
827                         interrupt-controller;
828                         #interrupt-cells = <0x2>;
829                 };
830
831                 gpio3: gpio3@ff7a0000 {
832                         compatible = "rockchip,gpio-bank";
833                         reg = <0x0 0xff7a0000 0x0 0x100>;
834                         clocks = <&cru PCLK_GPIO3>;
835                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
836
837                         gpio-controller;
838                         #gpio-cells = <0x2>;
839
840                         interrupt-controller;
841                         #interrupt-cells = <0x2>;
842                 };
843
844                 gpio4: gpio4@ff7b0000 {
845                         compatible = "rockchip,gpio-bank";
846                         reg = <0x0 0xff7b0000 0x0 0x100>;
847                         clocks = <&cru PCLK_GPIO4>;
848                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
849
850                         gpio-controller;
851                         #gpio-cells = <0x2>;
852
853                         interrupt-controller;
854                         #interrupt-cells = <0x2>;
855                 };
856
857                 gpio5: gpio5@ff7c0000 {
858                         compatible = "rockchip,gpio-bank";
859                         reg = <0x0 0xff7c0000 0x0 0x100>;
860                         clocks = <&cru PCLK_GPIO5>;
861                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
862
863                         gpio-controller;
864                         #gpio-cells = <0x2>;
865
866                         interrupt-controller;
867                         #interrupt-cells = <0x2>;
868                 };
869
870                 pcfg_pull_up: pcfg-pull-up {
871                         bias-pull-up;
872                 };
873
874                 pcfg_pull_down: pcfg-pull-down {
875                         bias-pull-down;
876                 };
877
878                 pcfg_pull_none: pcfg-pull-none {
879                         bias-disable;
880                 };
881
882                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
883                         bias-disable;
884                         drive-strength = <12>;
885                 };
886
887                 emmc {
888                         emmc_clk: emmc-clk {
889                                 rockchip,pins =
890                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
891                         };
892
893                         emmc_cmd: emmc-cmd {
894                                 rockchip,pins =
895                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
896                         };
897
898                         emmc_pwr: emmc-pwr {
899                                 rockchip,pins =
900                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
901                         };
902
903                         emmc_bus1: emmc-bus1 {
904                                 rockchip,pins =
905                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
906                         };
907
908                         emmc_bus4: emmc-bus4 {
909                                 rockchip,pins =
910                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
911                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
912                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
913                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
914                         };
915
916                         emmc_bus8: emmc-bus8 {
917                                 rockchip,pins =
918                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
919                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
920                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
921                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
922                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
923                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
924                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
925                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
926                         };
927                 };
928
929                 sdmmc {
930                         sdmmc_cd: sdmmc-cd {
931                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
932                         };
933
934                         sdmmc_bus1: sdmmc-bus1 {
935                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
936                         };
937
938                         sdmmc_bus4: sdmmc-bus4 {
939                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
940                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
941                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
942                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
943                         };
944
945                         sdmmc_clk: sdmmc-clk {
946                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
947                         };
948
949                         sdmmc_cmd: sdmmc-cmd {
950                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
951                         };
952                 };
953
954                 sdio {
955                         sdio_bus1: sdio-bus1 {
956                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
957                         };
958
959                         sdio_bus4: sdio-bus4 {
960                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
961                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
962                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
963                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
964                         };
965
966                         sdio_cmd: sdio-cmd {
967                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
968                         };
969
970                         sdio_clk: sdio-clk {
971                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
972                         };
973
974                         sdio_cd: sdio-cd {
975                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
976                         };
977
978                         sdio_wp: sdio-wp {
979                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
980                         };
981
982                         sdio_int: sdio-int {
983                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
984                         };
985
986                         sdio_pwr: sdio-pwr {
987                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
988                         };
989                 };
990
991                 hdmi_i2c {
992                         hdmii2c_xfer: hdmii2c-xfer {
993                                 rockchip,pins =
994                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
995                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
996                         };
997                 };
998
999                 hdmi_pin {
1000                         hdmi_cec: hdmi-cec {
1001                                 rockchip,pins =
1002                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1003                         };
1004                 };
1005
1006                 i2c0 {
1007                         i2c0_xfer: i2c0-xfer {
1008                                 rockchip,pins =
1009                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1010                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1011                         };
1012                 };
1013
1014                 i2c1 {
1015                         i2c1_xfer: i2c1-xfer {
1016                                 rockchip,pins =
1017                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1018                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1019                         };
1020                 };
1021
1022                 i2c2 {
1023                         i2c2_xfer: i2c2-xfer {
1024                                 rockchip,pins =
1025                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1026                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1027                         };
1028
1029                         i2c2_gpio: i2c2-gpio {
1030                                 rockchip,pins =
1031                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1032                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1033                         };
1034                 };
1035
1036                 i2c3 {
1037                         i2c3_xfer: i2c3-xfer {
1038                                 rockchip,pins =
1039                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1040                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1041                         };
1042                 };
1043
1044                 i2c4 {
1045                         i2c4_xfer: i2c4-xfer {
1046                                 rockchip,pins =
1047                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1048                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1049                         };
1050
1051                         i2c4_gpio: i2c4-gpio {
1052                                 rockchip,pins =
1053                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1054                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1055                         };
1056                 };
1057
1058                 i2c5 {
1059                         i2c5_xfer: i2c5-xfer {
1060                                 rockchip,pins =
1061                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1062                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1063                         };
1064                         i2c5_gpio: i2c5-gpio {
1065                                 rockchip,pins =
1066                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1067                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1068                         };
1069                 };
1070
1071                 i2s {
1072                         i2s_8ch_bus: i2s-8ch-bus {
1073                                 rockchip,pins =
1074                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1075                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1076                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1077                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1078                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1079                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1080                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1081                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1082                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1083                         };
1084                 };
1085
1086                 spdif {
1087                         spdif_bus: spdif-bus {
1088                                 rockchip,pins =
1089                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1090                         };
1091                 };
1092
1093                 spi0 {
1094                         spi0_clk: spi0-clk {
1095                                 rockchip,pins =
1096                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1097                         };
1098                         spi0_cs0: spi0-cs0 {
1099                                 rockchip,pins =
1100                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1101                         };
1102                         spi0_cs1: spi0-cs1 {
1103                                 rockchip,pins =
1104                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1105                         };
1106                         spi0_tx: spi0-tx {
1107                                 rockchip,pins =
1108                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1109                         };
1110                         spi0_rx: spi0-rx {
1111                                 rockchip,pins =
1112                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1113                         };
1114                 };
1115
1116                 spi1 {
1117                         spi1_clk: spi1-clk {
1118                                 rockchip,pins =
1119                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1120                         };
1121                         spi1_cs0: spi1-cs0 {
1122                                 rockchip,pins =
1123                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1124                         };
1125                         spi1_tx: spi1-tx {
1126                                 rockchip,pins =
1127                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1128                         };
1129                         spi1_rx: spi1-rx {
1130                                 rockchip,pins =
1131                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1132                         };
1133                 };
1134
1135                 uart0 {
1136                         uart0_xfer: uart0-xfer {
1137                                 rockchip,pins =
1138                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1139                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141
1142                         uart0_cts: uart0-cts {
1143                                 rockchip,pins =
1144                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146
1147                         uart0_rts: uart0-rts {
1148                                 rockchip,pins =
1149                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151                 };
1152
1153                 uart2_t0 {
1154                         uart2_t0_xfer: uart2_t0-xfer {
1155                                 rockchip,pins =
1156                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1157                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1158                         };
1159                         /* no rts / cts for uart2 */
1160                 };
1161
1162                 uart2_t1 {
1163                         uart2_t1_xfer: uart2_t1-xfer {
1164                                 rockchip,pins =
1165                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1166                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1167                         };
1168                         /* no rts / cts for uart2 */
1169                 };
1170
1171                 uart2_t2 {
1172                         uart2_t2_xfer: uart2_t2-xfer {
1173                                 rockchip,pins =
1174                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1175                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1176                         };
1177                         /* no rts / cts for uart2 */
1178                 };
1179
1180                 uart3 {
1181                         uart3_xfer: uart3-xfer {
1182                                 rockchip,pins =
1183                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1184                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1185                         };
1186
1187                         uart3_cts: uart3-cts {
1188                                 rockchip,pins =
1189                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1190                         };
1191
1192                         uart3_rts: uart3-rts {
1193                                 rockchip,pins =
1194                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196                 };
1197
1198                 pwm0 {
1199                         pwm0_pin: pwm0-pin {
1200                                 rockchip,pins =
1201                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1202                         };
1203                 };
1204
1205                 pwm1 {
1206                         pwm1_pin: pwm1-pin {
1207                                 rockchip,pins =
1208                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1209                         };
1210                 };
1211
1212                 pwm2_t0 {
1213                         pwm2_t0_pin: pwm2_t0-pin {
1214                                 rockchip,pins =
1215                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1216                         };
1217                 };
1218
1219                 pwm2_t1 {
1220                         pwm2_t1_pin: pwm2_t1-pin {
1221                                 rockchip,pins =
1222                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1223                         };
1224                 };
1225
1226                 pwm3_t0 {
1227                         pwm3_t0_pin: pwm3_t0-pin {
1228                                 rockchip,pins =
1229                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1230                         };
1231                 };
1232
1233                 pwm3_t1 {
1234                         pwm3_t1_pin: pwm3_t1-pin {
1235                                 rockchip,pins =
1236                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 pwm3_t2 {
1241                         pwm3_t2_pin: pwm3_t2-pin {
1242                                 rockchip,pins =
1243                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1244                         };
1245                 };
1246
1247                 lcdc {
1248                         lcdc_lcdc: lcdc-lcdc {
1249                                 rockchip,pins =
1250                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1251                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1252                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1253                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1254                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1255                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1256                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1257                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1258                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1259                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1260                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1261                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1262                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1263                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1264                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1265                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1266                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1267                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1268                         };
1269
1270                         lcdc_gpio: lcdc-gpio {
1271                                 rockchip,pins =
1272                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1273                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1274                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1275                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1276                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1277                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1278                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1279                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1280                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1281                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1282                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1283                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1284                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1285                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1286                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1287                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1288                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1289                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1290                         };
1291                 };
1292
1293                 gmac {
1294                         rgmii_pins: rgmii-pins {
1295                                 rockchip,pins =
1296                                         /* mac_rxd3 */
1297                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1298                                         /* mac_rxd2 */
1299                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1300                                         /* mac_txd3 */
1301                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1302                                         /* mac_txd2 */
1303                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1304                                         /* mac_rxd1 */
1305                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1306                                         /* mac_rxd0 */
1307                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1308                                         /* mac_txd1 */
1309                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1310                                         /* mac_txd0 */
1311                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1312                                         /* mac_txclkout */
1313                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1314                                         /* mac_crs */
1315                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1316                                         /* mac_rxclkin */
1317                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1318                                         /* mac_mdio */
1319                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1320                                         /* mac_txen */
1321                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1322                                         /* mac_clk */
1323                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1324                                         /* mac_rxer */
1325                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1326                                         /* mac_rxdv */
1327                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1328                                         /* mac_mdc */
1329                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331
1332                         rmii_pins: rmii-pins {
1333                                 rockchip,pins =
1334                                         /* mac_rxd1 */
1335                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1336                                         /* mac_rxd0 */
1337                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1338                                         /* mac_txd1 */
1339                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1340                                         /* mac_txd0 */
1341                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1342                                         /* mac_crs */
1343                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1344                                         /* mac_rxclkin */
1345                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1346                                         /* mac_mdio */
1347                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1348                                         /* mac_txen */
1349                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1350                                         /* mac_clk */
1351                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1352                                         /* mac_rxer */
1353                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1354                                         /* mac_rxdv */
1355                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1356                                         /* mac_mdc */
1357                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1358                         };
1359                 };
1360
1361                 eth_phy {
1362                         eth_phy_pwr: eth-phy-pwr {
1363                                 rockchip,pins =
1364                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1365                         };
1366                 };
1367         };
1368 };