arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3366";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x0>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&cpu_sleep>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <166>;
  88                 };
  89
  90                 cpu1: cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x1>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cpu-idle-states = <&cpu_sleep>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53","arm,armv8";
 102                         reg = <0x0 0x2>;
 103                         enable-method = "psci";
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                 };
 107
 108                 cpu3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         operating-points-v2 = <&cpu0_opp_table>;
 114                         cpu-idle-states = <&cpu_sleep>;
 115                 };
 116
 117                 idle-states {
 118                         entry-method = "psci";
 119                         cpu_sleep: cpu-sleep-0 {
 120                                 compatible = "arm,idle-state";
 121                                 local-timer-stop;
 122                                 arm,psci-suspend-param = <0x0010000>;
 123                                 entry-latency-us = <350>;
 124                                 exit-latency-us = <600>;
 125                                 min-residency-us = <1150>;
 126                         };
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp00 {
 135                         opp-hz = /bits/ 64 <408000000>;
 136                         opp-microvolt = <950000>;
 137                         clock-latency-ns = <40000>;
 138                         opp-suspend;
 139                 };
 140                 opp01 {
 141                         opp-hz = /bits/ 64 <600000000>;
 142                         opp-microvolt = <950000>;
 143                 };
 144                 opp02 {
 145                         opp-hz = /bits/ 64 <816000000>;
 146                         opp-microvolt = <1000000>;
 147                 };
 148                 opp03 {
 149                         opp-hz = /bits/ 64 <1008000000>;
 150                         opp-microvolt = <1075000>;
 151                 };
 152                 opp04 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <1175000>;
 155                 };
 156                 opp05 {
 157                         opp-hz = /bits/ 64 <1296000000>;
 158                         opp-microvolt = <1250000>;
 159                 };
 160         };
 161
 162         psci {
 163                 compatible = "arm,psci-1.0";
 164                 method = "smc";
 165         };
 166
 167         timer {
 168                 compatible = "arm,armv8-timer";
 169                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 171                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 173         };
 174
 175         arm-pmu {
 176                 compatible = "arm,cortex-a53-pmu";
 177                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 181                 interrupt-affinity = <&cpu0>,
 182                                      <&cpu1>,
 183                                      <&cpu2>,
 184                                      <&cpu3>;
 185         };
 186
 187         xin24m: xin24m {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190                 clock-frequency = <24000000>;
 191                 clock-output-names = "xin24m";
 192         };
 193
 194         gic: interrupt-controller@ffb71000 {
 195                 compatible = "arm,gic-400";
 196                 interrupt-controller;
 197                 #interrupt-cells = <3>;
 198                 #address-cells = <0>;
 199
 200                 reg = <0x0 0xffb71000 0x0 0x1000>,
 201                       <0x0 0xffb72000 0x0 0x1000>,
 202                       <0x0 0xffb74000 0x0 0x2000>,
 203                       <0x0 0xffb76000 0x0 0x2000>;
 204                 interrupts = <GIC_PPI 9
 205                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 206         };
 207
 208         nandc0: nandc@ff0c0000 {
 209                 compatible = "rockchip,rk-nandc";
 210                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 211                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 212                 nandc_id = <0>;
 213                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 214                 clock-names = "clk_nandc", "hclk_nandc";
 215                 status = "disabled";
 216         };
 217
 218         saradc: saradc@ff100000 {
 219                 compatible = "rockchip,saradc";
 220                 reg = <0x0 0xff100000 0x0 0x100>;
 221                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 222                 #io-channel-cells = <1>;
 223                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 224                 clock-names = "saradc", "apb_pclk";
 225                 status = "disabled";
 226         };
 227
 228         spi0: spi@ff110000 {
 229                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 232                 clock-names = "spiclk", "apb_pclk";
 233                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         spi1: spi@ff120000 {
 242                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 245                 clock-names = "spiclk", "apb_pclk";
 246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         scr: rkscr@ff1d0000 {
 255                 compatible = "rockchip-scr";
 256                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 262                 clocks = <&cru PCLK_SIM>;
 263                 clock-names = "g_pclk_sim_card";
 264                 status = "disabled";
 265         };
 266
 267         thermal-zones {
 268                 soc_thermal: soc-thermal {
 269                         polling-delay-passive = <100>; /* milliseconds */
 270                         polling-delay = <1000>; /* milliseconds */
 271                         sustainable-power = <1600>; /* milliwatts */
 272
 273                         thermal-sensors = <&tsadc 0>;
 274
 275                         trips {
 276                                 threshold: trip-point@0 {
 277                                         temperature = <70000>; /* millicelsius */
 278                                         hysteresis = <2000>; /* millicelsius */
 279                                         type = "passive";
 280                                 };
 281                                 target: trip-point@1 {
 282                                         temperature = <85000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 soc_crit: soc-crit {
 287                                         temperature = <95000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "critical";
 290                                 };
 291                         };
 292
 293                         cooling-maps {
 294                                 map0 {
 295                                         trip = <&target>;
 296                                         cooling-device =
 297                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 298                                 };
 299                                 map1 {
 300                                         trip = <&target>;
 301                                         cooling-device =
 302                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 303                                 };
 304                         };
 305                 };
 306
 307                 gpu_thermal: gpu-thermal {
 308                         polling-delay-passive = <100>; /* milliseconds */
 309                         polling-delay = <1000>; /* milliseconds */
 310
 311                         thermal-sensors = <&tsadc 1>;
 312                 };
 313         };
 314
 315         tsadc: tsadc@ff260000 {
 316                 compatible = "rockchip,rk3366-tsadc";
 317                 reg = <0x0 0xff260000 0x0 0x100>;
 318                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 320                 clock-names = "tsadc", "apb_pclk";
 321                 resets = <&cru SRST_TSADC>;
 322                 reset-names = "tsadc-apb";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&tsadc_gpio>;
 325                 #thermal-sensor-cells = <1>;
 326                 rockchip,hw-tshut-temp = <95000>;
 327                 status = "disabled";
 328         };
 329
 330         sdmmc: rksdmmc@ff400000 {
 331                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339                 status = "disabled";
 340         };
 341
 342         sdio: rksdmmc@ff410000 {
 343                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 344                 clock-freq-min-max = <400000 150000000>;
 345                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 346                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 347                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 348                 fifo-depth = <0x100>;
 349                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 350                 reg = <0x0 0xff410000 0x0 0x4000>;
 351                 status = "disabled";
 352         };
 353
 354         emmc: rksdmmc@ff420000 {
 355                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 358                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 362                 reg = <0x0 0xff420000 0x0 0x4000>;
 363                 status = "disabled";
 364         };
 365
 366         gmac: eth@ff440000 {
 367                 compatible = "rockchip,rk3366-gmac";
 368                 reg = <0x0 0xff440000 0x0 0x10000>;
 369                 rockchip,grf = <&grf>;
 370                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "macirq";
 372                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 373                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 374                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 375                          <&cru PCLK_GMAC>;
 376                 clock-names = "stmmaceth", "mac_clk_rx",
 377                               "mac_clk_tx", "clk_mac_ref",
 378                               "clk_mac_refout", "aclk_mac",
 379                               "pclk_mac";
 380                 resets = <&cru SRST_MAC>;
 381                 reset-names = "stmmaceth";
 382                 status = "disabled";
 383         };
 384
 385         i2c0: i2c@ff650000 {
 386                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 387                 reg = <0x0 0xff728000 0x0 0x1000>;
 388                 clocks = <&cru PCLK_I2C0>;
 389                 clock-names = "i2c";
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c0_xfer>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 status = "disabled";
 396         };
 397
 398         i2c2: i2c@ff140000 {
 399                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 400                 reg = <0x0 0xff140000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clock-names = "i2c";
 405                 clocks = <&cru PCLK_I2C2>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c2_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c3: i2c@ff150000 {
 412                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 413                 reg = <0x0 0xff150000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clock-names = "i2c";
 418                 clocks = <&cru PCLK_I2C3>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c3_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@ff160000 {
 425                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 426                 reg = <0x0 0xff160000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clock-names = "i2c";
 431                 clocks = <&cru PCLK_I2C4>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c4_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c5: i2c@ff170000 {
 438                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 439                 reg = <0x0 0xff170000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clock-names = "i2c";
 444                 clocks = <&cru PCLK_I2C5>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c5_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         uart0: serial@ff180000 {
 451                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 452                 reg = <0x0 0xff180000 0x0 0x100>;
 453                 clock-frequency = <24000000>;
 454                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 461                 status = "disabled";
 462         };
 463
 464         uart3: serial@ff1b0000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff1b0000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 475                 status = "disabled";
 476         };
 477
 478         usbphy: phy {
 479                 compatible = "rockchip,rk336x-usb-phy";
 480                 rockchip,grf = <&grf>;
 481                 #address-cells = <1>;
 482                 #size-cells = <0>;
 483
 484                 usbphy0: usb-phy0 {
 485                         #phy-cells = <0>;
 486                         #clock-cells = <0>;
 487                         reg = <0x700>;
 488                 };
 489
 490                 usbphy1: usb-phy1 {
 491                         #phy-cells = <0>;
 492                         #clock-cells = <0>;
 493                         reg = <0x728>;
 494                 };
 495         };
 496
 497         usb_host0_echi: usb@ff480000 {
 498                 compatible = "generic-ehci";
 499                 reg = <0x0 0xff480000 0x0 0x20000>;
 500                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 501                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 502                 clock-names = "sclk_otgphy0", "hclk_host0";
 503                 phys = <&usbphy1>;
 504                 phy-names = "usb";
 505                 status = "disabled";
 506         };
 507
 508         usb_host0_ohci: usb@ff4a0000 {
 509                 compatible = "generic-ohci";
 510                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 511                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 512                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 513                 clock-names = "sclk_otgphy0", "hclk_host0";
 514                 status = "disabled";
 515         };
 516
 517         usb_otg: usb@ff4c0000 {
 518                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 519                              "snps,dwc2";
 520                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 521                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 522                 clocks = <&cru HCLK_OTG>;
 523                 clock-names = "otg";
 524                 dr_mode = "otg";
 525                 g-np-tx-fifo-size = <16>;
 526                 g-rx-fifo-size = <275>;
 527                 g-tx-fifo-size = <256 128 128 64 64 32>;
 528                 g-use-dma;
 529                 status = "disabled";
 530         };
 531
 532         i2c1: i2c@ff660000 {
 533                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 534                 reg = <0x0 0xff660000 0x0 0x1000>;
 535                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 536                 #address-cells = <1>;
 537                 #size-cells = <0>;
 538                 clock-names = "i2c";
 539                 clocks = <&cru PCLK_I2C1>;
 540                 pinctrl-names = "default";
 541                 pinctrl-0 = <&i2c1_xfer>;
 542                 status = "disabled";
 543         };
 544
 545         pwm0: pwm@ff680000 {
 546                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 547                 reg = <0x0 0xff680000 0x0 0x10>;
 548                 #pwm-cells = <3>;
 549                 pinctrl-names = "default";
 550                 pinctrl-0 = <&pwm0_pin>;
 551                 clocks = <&cru PCLK_RKPWM>;
 552                 clock-names = "pwm";
 553                 status = "disabled";
 554         };
 555
 556         pwm1: pwm@ff680010 {
 557                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 558                 reg = <0x0 0xff680010 0x0 0x10>;
 559                 #pwm-cells = <3>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&pwm1_pin>;
 562                 clocks = <&cru PCLK_RKPWM>;
 563                 clock-names = "pwm";
 564                 status = "disabled";
 565         };
 566
 567         pwm2: pwm@ff680020 {
 568                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 569                 reg = <0x0 0xff680020 0x0 0x10>;
 570                 #pwm-cells = <3>;
 571                 clocks = <&cru PCLK_RKPWM>;
 572                 clock-names = "pwm";
 573                 status = "disabled";
 574         };
 575
 576         pwm3: pwm@ff680030 {
 577                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 578                 reg = <0x0 0xff680030 0x0 0x10>;
 579                 #pwm-cells = <3>;
 580                 pinctrl-names = "default";
 581                 pinctrl-0 = <&pwm3_t2_pin>;
 582                 clocks = <&cru PCLK_RKPWM>;
 583                 clock-names = "pwm";
 584                 status = "disabled";
 585         };
 586
 587         uart2: serial@ff690000 {
 588                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 589                 reg = <0x0 0xff690000 0x0 0x100>;
 590                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 591                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 592                 clock-names = "baudclk", "apb_pclk";
 593                 reg-shift = <2>;
 594                 reg-io-width = <4>;
 595                 pinctrl-names = "default";
 596                 pinctrl-0 = <&uart2_t1_xfer>;
 597                 status = "disabled";
 598         };
 599
 600         pmu: power-management@ff730000 {
 601                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 602                 reg = <0x0 0xff730000 0x0 0x1000>;
 603
 604                 power: power-controller {
 605                         status = "disabled";
 606                         compatible = "rockchip,rk3366-power-controller";
 607                         #power-domain-cells = <1>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610
 611                         /*
 612                          * Note: Although SCLK_* are the working clocks
 613                          * of device without including on the NOC, needed for
 614                          * synchronous reset.
 615                          *
 616                          * The clocks on the which NOC:
 617                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 618                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 619                          * ACLK_ISP is on ACLK_ISP_NIU.
 620                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 621                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 622                          *
 623                          * Which clock are device clocks:
 624                          *      clocks          devices
 625                          *      *_IEP           IEP:Image Enhancement Processor
 626                          *      *_ISP           ISP:Image Signal Processing
 627                          *      *_VOP*          VOP:Visual Output Processor
 628                          *      *_RGA           RGA
 629                          *      *_DPHY*         LVDS
 630                          *      *_HDMI          HDMI
 631                          *      *_MIPI_*        MIPI
 632                          */
 633                         pd_vio {
 634                                 reg = <RK3366_PD_VIO>;
 635                                 clocks = <&cru ACLK_IEP>,
 636                                          <&cru ACLK_ISP>,
 637                                          <&cru ACLK_RGA>,
 638                                          <&cru ACLK_HDCP>,
 639                                          <&cru ACLK_VOP_FULL>,
 640                                          <&cru ACLK_VOP_LITE>,
 641                                          <&cru ACLK_VOP_IEP>,
 642                                          <&cru DCLK_VOP_FULL>,
 643                                          <&cru DCLK_VOP_LITE>,
 644                                          <&cru HCLK_IEP>,
 645                                          <&cru HCLK_ISP>,
 646                                          <&cru HCLK_RGA>,
 647                                          <&cru HCLK_VOP_FULL>,
 648                                          <&cru HCLK_VOP_LITE>,
 649                                          <&cru HCLK_VIO_HDCPMMU>,
 650                                          <&cru PCLK_HDMI_CTRL>,
 651                                          <&cru PCLK_HDCP>,
 652                                          <&cru PCLK_MIPI_DSI0>,
 653                                          <&cru SCLK_VOP_FULL_PWM>,
 654                                          <&cru SCLK_HDCP>,
 655                                          <&cru SCLK_ISP>,
 656                                          <&cru SCLK_RGA>,
 657                                          <&cru SCLK_HDMI_CEC>,
 658                                          <&cru SCLK_HDMI_HDCP>;
 659                         };
 660
 661                         /*
 662                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 663                          * (video endecoder & decoder) clocks that on the
 664                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 665                          */
 666                         pd_vpu {
 667                                 reg = <RK3366_PD_VPU>;
 668                                 clocks = <&cru ACLK_VIDEO>,
 669                                          <&cru HCLK_VIDEO>;
 670                         };
 671
 672                         /*
 673                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 674                          * (video decoder) clocks that on the
 675                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 676                          */
 677                         pd_rkvdec {
 678                                 reg = <RK3366_PD_RKVDEC>;
 679                                 clocks = <&cru ACLK_RKVDEC>,
 680                                          <&cru HCLK_RKVDEC>;
 681                         };
 682
 683                         pd_video {
 684                                 reg = <RK3366_PD_VIDEO>;
 685                                 clocks = <&cru ACLK_VIDEO>,
 686                                          <&cru ACLK_RKVDEC>,
 687                                          <&cru HCLK_VIDEO>,
 688                                          <&cru HCLK_RKVDEC>,
 689                                          <&cru SCLK_HEVC_CABAC>,
 690                                          <&cru SCLK_HEVC_CORE>;
 691                         };
 692
 693                         /*
 694                          * Note: ACLK_GPU is the GPU clock,
 695                          * and on the ACLK_GPU_NIU (NOC).
 696                          */
 697                         pd_gpu {
 698                                 reg = <RK3366_PD_GPU>;
 699                                 clocks = <&cru ACLK_GPU>;
 700                         };
 701                 };
 702         };
 703
 704         pmugrf: syscon@ff738000 {
 705                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 706                 reg = <0x0 0xff738000 0x0 0x1000>;
 707
 708                 reboot-mode {
 709                         compatible = "syscon-reboot-mode";
 710                         offset = <0x200>;
 711                         mode-normal = <BOOT_NORMAL>;
 712                         mode-recovery = <BOOT_RECOVERY>;
 713                         mode-fastboot = <BOOT_FASTBOOT>;
 714                         mode-loader = <BOOT_LOADER>;
 715                 };
 716         };
 717
 718         amba {
 719                 compatible = "arm,amba-bus";
 720                 #address-cells = <2>;
 721                 #size-cells = <2>;
 722                 ranges;
 723
 724                 dmac_peri: dma-controller@ff250000 {
 725                         compatible = "arm,pl330", "arm,primecell";
 726                         reg = <0x0 0xff250000 0x0 0x4000>;
 727                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 728                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 729                         #dma-cells = <1>;
 730                         clocks = <&cru ACLK_DMAC_PERI>;
 731                         clock-names = "apb_pclk";
 732                 };
 733
 734                 dmac_bus: dma-controller@ff600000 {
 735                         compatible = "arm,pl330", "arm,primecell";
 736                         reg = <0x0 0xff600000 0x0 0x4000>;
 737                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 738                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 739                         #dma-cells = <1>;
 740                         clocks = <&cru ACLK_DMAC_BUS>;
 741                         clock-names = "apb_pclk";
 742                 };
 743         };
 744
 745         cru: clock-controller@ff760000 {
 746                 compatible = "rockchip,rk3366-cru";
 747                 reg = <0x0 0xff760000 0x0 0x1000>;
 748                 rockchip,grf = <&grf>;
 749                 #clock-cells = <1>;
 750                 #reset-cells = <1>;
 751                 assigned-clocks =
 752                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 753                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 754                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 755                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 756                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 757                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 758                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 759                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 760                         <&cru ACLK_PERI1>;
 761                 assigned-clock-rates =
 762                         <0>, <0>,
 763                         <0>, <0>,
 764                         <750000000>, <576000000>,
 765                         <594000000>, <594000000>,
 766                         <960000000>, <520000000>,
 767                         <375000000>, <288000000>,
 768                         <100000000>, <100000000>,
 769                         <288000000>, <288000000>,
 770                         <144000000>;
 771                 assigned-clock-parents =
 772                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 773                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 774         };
 775
 776         grf: syscon@ff770000 {
 777                 compatible = "rockchip,rk3366-grf", "syscon";
 778                 reg = <0x0 0xff770000 0x0 0x1000>;
 779         };
 780
 781         wdt: watchdog@ff800000 {
 782                 compatible = "snps,dw-wdt";
 783                 reg = <0x0 0xff800000 0x0 0x100>;
 784                 clocks = <&cru PCLK_WDT>;
 785                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 786                 status = "disabled";
 787         };
 788
 789         spdif: spdif@ff880000 {
 790                 compatible = "rockchip,rk3366-spdif";
 791                 reg = <0x0 0xff880000 0x0 0x1000>;
 792                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 793                 dmas = <&dmac_bus 3>;
 794                 dma-names = "tx";
 795                 clock-names = "mclk", "hclk";
 796                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&spdif_bus>;
 799                 status = "disabled";
 800         };
 801
 802         i2s_2ch: i2s-2ch@ff890000 {
 803                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 804                 reg = <0x0 0xff890000 0x0 0x1000>;
 805                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 806                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 807                 dma-names = "tx", "rx";
 808                 clock-names = "i2s_clk", "i2s_hclk";
 809                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 810                 status = "disabled";
 811         };
 812
 813         i2s_8ch: i2s-8ch@ff898000 {
 814                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 815                 reg = <0x0 0xff898000 0x0 0x1000>;
 816                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 817                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 818                 dma-names = "tx", "rx";
 819                 clock-names = "i2s_clk", "i2s_hclk";
 820                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 821                 pinctrl-names = "default";
 822                 pinctrl-0 = <&i2s_8ch_bus>;
 823                 status = "disabled";
 824         };
 825
 826         fb: fb {
 827                 compatible = "rockchip,rk-fb";
 828                 rockchip,disp-mode = <DUAL>;
 829                 status = "disabled";
 830         };
 831
 832         rk_screen: screen {
 833                 compatible = "rockchip,screen";
 834                 status = "disabled";
 835         };
 836
 837         vop_lite: vop@ff8f0000 {
 838                 compatible = "rockchip,rk3366-lcdc-lite";
 839                 rockchip,grf = <&grf>;
 840                 rockchip,pwr18 = <0>;
 841                 rockchip,iommu-enabled = <1>;
 842                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 843                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 844                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 845                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 846                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 847                 reset-names = "axi", "ahb", "dclk";
 848                 status = "disabled";
 849         };
 850
 851         vopl_mmu: vopl-mmu {
 852                 dbgname = "vop";
 853                 compatible = "rockchip,vopl_mmu";
 854                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 855                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 856                 interrupt-names = "vopl_mmu";
 857                 status = "disabled";
 858         };
 859
 860         iep: iep@ff900000 {
 861                 compatible = "rockchip,iep";
 862                 iommu_enabled = <1>;
 863                 reg = <0x0 0xff900000 0x0 0x800>;
 864                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 865                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 866                 clock-names = "aclk_iep", "hclk_iep";
 867                 version = <2>;
 868                 status = "disabled";
 869         };
 870
 871         rga: rga@ff920000 {
 872                 compatible = "rockchip,rga2";
 873                 dev_mode = <1>;
 874                 reg = <0x0 0xff920000 0x0 0x1000>;
 875                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 877                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 878                 status = "disabled";
 879         };
 880
 881         vop_big: vop@ff930000 {
 882                 compatible = "rockchip,rk3366-lcdc-big";
 883                 rockchip,grf = <&grf>;
 884                 rockchip,prop = <PRMRY>;
 885                 rockchip,pwr18 = <0>;
 886                 rockchip,iommu-enabled = <1>;
 887                 reg = <0x0 0xff930000 0x0 0x23f0>;
 888                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 889                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 890                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 891                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 892                 reset-names = "axi", "ahb", "dclk";
 893                 status = "disabled";
 894         };
 895
 896         vopb_mmu: vopb-mmu {
 897                 dbgname = "vop";
 898                 compatible = "rockchip,vopb_mmu";
 899                 reg = <0x0 0xff932400 0x0 0x100>;
 900                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 901                 interrupt-names = "vop_mmu";
 902                 status = "disabled";
 903         };
 904
 905         iep_mmu: iep-mmu {
 906                 dbgname = "iep";
 907                 compatible = "rockchip,iep_mmu";
 908                 reg = <0x0 0xff900800 0x0 0x100>;
 909                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 910                 interrupt-names = "iep_mmu";
 911                 status = "disabled";
 912         };
 913
 914         vpu_mmu: vpu_mmu {
 915                 dbgname = "vpu";
 916                 compatible = "rockchip,vpu_mmu";
 917                 reg = <0x0 0xff9a0800 0x0 0x100>;
 918                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 919                 interrupt-names = "vpu_mmu";
 920                 status = "disabled";
 921         };
 922
 923         vdec_mmu: vdec_mmu {
 924                 dbgname = "vdec";
 925                 compatible = "rockchip,vdec_mmu";
 926                 reg = <0x0 0xff9b0480 0x0 0x40>,
 927                       <0x0 0xff9b04c0 0x0 0x40>;
 928                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 929                 interrupt-names = "vdec_mmu";
 930                 status = "disabled";
 931         };
 932
 933         dsihost0: mipi@ff960000 {
 934                 compatible = "rockchip,rk3366-dsi";
 935                 rockchip,prop = <0>;
 936                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 937                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 938                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 939                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 940                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 941                 status = "disabled";
 942         };
 943
 944         lvds: lvds@ff968000 {
 945                 compatible = "rockchip,rk3366-lvds";
 946                 rockchip,grf = <&grf>;
 947                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 948                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 949                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 950                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 951                 status = "disabled";
 952         };
 953
 954         hdmi: hdmi@ff980000 {
 955                 compatible = "rockchip,rk3366-hdmi";
 956                 reg = <0x0 0xff980000 0x0 0x20000>;
 957                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 958                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 959                 clocks = <&cru PCLK_HDMI_CTRL>,
 960                          <&cru SCLK_HDMI_HDCP>,
 961                          <&cru SCLK_HDMI_CEC>,
 962                          <&cru DCLK_HDMIPHY>;
 963                 clock-names = "pclk_hdmi",
 964                               "hdcp_clk_hdmi",
 965                               "cec_clk_hdmi",
 966                               "dclk_hdmi_phy";
 967                 resets = <&cru SRST_HDMI>;
 968                 reset-names = "hdmi";
 969                 pinctrl-names = "default", "gpio";
 970                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 971                 pinctrl-1 = <&i2c5_gpio>;
 972                 status = "disabled";
 973         };
 974
 975         vpu: vpu_service@ff9a0000 {
 976                 compatible = "rockchip,vpu_service";
 977                 rockchip,grf = <&grf>;
 978                 iommu_enabled = <1>;
 979                 reg = <0x0 0xff9a0000 0x0 0x800>;
 980                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 981                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 982                 interrupt-names = "irq_dec", "irq_enc";
 983                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 984                 clock-names = "aclk_vcodec", "hclk_vcodec";
 985                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 986                 reset-names = "video_h", "video_a";
 987                 name = "vpu_service";
 988                 dev_mode = <0>;
 989                 status = "disabled";
 990         };
 991
 992         rkvdec: rkvdec@ff9b0000 {
 993                 compatible = "rockchip,rkvdec";
 994                 rockchip,grf = <&grf>;
 995                 iommu_enabled = <1>;
 996                 reg = <0x0 0xff9b0000 0x0 0x400>;
 997                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 998                 interrupt-names = "irq_dec";
 999                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1000                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1001                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1002                 reset-names = "video_h", "video_a";
1003                 dev_mode = <2>;
1004                 name = "rkvdec";
1005                 status = "disabled";
1006         };
1007
1008         pinctrl: pinctrl {
1009                 compatible = "rockchip,rk3366-pinctrl";
1010                 rockchip,grf = <&grf>;
1011                 rockchip,pmu = <&pmugrf>;
1012                 #address-cells = <0x2>;
1013                 #size-cells = <0x2>;
1014                 ranges;
1015
1016                 gpio0: gpio0@ff750000 {
1017                         compatible = "rockchip,gpio-bank";
1018                         reg = <0x0 0xff750000 0x0 0x100>;
1019                         clocks = <&cru PCLK_GPIO0>;
1020                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1021
1022                         gpio-controller;
1023                         #gpio-cells = <0x2>;
1024
1025                         interrupt-controller;
1026                         #interrupt-cells = <0x2>;
1027                 };
1028
1029                 gpio1: gpio1@ff780000 {
1030                         compatible = "rockchip,gpio-bank";
1031                         reg = <0x0 0xff758000 0x0 0x100>;
1032                         clocks = <&cru PCLK_GPIO1>;
1033                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1034
1035                         gpio-controller;
1036                         #gpio-cells = <0x2>;
1037
1038                         interrupt-controller;
1039                         #interrupt-cells = <0x2>;
1040                 };
1041
1042                 gpio2: gpio2@ff790000 {
1043                         compatible = "rockchip,gpio-bank";
1044                         reg = <0x0 0xff790000 0x0 0x100>;
1045                         clocks = <&cru PCLK_GPIO2>;
1046                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1047
1048                         gpio-controller;
1049                         #gpio-cells = <0x2>;
1050
1051                         interrupt-controller;
1052                         #interrupt-cells = <0x2>;
1053                 };
1054
1055                 gpio3: gpio3@ff7a0000 {
1056                         compatible = "rockchip,gpio-bank";
1057                         reg = <0x0 0xff7a0000 0x0 0x100>;
1058                         clocks = <&cru PCLK_GPIO3>;
1059                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1060
1061                         gpio-controller;
1062                         #gpio-cells = <0x2>;
1063
1064                         interrupt-controller;
1065                         #interrupt-cells = <0x2>;
1066                 };
1067
1068                 gpio4: gpio4@ff7b0000 {
1069                         compatible = "rockchip,gpio-bank";
1070                         reg = <0x0 0xff7b0000 0x0 0x100>;
1071                         clocks = <&cru PCLK_GPIO4>;
1072                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1073
1074                         gpio-controller;
1075                         #gpio-cells = <0x2>;
1076
1077                         interrupt-controller;
1078                         #interrupt-cells = <0x2>;
1079                 };
1080
1081                 gpio5: gpio5@ff7c0000 {
1082                         compatible = "rockchip,gpio-bank";
1083                         reg = <0x0 0xff7c0000 0x0 0x100>;
1084                         clocks = <&cru PCLK_GPIO5>;
1085                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1086
1087                         gpio-controller;
1088                         #gpio-cells = <0x2>;
1089
1090                         interrupt-controller;
1091                         #interrupt-cells = <0x2>;
1092                 };
1093
1094                 pcfg_pull_up: pcfg-pull-up {
1095                         bias-pull-up;
1096                 };
1097
1098                 pcfg_pull_down: pcfg-pull-down {
1099                         bias-pull-down;
1100                 };
1101
1102                 pcfg_pull_none: pcfg-pull-none {
1103                         bias-disable;
1104                 };
1105
1106                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1107                         bias-disable;
1108                         drive-strength = <12>;
1109                 };
1110
1111                 emmc {
1112                         emmc_clk: emmc-clk {
1113                                 rockchip,pins =
1114                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1115                         };
1116
1117                         emmc_cmd: emmc-cmd {
1118                                 rockchip,pins =
1119                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1120                         };
1121
1122                         emmc_pwr: emmc-pwr {
1123                                 rockchip,pins =
1124                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1125                         };
1126
1127                         emmc_bus1: emmc-bus1 {
1128                                 rockchip,pins =
1129                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1130                         };
1131
1132                         emmc_bus4: emmc-bus4 {
1133                                 rockchip,pins =
1134                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1135                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1136                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1137                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1138                         };
1139
1140                         emmc_bus8: emmc-bus8 {
1141                                 rockchip,pins =
1142                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1143                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1144                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1145                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1146                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1147                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1148                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1149                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1150                         };
1151                 };
1152
1153                 sdmmc {
1154                         sdmmc_cd: sdmmc-cd {
1155                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1156                         };
1157
1158                         sdmmc_bus1: sdmmc-bus1 {
1159                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1160                         };
1161
1162                         sdmmc_bus4: sdmmc-bus4 {
1163                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1164                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1165                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1166                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1167                         };
1168
1169                         sdmmc_clk: sdmmc-clk {
1170                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1171                         };
1172
1173                         sdmmc_cmd: sdmmc-cmd {
1174                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1175                         };
1176                 };
1177
1178                 sdio {
1179                         sdio_bus1: sdio-bus1 {
1180                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1181                         };
1182
1183                         sdio_bus4: sdio-bus4 {
1184                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1185                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1186                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1187                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1188                         };
1189
1190                         sdio_cmd: sdio-cmd {
1191                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1192                         };
1193
1194                         sdio_clk: sdio-clk {
1195                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1196                         };
1197
1198                         sdio_cd: sdio-cd {
1199                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1200                         };
1201
1202                         sdio_wp: sdio-wp {
1203                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1204                         };
1205
1206                         sdio_int: sdio-int {
1207                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1208                         };
1209
1210                         sdio_pwr: sdio-pwr {
1211                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1212                         };
1213                 };
1214
1215                 hdmi_i2c {
1216                         hdmii2c_xfer: hdmii2c-xfer {
1217                                 rockchip,pins =
1218                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1219                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1220                         };
1221                 };
1222
1223                 hdmi_pin {
1224                         hdmi_cec: hdmi-cec {
1225                                 rockchip,pins =
1226                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 i2c0 {
1231                         i2c0_xfer: i2c0-xfer {
1232                                 rockchip,pins =
1233                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1234                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1235                         };
1236                 };
1237
1238                 i2c1 {
1239                         i2c1_xfer: i2c1-xfer {
1240                                 rockchip,pins =
1241                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1242                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1243                         };
1244                 };
1245
1246                 i2c2 {
1247                         i2c2_xfer: i2c2-xfer {
1248                                 rockchip,pins =
1249                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1250                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1251                         };
1252
1253                         i2c2_gpio: i2c2-gpio {
1254                                 rockchip,pins =
1255                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1256                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1257                         };
1258                 };
1259
1260                 i2c3 {
1261                         i2c3_xfer: i2c3-xfer {
1262                                 rockchip,pins =
1263                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1264                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1265                         };
1266                 };
1267
1268                 i2c4 {
1269                         i2c4_xfer: i2c4-xfer {
1270                                 rockchip,pins =
1271                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1272                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1273                         };
1274
1275                         i2c4_gpio: i2c4-gpio {
1276                                 rockchip,pins =
1277                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1278                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1279                         };
1280                 };
1281
1282                 i2c5 {
1283                         i2c5_xfer: i2c5-xfer {
1284                                 rockchip,pins =
1285                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1286                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1287                         };
1288                         i2c5_gpio: i2c5-gpio {
1289                                 rockchip,pins =
1290                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1291                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1292                         };
1293                 };
1294
1295                 i2s {
1296                         i2s_8ch_bus: i2s-8ch-bus {
1297                                 rockchip,pins =
1298                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1299                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1300                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1301                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1302                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1303                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1304                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1305                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1306                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1307                         };
1308                 };
1309
1310                 spdif {
1311                         spdif_bus: spdif-bus {
1312                                 rockchip,pins =
1313                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1314                         };
1315                 };
1316
1317                 spi0 {
1318                         spi0_clk: spi0-clk {
1319                                 rockchip,pins =
1320                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1321                         };
1322                         spi0_cs0: spi0-cs0 {
1323                                 rockchip,pins =
1324                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1325                         };
1326                         spi0_cs1: spi0-cs1 {
1327                                 rockchip,pins =
1328                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1329                         };
1330                         spi0_tx: spi0-tx {
1331                                 rockchip,pins =
1332                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1333                         };
1334                         spi0_rx: spi0-rx {
1335                                 rockchip,pins =
1336                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1337                         };
1338                 };
1339
1340                 spi1 {
1341                         spi1_clk: spi1-clk {
1342                                 rockchip,pins =
1343                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1344                         };
1345                         spi1_cs0: spi1-cs0 {
1346                                 rockchip,pins =
1347                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1348                         };
1349                         spi1_tx: spi1-tx {
1350                                 rockchip,pins =
1351                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1352                         };
1353                         spi1_rx: spi1-rx {
1354                                 rockchip,pins =
1355                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1356                         };
1357                 };
1358
1359                 scr {
1360                         scr_clk: scr-clk {
1361                                 rockchip,pins =
1362                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1363                         };
1364
1365                         scr_io: scr-io {
1366                                 rockchip,pins =
1367                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1368                         };
1369
1370                         scr_rst: scr-rst {
1371                                 rockchip,pins =
1372                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1373                         };
1374
1375                         scr_detect: scr-detect {
1376                                 rockchip,pins =
1377                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1378                         };
1379                 };
1380
1381                 uart0 {
1382                         uart0_xfer: uart0-xfer {
1383                                 rockchip,pins =
1384                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1385                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1386                         };
1387
1388                         uart0_cts: uart0-cts {
1389                                 rockchip,pins =
1390                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1391                         };
1392
1393                         uart0_rts: uart0-rts {
1394                                 rockchip,pins =
1395                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1396                         };
1397                 };
1398
1399                 uart2_t0 {
1400                         uart2_t0_xfer: uart2_t0-xfer {
1401                                 rockchip,pins =
1402                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1403                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1404                         };
1405                         /* no rts / cts for uart2 */
1406                 };
1407
1408                 uart2_t1 {
1409                         uart2_t1_xfer: uart2_t1-xfer {
1410                                 rockchip,pins =
1411                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1412                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1413                         };
1414                         /* no rts / cts for uart2 */
1415                 };
1416
1417                 uart2_t2 {
1418                         uart2_t2_xfer: uart2_t2-xfer {
1419                                 rockchip,pins =
1420                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1421                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1422                         };
1423                         /* no rts / cts for uart2 */
1424                 };
1425
1426                 uart3 {
1427                         uart3_xfer: uart3-xfer {
1428                                 rockchip,pins =
1429                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1430                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1431                         };
1432
1433                         uart3_cts: uart3-cts {
1434                                 rockchip,pins =
1435                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1436                         };
1437
1438                         uart3_rts: uart3-rts {
1439                                 rockchip,pins =
1440                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1441                         };
1442                 };
1443
1444                 pwm0 {
1445                         pwm0_pin: pwm0-pin {
1446                                 rockchip,pins =
1447                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 pwm1 {
1452                         pwm1_pin: pwm1-pin {
1453                                 rockchip,pins =
1454                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 pwm2_t0 {
1459                         pwm2_t0_pin: pwm2_t0-pin {
1460                                 rockchip,pins =
1461                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1462                         };
1463                 };
1464
1465                 pwm2_t1 {
1466                         pwm2_t1_pin: pwm2_t1-pin {
1467                                 rockchip,pins =
1468                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1469                         };
1470                 };
1471
1472                 pwm3_t0 {
1473                         pwm3_t0_pin: pwm3_t0-pin {
1474                                 rockchip,pins =
1475                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1476                         };
1477                 };
1478
1479                 pwm3_t1 {
1480                         pwm3_t1_pin: pwm3_t1-pin {
1481                                 rockchip,pins =
1482                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1483                         };
1484                 };
1485
1486                 pwm3_t2 {
1487                         pwm3_t2_pin: pwm3_t2-pin {
1488                                 rockchip,pins =
1489                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 lcdc {
1494                         lcdc_lcdc: lcdc-lcdc {
1495                                 rockchip,pins =
1496                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1497                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1498                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1499                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1500                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1501                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1502                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1503                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1504                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1505                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1506                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1507                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1508                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1509                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1510                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1511                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1512                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1513                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1514                         };
1515
1516                         lcdc_gpio: lcdc-gpio {
1517                                 rockchip,pins =
1518                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1519                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1520                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1521                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1522                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1523                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1524                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1525                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1526                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1527                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1528                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1529                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1530                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1531                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1532                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1533                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1534                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1535                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1536                         };
1537                 };
1538
1539                 gmac {
1540                         rgmii_pins: rgmii-pins {
1541                                 rockchip,pins =
1542                                         /* mac_rxd3 */
1543                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1544                                         /* mac_rxd2 */
1545                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1546                                         /* mac_txd3 */
1547                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1548                                         /* mac_txd2 */
1549                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1550                                         /* mac_rxd1 */
1551                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1552                                         /* mac_rxd0 */
1553                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1554                                         /* mac_txd1 */
1555                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1556                                         /* mac_txd0 */
1557                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1558                                         /* mac_txclkout */
1559                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1560                                         /* mac_crs */
1561                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1562                                         /* mac_rxclkin */
1563                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_mdio */
1565                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_txen */
1567                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1568                                         /* mac_clk */
1569                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_rxer */
1571                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1572                                         /* mac_rxdv */
1573                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1574                                         /* mac_mdc */
1575                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1576                         };
1577
1578                         rmii_pins: rmii-pins {
1579                                 rockchip,pins =
1580                                         /* mac_rxd1 */
1581                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1582                                         /* mac_rxd0 */
1583                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1584                                         /* mac_txd1 */
1585                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1586                                         /* mac_txd0 */
1587                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1588                                         /* mac_crs */
1589                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1590                                         /* mac_rxclkin */
1591                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1592                                         /* mac_mdio */
1593                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1594                                         /* mac_txen */
1595                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1596                                         /* mac_clk */
1597                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1598                                         /* mac_rxer */
1599                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1600                                         /* mac_rxdv */
1601                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1602                                         /* mac_mdc */
1603                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1604                         };
1605                 };
1606
1607                 eth_phy {
1608                         eth_phy_pwr: eth-phy-pwr {
1609                                 rockchip,pins =
1610                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 tsadc_pin {
1615                         tsadc_gpio: tsadc-gpio {
1616                                 rockchip,pins =
1617                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1618                         };
1619
1620                         tsadc_int: tsadc-int {
1621                                 rockchip,pins =
1622                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1623                         };
1624                 };
1625         };
1626
1627         gpu: gpu@ffa30000 {
1628                 compatible = "arm,malit764",
1629                              "arm,malit76x",
1630                              "arm,malit7xx",
1631                              "arm,mali-midgard";
1632
1633                 reg = <0x0 0xffa30000 0 0x10000>;
1634
1635                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1636                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1637                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1638                 interrupt-names = "GPU", "MMU", "JOB";
1639
1640                 clocks = <&cru ACLK_GPU>;
1641                 clock-names = "clk_mali";
1642                 #cooling-cells = <2>; /* min followed by max */
1643                 operating-points-v2 = <&gpu_opp_table>;
1644                 status = "disabled";
1645
1646                 power_model {
1647                         compatible = "arm,mali-simple-power-model";
1648                         voltage = <900>;
1649                         frequency = <500>;
1650                         static-power = <300>;
1651                         dynamic-power = <1780>;
1652                         ts = <32000 4700 (-80) 2>;
1653                         thermal-zone = "gpu-thermal";
1654                 };
1655         };
1656
1657         gpu_opp_table: gpu_opp_table {
1658                 compatible = "operating-points-v2";
1659                 opp-shared;
1660
1661                 opp00 {
1662                         opp-hz = /bits/ 64 <96000000>;
1663                         opp-microvolt = <1100000>;
1664                 };
1665                 opp01 {
1666                         opp-hz = /bits/ 64 <192000000>;
1667                         opp-microvolt = <1100000>;
1668                 };
1669                 opp02 {
1670                         opp-hz = /bits/ 64 <288000000>;
1671                         opp-microvolt = <1100000>;
1672                 };
1673                 opp03 {
1674                         opp-hz = /bits/ 64 <375000000>;
1675                         opp-microvolt = <1125000>;
1676                 };
1677                 opp04 {
1678                         opp-hz = /bits/ 64 <480000000>;
1679                         opp-microvolt = <1200000>;
1680                 };
1681         };
1682 };