ARM64: dts: rockchip: add watchdog node for rk3366
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3366.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
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30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 #include <dt-bindings/clock/rk3366-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/irq.h>
46 #include <dt-bindings/interrupt-controller/arm-gic.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/display/rk_fb.h>
49 #include <dt-bindings/power/rk3366-power.h>
50 #include <dt-bindings/soc/rockchip_boot-mode.h>
51
52 / {
53         compatible = "rockchip,rk3366";
54         interrupt-parent = <&gic>;
55         #address-cells = <2>;
56         #size-cells = <2>;
57
58         aliases {
59                 i2c0 = &i2c0;
60                 i2c1 = &i2c1;
61                 i2c2 = &i2c2;
62                 i2c3 = &i2c3;
63                 i2c4 = &i2c4;
64                 i2c5 = &i2c5;
65                 serial0 = &uart0;
66                 serial2 = &uart2;
67                 serial3 = &uart3;
68                 spi0 = &spi0;
69                 spi1 = &spi1;
70         };
71
72         cpus {
73                 #address-cells = <0x2>;
74                 #size-cells = <0x0>;
75
76                 cpu0: cpu@0 {
77                         device_type = "cpu";
78                         compatible = "arm,cortex-a53","arm,armv8";
79                         reg = <0x0 0x0>;
80                         enable-method = "psci";
81                         clocks = <&cru ARMCLK>;
82                         operating-points-v2 = <&cpu0_opp_table>;
83                 };
84
85                 cpu1: cpu@1 {
86                         device_type = "cpu";
87                         compatible = "arm,cortex-a53","arm,armv8";
88                         reg = <0x0 0x1>;
89                         enable-method = "psci";
90                         operating-points-v2 = <&cpu0_opp_table>;
91                 };
92
93                 cpu2: cpu@2 {
94                         device_type = "cpu";
95                         compatible = "arm,cortex-a53","arm,armv8";
96                         reg = <0x0 0x2>;
97                         enable-method = "psci";
98                         operating-points-v2 = <&cpu0_opp_table>;
99                 };
100
101                 cpu3: cpu@3 {
102                         device_type = "cpu";
103                         compatible = "arm,cortex-a53","arm,armv8";
104                         reg = <0x0 0x3>;
105                         enable-method = "psci";
106                         operating-points-v2 = <&cpu0_opp_table>;
107                 };
108         };
109
110         cpu0_opp_table: opp_table0 {
111                 compatible = "operating-points-v2";
112                 opp-shared;
113
114                 opp00 {
115                         opp-hz = /bits/ 64 <408000000>;
116                         opp-microvolt = <1200000>;
117                         clock-latency-ns = <40000>;
118                         opp-suspend;
119                 };
120                 opp01 {
121                         opp-hz = /bits/ 64 <600000000>;
122                         opp-microvolt = <1200000>;
123                 };
124                 opp02 {
125                         opp-hz = /bits/ 64 <816000000>;
126                         opp-microvolt = <1200000>;
127                 };
128                 opp03 {
129                         opp-hz = /bits/ 64 <1008000000>;
130                         opp-microvolt = <1200000>;
131                 };
132                 opp04 {
133                         opp-hz = /bits/ 64 <1200000000>;
134                         opp-microvolt = <1200000>;
135                 };
136         };
137
138         psci {
139                 compatible = "arm,psci-1.0";
140                 method = "smc";
141         };
142
143         timer {
144                 compatible = "arm,armv8-timer";
145                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
146                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
147                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
148                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
149         };
150
151         xin24m: xin24m {
152                 compatible = "fixed-clock";
153                 #clock-cells = <0>;
154                 clock-frequency = <24000000>;
155                 clock-output-names = "xin24m";
156         };
157
158         gic: interrupt-controller@ffb71000 {
159                 compatible = "arm,gic-400";
160                 interrupt-controller;
161                 #interrupt-cells = <3>;
162                 #address-cells = <0>;
163
164                 reg = <0x0 0xffb71000 0x0 0x1000>,
165                       <0x0 0xffb72000 0x0 0x1000>,
166                       <0x0 0xffb74000 0x0 0x2000>,
167                       <0x0 0xffb76000 0x0 0x2000>;
168                 interrupts = <GIC_PPI 9
169                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
170         };
171
172         nandc0: nandc@ff0c0000 {
173                 compatible = "rockchip,rk-nandc";
174                 reg = <0x0 0xff0c0000 0x0 0x4000>;
175                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
176                 nandc_id = <0>;
177                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
178                 clock-names = "clk_nandc", "hclk_nandc";
179                 status = "disabled";
180         };
181
182         saradc: saradc@ff100000 {
183                 compatible = "rockchip,saradc";
184                 reg = <0x0 0xff100000 0x0 0x100>;
185                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
186                 #io-channel-cells = <1>;
187                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
188                 clock-names = "saradc", "apb_pclk";
189                 status = "disabled";
190         };
191
192         spi0: spi@ff110000 {
193                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
194                 reg = <0x0 0xff110000 0x0 0x1000>;
195                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
196                 clock-names = "spiclk", "apb_pclk";
197                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
198                 pinctrl-names = "default";
199                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
200                 #address-cells = <1>;
201                 #size-cells = <0>;
202                 status = "disabled";
203         };
204
205         spi1: spi@ff120000 {
206                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
207                 reg = <0x0 0xff120000 0x0 0x1000>;
208                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
209                 clock-names = "spiclk", "apb_pclk";
210                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
211                 pinctrl-names = "default";
212                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
213                 #address-cells = <1>;
214                 #size-cells = <0>;
215                 status = "disabled";
216         };
217
218         sdmmc: rksdmmc@ff400000 {
219                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
220                 clock-freq-min-max = <400000 150000000>;
221                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
222                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
223                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
224                 fifo-depth = <0x100>;
225                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
226                 reg = <0x0 0xff400000 0x0 0x4000>;
227                 status = "disabled";
228         };
229
230         sdio: rksdmmc@ff410000 {
231                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
232                 clock-freq-min-max = <400000 150000000>;
233                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
234                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236                 fifo-depth = <0x100>;
237                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
238                 reg = <0x0 0xff410000 0x0 0x4000>;
239                 status = "disabled";
240         };
241
242         emmc: rksdmmc@ff420000 {
243                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
244                 clock-freq-min-max = <400000 150000000>;
245                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
246                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248                 fifo-depth = <0x100>;
249                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
250                 reg = <0x0 0xff420000 0x0 0x4000>;
251                 status = "disabled";
252         };
253
254         gmac: eth@ff440000 {
255                 compatible = "rockchip,rk3366-gmac";
256                 reg = <0x0 0xff440000 0x0 0x10000>;
257                 rockchip,grf = <&grf>;
258                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
259                 interrupt-names = "macirq";
260                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
261                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
262                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
263                          <&cru PCLK_GMAC>;
264                 clock-names = "stmmaceth", "mac_clk_rx",
265                               "mac_clk_tx", "clk_mac_ref",
266                               "clk_mac_refout", "aclk_mac",
267                               "pclk_mac";
268                 resets = <&cru SRST_MAC>;
269                 reset-names = "stmmaceth";
270                 status = "disabled";
271         };
272
273         i2c0: i2c@ff650000 {
274                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
275                 reg = <0x0 0xff728000 0x0 0x1000>;
276                 clocks = <&cru PCLK_I2C0>;
277                 clock-names = "i2c";
278                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
279                 pinctrl-names = "default";
280                 pinctrl-0 = <&i2c0_xfer>;
281                 #address-cells = <1>;
282                 #size-cells = <0>;
283                 status = "disabled";
284         };
285
286         i2c2: i2c@ff140000 {
287                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
288                 reg = <0x0 0xff140000 0x0 0x1000>;
289                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
290                 #address-cells = <1>;
291                 #size-cells = <0>;
292                 clock-names = "i2c";
293                 clocks = <&cru PCLK_I2C2>;
294                 pinctrl-names = "default";
295                 pinctrl-0 = <&i2c2_xfer>;
296                 status = "disabled";
297         };
298
299         i2c3: i2c@ff150000 {
300                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
301                 reg = <0x0 0xff150000 0x0 0x1000>;
302                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
303                 #address-cells = <1>;
304                 #size-cells = <0>;
305                 clock-names = "i2c";
306                 clocks = <&cru PCLK_I2C3>;
307                 pinctrl-names = "default";
308                 pinctrl-0 = <&i2c3_xfer>;
309                 status = "disabled";
310         };
311
312         i2c4: i2c@ff160000 {
313                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
314                 reg = <0x0 0xff160000 0x0 0x1000>;
315                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
316                 #address-cells = <1>;
317                 #size-cells = <0>;
318                 clock-names = "i2c";
319                 clocks = <&cru PCLK_I2C4>;
320                 pinctrl-names = "default";
321                 pinctrl-0 = <&i2c4_xfer>;
322                 status = "disabled";
323         };
324
325         i2c5: i2c@ff170000 {
326                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
327                 reg = <0x0 0xff170000 0x0 0x1000>;
328                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
329                 #address-cells = <1>;
330                 #size-cells = <0>;
331                 clock-names = "i2c";
332                 clocks = <&cru PCLK_I2C5>;
333                 pinctrl-names = "default";
334                 pinctrl-0 = <&i2c5_xfer>;
335                 status = "disabled";
336         };
337
338         uart0: serial@ff180000 {
339                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
340                 reg = <0x0 0xff180000 0x0 0x100>;
341                 clock-frequency = <24000000>;
342                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
343                 clock-names = "baudclk", "apb_pclk";
344                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
345                 reg-shift = <2>;
346                 reg-io-width = <4>;
347                 pinctrl-names = "default";
348                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
349                 status = "disabled";
350         };
351
352         uart3: serial@ff1b0000 {
353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
354                 reg = <0x0 0xff1b0000 0x0 0x100>;
355                 clock-frequency = <24000000>;
356                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
357                 clock-names = "baudclk", "apb_pclk";
358                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
359                 reg-shift = <2>;
360                 reg-io-width = <4>;
361                 pinctrl-names = "default";
362                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
363                 status = "disabled";
364         };
365
366         usb_host0_echi: usb@ff480000 {
367                 compatible = "generic-ehci";
368                 reg = <0x0 0xff480000 0x0 0x20000>;
369                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
370                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
371                 clock-names = "sclk_otgphy0", "hclk_host0";
372                 status = "disabled";
373         };
374
375         usb_host0_ohci: usb@ff4a0000 {
376                 compatible = "generic-ohci";
377                 reg = <0x0 0xff4a0000 0x0 0x20000>;
378                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
379                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
380                 clock-names = "sclk_otgphy0", "hclk_host0";
381                 status = "disabled";
382         };
383
384         usb_otg: usb@ff4c0000 {
385                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
386                              "snps,dwc2";
387                 reg = <0x0 0xff4c0000 0x0 0x40000>;
388                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
389                 clocks = <&cru HCLK_OTG>;
390                 clock-names = "otg";
391                 dr_mode = "otg";
392                 g-np-tx-fifo-size = <16>;
393                 g-rx-fifo-size = <275>;
394                 g-tx-fifo-size = <256 128 128 64 64 32>;
395                 g-use-dma;
396                 status = "disabled";
397         };
398
399         i2c1: i2c@ff660000 {
400                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
401                 reg = <0x0 0xff660000 0x0 0x1000>;
402                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
403                 #address-cells = <1>;
404                 #size-cells = <0>;
405                 clock-names = "i2c";
406                 clocks = <&cru PCLK_I2C1>;
407                 pinctrl-names = "default";
408                 pinctrl-0 = <&i2c1_xfer>;
409                 status = "disabled";
410         };
411
412         pwm0: pwm@ff680000 {
413                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
414                 reg = <0x0 0xff680000 0x0 0x10>;
415                 #pwm-cells = <3>;
416                 pinctrl-names = "default";
417                 pinctrl-0 = <&pwm0_pin>;
418                 clocks = <&cru PCLK_RKPWM>;
419                 clock-names = "pwm";
420                 status = "disabled";
421         };
422
423         pwm1: pwm@ff680010 {
424                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
425                 reg = <0x0 0xff680010 0x0 0x10>;
426                 #pwm-cells = <3>;
427                 pinctrl-names = "default";
428                 pinctrl-0 = <&pwm1_pin>;
429                 clocks = <&cru PCLK_RKPWM>;
430                 clock-names = "pwm";
431                 status = "disabled";
432         };
433
434         pwm2: pwm@ff680020 {
435                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
436                 reg = <0x0 0xff680020 0x0 0x10>;
437                 #pwm-cells = <3>;
438                 clocks = <&cru PCLK_RKPWM>;
439                 clock-names = "pwm";
440                 status = "disabled";
441         };
442
443         pwm3: pwm@ff680030 {
444                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
445                 reg = <0x0 0xff680030 0x0 0x10>;
446                 #pwm-cells = <3>;
447                 pinctrl-names = "default";
448                 pinctrl-0 = <&pwm3_t2_pin>;
449                 clocks = <&cru PCLK_RKPWM>;
450                 clock-names = "pwm";
451                 status = "disabled";
452         };
453
454         uart2: serial@ff690000 {
455                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
456                 reg = <0x0 0xff690000 0x0 0x100>;
457                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
458                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
459                 clock-names = "baudclk", "apb_pclk";
460                 reg-shift = <2>;
461                 reg-io-width = <4>;
462                 pinctrl-names = "default";
463                 pinctrl-0 = <&uart2_t1_xfer>;
464                 status = "disabled";
465         };
466
467         pmu: power-management@ff730000 {
468                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
469                 reg = <0x0 0xff730000 0x0 0x1000>;
470
471                 power: power-controller {
472                         status = "disabled";
473                         compatible = "rockchip,rk3366-power-controller";
474                         #power-domain-cells = <1>;
475                         #address-cells = <1>;
476                         #size-cells = <0>;
477
478                         /*
479                          * Note: Although SCLK_* are the working clocks
480                          * of device without including on the NOC, needed for
481                          * synchronous reset.
482                          *
483                          * The clocks on the which NOC:
484                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
485                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
486                          * ACLK_ISP is on ACLK_ISP_NIU.
487                          * ACLK_HDCP is on ACLK_HDCP_NIU.
488                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
489                          *
490                          * Which clock are device clocks:
491                          *      clocks          devices
492                          *      *_IEP           IEP:Image Enhancement Processor
493                          *      *_ISP           ISP:Image Signal Processing
494                          *      *_VOP*          VOP:Visual Output Processor
495                          *      *_RGA           RGA
496                          *      *_DPHY*         LVDS
497                          *      *_HDMI          HDMI
498                          *      *_MIPI_*        MIPI
499                          */
500                         pd_vio {
501                                 reg = <RK3366_PD_VIO>;
502                                 clocks = <&cru ACLK_IEP>,
503                                          <&cru ACLK_ISP>,
504                                          <&cru ACLK_RGA>,
505                                          <&cru ACLK_HDCP>,
506                                          <&cru ACLK_VOP_FULL>,
507                                          <&cru ACLK_VOP_LITE>,
508                                          <&cru ACLK_VOP_IEP>,
509                                          <&cru DCLK_VOP_FULL>,
510                                          <&cru DCLK_VOP_LITE>,
511                                          <&cru HCLK_IEP>,
512                                          <&cru HCLK_ISP>,
513                                          <&cru HCLK_RGA>,
514                                          <&cru HCLK_VOP_FULL>,
515                                          <&cru HCLK_VOP_LITE>,
516                                          <&cru HCLK_VIO_HDCPMMU>,
517                                          <&cru PCLK_HDMI_CTRL>,
518                                          <&cru PCLK_HDCP>,
519                                          <&cru PCLK_MIPI_DSI0>,
520                                          <&cru SCLK_VOP_FULL_PWM>,
521                                          <&cru SCLK_HDCP>,
522                                          <&cru SCLK_ISP>,
523                                          <&cru SCLK_RGA>,
524                                          <&cru SCLK_HDMI_CEC>,
525                                          <&cru SCLK_HDMI_HDCP>;
526                         };
527
528                         /*
529                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
530                          * (video endecoder & decoder) clocks that on the
531                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
532                          */
533                         pd_vpu {
534                                 reg = <RK3366_PD_VPU>;
535                                 clocks = <&cru ACLK_VIDEO>,
536                                          <&cru HCLK_VIDEO>;
537                         };
538
539                         /*
540                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
541                          * (video decoder) clocks that on the
542                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
543                          */
544                         pd_rkvdec {
545                                 reg = <RK3366_PD_RKVDEC>;
546                                 clocks = <&cru ACLK_RKVDEC>,
547                                          <&cru HCLK_RKVDEC>;
548                         };
549
550                         pd_video {
551                                 reg = <RK3366_PD_VIDEO>;
552                                 clocks = <&cru ACLK_VIDEO>,
553                                          <&cru ACLK_RKVDEC>,
554                                          <&cru HCLK_VIDEO>,
555                                          <&cru HCLK_RKVDEC>,
556                                          <&cru SCLK_HEVC_CABAC>,
557                                          <&cru SCLK_HEVC_CORE>;
558                         };
559
560                         /*
561                          * Note: ACLK_GPU is the GPU clock,
562                          * and on the ACLK_GPU_NIU (NOC).
563                          */
564                         pd_gpu {
565                                 reg = <RK3366_PD_GPU>;
566                                 clocks = <&cru ACLK_GPU>;
567                         };
568                 };
569         };
570
571         pmugrf: syscon@ff738000 {
572                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
573                 reg = <0x0 0xff738000 0x0 0x1000>;
574
575                 reboot-mode {
576                         compatible = "syscon-reboot-mode";
577                         offset = <0x200>;
578                         mode-normal = <BOOT_NORMAL>;
579                         mode-recovery = <BOOT_RECOVERY>;
580                         mode-fastboot = <BOOT_FASTBOOT>;
581                         mode-loader = <BOOT_LOADER>;
582                 };
583         };
584
585         amba {
586                 compatible = "arm,amba-bus";
587                 #address-cells = <2>;
588                 #size-cells = <2>;
589                 ranges;
590
591                 dmac_peri: dma-controller@ff250000 {
592                         compatible = "arm,pl330", "arm,primecell";
593                         reg = <0x0 0xff250000 0x0 0x4000>;
594                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
595                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
596                         #dma-cells = <1>;
597                         clocks = <&cru ACLK_DMAC_PERI>;
598                         clock-names = "apb_pclk";
599                 };
600
601                 dmac_bus: dma-controller@ff600000 {
602                         compatible = "arm,pl330", "arm,primecell";
603                         reg = <0x0 0xff600000 0x0 0x4000>;
604                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
605                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
606                         #dma-cells = <1>;
607                         clocks = <&cru ACLK_DMAC_BUS>;
608                         clock-names = "apb_pclk";
609                 };
610         };
611
612         cru: clock-controller@ff760000 {
613                 compatible = "rockchip,rk3366-cru";
614                 reg = <0x0 0xff760000 0x0 0x1000>;
615                 rockchip,grf = <&grf>;
616                 #clock-cells = <1>;
617                 #reset-cells = <1>;
618                 assigned-clocks =
619                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
620                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
621                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
622                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
623                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>;
624                 assigned-clock-rates =
625                         <750000000>, <576000000>,
626                         <594000000>, <594000000>,
627                         <480000000>, <520000000>,
628                         <375000000>, <288000000>,
629                         <100000000>, <100000000>;
630         };
631
632         grf: syscon@ff770000 {
633                 compatible = "rockchip,rk3366-grf", "syscon";
634                 reg = <0x0 0xff770000 0x0 0x1000>;
635         };
636
637         wdt: watchdog@ff800000 {
638                 compatible = "snps,dw-wdt";
639                 reg = <0x0 0xff800000 0x0 0x100>;
640                 clocks = <&cru PCLK_WDT>;
641                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
642                 status = "disabled";
643         };
644
645         spdif: spdif@ff880000 {
646                 compatible = "rockchip,rk3366-spdif";
647                 reg = <0x0 0xff880000 0x0 0x1000>;
648                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
649                 dmas = <&dmac_bus 3>;
650                 dma-names = "tx";
651                 clock-names = "hclk", "mclk";
652                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
653                 pinctrl-names = "default";
654                 pinctrl-0 = <&spdif_bus>;
655                 status = "disabled";
656         };
657
658         i2s_2ch: i2s-2ch@ff890000 {
659                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
660                 reg = <0x0 0xff890000 0x0 0x1000>;
661                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
662                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
663                 dma-names = "tx", "rx";
664                 clock-names = "i2s_hclk", "i2s_clk";
665                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
666                 status = "disabled";
667         };
668
669         i2s_8ch: i2s-8ch@ff898000 {
670                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
671                 reg = <0x0 0xff898000 0x0 0x1000>;
672                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
673                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
674                 dma-names = "tx", "rx";
675                 clock-names = "i2s_hclk", "i2s_clk";
676                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
677                 pinctrl-names = "default";
678                 pinctrl-0 = <&i2s_8ch_bus>;
679                 status = "disabled";
680         };
681
682         fb: fb {
683                 compatible = "rockchip,rk-fb";
684                 rockchip,disp-mode = <DUAL>;
685                 status = "disabled";
686         };
687
688         rk_screen: screen {
689                 compatible = "rockchip,screen";
690                 status = "disabled";
691         };
692
693         vop_lite: vop@ff8f0000 {
694                 compatible = "rockchip,rk3366-lcdc-lite";
695                 rockchip,grf = <&grf>;
696                 rockchip,pwr18 = <0>;
697                 rockchip,iommu-enabled = <1>;
698                 reg = <0x0 0xff8f0000 0x0 0x1000>;
699                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
700                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
701                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
702                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
703                 reset-names = "axi", "ahb", "dclk";
704                 status = "disabled";
705         };
706
707         vopl_mmu: vopl-mmu {
708                 dbgname = "vop";
709                 compatible = "rockchip,vopl_mmu";
710                 reg = <0x0 0xff8f0f00 0x0 0x100>;
711                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
712                 interrupt-names = "vopl_mmu";
713                 status = "disabled";
714         };
715
716         rga: rga@ff920000 {
717                 compatible = "rockchip,rga2";
718                 dev_mode = <1>;
719                 reg = <0x0 0xff920000 0x0 0x1000>;
720                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
721                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
722                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
723                 status = "disabled";
724         };
725
726         vop_big: vop@ff930000 {
727                 compatible = "rockchip,rk3366-lcdc-big";
728                 rockchip,grf = <&grf>;
729                 rockchip,prop = <PRMRY>;
730                 rockchip,pwr18 = <0>;
731                 rockchip,iommu-enabled = <1>;
732                 reg = <0x0 0xff930000 0x0 0x23f0>;
733                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
734                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
735                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
736                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
737                 reset-names = "axi", "ahb", "dclk";
738                 status = "disabled";
739         };
740
741         vopb_mmu: vopb-mmu {
742                 dbgname = "vop";
743                 compatible = "rockchip,vopb_mmu";
744                 reg = <0x0 0xff932400 0x0 0x100>;
745                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
746                 interrupt-names = "vop_mmu";
747                 status = "disabled";
748         };
749
750         dsihost0: mipi@ff960000 {
751                 compatible = "rockchip,rk3368-dsi";
752                 rockchip,prop = <0>;
753                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
754                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
755                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
756                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
757                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
758                 status = "disabled";
759         };
760
761         lvds: lvds@ff968000 {
762                 compatible = "rockchip,rk3366-lvds";
763                 rockchip,grf = <&grf>;
764                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
765                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
766                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
767                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
768                 status = "disabled";
769         };
770
771         hdmi: hdmi@ff980000 {
772                 compatible = "rockchip,rk3366-hdmi";
773                 reg = <0x0 0xff980000 0x0 0x20000>;
774                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
775                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
776                 clocks = <&cru PCLK_HDMI_CTRL>,
777                          <&cru SCLK_HDMI_HDCP>,
778                          <&cru SCLK_HDMI_CEC>,
779                          <&cru DCLK_HDMIPHY>;
780                 clock-names = "pclk_hdmi",
781                               "hdcp_clk_hdmi",
782                               "cec_clk_hdmi",
783                               "dclk_hdmi_phy";
784                 resets = <&cru SRST_HDMI>;
785                 reset-names = "hdmi";
786                 pinctrl-names = "default", "gpio";
787                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
788                 pinctrl-1 = <&i2c5_gpio>;
789                 status = "disabled";
790         };
791
792         pinctrl: pinctrl {
793                 compatible = "rockchip,rk3366-pinctrl";
794                 rockchip,grf = <&grf>;
795                 rockchip,pmu = <&pmugrf>;
796                 #address-cells = <0x2>;
797                 #size-cells = <0x2>;
798                 ranges;
799
800                 gpio0: gpio0@ff750000 {
801                         compatible = "rockchip,gpio-bank";
802                         reg = <0x0 0xff750000 0x0 0x100>;
803                         clocks = <&cru PCLK_GPIO0>;
804                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
805
806                         gpio-controller;
807                         #gpio-cells = <0x2>;
808
809                         interrupt-controller;
810                         #interrupt-cells = <0x2>;
811                 };
812
813                 gpio1: gpio1@ff780000 {
814                         compatible = "rockchip,gpio-bank";
815                         reg = <0x0 0xff758000 0x0 0x100>;
816                         clocks = <&cru PCLK_GPIO1>;
817                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
818
819                         gpio-controller;
820                         #gpio-cells = <0x2>;
821
822                         interrupt-controller;
823                         #interrupt-cells = <0x2>;
824                 };
825
826                 gpio2: gpio2@ff790000 {
827                         compatible = "rockchip,gpio-bank";
828                         reg = <0x0 0xff790000 0x0 0x100>;
829                         clocks = <&cru PCLK_GPIO2>;
830                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
831
832                         gpio-controller;
833                         #gpio-cells = <0x2>;
834
835                         interrupt-controller;
836                         #interrupt-cells = <0x2>;
837                 };
838
839                 gpio3: gpio3@ff7a0000 {
840                         compatible = "rockchip,gpio-bank";
841                         reg = <0x0 0xff7a0000 0x0 0x100>;
842                         clocks = <&cru PCLK_GPIO3>;
843                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
844
845                         gpio-controller;
846                         #gpio-cells = <0x2>;
847
848                         interrupt-controller;
849                         #interrupt-cells = <0x2>;
850                 };
851
852                 gpio4: gpio4@ff7b0000 {
853                         compatible = "rockchip,gpio-bank";
854                         reg = <0x0 0xff7b0000 0x0 0x100>;
855                         clocks = <&cru PCLK_GPIO4>;
856                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
857
858                         gpio-controller;
859                         #gpio-cells = <0x2>;
860
861                         interrupt-controller;
862                         #interrupt-cells = <0x2>;
863                 };
864
865                 gpio5: gpio5@ff7c0000 {
866                         compatible = "rockchip,gpio-bank";
867                         reg = <0x0 0xff7c0000 0x0 0x100>;
868                         clocks = <&cru PCLK_GPIO5>;
869                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
870
871                         gpio-controller;
872                         #gpio-cells = <0x2>;
873
874                         interrupt-controller;
875                         #interrupt-cells = <0x2>;
876                 };
877
878                 pcfg_pull_up: pcfg-pull-up {
879                         bias-pull-up;
880                 };
881
882                 pcfg_pull_down: pcfg-pull-down {
883                         bias-pull-down;
884                 };
885
886                 pcfg_pull_none: pcfg-pull-none {
887                         bias-disable;
888                 };
889
890                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
891                         bias-disable;
892                         drive-strength = <12>;
893                 };
894
895                 emmc {
896                         emmc_clk: emmc-clk {
897                                 rockchip,pins =
898                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
899                         };
900
901                         emmc_cmd: emmc-cmd {
902                                 rockchip,pins =
903                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
904                         };
905
906                         emmc_pwr: emmc-pwr {
907                                 rockchip,pins =
908                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
909                         };
910
911                         emmc_bus1: emmc-bus1 {
912                                 rockchip,pins =
913                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
914                         };
915
916                         emmc_bus4: emmc-bus4 {
917                                 rockchip,pins =
918                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
919                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
920                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
921                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
922                         };
923
924                         emmc_bus8: emmc-bus8 {
925                                 rockchip,pins =
926                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
927                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
928                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
929                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
930                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
931                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
932                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
933                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
934                         };
935                 };
936
937                 sdmmc {
938                         sdmmc_cd: sdmmc-cd {
939                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
940                         };
941
942                         sdmmc_bus1: sdmmc-bus1 {
943                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
944                         };
945
946                         sdmmc_bus4: sdmmc-bus4 {
947                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
948                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
949                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
950                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
951                         };
952
953                         sdmmc_clk: sdmmc-clk {
954                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
955                         };
956
957                         sdmmc_cmd: sdmmc-cmd {
958                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
959                         };
960                 };
961
962                 sdio {
963                         sdio_bus1: sdio-bus1 {
964                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
965                         };
966
967                         sdio_bus4: sdio-bus4 {
968                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
969                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
970                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
971                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
972                         };
973
974                         sdio_cmd: sdio-cmd {
975                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
976                         };
977
978                         sdio_clk: sdio-clk {
979                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
980                         };
981
982                         sdio_cd: sdio-cd {
983                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
984                         };
985
986                         sdio_wp: sdio-wp {
987                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
988                         };
989
990                         sdio_int: sdio-int {
991                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
992                         };
993
994                         sdio_pwr: sdio-pwr {
995                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
996                         };
997                 };
998
999                 hdmi_i2c {
1000                         hdmii2c_xfer: hdmii2c-xfer {
1001                                 rockchip,pins =
1002                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1003                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1004                         };
1005                 };
1006
1007                 hdmi_pin {
1008                         hdmi_cec: hdmi-cec {
1009                                 rockchip,pins =
1010                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1011                         };
1012                 };
1013
1014                 i2c0 {
1015                         i2c0_xfer: i2c0-xfer {
1016                                 rockchip,pins =
1017                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1018                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1019                         };
1020                 };
1021
1022                 i2c1 {
1023                         i2c1_xfer: i2c1-xfer {
1024                                 rockchip,pins =
1025                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1026                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1027                         };
1028                 };
1029
1030                 i2c2 {
1031                         i2c2_xfer: i2c2-xfer {
1032                                 rockchip,pins =
1033                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1034                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1035                         };
1036
1037                         i2c2_gpio: i2c2-gpio {
1038                                 rockchip,pins =
1039                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1040                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1041                         };
1042                 };
1043
1044                 i2c3 {
1045                         i2c3_xfer: i2c3-xfer {
1046                                 rockchip,pins =
1047                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1048                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1049                         };
1050                 };
1051
1052                 i2c4 {
1053                         i2c4_xfer: i2c4-xfer {
1054                                 rockchip,pins =
1055                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1056                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1057                         };
1058
1059                         i2c4_gpio: i2c4-gpio {
1060                                 rockchip,pins =
1061                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1062                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1063                         };
1064                 };
1065
1066                 i2c5 {
1067                         i2c5_xfer: i2c5-xfer {
1068                                 rockchip,pins =
1069                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1070                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072                         i2c5_gpio: i2c5-gpio {
1073                                 rockchip,pins =
1074                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1075                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 i2s {
1080                         i2s_8ch_bus: i2s-8ch-bus {
1081                                 rockchip,pins =
1082                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1083                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1084                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1085                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1086                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1087                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1088                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1089                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1090                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1091                         };
1092                 };
1093
1094                 spdif {
1095                         spdif_bus: spdif-bus {
1096                                 rockchip,pins =
1097                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1098                         };
1099                 };
1100
1101                 spi0 {
1102                         spi0_clk: spi0-clk {
1103                                 rockchip,pins =
1104                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1105                         };
1106                         spi0_cs0: spi0-cs0 {
1107                                 rockchip,pins =
1108                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1109                         };
1110                         spi0_cs1: spi0-cs1 {
1111                                 rockchip,pins =
1112                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1113                         };
1114                         spi0_tx: spi0-tx {
1115                                 rockchip,pins =
1116                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1117                         };
1118                         spi0_rx: spi0-rx {
1119                                 rockchip,pins =
1120                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1121                         };
1122                 };
1123
1124                 spi1 {
1125                         spi1_clk: spi1-clk {
1126                                 rockchip,pins =
1127                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1128                         };
1129                         spi1_cs0: spi1-cs0 {
1130                                 rockchip,pins =
1131                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1132                         };
1133                         spi1_tx: spi1-tx {
1134                                 rockchip,pins =
1135                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1136                         };
1137                         spi1_rx: spi1-rx {
1138                                 rockchip,pins =
1139                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1140                         };
1141                 };
1142
1143                 uart0 {
1144                         uart0_xfer: uart0-xfer {
1145                                 rockchip,pins =
1146                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1147                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1148                         };
1149
1150                         uart0_cts: uart0-cts {
1151                                 rockchip,pins =
1152                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1153                         };
1154
1155                         uart0_rts: uart0-rts {
1156                                 rockchip,pins =
1157                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1158                         };
1159                 };
1160
1161                 uart2_t0 {
1162                         uart2_t0_xfer: uart2_t0-xfer {
1163                                 rockchip,pins =
1164                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1165                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1166                         };
1167                         /* no rts / cts for uart2 */
1168                 };
1169
1170                 uart2_t1 {
1171                         uart2_t1_xfer: uart2_t1-xfer {
1172                                 rockchip,pins =
1173                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1174                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1175                         };
1176                         /* no rts / cts for uart2 */
1177                 };
1178
1179                 uart2_t2 {
1180                         uart2_t2_xfer: uart2_t2-xfer {
1181                                 rockchip,pins =
1182                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1183                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1184                         };
1185                         /* no rts / cts for uart2 */
1186                 };
1187
1188                 uart3 {
1189                         uart3_xfer: uart3-xfer {
1190                                 rockchip,pins =
1191                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1192                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1193                         };
1194
1195                         uart3_cts: uart3-cts {
1196                                 rockchip,pins =
1197                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1198                         };
1199
1200                         uart3_rts: uart3-rts {
1201                                 rockchip,pins =
1202                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204                 };
1205
1206                 pwm0 {
1207                         pwm0_pin: pwm0-pin {
1208                                 rockchip,pins =
1209                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211                 };
1212
1213                 pwm1 {
1214                         pwm1_pin: pwm1-pin {
1215                                 rockchip,pins =
1216                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1217                         };
1218                 };
1219
1220                 pwm2_t0 {
1221                         pwm2_t0_pin: pwm2_t0-pin {
1222                                 rockchip,pins =
1223                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1224                         };
1225                 };
1226
1227                 pwm2_t1 {
1228                         pwm2_t1_pin: pwm2_t1-pin {
1229                                 rockchip,pins =
1230                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1231                         };
1232                 };
1233
1234                 pwm3_t0 {
1235                         pwm3_t0_pin: pwm3_t0-pin {
1236                                 rockchip,pins =
1237                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1238                         };
1239                 };
1240
1241                 pwm3_t1 {
1242                         pwm3_t1_pin: pwm3_t1-pin {
1243                                 rockchip,pins =
1244                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1245                         };
1246                 };
1247
1248                 pwm3_t2 {
1249                         pwm3_t2_pin: pwm3_t2-pin {
1250                                 rockchip,pins =
1251                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1252                         };
1253                 };
1254
1255                 lcdc {
1256                         lcdc_lcdc: lcdc-lcdc {
1257                                 rockchip,pins =
1258                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1259                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1260                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1261                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1262                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1263                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1264                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1265                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1266                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1267                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1268                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1269                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1270                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1271                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1272                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1273                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1274                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1275                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1276                         };
1277
1278                         lcdc_gpio: lcdc-gpio {
1279                                 rockchip,pins =
1280                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1281                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1282                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1283                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1284                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1285                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1286                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1287                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1288                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1289                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1290                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1291                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1292                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1293                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1294                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1295                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1296                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1297                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1298                         };
1299                 };
1300
1301                 gmac {
1302                         rgmii_pins: rgmii-pins {
1303                                 rockchip,pins =
1304                                         /* mac_rxd3 */
1305                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1306                                         /* mac_rxd2 */
1307                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1308                                         /* mac_txd3 */
1309                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1310                                         /* mac_txd2 */
1311                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1312                                         /* mac_rxd1 */
1313                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1314                                         /* mac_rxd0 */
1315                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1316                                         /* mac_txd1 */
1317                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1318                                         /* mac_txd0 */
1319                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1320                                         /* mac_txclkout */
1321                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1322                                         /* mac_crs */
1323                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1324                                         /* mac_rxclkin */
1325                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1326                                         /* mac_mdio */
1327                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1328                                         /* mac_txen */
1329                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1330                                         /* mac_clk */
1331                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1332                                         /* mac_rxer */
1333                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1334                                         /* mac_rxdv */
1335                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1336                                         /* mac_mdc */
1337                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1338                         };
1339
1340                         rmii_pins: rmii-pins {
1341                                 rockchip,pins =
1342                                         /* mac_rxd1 */
1343                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1344                                         /* mac_rxd0 */
1345                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1346                                         /* mac_txd1 */
1347                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1348                                         /* mac_txd0 */
1349                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1350                                         /* mac_crs */
1351                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1352                                         /* mac_rxclkin */
1353                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1354                                         /* mac_mdio */
1355                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1356                                         /* mac_txen */
1357                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1358                                         /* mac_clk */
1359                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1360                                         /* mac_rxer */
1361                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1362                                         /* mac_rxdv */
1363                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1364                                         /* mac_mdc */
1365                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1366                         };
1367                 };
1368
1369                 eth_phy {
1370                         eth_phy_pwr: eth-phy-pwr {
1371                                 rockchip,pins =
1372                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1373                         };
1374                 };
1375         };
1376 };