arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/display/mipi_dsi.h>
  50 #include <dt-bindings/power/rk3366-power.h>
  51 #include <dt-bindings/soc/rockchip_boot-mode.h>
  52 #include <dt-bindings/thermal/thermal.h>
  53
  54 / {
  55         compatible = "rockchip,rk3366";
  56         interrupt-parent = <&gic>;
  57         #address-cells = <2>;
  58         #size-cells = <2>;
  59
  60         aliases {
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65                 i2c4 = &i2c4;
  66                 i2c5 = &i2c5;
  67                 serial0 = &uart0;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72         };
  73
  74         cpus {
  75                 #address-cells = <0x2>;
  76                 #size-cells = <0x0>;
  77
  78                 cpu0: cpu@0 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a53","arm,armv8";
  81                         reg = <0x0 0x0>;
  82                         enable-method = "psci";
  83                         clocks = <&cru ARMCLK>;
  84                         operating-points-v2 = <&cpu0_opp_table>;
  85                         cpu-idle-states = <&cpu_sleep>;
  86                         #cooling-cells = <2>; /* min followed by max */
  87                         dynamic-power-coefficient = <166>;
  88                 };
  89
  90                 cpu1: cpu@1 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53","arm,armv8";
  93                         reg = <0x0 0x1>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                         cpu-idle-states = <&cpu_sleep>;
  97                 };
  98
  99                 cpu2: cpu@2 {
 100                         device_type = "cpu";
 101                         compatible = "arm,cortex-a53","arm,armv8";
 102                         reg = <0x0 0x2>;
 103                         enable-method = "psci";
 104                         operating-points-v2 = <&cpu0_opp_table>;
 105                         cpu-idle-states = <&cpu_sleep>;
 106                 };
 107
 108                 cpu3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53","arm,armv8";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         operating-points-v2 = <&cpu0_opp_table>;
 114                         cpu-idle-states = <&cpu_sleep>;
 115                 };
 116
 117                 idle-states {
 118                         entry-method = "psci";
 119                         cpu_sleep: cpu-sleep-0 {
 120                                 compatible = "arm,idle-state";
 121                                 local-timer-stop;
 122                                 arm,psci-suspend-param = <0x0010000>;
 123                                 entry-latency-us = <350>;
 124                                 exit-latency-us = <600>;
 125                                 min-residency-us = <1150>;
 126                         };
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 opp@408000000 {
 135                         opp-hz = /bits/ 64 <408000000>;
 136                         opp-microvolt = <950000>;
 137                         clock-latency-ns = <40000>;
 138                         opp-suspend;
 139                 };
 140                 opp@600000000 {
 141                         opp-hz = /bits/ 64 <600000000>;
 142                         opp-microvolt = <950000>;
 143                 };
 144                 opp@816000000 {
 145                         opp-hz = /bits/ 64 <816000000>;
 146                         opp-microvolt = <1000000>;
 147                 };
 148                 opp@1008000000 {
 149                         opp-hz = /bits/ 64 <1008000000>;
 150                         opp-microvolt = <1075000>;
 151                 };
 152                 opp@1200000000 {
 153                         opp-hz = /bits/ 64 <1200000000>;
 154                         opp-microvolt = <1175000>;
 155                 };
 156                 opp@1296000000 {
 157                         opp-hz = /bits/ 64 <1296000000>;
 158                         opp-microvolt = <1250000>;
 159                 };
 160         };
 161
 162         psci {
 163                 compatible = "arm,psci-1.0";
 164                 method = "smc";
 165         };
 166
 167         timer {
 168                 compatible = "arm,armv8-timer";
 169                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 170                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 171                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 173         };
 174
 175         arm-pmu {
 176                 compatible = "arm,cortex-a53-pmu";
 177                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 178                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 179                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 180                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 181                 interrupt-affinity = <&cpu0>,
 182                                      <&cpu1>,
 183                                      <&cpu2>,
 184                                      <&cpu3>;
 185         };
 186
 187         xin24m: xin24m {
 188                 compatible = "fixed-clock";
 189                 #clock-cells = <0>;
 190                 clock-frequency = <24000000>;
 191                 clock-output-names = "xin24m";
 192         };
 193
 194         gic: interrupt-controller@ffb71000 {
 195                 compatible = "arm,gic-400";
 196                 interrupt-controller;
 197                 #interrupt-cells = <3>;
 198                 #address-cells = <0>;
 199
 200                 reg = <0x0 0xffb71000 0x0 0x1000>,
 201                       <0x0 0xffb72000 0x0 0x1000>,
 202                       <0x0 0xffb74000 0x0 0x2000>,
 203                       <0x0 0xffb76000 0x0 0x2000>;
 204                 interrupts = <GIC_PPI 9
 205                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 206         };
 207
 208         nandc0: nandc@ff0c0000 {
 209                 compatible = "rockchip,rk-nandc";
 210                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 211                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 212                 nandc_id = <0>;
 213                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 214                 clock-names = "clk_nandc", "hclk_nandc";
 215                 status = "disabled";
 216         };
 217
 218         saradc: saradc@ff100000 {
 219                 compatible = "rockchip,saradc";
 220                 reg = <0x0 0xff100000 0x0 0x100>;
 221                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 222                 #io-channel-cells = <1>;
 223                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 224                 clock-names = "saradc", "apb_pclk";
 225                 status = "disabled";
 226         };
 227
 228         spi0: spi@ff110000 {
 229                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 230                 reg = <0x0 0xff110000 0x0 0x1000>;
 231                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 232                 clock-names = "spiclk", "apb_pclk";
 233                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 234                 pinctrl-names = "default";
 235                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 236                 #address-cells = <1>;
 237                 #size-cells = <0>;
 238                 status = "disabled";
 239         };
 240
 241         spi1: spi@ff120000 {
 242                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 243                 reg = <0x0 0xff120000 0x0 0x1000>;
 244                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 245                 clock-names = "spiclk", "apb_pclk";
 246                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 247                 pinctrl-names = "default";
 248                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 249                 #address-cells = <1>;
 250                 #size-cells = <0>;
 251                 status = "disabled";
 252         };
 253
 254         scr: rkscr@ff1d0000 {
 255                 compatible = "rockchip-scr";
 256                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 257                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 258                 #address-cells = <1>;
 259                 #size-cells = <0>;
 260                 pinctrl-names = "default";
 261                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 262                 clocks = <&cru PCLK_SIM>;
 263                 clock-names = "g_pclk_sim_card";
 264                 status = "disabled";
 265         };
 266
 267         thermal-zones {
 268                 soc_thermal: soc-thermal {
 269                         polling-delay-passive = <100>; /* milliseconds */
 270                         polling-delay = <1000>; /* milliseconds */
 271                         sustainable-power = <1600>; /* milliwatts */
 272
 273                         thermal-sensors = <&tsadc 0>;
 274
 275                         trips {
 276                                 threshold: trip-point@0 {
 277                                         temperature = <70000>; /* millicelsius */
 278                                         hysteresis = <2000>; /* millicelsius */
 279                                         type = "passive";
 280                                 };
 281                                 target: trip-point@1 {
 282                                         temperature = <85000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 soc_crit: soc-crit {
 287                                         temperature = <95000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "critical";
 290                                 };
 291                         };
 292
 293                         cooling-maps {
 294                                 map0 {
 295                                         trip = <&target>;
 296                                         cooling-device =
 297                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 298                                 };
 299                                 map1 {
 300                                         trip = <&target>;
 301                                         cooling-device =
 302                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 303                                 };
 304                         };
 305                 };
 306
 307                 gpu_thermal: gpu-thermal {
 308                         polling-delay-passive = <100>; /* milliseconds */
 309                         polling-delay = <1000>; /* milliseconds */
 310
 311                         thermal-sensors = <&tsadc 1>;
 312                 };
 313         };
 314
 315         tsadc: tsadc@ff260000 {
 316                 compatible = "rockchip,rk3366-tsadc";
 317                 reg = <0x0 0xff260000 0x0 0x100>;
 318                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 319                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 320                 clock-names = "tsadc", "apb_pclk";
 321                 resets = <&cru SRST_TSADC>;
 322                 reset-names = "tsadc-apb";
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&tsadc_gpio>;
 325                 #thermal-sensor-cells = <1>;
 326                 rockchip,hw-tshut-temp = <95000>;
 327                 status = "disabled";
 328         };
 329
 330         sdmmc: rksdmmc@ff400000 {
 331                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 332                 clock-freq-min-max = <400000 150000000>;
 333                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 334                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 335                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 336                 fifo-depth = <0x100>;
 337                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 338                 reg = <0x0 0xff400000 0x0 0x4000>;
 339                 status = "disabled";
 340         };
 341
 342         sdio: rksdmmc@ff410000 {
 343                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 344                 clock-freq-min-max = <400000 150000000>;
 345                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 346                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 347                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 348                 fifo-depth = <0x100>;
 349                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 350                 reg = <0x0 0xff410000 0x0 0x4000>;
 351                 status = "disabled";
 352         };
 353
 354         emmc: rksdmmc@ff420000 {
 355                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 356                 clock-freq-min-max = <400000 150000000>;
 357                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 358                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 359                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 360                 fifo-depth = <0x100>;
 361                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 362                 reg = <0x0 0xff420000 0x0 0x4000>;
 363                 status = "disabled";
 364         };
 365
 366         gmac: eth@ff440000 {
 367                 compatible = "rockchip,rk3366-gmac";
 368                 reg = <0x0 0xff440000 0x0 0x10000>;
 369                 rockchip,grf = <&grf>;
 370                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 371                 interrupt-names = "macirq";
 372                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 373                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 374                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 375                          <&cru PCLK_GMAC>;
 376                 clock-names = "stmmaceth", "mac_clk_rx",
 377                               "mac_clk_tx", "clk_mac_ref",
 378                               "clk_mac_refout", "aclk_mac",
 379                               "pclk_mac";
 380                 resets = <&cru SRST_MAC>;
 381                 reset-names = "stmmaceth";
 382                 status = "disabled";
 383         };
 384
 385         i2c0: i2c@ff650000 {
 386                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 387                 reg = <0x0 0xff728000 0x0 0x1000>;
 388                 clocks = <&cru PCLK_I2C0>;
 389                 clock-names = "i2c";
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 pinctrl-names = "default";
 392                 pinctrl-0 = <&i2c0_xfer>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 status = "disabled";
 396         };
 397
 398         i2c2: i2c@ff140000 {
 399                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 400                 reg = <0x0 0xff140000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clock-names = "i2c";
 405                 clocks = <&cru PCLK_I2C2>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c2_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c3: i2c@ff150000 {
 412                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 413                 reg = <0x0 0xff150000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clock-names = "i2c";
 418                 clocks = <&cru PCLK_I2C3>;
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c3_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c4: i2c@ff160000 {
 425                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 426                 reg = <0x0 0xff160000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clock-names = "i2c";
 431                 clocks = <&cru PCLK_I2C4>;
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c4_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c5: i2c@ff170000 {
 438                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 439                 reg = <0x0 0xff170000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clock-names = "i2c";
 444                 clocks = <&cru PCLK_I2C5>;
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c5_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         uart0: serial@ff180000 {
 451                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 452                 reg = <0x0 0xff180000 0x0 0x100>;
 453                 clock-frequency = <24000000>;
 454                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 455                 clock-names = "baudclk", "apb_pclk";
 456                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 457                 reg-shift = <2>;
 458                 reg-io-width = <4>;
 459                 pinctrl-names = "default";
 460                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 461                 status = "disabled";
 462         };
 463
 464         uart3: serial@ff1b0000 {
 465                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 466                 reg = <0x0 0xff1b0000 0x0 0x100>;
 467                 clock-frequency = <24000000>;
 468                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 469                 clock-names = "baudclk", "apb_pclk";
 470                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 475                 status = "disabled";
 476         };
 477
 478         usb_host0_ehci: usb@ff480000 {
 479                 compatible = "generic-ehci";
 480                 reg = <0x0 0xff480000 0x0 0x20000>;
 481                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 482                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 483                 clock-names = "sclk_otgphy0", "hclk_host0";
 484                 phys = <&u2phy_host>;
 485                 phy-names = "usb";
 486                 status = "disabled";
 487         };
 488
 489         usb_host0_ohci: usb@ff4a0000 {
 490                 compatible = "generic-ohci";
 491                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 492                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 493                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 494                 clock-names = "sclk_otgphy0", "hclk_host0";
 495                 status = "disabled";
 496         };
 497
 498         usb_otg: usb@ff4c0000 {
 499                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 500                              "snps,dwc2";
 501                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 502                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&cru HCLK_OTG>;
 504                 clock-names = "otg";
 505                 dr_mode = "otg";
 506                 g-np-tx-fifo-size = <16>;
 507                 g-rx-fifo-size = <275>;
 508                 g-tx-fifo-size = <256 128 128 64 64 32>;
 509                 g-use-dma;
 510                 status = "disabled";
 511         };
 512
 513         i2c1: i2c@ff660000 {
 514                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 515                 reg = <0x0 0xff660000 0x0 0x1000>;
 516                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 517                 #address-cells = <1>;
 518                 #size-cells = <0>;
 519                 clock-names = "i2c";
 520                 clocks = <&cru PCLK_I2C1>;
 521                 pinctrl-names = "default";
 522                 pinctrl-0 = <&i2c1_xfer>;
 523                 status = "disabled";
 524         };
 525
 526         pwm0: pwm@ff680000 {
 527                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 528                 reg = <0x0 0xff680000 0x0 0x10>;
 529                 #pwm-cells = <3>;
 530                 pinctrl-names = "default";
 531                 pinctrl-0 = <&pwm0_pin>;
 532                 clocks = <&cru PCLK_RKPWM>;
 533                 clock-names = "pwm";
 534                 status = "disabled";
 535         };
 536
 537         pwm1: pwm@ff680010 {
 538                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 539                 reg = <0x0 0xff680010 0x0 0x10>;
 540                 #pwm-cells = <3>;
 541                 pinctrl-names = "default";
 542                 pinctrl-0 = <&pwm1_pin>;
 543                 clocks = <&cru PCLK_RKPWM>;
 544                 clock-names = "pwm";
 545                 status = "disabled";
 546         };
 547
 548         pwm2: pwm@ff680020 {
 549                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 550                 reg = <0x0 0xff680020 0x0 0x10>;
 551                 #pwm-cells = <3>;
 552                 clocks = <&cru PCLK_RKPWM>;
 553                 clock-names = "pwm";
 554                 status = "disabled";
 555         };
 556
 557         pwm3: pwm@ff680030 {
 558                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 559                 reg = <0x0 0xff680030 0x0 0x10>;
 560                 #pwm-cells = <3>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&pwm3_t2_pin>;
 563                 clocks = <&cru PCLK_RKPWM>;
 564                 clock-names = "pwm";
 565                 status = "disabled";
 566         };
 567
 568         uart2: serial@ff690000 {
 569                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 570                 reg = <0x0 0xff690000 0x0 0x100>;
 571                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 573                 clock-names = "baudclk", "apb_pclk";
 574                 reg-shift = <2>;
 575                 reg-io-width = <4>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&uart2_t1_xfer>;
 578                 status = "disabled";
 579         };
 580
 581         pmu: power-management@ff730000 {
 582                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 583                 reg = <0x0 0xff730000 0x0 0x1000>;
 584
 585                 power: power-controller {
 586                         status = "disabled";
 587                         compatible = "rockchip,rk3366-power-controller";
 588                         #power-domain-cells = <1>;
 589                         #address-cells = <1>;
 590                         #size-cells = <0>;
 591
 592                         /*
 593                          * Note: Although SCLK_* are the working clocks
 594                          * of device without including on the NOC, needed for
 595                          * synchronous reset.
 596                          *
 597                          * The clocks on the which NOC:
 598                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 599                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 600                          * ACLK_ISP is on ACLK_ISP_NIU.
 601                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 602                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 603                          *
 604                          * Which clock are device clocks:
 605                          *      clocks          devices
 606                          *      *_IEP           IEP:Image Enhancement Processor
 607                          *      *_ISP           ISP:Image Signal Processing
 608                          *      *_VOP*          VOP:Visual Output Processor
 609                          *      *_RGA           RGA
 610                          *      *_DPHY*         LVDS
 611                          *      *_HDMI          HDMI
 612                          *      *_MIPI_*        MIPI
 613                          */
 614                         pd_vio {
 615                                 reg = <RK3366_PD_VIO>;
 616                                 clocks = <&cru ACLK_IEP>,
 617                                          <&cru ACLK_ISP>,
 618                                          <&cru ACLK_RGA>,
 619                                          <&cru ACLK_HDCP>,
 620                                          <&cru ACLK_VOP_FULL>,
 621                                          <&cru ACLK_VOP_LITE>,
 622                                          <&cru ACLK_VOP_IEP>,
 623                                          <&cru DCLK_VOP_FULL>,
 624                                          <&cru DCLK_VOP_LITE>,
 625                                          <&cru HCLK_IEP>,
 626                                          <&cru HCLK_ISP>,
 627                                          <&cru HCLK_RGA>,
 628                                          <&cru HCLK_VOP_FULL>,
 629                                          <&cru HCLK_VOP_LITE>,
 630                                          <&cru HCLK_VIO_HDCPMMU>,
 631                                          <&cru PCLK_HDMI_CTRL>,
 632                                          <&cru PCLK_HDCP>,
 633                                          <&cru PCLK_MIPI_DSI0>,
 634                                          <&cru SCLK_VOP_FULL_PWM>,
 635                                          <&cru SCLK_HDCP>,
 636                                          <&cru SCLK_ISP>,
 637                                          <&cru SCLK_RGA>,
 638                                          <&cru SCLK_HDMI_CEC>,
 639                                          <&cru SCLK_HDMI_HDCP>;
 640                         };
 641
 642                         /*
 643                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 644                          * (video endecoder & decoder) clocks that on the
 645                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 646                          */
 647                         pd_vpu {
 648                                 reg = <RK3366_PD_VPU>;
 649                                 clocks = <&cru ACLK_VIDEO>,
 650                                          <&cru HCLK_VIDEO>;
 651                         };
 652
 653                         /*
 654                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 655                          * (video decoder) clocks that on the
 656                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 657                          */
 658                         pd_rkvdec {
 659                                 reg = <RK3366_PD_RKVDEC>;
 660                                 clocks = <&cru ACLK_RKVDEC>,
 661                                          <&cru HCLK_RKVDEC>;
 662                         };
 663
 664                         pd_video {
 665                                 reg = <RK3366_PD_VIDEO>;
 666                                 clocks = <&cru ACLK_VIDEO>,
 667                                          <&cru ACLK_RKVDEC>,
 668                                          <&cru HCLK_VIDEO>,
 669                                          <&cru HCLK_RKVDEC>,
 670                                          <&cru SCLK_HEVC_CABAC>,
 671                                          <&cru SCLK_HEVC_CORE>;
 672                         };
 673
 674                         /*
 675                          * Note: ACLK_GPU is the GPU clock,
 676                          * and on the ACLK_GPU_NIU (NOC).
 677                          */
 678                         pd_gpu {
 679                                 reg = <RK3366_PD_GPU>;
 680                                 clocks = <&cru ACLK_GPU>;
 681                         };
 682                 };
 683         };
 684
 685         pmugrf: syscon@ff738000 {
 686                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 687                 reg = <0x0 0xff738000 0x0 0x1000>;
 688
 689                 reboot-mode {
 690                         compatible = "syscon-reboot-mode";
 691                         offset = <0x200>;
 692                         mode-normal = <BOOT_NORMAL>;
 693                         mode-recovery = <BOOT_RECOVERY>;
 694                         mode-fastboot = <BOOT_FASTBOOT>;
 695                         mode-loader = <BOOT_LOADER>;
 696                 };
 697         };
 698
 699         amba {
 700                 compatible = "arm,amba-bus";
 701                 #address-cells = <2>;
 702                 #size-cells = <2>;
 703                 ranges;
 704
 705                 dmac_peri: dma-controller@ff250000 {
 706                         compatible = "arm,pl330", "arm,primecell";
 707                         reg = <0x0 0xff250000 0x0 0x4000>;
 708                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 709                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 710                         #dma-cells = <1>;
 711                         clocks = <&cru ACLK_DMAC_PERI>;
 712                         clock-names = "apb_pclk";
 713                         peripherals-req-type-burst;
 714                 };
 715
 716                 dmac_bus: dma-controller@ff600000 {
 717                         compatible = "arm,pl330", "arm,primecell";
 718                         reg = <0x0 0xff600000 0x0 0x4000>;
 719                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 720                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 721                         #dma-cells = <1>;
 722                         clocks = <&cru ACLK_DMAC_BUS>;
 723                         clock-names = "apb_pclk";
 724                         peripherals-req-type-burst;
 725                 };
 726         };
 727
 728         cru: clock-controller@ff760000 {
 729                 compatible = "rockchip,rk3366-cru";
 730                 reg = <0x0 0xff760000 0x0 0x1000>;
 731                 rockchip,grf = <&grf>;
 732                 #clock-cells = <1>;
 733                 #reset-cells = <1>;
 734                 assigned-clocks =
 735                         <&cru SCLK_WIFIDSP>, <&cru SCLK_32K>,
 736                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 737                         <&cru SCLK_I2S_8CH_SRC>, <&cru SCLK_I2S_2CH_SRC>,
 738                         <&cru SCLK_SPDIF_8CH_SRC>,
 739                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 740                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 741                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 742                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 743                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 744                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 745                         <&cru ACLK_PERI1>;
 746                 assigned-clock-rates =
 747                         <0>, <0>,
 748                         <0>, <0>,
 749                         <0>, <0>,
 750                         <0>,
 751                         <750000000>, <576000000>,
 752                         <594000000>, <594000000>,
 753                         <960000000>, <520000000>,
 754                         <375000000>, <288000000>,
 755                         <100000000>, <100000000>,
 756                         <288000000>, <288000000>,
 757                         <144000000>;
 758                 assigned-clock-parents =
 759                         <&cru SCLK_WIFI_WPLL>, <&cru SCLK_32K_INTR>,
 760                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>,
 761                         <&cru PLL_GPLL>, <&cru PLL_GPLL>,
 762                         <&cru PLL_GPLL>;
 763         };
 764
 765         grf: syscon@ff770000 {
 766                 compatible = "rockchip,rk3366-grf", "syscon", "simple-mfd";
 767                 reg = <0x0 0xff770000 0x0 0x1000>;
 768                 #address-cells = <1>;
 769                 #size-cells = <1>;
 770
 771                 u2phy: usb2-phy@700 {
 772                         compatible = "rockchip,rk3366-usb2phy";
 773                         reg = <0x700 0x2c>;
 774                         clocks = <&cru SCLK_OTG_PHY0>;
 775                         clock-names = "phyclk";
 776                         #clock-cells = <0>;
 777                         clock-output-names = "sclk_otgphy0_480m";
 778
 779                         u2phy_host: host-port {
 780                                 #phy-cells = <0>;
 781                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 782                                 interrupt-names = "linestate";
 783                                 status = "okay";
 784                         };
 785                 };
 786         };
 787
 788         wdt: watchdog@ff800000 {
 789                 compatible = "snps,dw-wdt";
 790                 reg = <0x0 0xff800000 0x0 0x100>;
 791                 clocks = <&cru PCLK_WDT>;
 792                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 793                 status = "disabled";
 794         };
 795
 796         spdif: spdif@ff880000 {
 797                 compatible = "rockchip,rk3366-spdif";
 798                 reg = <0x0 0xff880000 0x0 0x1000>;
 799                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 800                 dmas = <&dmac_bus 3>;
 801                 dma-names = "tx";
 802                 clock-names = "mclk", "hclk";
 803                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 804                 pinctrl-names = "default";
 805                 pinctrl-0 = <&spdif_bus>;
 806                 status = "disabled";
 807         };
 808
 809         i2s_2ch: i2s-2ch@ff890000 {
 810                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 811                 reg = <0x0 0xff890000 0x0 0x1000>;
 812                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 813                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 814                 dma-names = "tx", "rx";
 815                 clock-names = "i2s_clk", "i2s_hclk";
 816                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 817                 status = "disabled";
 818         };
 819
 820         i2s_8ch: i2s-8ch@ff898000 {
 821                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 822                 reg = <0x0 0xff898000 0x0 0x1000>;
 823                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 824                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 825                 dma-names = "tx", "rx";
 826                 clock-names = "i2s_clk", "i2s_hclk";
 827                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 828                 pinctrl-names = "default";
 829                 pinctrl-0 = <&i2s_8ch_bus>;
 830                 status = "disabled";
 831         };
 832
 833         fb: fb {
 834                 compatible = "rockchip,rk-fb";
 835                 rockchip,disp-mode = <DUAL>;
 836                 status = "disabled";
 837         };
 838
 839         rk_screen: screen {
 840                 compatible = "rockchip,screen";
 841                 status = "disabled";
 842         };
 843
 844         vop_lite: vop@ff8f0000 {
 845                 compatible = "rockchip,rk3366-lcdc-lite";
 846                 rockchip,grf = <&grf>;
 847                 rockchip,pwr18 = <0>;
 848                 rockchip,iommu-enabled = <1>;
 849                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 850                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 851                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 852                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 853                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 854                 reset-names = "axi", "ahb", "dclk";
 855                 status = "disabled";
 856         };
 857
 858         vopl_mmu: vopl-mmu {
 859                 dbgname = "vop";
 860                 compatible = "rockchip,vopl_mmu";
 861                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 862                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 863                 interrupt-names = "vopl_mmu";
 864                 status = "disabled";
 865         };
 866
 867         iep: iep@ff900000 {
 868                 compatible = "rockchip,iep";
 869                 iommu_enabled = <1>;
 870                 reg = <0x0 0xff900000 0x0 0x800>;
 871                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 873                 clock-names = "aclk_iep", "hclk_iep";
 874                 version = <2>;
 875                 status = "disabled";
 876         };
 877
 878         rga: rga@ff920000 {
 879                 compatible = "rockchip,rga2";
 880                 dev_mode = <1>;
 881                 reg = <0x0 0xff920000 0x0 0x1000>;
 882                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 883                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 884                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 885                 status = "disabled";
 886         };
 887
 888         vop_big: vop@ff930000 {
 889                 compatible = "rockchip,rk3366-lcdc-big";
 890                 rockchip,grf = <&grf>;
 891                 rockchip,prop = <PRMRY>;
 892                 rockchip,pwr18 = <0>;
 893                 rockchip,iommu-enabled = <1>;
 894                 reg = <0x0 0xff930000 0x0 0x23f0>;
 895                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 896                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 897                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 898                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 899                 reset-names = "axi", "ahb", "dclk";
 900                 status = "disabled";
 901         };
 902
 903         vopb_mmu: vopb-mmu {
 904                 dbgname = "vop";
 905                 compatible = "rockchip,vopb_mmu";
 906                 reg = <0x0 0xff932400 0x0 0x100>;
 907                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 908                 interrupt-names = "vop_mmu";
 909                 status = "disabled";
 910         };
 911
 912         iep_mmu: iep-mmu {
 913                 dbgname = "iep";
 914                 compatible = "rockchip,iep_mmu";
 915                 reg = <0x0 0xff900800 0x0 0x100>;
 916                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 917                 interrupt-names = "iep_mmu";
 918                 status = "disabled";
 919         };
 920
 921         vpu_mmu: vpu_mmu {
 922                 dbgname = "vpu";
 923                 compatible = "rockchip,vpu_mmu";
 924                 reg = <0x0 0xff9a0800 0x0 0x100>;
 925                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 926                 interrupt-names = "vpu_mmu";
 927                 status = "disabled";
 928         };
 929
 930         vdec_mmu: vdec_mmu {
 931                 dbgname = "vdec";
 932                 compatible = "rockchip,vdec_mmu";
 933                 reg = <0x0 0xff9b0480 0x0 0x40>,
 934                       <0x0 0xff9b04c0 0x0 0x40>;
 935                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 936                 interrupt-names = "vdec_mmu";
 937                 status = "disabled";
 938         };
 939
 940         dsihost0: mipi@ff960000 {
 941                 compatible = "rockchip,rk3366-dsi";
 942                 rockchip,prop = <0>;
 943                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 944                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 945                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 946                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 947                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 948                 status = "disabled";
 949         };
 950
 951         lvds: lvds@ff968000 {
 952                 compatible = "rockchip,rk3366-lvds";
 953                 rockchip,grf = <&grf>;
 954                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 955                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 956                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 957                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 958                 status = "disabled";
 959         };
 960
 961         hdmi: hdmi@ff980000 {
 962                 compatible = "rockchip,rk3366-hdmi";
 963                 reg = <0x0 0xff980000 0x0 0x20000>;
 964                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 965                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 966                 clocks = <&cru PCLK_HDMI_CTRL>,
 967                          <&cru SCLK_HDMI_HDCP>,
 968                          <&cru SCLK_HDMI_CEC>,
 969                          <&cru DCLK_HDMIPHY>;
 970                 clock-names = "pclk_hdmi",
 971                               "hdcp_clk_hdmi",
 972                               "cec_clk_hdmi",
 973                               "dclk_hdmi_phy";
 974                 resets = <&cru SRST_HDMI>;
 975                 reset-names = "hdmi";
 976                 pinctrl-names = "default", "gpio";
 977                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 978                 pinctrl-1 = <&i2c5_gpio>;
 979                 status = "disabled";
 980         };
 981
 982         vpu: vpu_service@ff9a0000 {
 983                 compatible = "rockchip,vpu_service";
 984                 rockchip,grf = <&grf>;
 985                 iommu_enabled = <1>;
 986                 reg = <0x0 0xff9a0000 0x0 0x800>;
 987                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 988                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 989                 interrupt-names = "irq_dec", "irq_enc";
 990                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 991                 clock-names = "aclk_vcodec", "hclk_vcodec";
 992                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 993                 reset-names = "video_h", "video_a";
 994                 name = "vpu_service";
 995                 dev_mode = <0>;
 996                 status = "disabled";
 997         };
 998
 999         rkvdec: rkvdec@ff9b0000 {
1000                 compatible = "rockchip,rkvdec";
1001                 rockchip,grf = <&grf>;
1002                 iommu_enabled = <1>;
1003                 reg = <0x0 0xff9b0000 0x0 0x400>;
1004                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1005                 interrupt-names = "irq_dec";
1006                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
1007                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
1008                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
1009                 reset-names = "video_h", "video_a";
1010                 dev_mode = <2>;
1011                 name = "rkvdec";
1012                 status = "disabled";
1013         };
1014
1015         pinctrl: pinctrl {
1016                 compatible = "rockchip,rk3366-pinctrl";
1017                 rockchip,grf = <&grf>;
1018                 rockchip,pmu = <&pmugrf>;
1019                 #address-cells = <0x2>;
1020                 #size-cells = <0x2>;
1021                 ranges;
1022
1023                 gpio0: gpio0@ff750000 {
1024                         compatible = "rockchip,gpio-bank";
1025                         reg = <0x0 0xff750000 0x0 0x100>;
1026                         clocks = <&cru PCLK_GPIO0>;
1027                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1028
1029                         gpio-controller;
1030                         #gpio-cells = <0x2>;
1031
1032                         interrupt-controller;
1033                         #interrupt-cells = <0x2>;
1034                 };
1035
1036                 gpio1: gpio1@ff780000 {
1037                         compatible = "rockchip,gpio-bank";
1038                         reg = <0x0 0xff758000 0x0 0x100>;
1039                         clocks = <&cru PCLK_GPIO1>;
1040                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1041
1042                         gpio-controller;
1043                         #gpio-cells = <0x2>;
1044
1045                         interrupt-controller;
1046                         #interrupt-cells = <0x2>;
1047                 };
1048
1049                 gpio2: gpio2@ff790000 {
1050                         compatible = "rockchip,gpio-bank";
1051                         reg = <0x0 0xff790000 0x0 0x100>;
1052                         clocks = <&cru PCLK_GPIO2>;
1053                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1054
1055                         gpio-controller;
1056                         #gpio-cells = <0x2>;
1057
1058                         interrupt-controller;
1059                         #interrupt-cells = <0x2>;
1060                 };
1061
1062                 gpio3: gpio3@ff7a0000 {
1063                         compatible = "rockchip,gpio-bank";
1064                         reg = <0x0 0xff7a0000 0x0 0x100>;
1065                         clocks = <&cru PCLK_GPIO3>;
1066                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1067
1068                         gpio-controller;
1069                         #gpio-cells = <0x2>;
1070
1071                         interrupt-controller;
1072                         #interrupt-cells = <0x2>;
1073                 };
1074
1075                 gpio4: gpio4@ff7b0000 {
1076                         compatible = "rockchip,gpio-bank";
1077                         reg = <0x0 0xff7b0000 0x0 0x100>;
1078                         clocks = <&cru PCLK_GPIO4>;
1079                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1080
1081                         gpio-controller;
1082                         #gpio-cells = <0x2>;
1083
1084                         interrupt-controller;
1085                         #interrupt-cells = <0x2>;
1086                 };
1087
1088                 gpio5: gpio5@ff7c0000 {
1089                         compatible = "rockchip,gpio-bank";
1090                         reg = <0x0 0xff7c0000 0x0 0x100>;
1091                         clocks = <&cru PCLK_GPIO5>;
1092                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1093
1094                         gpio-controller;
1095                         #gpio-cells = <0x2>;
1096
1097                         interrupt-controller;
1098                         #interrupt-cells = <0x2>;
1099                 };
1100
1101                 pcfg_pull_up: pcfg-pull-up {
1102                         bias-pull-up;
1103                 };
1104
1105                 pcfg_pull_down: pcfg-pull-down {
1106                         bias-pull-down;
1107                 };
1108
1109                 pcfg_pull_none: pcfg-pull-none {
1110                         bias-disable;
1111                 };
1112
1113                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1114                         bias-disable;
1115                         drive-strength = <12>;
1116                 };
1117
1118                 emmc {
1119                         emmc_clk: emmc-clk {
1120                                 rockchip,pins =
1121                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1122                         };
1123
1124                         emmc_cmd: emmc-cmd {
1125                                 rockchip,pins =
1126                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1127                         };
1128
1129                         emmc_pwr: emmc-pwr {
1130                                 rockchip,pins =
1131                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1132                         };
1133
1134                         emmc_bus1: emmc-bus1 {
1135                                 rockchip,pins =
1136                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1137                         };
1138
1139                         emmc_bus4: emmc-bus4 {
1140                                 rockchip,pins =
1141                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1142                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1143                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1144                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1145                         };
1146
1147                         emmc_bus8: emmc-bus8 {
1148                                 rockchip,pins =
1149                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1150                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1151                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1152                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1153                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1154                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1155                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1156                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1157                         };
1158                 };
1159
1160                 sdmmc {
1161                         sdmmc_cd: sdmmc-cd {
1162                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1163                         };
1164
1165                         sdmmc_bus1: sdmmc-bus1 {
1166                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1167                         };
1168
1169                         sdmmc_bus4: sdmmc-bus4 {
1170                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1171                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1172                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1173                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1174                         };
1175
1176                         sdmmc_clk: sdmmc-clk {
1177                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1178                         };
1179
1180                         sdmmc_cmd: sdmmc-cmd {
1181                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1182                         };
1183                 };
1184
1185                 sdio {
1186                         sdio_bus1: sdio-bus1 {
1187                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1188                         };
1189
1190                         sdio_bus4: sdio-bus4 {
1191                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1192                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1193                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1194                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1195                         };
1196
1197                         sdio_cmd: sdio-cmd {
1198                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1199                         };
1200
1201                         sdio_clk: sdio-clk {
1202                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204
1205                         sdio_cd: sdio-cd {
1206                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1207                         };
1208
1209                         sdio_wp: sdio-wp {
1210                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1211                         };
1212
1213                         sdio_int: sdio-int {
1214                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1215                         };
1216
1217                         sdio_pwr: sdio-pwr {
1218                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1219                         };
1220                 };
1221
1222                 hdmi_i2c {
1223                         hdmii2c_xfer: hdmii2c-xfer {
1224                                 rockchip,pins =
1225                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1226                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 hdmi_pin {
1231                         hdmi_cec: hdmi-cec {
1232                                 rockchip,pins =
1233                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1234                         };
1235                 };
1236
1237                 i2c0 {
1238                         i2c0_xfer: i2c0-xfer {
1239                                 rockchip,pins =
1240                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1241                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1242                         };
1243                 };
1244
1245                 i2c1 {
1246                         i2c1_xfer: i2c1-xfer {
1247                                 rockchip,pins =
1248                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1249                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1250                         };
1251                 };
1252
1253                 i2c2 {
1254                         i2c2_xfer: i2c2-xfer {
1255                                 rockchip,pins =
1256                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1257                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1258                         };
1259
1260                         i2c2_gpio: i2c2-gpio {
1261                                 rockchip,pins =
1262                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1263                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1264                         };
1265                 };
1266
1267                 i2c3 {
1268                         i2c3_xfer: i2c3-xfer {
1269                                 rockchip,pins =
1270                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1271                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1272                         };
1273                 };
1274
1275                 i2c4 {
1276                         i2c4_xfer: i2c4-xfer {
1277                                 rockchip,pins =
1278                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1279                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1280                         };
1281
1282                         i2c4_gpio: i2c4-gpio {
1283                                 rockchip,pins =
1284                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1285                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1286                         };
1287                 };
1288
1289                 i2c5 {
1290                         i2c5_xfer: i2c5-xfer {
1291                                 rockchip,pins =
1292                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1293                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1294                         };
1295                         i2c5_gpio: i2c5-gpio {
1296                                 rockchip,pins =
1297                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1298                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1299                         };
1300                 };
1301
1302                 i2s {
1303                         i2s_8ch_bus: i2s-8ch-bus {
1304                                 rockchip,pins =
1305                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1306                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1307                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1308                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1309                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1310                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1311                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1312                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1313                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1314                         };
1315                 };
1316
1317                 spdif {
1318                         spdif_bus: spdif-bus {
1319                                 rockchip,pins =
1320                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1321                         };
1322                 };
1323
1324                 spi0 {
1325                         spi0_clk: spi0-clk {
1326                                 rockchip,pins =
1327                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1328                         };
1329                         spi0_cs0: spi0-cs0 {
1330                                 rockchip,pins =
1331                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1332                         };
1333                         spi0_cs1: spi0-cs1 {
1334                                 rockchip,pins =
1335                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1336                         };
1337                         spi0_tx: spi0-tx {
1338                                 rockchip,pins =
1339                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1340                         };
1341                         spi0_rx: spi0-rx {
1342                                 rockchip,pins =
1343                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1344                         };
1345                 };
1346
1347                 spi1 {
1348                         spi1_clk: spi1-clk {
1349                                 rockchip,pins =
1350                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1351                         };
1352                         spi1_cs0: spi1-cs0 {
1353                                 rockchip,pins =
1354                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1355                         };
1356                         spi1_tx: spi1-tx {
1357                                 rockchip,pins =
1358                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1359                         };
1360                         spi1_rx: spi1-rx {
1361                                 rockchip,pins =
1362                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1363                         };
1364                 };
1365
1366                 scr {
1367                         scr_clk: scr-clk {
1368                                 rockchip,pins =
1369                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1370                         };
1371
1372                         scr_io: scr-io {
1373                                 rockchip,pins =
1374                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1375                         };
1376
1377                         scr_rst: scr-rst {
1378                                 rockchip,pins =
1379                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1380                         };
1381
1382                         scr_detect: scr-detect {
1383                                 rockchip,pins =
1384                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1385                         };
1386                 };
1387
1388                 uart0 {
1389                         uart0_xfer: uart0-xfer {
1390                                 rockchip,pins =
1391                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1392                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1393                         };
1394
1395                         uart0_cts: uart0-cts {
1396                                 rockchip,pins =
1397                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1398                         };
1399
1400                         uart0_rts: uart0-rts {
1401                                 rockchip,pins =
1402                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1403                         };
1404                 };
1405
1406                 uart2_t0 {
1407                         uart2_t0_xfer: uart2_t0-xfer {
1408                                 rockchip,pins =
1409                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1410                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1411                         };
1412                         /* no rts / cts for uart2 */
1413                 };
1414
1415                 uart2_t1 {
1416                         uart2_t1_xfer: uart2_t1-xfer {
1417                                 rockchip,pins =
1418                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1419                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1420                         };
1421                         /* no rts / cts for uart2 */
1422                 };
1423
1424                 uart2_t2 {
1425                         uart2_t2_xfer: uart2_t2-xfer {
1426                                 rockchip,pins =
1427                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1428                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1429                         };
1430                         /* no rts / cts for uart2 */
1431                 };
1432
1433                 uart3 {
1434                         uart3_xfer: uart3-xfer {
1435                                 rockchip,pins =
1436                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1437                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1438                         };
1439
1440                         uart3_cts: uart3-cts {
1441                                 rockchip,pins =
1442                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1443                         };
1444
1445                         uart3_rts: uart3-rts {
1446                                 rockchip,pins =
1447                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 pwm0 {
1452                         pwm0_pin: pwm0-pin {
1453                                 rockchip,pins =
1454                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1455                         };
1456                 };
1457
1458                 pwm1 {
1459                         pwm1_pin: pwm1-pin {
1460                                 rockchip,pins =
1461                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1462                         };
1463                 };
1464
1465                 pwm2_t0 {
1466                         pwm2_t0_pin: pwm2_t0-pin {
1467                                 rockchip,pins =
1468                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1469                         };
1470                 };
1471
1472                 pwm2_t1 {
1473                         pwm2_t1_pin: pwm2_t1-pin {
1474                                 rockchip,pins =
1475                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1476                         };
1477                 };
1478
1479                 pwm3_t0 {
1480                         pwm3_t0_pin: pwm3_t0-pin {
1481                                 rockchip,pins =
1482                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1483                         };
1484                 };
1485
1486                 pwm3_t1 {
1487                         pwm3_t1_pin: pwm3_t1-pin {
1488                                 rockchip,pins =
1489                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1490                         };
1491                 };
1492
1493                 pwm3_t2 {
1494                         pwm3_t2_pin: pwm3_t2-pin {
1495                                 rockchip,pins =
1496                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1497                         };
1498                 };
1499
1500                 lcdc {
1501                         lcdc_lcdc: lcdc-lcdc {
1502                                 rockchip,pins =
1503                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1504                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1505                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1506                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1507                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1508                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1509                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1510                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1511                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1512                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1513                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1514                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1515                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1516                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1517                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1518                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1519                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1520                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1521                         };
1522
1523                         lcdc_gpio: lcdc-gpio {
1524                                 rockchip,pins =
1525                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1526                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1527                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1528                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1529                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1530                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1531                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1532                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1533                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1534                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1535                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1536                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1537                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1538                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1539                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1540                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1541                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1542                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1543                         };
1544                 };
1545
1546                 gmac {
1547                         rgmii_pins: rgmii-pins {
1548                                 rockchip,pins =
1549                                         /* mac_rxd3 */
1550                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1551                                         /* mac_rxd2 */
1552                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1553                                         /* mac_txd3 */
1554                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1555                                         /* mac_txd2 */
1556                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1557                                         /* mac_rxd1 */
1558                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1559                                         /* mac_rxd0 */
1560                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1561                                         /* mac_txd1 */
1562                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1563                                         /* mac_txd0 */
1564                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1565                                         /* mac_txclkout */
1566                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1567                                         /* mac_crs */
1568                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1569                                         /* mac_rxclkin */
1570                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1571                                         /* mac_mdio */
1572                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1573                                         /* mac_txen */
1574                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1575                                         /* mac_clk */
1576                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1577                                         /* mac_rxer */
1578                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1579                                         /* mac_rxdv */
1580                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1581                                         /* mac_mdc */
1582                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1583                         };
1584
1585                         rmii_pins: rmii-pins {
1586                                 rockchip,pins =
1587                                         /* mac_rxd1 */
1588                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1589                                         /* mac_rxd0 */
1590                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1591                                         /* mac_txd1 */
1592                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1593                                         /* mac_txd0 */
1594                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1595                                         /* mac_crs */
1596                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1597                                         /* mac_rxclkin */
1598                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1599                                         /* mac_mdio */
1600                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1601                                         /* mac_txen */
1602                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1603                                         /* mac_clk */
1604                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1605                                         /* mac_rxer */
1606                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1607                                         /* mac_rxdv */
1608                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1609                                         /* mac_mdc */
1610                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1611                         };
1612                 };
1613
1614                 eth_phy {
1615                         eth_phy_pwr: eth-phy-pwr {
1616                                 rockchip,pins =
1617                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1618                         };
1619                 };
1620
1621                 tsadc_pin {
1622                         tsadc_gpio: tsadc-gpio {
1623                                 rockchip,pins =
1624                                         <0 22 RK_FUNC_GPIO &pcfg_pull_none>;
1625                         };
1626
1627                         tsadc_int: tsadc-int {
1628                                 rockchip,pins =
1629                                         <0 22 RK_FUNC_2 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 usb2 {
1634                         host_vbus_drv: host-vbus-drv {
1635                                 rockchip,pins =
1636                                         <0 16 RK_FUNC_GPIO &pcfg_pull_none>;
1637                         };
1638                 };
1639
1640         };
1641
1642         gpu: gpu@ffa30000 {
1643                 compatible = "arm,malit764",
1644                              "arm,malit76x",
1645                              "arm,malit7xx",
1646                              "arm,mali-midgard";
1647
1648                 reg = <0x0 0xffa30000 0 0x10000>;
1649
1650                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1651                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1652                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1653                 interrupt-names = "GPU", "MMU", "JOB";
1654
1655                 clocks = <&cru ACLK_GPU>;
1656                 clock-names = "clk_mali";
1657                 #cooling-cells = <2>; /* min followed by max */
1658                 operating-points-v2 = <&gpu_opp_table>;
1659                 status = "disabled";
1660
1661                 power_model {
1662                         compatible = "arm,mali-simple-power-model";
1663                         voltage = <900>;
1664                         frequency = <500>;
1665                         static-power = <300>;
1666                         dynamic-power = <1780>;
1667                         ts = <32000 4700 (-80) 2>;
1668                         thermal-zone = "gpu-thermal";
1669                 };
1670         };
1671
1672         gpu_opp_table: gpu_opp_table {
1673                 compatible = "operating-points-v2";
1674                 opp-shared;
1675
1676                 opp@96000000 {
1677                         opp-hz = /bits/ 64 <96000000>;
1678                         opp-microvolt = <1100000>;
1679                 };
1680                 opp@192000000 {
1681                         opp-hz = /bits/ 64 <192000000>;
1682                         opp-microvolt = <1100000>;
1683                 };
1684                 opp@288000000 {
1685                         opp-hz = /bits/ 64 <288000000>;
1686                         opp-microvolt = <1100000>;
1687                 };
1688                 opp@375000000 {
1689                         opp-hz = /bits/ 64 <375000000>;
1690                         opp-microvolt = <1125000>;
1691                 };
1692                 opp@480000000 {
1693                         opp-hz = /bits/ 64 <480000000>;
1694                         opp-microvolt = <1200000>;
1695                 };
1696         };
1697 };