arch/arm64/boot/dts/rockchip/rk3366.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3366-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/display/rk_fb.h>
  49 #include <dt-bindings/power/rk3366-power.h>
  50 #include <dt-bindings/soc/rockchip_boot-mode.h>
  51
  52 / {
  53         compatible = "rockchip,rk3366";
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial2 = &uart2;
  67                 serial3 = &uart3;
  68                 spi0 = &spi0;
  69                 spi1 = &spi1;
  70         };
  71
  72         cpus {
  73                 #address-cells = <0x2>;
  74                 #size-cells = <0x0>;
  75
  76                 cpu0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a53","arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         clocks = <&cru ARMCLK>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                 };
  84
  85                 cpu1: cpu@1 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53","arm,armv8";
  88                         reg = <0x0 0x1>;
  89                         enable-method = "psci";
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                 };
  92
  93                 cpu2: cpu@2 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a53","arm,armv8";
  96                         reg = <0x0 0x2>;
  97                         enable-method = "psci";
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                 };
 100
 101                 cpu3: cpu@3 {
 102                         device_type = "cpu";
 103                         compatible = "arm,cortex-a53","arm,armv8";
 104                         reg = <0x0 0x3>;
 105                         enable-method = "psci";
 106                         operating-points-v2 = <&cpu0_opp_table>;
 107                 };
 108         };
 109
 110         cpu0_opp_table: opp_table0 {
 111                 compatible = "operating-points-v2";
 112                 opp-shared;
 113
 114                 opp00 {
 115                         opp-hz = /bits/ 64 <408000000>;
 116                         opp-microvolt = <950000>;
 117                         clock-latency-ns = <40000>;
 118                         opp-suspend;
 119                 };
 120                 opp01 {
 121                         opp-hz = /bits/ 64 <600000000>;
 122                         opp-microvolt = <950000>;
 123                 };
 124                 opp02 {
 125                         opp-hz = /bits/ 64 <816000000>;
 126                         opp-microvolt = <1000000>;
 127                 };
 128                 opp03 {
 129                         opp-hz = /bits/ 64 <1008000000>;
 130                         opp-microvolt = <1075000>;
 131                 };
 132                 opp04 {
 133                         opp-hz = /bits/ 64 <1200000000>;
 134                         opp-microvolt = <1175000>;
 135                 };
 136                 opp05 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1250000>;
 139                 };
 140         };
 141
 142         psci {
 143                 compatible = "arm,psci-1.0";
 144                 method = "smc";
 145         };
 146
 147         timer {
 148                 compatible = "arm,armv8-timer";
 149                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 150                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 151                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 152                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 153         };
 154
 155         arm-pmu {
 156                 compatible = "arm,cortex-a53-pmu";
 157                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 158                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 159                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 160                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 161                 interrupt-affinity = <&cpu0>,
 162                                      <&cpu1>,
 163                                      <&cpu2>,
 164                                      <&cpu3>;
 165         };
 166
 167         xin24m: xin24m {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170                 clock-frequency = <24000000>;
 171                 clock-output-names = "xin24m";
 172         };
 173
 174         gic: interrupt-controller@ffb71000 {
 175                 compatible = "arm,gic-400";
 176                 interrupt-controller;
 177                 #interrupt-cells = <3>;
 178                 #address-cells = <0>;
 179
 180                 reg = <0x0 0xffb71000 0x0 0x1000>,
 181                       <0x0 0xffb72000 0x0 0x1000>,
 182                       <0x0 0xffb74000 0x0 0x2000>,
 183                       <0x0 0xffb76000 0x0 0x2000>;
 184                 interrupts = <GIC_PPI 9
 185                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 186         };
 187
 188         nandc0: nandc@ff0c0000 {
 189                 compatible = "rockchip,rk-nandc";
 190                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 191                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 192                 nandc_id = <0>;
 193                 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
 194                 clock-names = "clk_nandc", "hclk_nandc";
 195                 status = "disabled";
 196         };
 197
 198         saradc: saradc@ff100000 {
 199                 compatible = "rockchip,saradc";
 200                 reg = <0x0 0xff100000 0x0 0x100>;
 201                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 202                 #io-channel-cells = <1>;
 203                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 204                 clock-names = "saradc", "apb_pclk";
 205                 status = "disabled";
 206         };
 207
 208         spi0: spi@ff110000 {
 209                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 210                 reg = <0x0 0xff110000 0x0 0x1000>;
 211                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 212                 clock-names = "spiclk", "apb_pclk";
 213                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 214                 pinctrl-names = "default";
 215                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 216                 #address-cells = <1>;
 217                 #size-cells = <0>;
 218                 status = "disabled";
 219         };
 220
 221         spi1: spi@ff120000 {
 222                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 223                 reg = <0x0 0xff120000 0x0 0x1000>;
 224                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 225                 clock-names = "spiclk", "apb_pclk";
 226                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 227                 pinctrl-names = "default";
 228                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 229                 #address-cells = <1>;
 230                 #size-cells = <0>;
 231                 status = "disabled";
 232         };
 233
 234         scr: rkscr@ff1d0000 {
 235                 compatible = "rockchip-scr";
 236                 reg = <0x0 0xff1d0000 0x0 0x10000>;
 237                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&scr_io &scr_detect &scr_rst &scr_clk>;
 242                 clocks = <&cru PCLK_SIM>;
 243                 clock-names = "g_pclk_sim_card";
 244                 status = "disabled";
 245         };
 246
 247         sdmmc: rksdmmc@ff400000 {
 248                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 249                 clock-freq-min-max = <400000 150000000>;
 250                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 251                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 252                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 253                 fifo-depth = <0x100>;
 254                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 255                 reg = <0x0 0xff400000 0x0 0x4000>;
 256                 status = "disabled";
 257         };
 258
 259         sdio: rksdmmc@ff410000 {
 260                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 261                 clock-freq-min-max = <400000 150000000>;
 262                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO0>,
 263                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 264                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 265                 fifo-depth = <0x100>;
 266                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 267                 reg = <0x0 0xff410000 0x0 0x4000>;
 268                 status = "disabled";
 269         };
 270
 271         emmc: rksdmmc@ff420000 {
 272                 compatible = "rockchip,rk3366-dw-mshc","rockchip,rk3288-dw-mshc";
 273                 clock-freq-min-max = <400000 150000000>;
 274                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 275                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 276                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 277                 fifo-depth = <0x100>;
 278                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 279                 reg = <0x0 0xff420000 0x0 0x4000>;
 280                 status = "disabled";
 281         };
 282
 283         gmac: eth@ff440000 {
 284                 compatible = "rockchip,rk3366-gmac";
 285                 reg = <0x0 0xff440000 0x0 0x10000>;
 286                 rockchip,grf = <&grf>;
 287                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 288                 interrupt-names = "macirq";
 289                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 290                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 291                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 292                          <&cru PCLK_GMAC>;
 293                 clock-names = "stmmaceth", "mac_clk_rx",
 294                               "mac_clk_tx", "clk_mac_ref",
 295                               "clk_mac_refout", "aclk_mac",
 296                               "pclk_mac";
 297                 resets = <&cru SRST_MAC>;
 298                 reset-names = "stmmaceth";
 299                 status = "disabled";
 300         };
 301
 302         i2c0: i2c@ff650000 {
 303                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 304                 reg = <0x0 0xff728000 0x0 0x1000>;
 305                 clocks = <&cru PCLK_I2C0>;
 306                 clock-names = "i2c";
 307                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 308                 pinctrl-names = "default";
 309                 pinctrl-0 = <&i2c0_xfer>;
 310                 #address-cells = <1>;
 311                 #size-cells = <0>;
 312                 status = "disabled";
 313         };
 314
 315         i2c2: i2c@ff140000 {
 316                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 317                 reg = <0x0 0xff140000 0x0 0x1000>;
 318                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 clock-names = "i2c";
 322                 clocks = <&cru PCLK_I2C2>;
 323                 pinctrl-names = "default";
 324                 pinctrl-0 = <&i2c2_xfer>;
 325                 status = "disabled";
 326         };
 327
 328         i2c3: i2c@ff150000 {
 329                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 330                 reg = <0x0 0xff150000 0x0 0x1000>;
 331                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 332                 #address-cells = <1>;
 333                 #size-cells = <0>;
 334                 clock-names = "i2c";
 335                 clocks = <&cru PCLK_I2C3>;
 336                 pinctrl-names = "default";
 337                 pinctrl-0 = <&i2c3_xfer>;
 338                 status = "disabled";
 339         };
 340
 341         i2c4: i2c@ff160000 {
 342                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 343                 reg = <0x0 0xff160000 0x0 0x1000>;
 344                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 clock-names = "i2c";
 348                 clocks = <&cru PCLK_I2C4>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&i2c4_xfer>;
 351                 status = "disabled";
 352         };
 353
 354         i2c5: i2c@ff170000 {
 355                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 356                 reg = <0x0 0xff170000 0x0 0x1000>;
 357                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 clock-names = "i2c";
 361                 clocks = <&cru PCLK_I2C5>;
 362                 pinctrl-names = "default";
 363                 pinctrl-0 = <&i2c5_xfer>;
 364                 status = "disabled";
 365         };
 366
 367         uart0: serial@ff180000 {
 368                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 369                 reg = <0x0 0xff180000 0x0 0x100>;
 370                 clock-frequency = <24000000>;
 371                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 372                 clock-names = "baudclk", "apb_pclk";
 373                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 374                 reg-shift = <2>;
 375                 reg-io-width = <4>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 378                 status = "disabled";
 379         };
 380
 381         uart3: serial@ff1b0000 {
 382                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 383                 reg = <0x0 0xff1b0000 0x0 0x100>;
 384                 clock-frequency = <24000000>;
 385                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 386                 clock-names = "baudclk", "apb_pclk";
 387                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 388                 reg-shift = <2>;
 389                 reg-io-width = <4>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
 392                 status = "disabled";
 393         };
 394
 395         usbphy: phy {
 396                 compatible = "rockchip,rk336x-usb-phy";
 397                 rockchip,grf = <&grf>;
 398                 #address-cells = <1>;
 399                 #size-cells = <0>;
 400
 401                 usbphy0: usb-phy0 {
 402                         #phy-cells = <0>;
 403                         #clock-cells = <0>;
 404                         reg = <0x700>;
 405                 };
 406
 407                 usbphy1: usb-phy1 {
 408                         #phy-cells = <0>;
 409                         #clock-cells = <0>;
 410                         reg = <0x728>;
 411                 };
 412         };
 413
 414         usb_host0_echi: usb@ff480000 {
 415                 compatible = "generic-ehci";
 416                 reg = <0x0 0xff480000 0x0 0x20000>;
 417                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 418                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 419                 clock-names = "sclk_otgphy0", "hclk_host0";
 420                 phys = <&usbphy1>;
 421                 phy-names = "usb";
 422                 status = "disabled";
 423         };
 424
 425         usb_host0_ohci: usb@ff4a0000 {
 426                 compatible = "generic-ohci";
 427                 reg = <0x0 0xff4a0000 0x0 0x20000>;
 428                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 429                 clocks = <&cru SCLK_OTG_PHY0>, <&cru HCLK_HOST>;
 430                 clock-names = "sclk_otgphy0", "hclk_host0";
 431                 status = "disabled";
 432         };
 433
 434         usb_otg: usb@ff4c0000 {
 435                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 436                              "snps,dwc2";
 437                 reg = <0x0 0xff4c0000 0x0 0x40000>;
 438                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 439                 clocks = <&cru HCLK_OTG>;
 440                 clock-names = "otg";
 441                 dr_mode = "otg";
 442                 g-np-tx-fifo-size = <16>;
 443                 g-rx-fifo-size = <275>;
 444                 g-tx-fifo-size = <256 128 128 64 64 32>;
 445                 g-use-dma;
 446                 status = "disabled";
 447         };
 448
 449         i2c1: i2c@ff660000 {
 450                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 451                 reg = <0x0 0xff660000 0x0 0x1000>;
 452                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 clock-names = "i2c";
 456                 clocks = <&cru PCLK_I2C1>;
 457                 pinctrl-names = "default";
 458                 pinctrl-0 = <&i2c1_xfer>;
 459                 status = "disabled";
 460         };
 461
 462         pwm0: pwm@ff680000 {
 463                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 464                 reg = <0x0 0xff680000 0x0 0x10>;
 465                 #pwm-cells = <3>;
 466                 pinctrl-names = "default";
 467                 pinctrl-0 = <&pwm0_pin>;
 468                 clocks = <&cru PCLK_RKPWM>;
 469                 clock-names = "pwm";
 470                 status = "disabled";
 471         };
 472
 473         pwm1: pwm@ff680010 {
 474                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 475                 reg = <0x0 0xff680010 0x0 0x10>;
 476                 #pwm-cells = <3>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&pwm1_pin>;
 479                 clocks = <&cru PCLK_RKPWM>;
 480                 clock-names = "pwm";
 481                 status = "disabled";
 482         };
 483
 484         pwm2: pwm@ff680020 {
 485                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 486                 reg = <0x0 0xff680020 0x0 0x10>;
 487                 #pwm-cells = <3>;
 488                 clocks = <&cru PCLK_RKPWM>;
 489                 clock-names = "pwm";
 490                 status = "disabled";
 491         };
 492
 493         pwm3: pwm@ff680030 {
 494                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 495                 reg = <0x0 0xff680030 0x0 0x10>;
 496                 #pwm-cells = <3>;
 497                 pinctrl-names = "default";
 498                 pinctrl-0 = <&pwm3_t2_pin>;
 499                 clocks = <&cru PCLK_RKPWM>;
 500                 clock-names = "pwm";
 501                 status = "disabled";
 502         };
 503
 504         uart2: serial@ff690000 {
 505                 compatible = "rockchip,rk3366-uart", "snps,dw-apb-uart";
 506                 reg = <0x0 0xff690000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 508                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 509                 clock-names = "baudclk", "apb_pclk";
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&uart2_t1_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         pmu: power-management@ff730000 {
 518                 compatible = "rockchip,rk3366-pmu", "syscon", "simple-mfd";
 519                 reg = <0x0 0xff730000 0x0 0x1000>;
 520
 521                 power: power-controller {
 522                         status = "disabled";
 523                         compatible = "rockchip,rk3366-power-controller";
 524                         #power-domain-cells = <1>;
 525                         #address-cells = <1>;
 526                         #size-cells = <0>;
 527
 528                         /*
 529                          * Note: Although SCLK_* are the working clocks
 530                          * of device without including on the NOC, needed for
 531                          * synchronous reset.
 532                          *
 533                          * The clocks on the which NOC:
 534                          * ACLK_IEP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 535                          * ACLK_RGA/ACLK_VOP1 are on ACLK_RGA_NIU.
 536                          * ACLK_ISP is on ACLK_ISP_NIU.
 537                          * ACLK_HDCP is on ACLK_HDCP_NIU.
 538                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 539                          *
 540                          * Which clock are device clocks:
 541                          *      clocks          devices
 542                          *      *_IEP           IEP:Image Enhancement Processor
 543                          *      *_ISP           ISP:Image Signal Processing
 544                          *      *_VOP*          VOP:Visual Output Processor
 545                          *      *_RGA           RGA
 546                          *      *_DPHY*         LVDS
 547                          *      *_HDMI          HDMI
 548                          *      *_MIPI_*        MIPI
 549                          */
 550                         pd_vio {
 551                                 reg = <RK3366_PD_VIO>;
 552                                 clocks = <&cru ACLK_IEP>,
 553                                          <&cru ACLK_ISP>,
 554                                          <&cru ACLK_RGA>,
 555                                          <&cru ACLK_HDCP>,
 556                                          <&cru ACLK_VOP_FULL>,
 557                                          <&cru ACLK_VOP_LITE>,
 558                                          <&cru ACLK_VOP_IEP>,
 559                                          <&cru DCLK_VOP_FULL>,
 560                                          <&cru DCLK_VOP_LITE>,
 561                                          <&cru HCLK_IEP>,
 562                                          <&cru HCLK_ISP>,
 563                                          <&cru HCLK_RGA>,
 564                                          <&cru HCLK_VOP_FULL>,
 565                                          <&cru HCLK_VOP_LITE>,
 566                                          <&cru HCLK_VIO_HDCPMMU>,
 567                                          <&cru PCLK_HDMI_CTRL>,
 568                                          <&cru PCLK_HDCP>,
 569                                          <&cru PCLK_MIPI_DSI0>,
 570                                          <&cru SCLK_VOP_FULL_PWM>,
 571                                          <&cru SCLK_HDCP>,
 572                                          <&cru SCLK_ISP>,
 573                                          <&cru SCLK_RGA>,
 574                                          <&cru SCLK_HDMI_CEC>,
 575                                          <&cru SCLK_HDMI_HDCP>;
 576                         };
 577
 578                         /*
 579                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 580                          * (video endecoder & decoder) clocks that on the
 581                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 582                          */
 583                         pd_vpu {
 584                                 reg = <RK3366_PD_VPU>;
 585                                 clocks = <&cru ACLK_VIDEO>,
 586                                          <&cru HCLK_VIDEO>;
 587                         };
 588
 589                         /*
 590                          * Note: ACLK_RKVDEC/HCLK_RKVDEC are RKVDEC
 591                          * (video decoder) clocks that on the
 592                          * ACLK_RKVDEC_NIU and HCLK_RKVDEC_NIU (NOC).
 593                          */
 594                         pd_rkvdec {
 595                                 reg = <RK3366_PD_RKVDEC>;
 596                                 clocks = <&cru ACLK_RKVDEC>,
 597                                          <&cru HCLK_RKVDEC>;
 598                         };
 599
 600                         pd_video {
 601                                 reg = <RK3366_PD_VIDEO>;
 602                                 clocks = <&cru ACLK_VIDEO>,
 603                                          <&cru ACLK_RKVDEC>,
 604                                          <&cru HCLK_VIDEO>,
 605                                          <&cru HCLK_RKVDEC>,
 606                                          <&cru SCLK_HEVC_CABAC>,
 607                                          <&cru SCLK_HEVC_CORE>;
 608                         };
 609
 610                         /*
 611                          * Note: ACLK_GPU is the GPU clock,
 612                          * and on the ACLK_GPU_NIU (NOC).
 613                          */
 614                         pd_gpu {
 615                                 reg = <RK3366_PD_GPU>;
 616                                 clocks = <&cru ACLK_GPU>;
 617                         };
 618                 };
 619         };
 620
 621         pmugrf: syscon@ff738000 {
 622                 compatible = "rockchip,rk3366-pmugrf", "syscon", "simple-mfd";
 623                 reg = <0x0 0xff738000 0x0 0x1000>;
 624
 625                 reboot-mode {
 626                         compatible = "syscon-reboot-mode";
 627                         offset = <0x200>;
 628                         mode-normal = <BOOT_NORMAL>;
 629                         mode-recovery = <BOOT_RECOVERY>;
 630                         mode-fastboot = <BOOT_FASTBOOT>;
 631                         mode-loader = <BOOT_LOADER>;
 632                 };
 633         };
 634
 635         amba {
 636                 compatible = "arm,amba-bus";
 637                 #address-cells = <2>;
 638                 #size-cells = <2>;
 639                 ranges;
 640
 641                 dmac_peri: dma-controller@ff250000 {
 642                         compatible = "arm,pl330", "arm,primecell";
 643                         reg = <0x0 0xff250000 0x0 0x4000>;
 644                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 645                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 646                         #dma-cells = <1>;
 647                         clocks = <&cru ACLK_DMAC_PERI>;
 648                         clock-names = "apb_pclk";
 649                 };
 650
 651                 dmac_bus: dma-controller@ff600000 {
 652                         compatible = "arm,pl330", "arm,primecell";
 653                         reg = <0x0 0xff600000 0x0 0x4000>;
 654                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 655                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 656                         #dma-cells = <1>;
 657                         clocks = <&cru ACLK_DMAC_BUS>;
 658                         clock-names = "apb_pclk";
 659                 };
 660         };
 661
 662         cru: clock-controller@ff760000 {
 663                 compatible = "rockchip,rk3366-cru";
 664                 reg = <0x0 0xff760000 0x0 0x1000>;
 665                 rockchip,grf = <&grf>;
 666                 #clock-cells = <1>;
 667                 #reset-cells = <1>;
 668                 assigned-clocks =
 669                         <&cru SCLK_32K>,
 670                         <&cru DCLK_VOP_FULL>, <&cru DCLK_VOP_LITE>,
 671                         <&cru PLL_CPLL>, <&cru PLL_GPLL>,
 672                         <&cru PLL_NPLL>, <&cru PLL_MPLL>,
 673                         <&cru PLL_WPLL>, <&cru PLL_BPLL>,
 674                         <&cru ACLK_VOP_FULL>, <&cru ACLK_VOP_LITE>,
 675                         <&cru HCLK_VOP_LITE>,<&cru HCLK_VOP_LITE>,
 676                         <&cru ACLK_BUS>, <&cru ACLK_PERI0>,
 677                         <&cru ACLK_PERI1>;
 678                 assigned-clock-rates =
 679                         <0>,
 680                         <0>, <0>,
 681                         <750000000>, <576000000>,
 682                         <594000000>, <594000000>,
 683                         <960000000>, <520000000>,
 684                         <375000000>, <288000000>,
 685                         <100000000>, <100000000>,
 686                         <288000000>, <288000000>,
 687                         <144000000>;
 688                 assigned-clock-parents =
 689                         <&cru SCLK_32K_INTR>,
 690                         <&cru SCLK_MPLL_SRC>, <&cru PLL_NPLL>;
 691         };
 692
 693         grf: syscon@ff770000 {
 694                 compatible = "rockchip,rk3366-grf", "syscon";
 695                 reg = <0x0 0xff770000 0x0 0x1000>;
 696         };
 697
 698         wdt: watchdog@ff800000 {
 699                 compatible = "snps,dw-wdt";
 700                 reg = <0x0 0xff800000 0x0 0x100>;
 701                 clocks = <&cru PCLK_WDT>;
 702                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 703                 status = "disabled";
 704         };
 705
 706         spdif: spdif@ff880000 {
 707                 compatible = "rockchip,rk3366-spdif";
 708                 reg = <0x0 0xff880000 0x0 0x1000>;
 709                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 710                 dmas = <&dmac_bus 3>;
 711                 dma-names = "tx";
 712                 clock-names = "hclk", "mclk";
 713                 clocks = <&cru HCLK_SPDIF>, <&cru SCLK_SPDIF_8CH>;
 714                 pinctrl-names = "default";
 715                 pinctrl-0 = <&spdif_bus>;
 716                 status = "disabled";
 717         };
 718
 719         i2s_2ch: i2s-2ch@ff890000 {
 720                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 721                 reg = <0x0 0xff890000 0x0 0x1000>;
 722                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 723                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 724                 dma-names = "tx", "rx";
 725                 clock-names = "i2s_hclk", "i2s_clk";
 726                 clocks = <&cru HCLK_I2S_2CH>, <&cru SCLK_I2S_2CH>;
 727                 status = "disabled";
 728         };
 729
 730         i2s_8ch: i2s-8ch@ff898000 {
 731                 compatible = "rockchip,rk3366-i2s", "rockchip,rk3066-i2s";
 732                 reg = <0x0 0xff898000 0x0 0x1000>;
 733                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 734                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 735                 dma-names = "tx", "rx";
 736                 clock-names = "i2s_hclk", "i2s_clk";
 737                 clocks = <&cru HCLK_I2S_8CH>, <&cru SCLK_I2S_8CH>;
 738                 pinctrl-names = "default";
 739                 pinctrl-0 = <&i2s_8ch_bus>;
 740                 status = "disabled";
 741         };
 742
 743         fb: fb {
 744                 compatible = "rockchip,rk-fb";
 745                 rockchip,disp-mode = <DUAL>;
 746                 status = "disabled";
 747         };
 748
 749         rk_screen: screen {
 750                 compatible = "rockchip,screen";
 751                 status = "disabled";
 752         };
 753
 754         vop_lite: vop@ff8f0000 {
 755                 compatible = "rockchip,rk3366-lcdc-lite";
 756                 rockchip,grf = <&grf>;
 757                 rockchip,pwr18 = <0>;
 758                 rockchip,iommu-enabled = <1>;
 759                 reg = <0x0 0xff8f0000 0x0 0x1000>;
 760                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 761                 clocks = <&cru ACLK_VOP_LITE>, <&cru DCLK_VOP_LITE>, <&cru HCLK_VOP_LITE>;
 762                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 763                 resets = <&cru SRST_VOP1_AXI>, <&cru SRST_VOP1_DCLK>, <&cru SRST_VOP1_AHB>;
 764                 reset-names = "axi", "ahb", "dclk";
 765                 status = "disabled";
 766         };
 767
 768         vopl_mmu: vopl-mmu {
 769                 dbgname = "vop";
 770                 compatible = "rockchip,vopl_mmu";
 771                 reg = <0x0 0xff8f0f00 0x0 0x100>;
 772                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 773                 interrupt-names = "vopl_mmu";
 774                 status = "disabled";
 775         };
 776
 777         iep: iep@ff900000 {
 778                 compatible = "rockchip,iep";
 779                 iommu_enabled = <1>;
 780                 reg = <0x0 0xff900000 0x0 0x800>;
 781                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 782                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
 783                 clock-names = "aclk_iep", "hclk_iep";
 784                 version = <2>;
 785                 status = "disabled";
 786         };
 787
 788         rga: rga@ff920000 {
 789                 compatible = "rockchip,rga2";
 790                 dev_mode = <1>;
 791                 reg = <0x0 0xff920000 0x0 0x1000>;
 792                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 793                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
 794                 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
 795                 status = "disabled";
 796         };
 797
 798         vop_big: vop@ff930000 {
 799                 compatible = "rockchip,rk3366-lcdc-big";
 800                 rockchip,grf = <&grf>;
 801                 rockchip,prop = <PRMRY>;
 802                 rockchip,pwr18 = <0>;
 803                 rockchip,iommu-enabled = <1>;
 804                 reg = <0x0 0xff930000 0x0 0x23f0>;
 805                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 806                 clocks = <&cru ACLK_VOP_FULL>, <&cru DCLK_VOP_FULL>, <&cru HCLK_VOP_FULL>;
 807                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 808                 resets = <&cru SRST_VOP0_AXI>, <&cru SRST_VOP0_DCLK>, <&cru SRST_VOP0_AHB>;
 809                 reset-names = "axi", "ahb", "dclk";
 810                 status = "disabled";
 811         };
 812
 813         vopb_mmu: vopb-mmu {
 814                 dbgname = "vop";
 815                 compatible = "rockchip,vopb_mmu";
 816                 reg = <0x0 0xff932400 0x0 0x100>;
 817                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 818                 interrupt-names = "vop_mmu";
 819                 status = "disabled";
 820         };
 821
 822         iep_mmu: iep-mmu {
 823                 dbgname = "iep";
 824                 compatible = "rockchip,iep_mmu";
 825                 reg = <0x0 0xff900800 0x0 0x100>;
 826                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 827                 interrupt-names = "iep_mmu";
 828                 status = "disabled";
 829         };
 830
 831         vpu_mmu: vpu_mmu {
 832                 dbgname = "vpu";
 833                 compatible = "rockchip,vpu_mmu";
 834                 reg = <0x0 0xff9a0800 0x0 0x100>;
 835                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 836                 interrupt-names = "vpu_mmu";
 837                 status = "disabled";
 838         };
 839
 840         vdec_mmu: vdec_mmu {
 841                 dbgname = "vdec";
 842                 compatible = "rockchip,vdec_mmu";
 843                 reg = <0x0 0xff9b0480 0x0 0x40>,
 844                       <0x0 0xff9b04c0 0x0 0x40>;
 845                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 846                 interrupt-names = "vdec_mmu";
 847                 status = "disabled";
 848         };
 849
 850         dsihost0: mipi@ff960000 {
 851                 compatible = "rockchip,rk3366-dsi";
 852                 rockchip,prop = <0>;
 853                 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
 854                 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
 855                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 856                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 857                 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host";
 858                 status = "disabled";
 859         };
 860
 861         lvds: lvds@ff968000 {
 862                 compatible = "rockchip,rk3366-lvds";
 863                 rockchip,grf = <&grf>;
 864                 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
 865                 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
 866                 clocks = <&cru PCLK_DPHYTX>, <&cru PCLK_MIPI_DSI0>;
 867                 clock-names = "pclk_lvds", "pclk_lvds_ctl";
 868                 status = "disabled";
 869         };
 870
 871         hdmi: hdmi@ff980000 {
 872                 compatible = "rockchip,rk3366-hdmi";
 873                 reg = <0x0 0xff980000 0x0 0x20000>;
 874                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 875                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 876                 clocks = <&cru PCLK_HDMI_CTRL>,
 877                          <&cru SCLK_HDMI_HDCP>,
 878                          <&cru SCLK_HDMI_CEC>,
 879                          <&cru DCLK_HDMIPHY>;
 880                 clock-names = "pclk_hdmi",
 881                               "hdcp_clk_hdmi",
 882                               "cec_clk_hdmi",
 883                               "dclk_hdmi_phy";
 884                 resets = <&cru SRST_HDMI>;
 885                 reset-names = "hdmi";
 886                 pinctrl-names = "default", "gpio";
 887                 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
 888                 pinctrl-1 = <&i2c5_gpio>;
 889                 status = "disabled";
 890         };
 891
 892         vpu: vpu_service@ff9a0000 {
 893                 compatible = "rockchip,vpu_service";
 894                 rockchip,grf = <&grf>;
 895                 iommu_enabled = <1>;
 896                 reg = <0x0 0xff9a0000 0x0 0x800>;
 897                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 898                         <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 899                 interrupt-names = "irq_dec", "irq_enc";
 900                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
 901                 clock-names = "aclk_vcodec", "hclk_vcodec";
 902                 resets = <&cru SRST_VIDEO_AHB>, <&cru SRST_VIDEO_AXI>;
 903                 reset-names = "video_h", "video_a";
 904                 name = "vpu_service";
 905                 dev_mode = <0>;
 906                 status = "disabled";
 907         };
 908
 909         rkvdec: rkvdec@ff9b0000 {
 910                 compatible = "rockchip,rkvdec";
 911                 rockchip,grf = <&grf>;
 912                 iommu_enabled = <1>;
 913                 reg = <0x0 0xff9b0000 0x0 0x400>;
 914                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 915                 interrupt-names = "irq_dec";
 916                 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>,<&cru SCLK_HEVC_CABAC>,<&cru SCLK_HEVC_CORE>;
 917                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_cabac", "clk_core";
 918                 resets = <&cru SRST_RKVDEC_AHB>, <&cru SRST_VIDEO_AXI>;
 919                 reset-names = "video_h", "video_a";
 920                 dev_mode = <2>;
 921                 name = "rkvdec";
 922                 status = "disabled";
 923         };
 924
 925         pinctrl: pinctrl {
 926                 compatible = "rockchip,rk3366-pinctrl";
 927                 rockchip,grf = <&grf>;
 928                 rockchip,pmu = <&pmugrf>;
 929                 #address-cells = <0x2>;
 930                 #size-cells = <0x2>;
 931                 ranges;
 932
 933                 gpio0: gpio0@ff750000 {
 934                         compatible = "rockchip,gpio-bank";
 935                         reg = <0x0 0xff750000 0x0 0x100>;
 936                         clocks = <&cru PCLK_GPIO0>;
 937                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 938
 939                         gpio-controller;
 940                         #gpio-cells = <0x2>;
 941
 942                         interrupt-controller;
 943                         #interrupt-cells = <0x2>;
 944                 };
 945
 946                 gpio1: gpio1@ff780000 {
 947                         compatible = "rockchip,gpio-bank";
 948                         reg = <0x0 0xff758000 0x0 0x100>;
 949                         clocks = <&cru PCLK_GPIO1>;
 950                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 951
 952                         gpio-controller;
 953                         #gpio-cells = <0x2>;
 954
 955                         interrupt-controller;
 956                         #interrupt-cells = <0x2>;
 957                 };
 958
 959                 gpio2: gpio2@ff790000 {
 960                         compatible = "rockchip,gpio-bank";
 961                         reg = <0x0 0xff790000 0x0 0x100>;
 962                         clocks = <&cru PCLK_GPIO2>;
 963                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 964
 965                         gpio-controller;
 966                         #gpio-cells = <0x2>;
 967
 968                         interrupt-controller;
 969                         #interrupt-cells = <0x2>;
 970                 };
 971
 972                 gpio3: gpio3@ff7a0000 {
 973                         compatible = "rockchip,gpio-bank";
 974                         reg = <0x0 0xff7a0000 0x0 0x100>;
 975                         clocks = <&cru PCLK_GPIO3>;
 976                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 977
 978                         gpio-controller;
 979                         #gpio-cells = <0x2>;
 980
 981                         interrupt-controller;
 982                         #interrupt-cells = <0x2>;
 983                 };
 984
 985                 gpio4: gpio4@ff7b0000 {
 986                         compatible = "rockchip,gpio-bank";
 987                         reg = <0x0 0xff7b0000 0x0 0x100>;
 988                         clocks = <&cru PCLK_GPIO4>;
 989                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 990
 991                         gpio-controller;
 992                         #gpio-cells = <0x2>;
 993
 994                         interrupt-controller;
 995                         #interrupt-cells = <0x2>;
 996                 };
 997
 998                 gpio5: gpio5@ff7c0000 {
 999                         compatible = "rockchip,gpio-bank";
1000                         reg = <0x0 0xff7c0000 0x0 0x100>;
1001                         clocks = <&cru PCLK_GPIO5>;
1002                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1003
1004                         gpio-controller;
1005                         #gpio-cells = <0x2>;
1006
1007                         interrupt-controller;
1008                         #interrupt-cells = <0x2>;
1009                 };
1010
1011                 pcfg_pull_up: pcfg-pull-up {
1012                         bias-pull-up;
1013                 };
1014
1015                 pcfg_pull_down: pcfg-pull-down {
1016                         bias-pull-down;
1017                 };
1018
1019                 pcfg_pull_none: pcfg-pull-none {
1020                         bias-disable;
1021                 };
1022
1023                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1024                         bias-disable;
1025                         drive-strength = <12>;
1026                 };
1027
1028                 emmc {
1029                         emmc_clk: emmc-clk {
1030                                 rockchip,pins =
1031                                         <3 4 RK_FUNC_2 &pcfg_pull_none>;
1032                         };
1033
1034                         emmc_cmd: emmc-cmd {
1035                                 rockchip,pins =
1036                                         <2 26 RK_FUNC_2 &pcfg_pull_up>;
1037                         };
1038
1039                         emmc_pwr: emmc-pwr {
1040                                 rockchip,pins =
1041                                         <2 27 RK_FUNC_2 &pcfg_pull_up>;
1042                         };
1043
1044                         emmc_bus1: emmc-bus1 {
1045                                 rockchip,pins =
1046                                         <2 18 RK_FUNC_2 &pcfg_pull_up>;
1047                         };
1048
1049                         emmc_bus4: emmc-bus4 {
1050                                 rockchip,pins =
1051                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1052                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1053                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1054                                         <2 21 RK_FUNC_2 &pcfg_pull_up>;
1055                         };
1056
1057                         emmc_bus8: emmc-bus8 {
1058                                 rockchip,pins =
1059                                         <2 18 RK_FUNC_2 &pcfg_pull_up>,
1060                                         <2 19 RK_FUNC_2 &pcfg_pull_up>,
1061                                         <2 20 RK_FUNC_2 &pcfg_pull_up>,
1062                                         <2 21 RK_FUNC_2 &pcfg_pull_up>,
1063                                         <2 22 RK_FUNC_2 &pcfg_pull_up>,
1064                                         <2 23 RK_FUNC_2 &pcfg_pull_up>,
1065                                         <2 24 RK_FUNC_2 &pcfg_pull_up>,
1066                                         <2 25 RK_FUNC_2 &pcfg_pull_up>;
1067                         };
1068                 };
1069
1070                 sdmmc {
1071                         sdmmc_cd: sdmmc-cd {
1072                                 rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_up>;
1073                         };
1074
1075                         sdmmc_bus1: sdmmc-bus1 {
1076                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>;
1077                         };
1078
1079                         sdmmc_bus4: sdmmc-bus4 {
1080                                 rockchip,pins = <5 0 RK_FUNC_1 &pcfg_pull_up>,
1081                                                 <5 1 RK_FUNC_1 &pcfg_pull_up>,
1082                                                 <5 2 RK_FUNC_1 &pcfg_pull_up>,
1083                                                 <5 3 RK_FUNC_1 &pcfg_pull_up>;
1084                         };
1085
1086                         sdmmc_clk: sdmmc-clk {
1087                                 rockchip,pins = <5 4 RK_FUNC_1 &pcfg_pull_none>;
1088                         };
1089
1090                         sdmmc_cmd: sdmmc-cmd {
1091                                 rockchip,pins = <5 5 RK_FUNC_1 &pcfg_pull_up>;
1092                         };
1093                 };
1094
1095                 sdio {
1096                         sdio_bus1: sdio-bus1 {
1097                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>;
1098                         };
1099
1100                         sdio_bus4: sdio-bus4 {
1101                                 rockchip,pins = <3 12 RK_FUNC_1 &pcfg_pull_up>,
1102                                                 <3 13 RK_FUNC_1 &pcfg_pull_up>,
1103                                                 <3 14 RK_FUNC_1 &pcfg_pull_up>,
1104                                                 <3 15 RK_FUNC_1 &pcfg_pull_up>;
1105                         };
1106
1107                         sdio_cmd: sdio-cmd {
1108                                 rockchip,pins = <3 16 RK_FUNC_1 &pcfg_pull_up>;
1109                         };
1110
1111                         sdio_clk: sdio-clk {
1112                                 rockchip,pins = <3 17 RK_FUNC_1 &pcfg_pull_none>;
1113                         };
1114
1115                         sdio_cd: sdio-cd {
1116                                 rockchip,pins = <3 18 RK_FUNC_1 &pcfg_pull_up>;
1117                         };
1118
1119                         sdio_wp: sdio-wp {
1120                                 rockchip,pins = <3 19 RK_FUNC_1 &pcfg_pull_up>;
1121                         };
1122
1123                         sdio_int: sdio-int {
1124                                 rockchip,pins = <3 20 RK_FUNC_1 &pcfg_pull_up>;
1125                         };
1126
1127                         sdio_pwr: sdio-pwr {
1128                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_up>;
1129                         };
1130                 };
1131
1132                 hdmi_i2c {
1133                         hdmii2c_xfer: hdmii2c-xfer {
1134                                 rockchip,pins =
1135                                         <5 13 RK_FUNC_2 &pcfg_pull_none>,
1136                                         <5 14 RK_FUNC_2 &pcfg_pull_none>;
1137                         };
1138                 };
1139
1140                 hdmi_pin {
1141                         hdmi_cec: hdmi-cec {
1142                                 rockchip,pins =
1143                                         <5 12 RK_FUNC_1 &pcfg_pull_none>;
1144                         };
1145                 };
1146
1147                 i2c0 {
1148                         i2c0_xfer: i2c0-xfer {
1149                                 rockchip,pins =
1150                                         <0 3 RK_FUNC_1 &pcfg_pull_none>,
1151                                         <0 4 RK_FUNC_1 &pcfg_pull_none>;
1152                         };
1153                 };
1154
1155                 i2c1 {
1156                         i2c1_xfer: i2c1-xfer {
1157                                 rockchip,pins =
1158                                         <4 25 RK_FUNC_1 &pcfg_pull_none>,
1159                                         <4 26 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161                 };
1162
1163                 i2c2 {
1164                         i2c2_xfer: i2c2-xfer {
1165                                 rockchip,pins =
1166                                         <5 15 RK_FUNC_2 &pcfg_pull_none>,
1167                                         <5 16 RK_FUNC_2 &pcfg_pull_none>;
1168                         };
1169
1170                         i2c2_gpio: i2c2-gpio {
1171                                 rockchip,pins =
1172                                         <5 15 RK_FUNC_GPIO &pcfg_pull_none>,
1173                                         <5 16 RK_FUNC_GPIO &pcfg_pull_none>;
1174                         };
1175                 };
1176
1177                 i2c3 {
1178                         i2c3_xfer: i2c3-xfer {
1179                                 rockchip,pins =
1180                                         <2 16 RK_FUNC_2 &pcfg_pull_none>,
1181                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1182                         };
1183                 };
1184
1185                 i2c4 {
1186                         i2c4_xfer: i2c4-xfer {
1187                                 rockchip,pins =
1188                                         <5 8 RK_FUNC_1 &pcfg_pull_none>,
1189                                         <5 9 RK_FUNC_1 &pcfg_pull_none>;
1190                         };
1191
1192                         i2c4_gpio: i2c4-gpio {
1193                                 rockchip,pins =
1194                                         <5 8 RK_FUNC_GPIO &pcfg_pull_none>,
1195                                         <5 9 RK_FUNC_GPIO &pcfg_pull_none>;
1196                         };
1197                 };
1198
1199                 i2c5 {
1200                         i2c5_xfer: i2c5-xfer {
1201                                 rockchip,pins =
1202                                         <5 13 RK_FUNC_1 &pcfg_pull_none>,
1203                                         <5 14 RK_FUNC_1 &pcfg_pull_none>;
1204                         };
1205                         i2c5_gpio: i2c5-gpio {
1206                                 rockchip,pins =
1207                                         <5 13 RK_FUNC_GPIO &pcfg_pull_none>,
1208                                         <5 14 RK_FUNC_GPIO &pcfg_pull_none>;
1209                         };
1210                 };
1211
1212                 i2s {
1213                         i2s_8ch_bus: i2s-8ch-bus {
1214                                 rockchip,pins =
1215                                         <4 16 RK_FUNC_1 &pcfg_pull_none>,
1216                                         <4 17 RK_FUNC_1 &pcfg_pull_none>,
1217                                         <4 18 RK_FUNC_1 &pcfg_pull_none>,
1218                                         <4 19 RK_FUNC_1 &pcfg_pull_none>,
1219                                         <4 20 RK_FUNC_1 &pcfg_pull_none>,
1220                                         <4 21 RK_FUNC_1 &pcfg_pull_none>,
1221                                         <4 22 RK_FUNC_1 &pcfg_pull_none>,
1222                                         <4 23 RK_FUNC_1 &pcfg_pull_none>,
1223                                         <4 24 RK_FUNC_1 &pcfg_pull_none>;
1224                         };
1225                 };
1226
1227                 spdif {
1228                         spdif_bus: spdif-bus {
1229                                 rockchip,pins =
1230                                         <5 19 RK_FUNC_1 &pcfg_pull_none>;
1231                         };
1232                 };
1233
1234                 spi0 {
1235                         spi0_clk: spi0-clk {
1236                                 rockchip,pins =
1237                                         <2 29 RK_FUNC_2 &pcfg_pull_up>;
1238                         };
1239                         spi0_cs0: spi0-cs0 {
1240                                 rockchip,pins =
1241                                         <2 24 RK_FUNC_3 &pcfg_pull_up>;
1242                         };
1243                         spi0_cs1: spi0-cs1 {
1244                                 rockchip,pins =
1245                                         <2 25 RK_FUNC_3 &pcfg_pull_up>;
1246                         };
1247                         spi0_tx: spi0-tx {
1248                                 rockchip,pins =
1249                                         <2 23 RK_FUNC_3 &pcfg_pull_up>;
1250                         };
1251                         spi0_rx: spi0-rx {
1252                                 rockchip,pins =
1253                                         <2 22 RK_FUNC_3 &pcfg_pull_up>;
1254                         };
1255                 };
1256
1257                 spi1 {
1258                         spi1_clk: spi1-clk {
1259                                 rockchip,pins =
1260                                         <2 4 RK_FUNC_3 &pcfg_pull_up>;
1261                         };
1262                         spi1_cs0: spi1-cs0 {
1263                                 rockchip,pins =
1264                                         <2 5 RK_FUNC_3 &pcfg_pull_up>;
1265                         };
1266                         spi1_tx: spi1-tx {
1267                                 rockchip,pins =
1268                                         <2 6 RK_FUNC_3 &pcfg_pull_up>;
1269                         };
1270                         spi1_rx: spi1-rx {
1271                                 rockchip,pins =
1272                                         <2 7 RK_FUNC_3 &pcfg_pull_up>;
1273                         };
1274                 };
1275
1276                 scr {
1277                         scr_clk: scr-clk {
1278                                 rockchip,pins =
1279                                         <5 8 RK_FUNC_2 &pcfg_pull_none>;
1280                         };
1281
1282                         scr_io: scr-io {
1283                                 rockchip,pins =
1284                                         <5 9 RK_FUNC_2 &pcfg_pull_up>;
1285                         };
1286
1287                         scr_rst: scr-rst {
1288                                 rockchip,pins =
1289                                         <5 10 RK_FUNC_1 &pcfg_pull_none>;
1290                         };
1291
1292                         scr_detect: scr-detect {
1293                                 rockchip,pins =
1294                                         <5 11 RK_FUNC_1 &pcfg_pull_none>;
1295                         };
1296                 };
1297
1298                 uart0 {
1299                         uart0_xfer: uart0-xfer {
1300                                 rockchip,pins =
1301                                         <3 8 RK_FUNC_1 &pcfg_pull_up>,
1302                                         <3 9 RK_FUNC_1 &pcfg_pull_none>;
1303                         };
1304
1305                         uart0_cts: uart0-cts {
1306                                 rockchip,pins =
1307                                         <3 10 RK_FUNC_1 &pcfg_pull_none>;
1308                         };
1309
1310                         uart0_rts: uart0-rts {
1311                                 rockchip,pins =
1312                                         <3 11 RK_FUNC_1 &pcfg_pull_none>;
1313                         };
1314                 };
1315
1316                 uart2_t0 {
1317                         uart2_t0_xfer: uart2_t0-xfer {
1318                                 rockchip,pins =
1319                                         <0 22 RK_FUNC_1 &pcfg_pull_up>,
1320                                         <0 21 RK_FUNC_1 &pcfg_pull_none>;
1321                         };
1322                         /* no rts / cts for uart2 */
1323                 };
1324
1325                 uart2_t1 {
1326                         uart2_t1_xfer: uart2_t1-xfer {
1327                                 rockchip,pins =
1328                                         <5 0 RK_FUNC_2 &pcfg_pull_up>,
1329                                         <5 1 RK_FUNC_2 &pcfg_pull_none>;
1330                         };
1331                         /* no rts / cts for uart2 */
1332                 };
1333
1334                 uart2_t2 {
1335                         uart2_t2_xfer: uart2_t2-xfer {
1336                                 rockchip,pins =
1337                                         <5 14 RK_FUNC_3 &pcfg_pull_up>,
1338                                         <5 13 RK_FUNC_3 &pcfg_pull_none>;
1339                         };
1340                         /* no rts / cts for uart2 */
1341                 };
1342
1343                 uart3 {
1344                         uart3_xfer: uart3-xfer {
1345                                 rockchip,pins =
1346                                         <5 15 RK_FUNC_1 &pcfg_pull_up>,
1347                                         <5 16 RK_FUNC_1 &pcfg_pull_none>;
1348                         };
1349
1350                         uart3_cts: uart3-cts {
1351                                 rockchip,pins =
1352                                         <5 17 RK_FUNC_1 &pcfg_pull_none>;
1353                         };
1354
1355                         uart3_rts: uart3-rts {
1356                                 rockchip,pins =
1357                                         <5 18 RK_FUNC_1 &pcfg_pull_none>;
1358                         };
1359                 };
1360
1361                 pwm0 {
1362                         pwm0_pin: pwm0-pin {
1363                                 rockchip,pins =
1364                                         <0 8 RK_FUNC_1 &pcfg_pull_none>;
1365                         };
1366                 };
1367
1368                 pwm1 {
1369                         pwm1_pin: pwm1-pin {
1370                                 rockchip,pins =
1371                                         <1 6 RK_FUNC_2 &pcfg_pull_none>;
1372                         };
1373                 };
1374
1375                 pwm2_t0 {
1376                         pwm2_t0_pin: pwm2_t0-pin {
1377                                 rockchip,pins =
1378                                         <2 15 RK_FUNC_3 &pcfg_pull_none>;
1379                         };
1380                 };
1381
1382                 pwm2_t1 {
1383                         pwm2_t1_pin: pwm2_t1-pin {
1384                                 rockchip,pins =
1385                                         <5 17 RK_FUNC_2 &pcfg_pull_none>;
1386                         };
1387                 };
1388
1389                 pwm3_t0 {
1390                         pwm3_t0_pin: pwm3_t0-pin {
1391                                 rockchip,pins =
1392                                         <1 0 RK_FUNC_2 &pcfg_pull_none>;
1393                         };
1394                 };
1395
1396                 pwm3_t1 {
1397                         pwm3_t1_pin: pwm3_t1-pin {
1398                                 rockchip,pins =
1399                                         <0 21 RK_FUNC_2 &pcfg_pull_none>;
1400                         };
1401                 };
1402
1403                 pwm3_t2 {
1404                         pwm3_t2_pin: pwm3_t2-pin {
1405                                 rockchip,pins =
1406                                         <5 18 RK_FUNC_2 &pcfg_pull_none>;
1407                         };
1408                 };
1409
1410                 lcdc {
1411                         lcdc_lcdc: lcdc-lcdc {
1412                                 rockchip,pins =
1413                                         <0 24 RK_FUNC_2 &pcfg_pull_none>, /* HSYNC */
1414                                         <0 25 RK_FUNC_2 &pcfg_pull_none>, /* VSYNC */
1415                                         <0 26 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D10 */
1416                                         <0 27 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D11 */
1417                                         <0 28 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D12 */
1418                                         <0 29 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D13 */
1419                                         <0 30 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D14 */
1420                                         <0 31 RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D15 */
1421                                         <1 0  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D16 */
1422                                         <1 1  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D17 */
1423                                         <1 2  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D18 */
1424                                         <1 3  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D19 */
1425                                         <1 4  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D20 */
1426                                         <1 5  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D21 */
1427                                         <1 6  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D22 */
1428                                         <1 7  RK_FUNC_1 &pcfg_pull_none>, /* LCDC_D23 */
1429                                         <1 8  RK_FUNC_1 &pcfg_pull_none>, /* DEN */
1430                                         <1 9  RK_FUNC_1 &pcfg_pull_none>; /* DCLK */
1431                         };
1432
1433                         lcdc_gpio: lcdc-gpio {
1434                                 rockchip,pins =
1435                                         <0 24 RK_FUNC_GPIO &pcfg_pull_none>, /* HSYNC */
1436                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>, /* VSYNC */
1437                                         <0 26 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D10 */
1438                                         <0 27 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D11 */
1439                                         <0 28 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */
1440                                         <0 29 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */
1441                                         <0 30 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */
1442                                         <0 31 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */
1443                                         <1 0  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */
1444                                         <1 1  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D17 */
1445                                         <1 2  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D18 */
1446                                         <1 3  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D19 */
1447                                         <1 4  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D20 */
1448                                         <1 5  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D21 */
1449                                         <1 6  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D22 */
1450                                         <1 7  RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D23 */
1451                                         <1 8  RK_FUNC_GPIO &pcfg_pull_none>, /* DEN */
1452                                         <1 9  RK_FUNC_GPIO &pcfg_pull_none>; /* DCLK */
1453                         };
1454                 };
1455
1456                 gmac {
1457                         rgmii_pins: rgmii-pins {
1458                                 rockchip,pins =
1459                                         /* mac_rxd3 */
1460                                         <2 7  RK_FUNC_1 &pcfg_pull_none>,
1461                                         /* mac_rxd2 */
1462                                         <2 6  RK_FUNC_1 &pcfg_pull_none>,
1463                                         /* mac_txd3 */
1464                                         <2 5  RK_FUNC_1 &pcfg_pull_none_12ma>,
1465                                         /* mac_txd2 */
1466                                         <2 4  RK_FUNC_1 &pcfg_pull_none_12ma>,
1467                                         /* mac_rxd1 */
1468                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1469                                         /* mac_rxd0 */
1470                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1471                                         /* mac_txd1 */
1472                                         <2 1  RK_FUNC_1 &pcfg_pull_none_12ma>,
1473                                         /* mac_txd0 */
1474                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1475                                         /* mac_txclkout */
1476                                         <2 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1477                                         /* mac_crs */
1478                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1479                                         /* mac_rxclkin */
1480                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1481                                         /* mac_mdio */
1482                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1483                                         /* mac_txen */
1484                                         <2 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1485                                         /* mac_clk */
1486                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1487                                         /* mac_rxer */
1488                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1489                                         /* mac_rxdv */
1490                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1491                                         /* mac_mdc */
1492                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1493                         };
1494
1495                         rmii_pins: rmii-pins {
1496                                 rockchip,pins =
1497                                         /* mac_rxd1 */
1498                                         <2 3  RK_FUNC_1 &pcfg_pull_none>,
1499                                         /* mac_rxd0 */
1500                                         <2 2  RK_FUNC_1 &pcfg_pull_none>,
1501                                         /* mac_txd1 */
1502                                         <2 1  RK_FUNC_1 &pcfg_pull_none>,
1503                                         /* mac_txd0 */
1504                                         <2 0  RK_FUNC_1 &pcfg_pull_none>,
1505                                         /* mac_crs */
1506                                         /* <2 15 RK_FUNC_1 &pcfg_pull_none>, */
1507                                         /* mac_rxclkin */
1508                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
1509                                         /* mac_mdio */
1510                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
1511                                         /* mac_txen */
1512                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
1513                                         /* mac_clk */
1514                                         <2 11 RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_rxer */
1516                                         /* <2 10 RK_FUNC_1 &pcfg_pull_none>, */
1517                                         /* mac_rxdv */
1518                                         <2 9  RK_FUNC_1 &pcfg_pull_none>,
1519                                         /* mac_mdc */
1520                                         <2 8  RK_FUNC_1 &pcfg_pull_none>;
1521                         };
1522                 };
1523
1524                 eth_phy {
1525                         eth_phy_pwr: eth-phy-pwr {
1526                                 rockchip,pins =
1527                                         <0 25 RK_FUNC_GPIO &pcfg_pull_none>;
1528                         };
1529                 };
1530         };
1531
1532         gpu: gpu@ffa30000 {
1533                 compatible = "arm,malit764",
1534                              "arm,malit76x",
1535                              "arm,malit7xx",
1536                              "arm,mali-midgard";
1537
1538                 reg = <0x0 0xffa30000 0 0x10000>;
1539
1540                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1541                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1542                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1543                 interrupt-names = "GPU", "MMU", "JOB";
1544
1545                 clocks = <&cru ACLK_GPU>;
1546                 clock-names = "clk_mali";
1547                 operating-points-v2 = <&gpu_opp_table>;
1548                 status = "disabled";
1549         };
1550
1551         gpu_opp_table: gpu_opp_table {
1552                 compatible = "operating-points-v2";
1553                 opp-shared;
1554
1555                 opp00 {
1556                         opp-hz = /bits/ 64 <96000000>;
1557                         opp-microvolt = <1150000>;
1558                 };
1559                 opp01 {
1560                         opp-hz = /bits/ 64 <192000000>;
1561                         opp-microvolt = <1150000>;
1562                 };
1563                 opp02 {
1564                         opp-hz = /bits/ 64 <288000000>;
1565                         opp-microvolt = <1150000>;
1566                 };
1567                 opp03 {
1568                         opp-hz = /bits/ 64 <375000000>;
1569                         opp-microvolt = <1150000>;
1570                 };
1571                 opp04 {
1572                         opp-hz = /bits/ 64 <480000000>;
1573                         opp-microvolt = <1150000>;
1574                 };
1575         };
1576 };