arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49
  50 / {
  51         compatible = "rockchip,rk3328";
  52
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60                 serial2 = &uart2;
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x0>;
  75                         enable-method = "psci";
  76 //                      clocks = <&cru ARMCLK>;
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                 };
  79                 cpu1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x1>;
  83                         enable-method = "psci";
  84                 };
  85                 cpu2: cpu@2 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53", "arm,armv8";
  88                         reg = <0x0 0x2>;
  89                         enable-method = "psci";
  90                 };
  91                 cpu3: cpu@3 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53", "arm,armv8";
  94                         reg = <0x0 0x3>;
  95                         enable-method = "psci";
  96                 };
  97         };
  98
  99         cpu0_opp_table: opp_table0 {
 100                 compatible = "operating-points-v2";
 101                 opp-shared;
 102
 103                 opp@408000000 {
 104                         opp-hz = /bits/ 64 <408000000>;
 105                         opp-microvolt = <950000>;
 106                         clock-latency-ns = <40000>;
 107                         opp-suspend;
 108                 };
 109                 opp@600000000 {
 110                         opp-hz = /bits/ 64 <600000000>;
 111                         opp-microvolt = <950000>;
 112                         clock-latency-ns = <40000>;
 113                 };
 114                 opp@816000000 {
 115                         opp-hz = /bits/ 64 <816000000>;
 116                         opp-microvolt = <1000000>;
 117                         clock-latency-ns = <40000>;
 118                 };
 119                 opp@1008000000 {
 120                         opp-hz = /bits/ 64 <1008000000>;
 121                         opp-microvolt = <1100000>;
 122                         clock-latency-ns = <40000>;
 123                 };
 124                 opp@1200000000 {
 125                         opp-hz = /bits/ 64 <1200000000>;
 126                         opp-microvolt = <1225000>;
 127                         clock-latency-ns = <40000>;
 128                 };
 129                 opp@1296000000 {
 130                         opp-hz = /bits/ 64 <1296000000>;
 131                         opp-microvolt = <1300000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134         };
 135
 136         arm-pmu {
 137                 compatible = "arm,cortex-a53-pmu";
 138                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 142                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 153                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 156         };
 157
 158         xin24m: xin24m {
 159                 compatible = "fixed-clock";
 160                 #clock-cells = <0>;
 161                 clock-frequency = <24000000>;
 162                 clock-output-names = "xin24m";
 163         };
 164
 165         i2s0: i2s@ff000000 {
 166                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 167                 reg = <0x0 0xff000000 0x0 0x1000>;
 168                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 170                 clock-names = "i2s_clk", "i2s_hclk";
 171                 dmas = <&dmac 11>, <&dmac 12>;
 172                 #dma-cells = <2>;
 173                 dma-names = "tx", "rx";
 174                 status = "disabled";
 175         };
 176
 177         i2s1: i2s@ff010000 {
 178                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 179                 reg = <0x0 0xff010000 0x0 0x1000>;
 180                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 182                 clock-names = "i2s_clk", "i2s_hclk";
 183                 dmas = <&dmac 14>, <&dmac 15>;
 184                 #dma-cells = <2>;
 185                 dma-names = "tx", "rx";
 186                 status = "disabled";
 187         };
 188
 189         i2s2: i2s@ff020000 {
 190                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 191                 reg = <0x0 0xff020000 0x0 0x1000>;
 192                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 194                 clock-names = "i2s_clk", "i2s_hclk";
 195                 dmas = <&dmac 0>, <&dmac 1>;
 196                 #dma-cells = <2>;
 197                 dma-names = "tx", "rx";
 198                 pinctrl-names = "default", "sleep";
 199                 pinctrl-0 = <&i2s2m0_mclk
 200                              &i2s2m0_sclk
 201                              &i2s2m0_lrcktx
 202                              &i2s2m0_lrckrx
 203                              &i2s2m0_sdo
 204                              &i2s2m0_sdi>;
 205                 pinctrl-1 = <&i2s2m0_sleep>;
 206                 status = "disabled";
 207         };
 208
 209         spdif: spdif@ff030000 {
 210                 compatible = "rockchip,rk3328-spdif";
 211                 reg = <0x0 0xff030000 0x0 0x1000>;
 212                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 214                 clock-names = "mclk", "hclk";
 215                 dmas = <&dmac 10>;
 216                 #dma-cells = <1>;
 217                 dma-names = "tx";
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&spdifm2_tx>;
 220                 status = "disabled";
 221         };
 222
 223         grf: syscon@ff100000 {
 224                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 225                 reg = <0x0 0xff100000 0x0 0x1000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228
 229                 io_domains: io-domains {
 230                         compatible = "rockchip,rk3328-io-voltage-domain";
 231                         status = "disabled";
 232                 };
 233
 234                 reboot-mode {
 235                         compatible = "syscon-reboot-mode";
 236                         offset = <0x5c8>;
 237                         mode-bootloader = <BOOT_LOADER>;
 238                         mode-charge = <BOOT_CHARGING>;
 239                         mode-fastboot = <BOOT_FASTBOOT>;
 240                         mode-loader = <BOOT_LOADER>;
 241                         mode-normal = <BOOT_NORMAL>;
 242                         mode-recovery = <BOOT_RECOVERY>;
 243                         mode-ums = <BOOT_UMS>;
 244                 };
 245         };
 246
 247         uart0: serial@ff110000 {
 248                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 249                 reg = <0x0 0xff110000 0x0 0x100>;
 250                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 252                 clock-names = "baudclk", "apb_pclk";
 253                 reg-shift = <2>;
 254                 reg-io-width = <4>;
 255                 dmas = <&dmac 2>, <&dmac 3>;
 256                 #dma-cells = <2>;
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 259                 status = "disabled";
 260         };
 261
 262         uart1: serial@ff120000 {
 263                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 264                 reg = <0x0 0xff120000 0x0 0x100>;
 265                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 267                 clock-names = "sclk_uart", "pclk_uart";
 268                 reg-shift = <2>;
 269                 reg-io-width = <4>;
 270                 dmas = <&dmac 4>, <&dmac 5>;
 271                 #dma-cells = <2>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 274                 status = "disabled";
 275         };
 276
 277         uart2: serial@ff130000 {
 278                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 279                 reg = <0x0 0xff130000 0x0 0x100>;
 280                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 282                 clock-names = "baudclk", "apb_pclk";
 283                 reg-shift = <2>;
 284                 reg-io-width = <4>;
 285                 dmas = <&dmac 6>, <&dmac 7>;
 286                 #dma-cells = <2>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&uart2m1_xfer>;
 289                 status = "disabled";
 290         };
 291
 292         pmu: power-management@ff140000 {
 293                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 294                 reg = <0x0 0xff140000 0x0 0x1000>;
 295         };
 296
 297         i2c0: i2c@ff150000 {
 298                 compatible = "rockchip,rk3328-i2c";
 299                 reg = <0x0 0xff150000 0x0 0x1000>;
 300                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 304                 clock-names = "i2c", "pclk";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c0_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         i2c1: i2c@ff160000 {
 311                 compatible = "rockchip,rk3328-i2c";
 312                 reg = <0x0 0xff160000 0x0 0x1000>;
 313                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 317                 clock-names = "i2c", "pclk";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&i2c1_xfer>;
 320                 status = "disabled";
 321         };
 322
 323         i2c2: i2c@ff170000 {
 324                 compatible = "rockchip,rk3328-i2c";
 325                 reg = <0x0 0xff170000 0x0 0x1000>;
 326                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 330                 clock-names = "i2c", "pclk";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&i2c2_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         i2c3: i2c@ff180000 {
 337                 compatible = "rockchip,rk3328-i2c";
 338                 reg = <0x0 0xff180000 0x0 0x1000>;
 339                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 343                 clock-names = "i2c", "pclk";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c3_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         spi0: spi@ff190000 {
 350                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 351                 reg = <0x0 0xff190000 0x0 0x1000>;
 352                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 356                 clock-names = "spiclk", "apb_pclk";
 357                 dmas = <&dmac 8>, <&dmac 9>;
 358                 #dma-cells = <2>;
 359                 dma-names = "tx", "rx";
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 362                 status = "disabled";
 363         };
 364
 365         wdt: watchdog@ff1a0000 {
 366                 compatible = "snps,dw-wdt";
 367                 reg = <0x0 0xff1a0000 0x0 0x100>;
 368                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 369                 status = "disabled";
 370         };
 371
 372         amba {
 373                 compatible = "simple-bus";
 374                 #address-cells = <2>;
 375                 #size-cells = <2>;
 376                 ranges;
 377
 378                 dmac: dmac@ff1f0000 {
 379                         compatible = "arm,pl330", "arm,primecell";
 380                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 381                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 382                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&cru ACLK_DMAC>;
 384                         clock-names = "apb_pclk";
 385                         #dma-cells = <1>;
 386                 };
 387         };
 388
 389         saradc: saradc@ff280000 {
 390                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 391                 reg = <0x0 0xff280000 0x0 0x100>;
 392                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 393                 #io-channel-cells = <1>;
 394                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 395                 clock-names = "saradc", "apb_pclk";
 396                 resets = <&cru SRST_SARADC_P>;
 397                 reset-names = "saradc-apb";
 398                 status = "disabled";
 399         };
 400
 401         cru: clock-controller@ff440000 {
 402                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 403                 reg = <0x0 0xff440000 0x0 0x1000>;
 404                 rockchip,grf = <&grf>;
 405                 #clock-cells = <1>;
 406                 #reset-cells = <1>;
 407                 assigned-clocks =
 408                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 409                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 410                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 411                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 412                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 413                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 414                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 415                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 416                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 417                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 418                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 419                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 420                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 421                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 422                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 423                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 424                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 425                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 426                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 427                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 428                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 429                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 430                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 431                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 432                 assigned-clock-parents =
 433                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 434                         <&cru PLL_GPLL>, <&xin24m>,
 435                         <&xin24m>, <&xin24m>;
 436                 assigned-clock-rates =
 437                         <0>, <61440000>,
 438                         <0>, <24000000>,
 439                         <24000000>, <24000000>,
 440                         <15000000>, <15000000>,
 441                         <100000000>, <100000000>,
 442                         <100000000>, <100000000>,
 443                         <50000000>, <100000000>,
 444                         <100000000>, <100000000>,
 445                         <50000000>, <50000000>,
 446                         <50000000>, <50000000>,
 447                         <24000000>, <600000000>,
 448                         <491520000>, <1200000000>,
 449                         <150000000>, <75000000>,
 450                         <75000000>, <150000000>,
 451                         <75000000>, <75000000>,
 452                         <300000000>, <100000000>,
 453                         <300000000>, <200000000>,
 454                         <400000000>, <500000000>,
 455                         <200000000>, <300000000>,
 456                         <300000000>, <250000000>,
 457                         <200000000>, <100000000>,
 458                         <24000000>, <100000000>,
 459                         <150000000>, <50000000>,
 460                         <32768>, <32768>;
 461         };
 462
 463         sdmmc: rksdmmc@ff500000 {
 464                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 465                 reg = <0x0 0xff500000 0x0 0x4000>;
 466                 clock-freq-min-max = <400000 150000000>;
 467                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 468                 clock-names = "biu", "ciu";
 469                 fifo-depth = <0x100>;
 470                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 471                 status = "disabled";
 472         };
 473
 474         sdio: dwmmc@ff510000 {
 475                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 476                 reg = <0x0 0xff510000 0x0 0x4000>;
 477                 clock-freq-min-max = <400000 150000000>;
 478                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 479                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 480                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 481                 fifo-depth = <0x100>;
 482                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 483                 status = "disabled";
 484         };
 485
 486         emmc: rksdmmc@ff520000 {
 487                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 488                 reg = <0x0 0xff520000 0x0 0x4000>;
 489                 clock-freq-min-max = <400000 150000000>;
 490                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 491                 clock-names = "biu", "ciu";
 492                 fifo-depth = <0x100>;
 493                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 494                 status = "disabled";
 495         };
 496
 497         sdmmc_ext: rksdmmc@ff5f0000 {
 498                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 499                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 500                 clock-freq-min-max = <400000 150000000>;
 501                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 502                 clock-names = "biu", "ciu";
 503                 fifo-depth = <0x100>;
 504                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 505                 status = "disabled";
 506         };
 507
 508         gic: interrupt-controller@ff811000 {
 509                 compatible = "arm,gic-400";
 510                 #interrupt-cells = <3>;
 511                 #address-cells = <0>;
 512                 interrupt-controller;
 513                 reg = <0x0 0xff811000 0 0x1000>,
 514                       <0x0 0xff812000 0 0x2000>,
 515                       <0x0 0xff814000 0 0x2000>,
 516                       <0x0 0xff816000 0 0x2000>;
 517                 interrupts = <GIC_PPI 9
 518                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 519         };
 520
 521         pinctrl: pinctrl {
 522                 compatible = "rockchip,rk3328-pinctrl";
 523                 rockchip,grf = <&grf>;
 524                 #address-cells = <2>;
 525                 #size-cells = <2>;
 526                 ranges;
 527
 528                 gpio0: gpio0@ff210000 {
 529                         compatible = "rockchip,gpio-bank";
 530                         reg = <0x0 0xff210000 0x0 0x100>;
 531                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 532                         clocks = <&cru PCLK_GPIO0>;
 533
 534                         gpio-controller;
 535                         #gpio-cells = <2>;
 536
 537                         interrupt-controller;
 538                         #interrupt-cells = <2>;
 539                 };
 540
 541                 gpio1: gpio1@ff220000 {
 542                         compatible = "rockchip,gpio-bank";
 543                         reg = <0x0 0xff220000 0x0 0x100>;
 544                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 545                         clocks = <&cru PCLK_GPIO1>;
 546
 547                         gpio-controller;
 548                         #gpio-cells = <2>;
 549
 550                         interrupt-controller;
 551                         #interrupt-cells = <2>;
 552                 };
 553
 554                 gpio2: gpio2@ff230000 {
 555                         compatible = "rockchip,gpio-bank";
 556                         reg = <0x0 0xff230000 0x0 0x100>;
 557                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 558                         clocks = <&cru PCLK_GPIO2>;
 559
 560                         gpio-controller;
 561                         #gpio-cells = <2>;
 562
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                 };
 566
 567                 gpio3: gpio3@ff240000 {
 568                         compatible = "rockchip,gpio-bank";
 569                         reg = <0x0 0xff240000 0x0 0x100>;
 570                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 571                         clocks = <&cru PCLK_GPIO3>;
 572
 573                         gpio-controller;
 574                         #gpio-cells = <2>;
 575
 576                         interrupt-controller;
 577                         #interrupt-cells = <2>;
 578                 };
 579
 580                 pcfg_pull_up: pcfg-pull-up {
 581                         bias-pull-up;
 582                 };
 583
 584                 pcfg_pull_down: pcfg-pull-down {
 585                         bias-pull-down;
 586                 };
 587
 588                 pcfg_pull_none: pcfg-pull-none {
 589                         bias-disable;
 590                 };
 591
 592                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 593                         bias-disable;
 594                         drive-strength = <2>;
 595                 };
 596
 597                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 598                         bias-pull-up;
 599                         drive-strength = <2>;
 600                 };
 601
 602                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 603                         bias-pull-up;
 604                         drive-strength = <4>;
 605                 };
 606
 607                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 608                         bias-disable;
 609                         drive-strength = <4>;
 610                 };
 611
 612                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 613                         bias-pull-down;
 614                         drive-strength = <4>;
 615                 };
 616
 617                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 618                         bias-disable;
 619                         drive-strength = <8>;
 620                 };
 621
 622                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 623                         bias-pull-up;
 624                         drive-strength = <8>;
 625                 };
 626
 627                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 628                         bias-disable;
 629                         drive-strength = <12>;
 630                 };
 631
 632                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 633                         bias-pull-up;
 634                         drive-strength = <12>;
 635                 };
 636
 637                 pcfg_output_high: pcfg-output-high {
 638                         output-high;
 639                 };
 640
 641                 pcfg_output_low: pcfg-output-low {
 642                         output-low;
 643                 };
 644
 645                 pcfg_input_high: pcfg-input-high {
 646                         bias-pull-up;
 647                         input-enable;
 648                 };
 649
 650                 pcfg_input: pcfg-input {
 651                         input-enable;
 652                 };
 653
 654                 i2c0 {
 655                         i2c0_xfer: i2c0-xfer {
 656                                 rockchip,pins =
 657                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 658                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 659                         };
 660                 };
 661
 662                 i2c1 {
 663                         i2c1_xfer: i2c1-xfer {
 664                                 rockchip,pins =
 665                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 666                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 667                         };
 668                 };
 669
 670                 i2c2 {
 671                         i2c2_xfer: i2c2-xfer {
 672                                 rockchip,pins =
 673                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 674                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 675                         };
 676                 };
 677
 678                 i2c3 {
 679                         i2c3_xfer: i2c3-xfer {
 680                                 rockchip,pins =
 681                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 682                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 683                         };
 684                         i2c3_gpio: i2c3-gpio {
 685                                 rockchip,pins =
 686                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 687                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 688                         };
 689                 };
 690
 691                 hdmi_i2c {
 692                         hdmii2c_xfer: hdmii2c-xfer {
 693                                 rockchip,pins =
 694                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 695                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 696                         };
 697                 };
 698
 699                 uart0 {
 700                         uart0_xfer: uart0-xfer {
 701                                 rockchip,pins =
 702                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 703                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 704                         };
 705
 706                         uart0_cts: uart0-cts {
 707                                 rockchip,pins =
 708                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 709                         };
 710
 711                         uart0_rts: uart0-rts {
 712                                 rockchip,pins =
 713                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 714                         };
 715
 716                         uart0_rts_gpio: uart0-rts-gpio {
 717                                 rockchip,pins =
 718                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 719                         };
 720                 };
 721
 722                 uart1 {
 723                         uart1_xfer: uart1-xfer {
 724                                 rockchip,pins =
 725                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 726                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 727                         };
 728
 729                         uart1_cts: uart1-cts {
 730                                 rockchip,pins =
 731                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 732                         };
 733
 734                         uart1_rts: uart1-rts {
 735                                 rockchip,pins =
 736                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 737                         };
 738
 739                         uart1_rts_gpio: uart1-rts-gpio {
 740                                 rockchip,pins =
 741                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 742                         };
 743                 };
 744
 745                 uart2-0 {
 746                         uart2m0_xfer: uart2m0-xfer {
 747                                 rockchip,pins =
 748                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 749                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 750                         };
 751                 };
 752
 753                 uart2-1 {
 754                         uart2m1_xfer: uart2m1-xfer {
 755                                 rockchip,pins =
 756                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 757                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 758                         };
 759                 };
 760
 761                 spi0-0 {
 762                         spi0m0_clk: spi0m0-clk {
 763                                 rockchip,pins =
 764                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 765                         };
 766
 767                         spi0m0_cs0: spi0m0-cs0 {
 768                                 rockchip,pins =
 769                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 770                         };
 771
 772                         spi0m0_tx: spi0m0-tx {
 773                                 rockchip,pins =
 774                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 775                         };
 776
 777                         spi0m0_rx: spi0m0-rx {
 778                                 rockchip,pins =
 779                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 780                         };
 781
 782                         spi0m0_cs1: spi0m0-cs1 {
 783                                 rockchip,pins =
 784                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 785                         };
 786                 };
 787
 788                 spi0-1 {
 789                         spi0m1_clk: spi0m1-clk {
 790                                 rockchip,pins =
 791                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 792                         };
 793
 794                         spi0m1_cs0: spi0m1-cs0 {
 795                                 rockchip,pins =
 796                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 797                         };
 798
 799                         spi0m1_tx: spi0m1-tx {
 800                                 rockchip,pins =
 801                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 802                         };
 803
 804                         spi0m1_rx: spi0m1-rx {
 805                                 rockchip,pins =
 806                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 807                         };
 808
 809                         spi0m1_cs1: spi0m1-cs1 {
 810                                 rockchip,pins =
 811                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 812                         };
 813                 };
 814
 815                 spi0-2 {
 816                         spi0m2_clk: spi0m2-clk {
 817                                 rockchip,pins =
 818                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 819                         };
 820
 821                         spi0m2_cs0: spi0m2-cs0 {
 822                                 rockchip,pins =
 823                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 824                         };
 825
 826                         spi0m2_tx: spi0m2-tx {
 827                                 rockchip,pins =
 828                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 829                         };
 830
 831                         spi0m2_rx: spi0m2-rx {
 832                                 rockchip,pins =
 833                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 834                         };
 835                 };
 836
 837                 i2s1 {
 838                         i2s1_mclk: i2s1-mclk {
 839                                 rockchip,pins =
 840                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 841                         };
 842
 843                         i2s1_sclk: i2s1-sclk {
 844                                 rockchip,pins =
 845                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 846                         };
 847
 848                         i2s1_lrckrx: i2s1-lrckrx {
 849                                 rockchip,pins =
 850                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 851                         };
 852
 853                         i2s1_lrcktx: i2s1-lrcktx {
 854                                 rockchip,pins =
 855                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 856                         };
 857
 858                         i2s1_sdi: i2s1-sdi {
 859                                 rockchip,pins =
 860                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862
 863                         i2s1_sdo: i2s1-sdo {
 864                                 rockchip,pins =
 865                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 866                         };
 867
 868                         i2s1_sdio1: i2s1-sdio1 {
 869                                 rockchip,pins =
 870                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872
 873                         i2s1_sdio2: i2s1-sdio2 {
 874                                 rockchip,pins =
 875                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 876                         };
 877
 878                         i2s1_sdio3: i2s1-sdio3 {
 879                                 rockchip,pins =
 880                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 881                         };
 882
 883                         i2s1_sleep: i2s1-sleep {
 884                                 rockchip,pins =
 885                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 886                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 887                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 888                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 889                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 890                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 891                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 892                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 893                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 894                         };
 895                 };
 896
 897                 i2s2-0 {
 898                         i2s2m0_mclk: i2s2m0-mclk {
 899                                 rockchip,pins =
 900                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 901                         };
 902
 903                         i2s2m0_sclk: i2s2m0-sclk {
 904                                 rockchip,pins =
 905                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 906                         };
 907
 908                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 909                                 rockchip,pins =
 910                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 911                         };
 912
 913                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 914                                 rockchip,pins =
 915                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 916                         };
 917
 918                         i2s2m0_sdi: i2s2m0-sdi {
 919                                 rockchip,pins =
 920                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 921                         };
 922
 923                         i2s2m0_sdo: i2s2m0-sdo {
 924                                 rockchip,pins =
 925                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 926                         };
 927
 928                         i2s2m0_sleep: i2s2m0-sleep {
 929                                 rockchip,pins =
 930                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 931                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 932                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 933                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 934                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 935                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 936                         };
 937                 };
 938
 939                 i2s2-1 {
 940                         i2s2m1_mclk: i2s2m1-mclk {
 941                                 rockchip,pins =
 942                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 943                         };
 944
 945                         i2s2m1_sclk: i2s2m1-sclk {
 946                                 rockchip,pins =
 947                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 948                         };
 949
 950                         i2s2m1_lrckrx: i2sm1-lrckrx {
 951                                 rockchip,pins =
 952                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 953                         };
 954
 955                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 956                                 rockchip,pins =
 957                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 958                         };
 959
 960                         i2s2m1_sdi: i2s2m1-sdi {
 961                                 rockchip,pins =
 962                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 963                         };
 964
 965                         i2s2m1_sdo: i2s2m1-sdo {
 966                                 rockchip,pins =
 967                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 968                         };
 969
 970                         i2s2m1_sleep: i2s2m1-sleep {
 971                                 rockchip,pins =
 972                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 973                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 974                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 975                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 976                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 977                         };
 978                 };
 979
 980                 spdif-0 {
 981                         spdifm0_tx: spdifm0-tx {
 982                                 rockchip,pins =
 983                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 984                         };
 985                 };
 986
 987                 spdif-1 {
 988                         spdifm1_tx: spdifm1-tx {
 989                                 rockchip,pins =
 990                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 991                         };
 992                 };
 993
 994                 spdif-2 {
 995                         spdifm2_tx: spdifm2-tx {
 996                                 rockchip,pins =
 997                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
 998                         };
 999                 };
1000
1001                 sdmmc0-0 {
1002                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1003                                 rockchip,pins =
1004                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1005                         };
1006
1007                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1008                                 rockchip,pins =
1009                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1010                         };
1011                 };
1012
1013                 sdmmc0-1 {
1014                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1015                                 rockchip,pins =
1016                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1017                         };
1018
1019                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1020                                 rockchip,pins =
1021                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1022                         };
1023                 };
1024
1025                 sdmmc0 {
1026                         sdmmc0_clk: sdmmc0-clk {
1027                                 rockchip,pins =
1028                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1029                         };
1030
1031                         sdmmc0_cmd: sdmmc0-cmd {
1032                                 rockchip,pins =
1033                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1034                         };
1035
1036                         sdmmc0_dectn: sdmmc0-dectn {
1037                                 rockchip,pins =
1038                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1039                         };
1040
1041                         sdmmc0_wrprt: sdmmc0-wrprt {
1042                                 rockchip,pins =
1043                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1044                         };
1045
1046                         sdmmc0_bus1: sdmmc0-bus1 {
1047                                 rockchip,pins =
1048                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1049                         };
1050
1051                         sdmmc0_bus4: sdmmc0-bus4 {
1052                                 rockchip,pins =
1053                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1054                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1055                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1056                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1057                         };
1058
1059                         sdmmc0_gpio: sdmmc0-gpio {
1060                                 rockchip,pins =
1061                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1062                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1063                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1064                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1065                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1066                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1067                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1068                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1069                         };
1070                 };
1071
1072                 sdmmc0ext {
1073                         sdmmc0ext_clk: sdmmc0ext-clk {
1074                                 rockchip,pins =
1075                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1076                         };
1077
1078                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1079                                 rockchip,pins =
1080                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1081                         };
1082
1083                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1084                                 rockchip,pins =
1085                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1086                         };
1087
1088                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1089                                 rockchip,pins =
1090                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1091                         };
1092
1093                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1094                                 rockchip,pins =
1095                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1096                         };
1097
1098                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1099                                 rockchip,pins =
1100                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1101                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1102                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1103                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1104                         };
1105
1106                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1107                                 rockchip,pins =
1108                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1109                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1110                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1111                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1112                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1113                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1114                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1115                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1116                         };
1117                 };
1118
1119                 sdmmc1 {
1120                         sdmmc1_clk: sdmmc1-clk {
1121                                 rockchip,pins =
1122                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1123                         };
1124
1125                         sdmmc1_cmd: sdmmc1-cmd {
1126                                 rockchip,pins =
1127                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1128                         };
1129
1130                         sdmmc1_pwren: sdmmc1-pwren {
1131                                 rockchip,pins =
1132                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1133                         };
1134
1135                         sdmmc1_wrprt: sdmmc1-wrprt {
1136                                 rockchip,pins =
1137                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1138                         };
1139
1140                         sdmmc1_dectn: sdmmc1-dectn {
1141                                 rockchip,pins =
1142                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1143                         };
1144
1145                         sdmmc1_bus1: sdmmc1-bus1 {
1146                                 rockchip,pins =
1147                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1148                         };
1149
1150                         sdmmc1_bus4: sdmmc1-bus4 {
1151                                 rockchip,pins =
1152                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1153                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1154                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1155                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1156                         };
1157
1158                         sdmmc1_gpio: sdmmc1-gpio {
1159                                 rockchip,pins =
1160                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1161                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1162                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1163                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1164                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1165                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1166                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1167                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1168                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1169                         };
1170                 };
1171
1172                 emmc {
1173                         emmc_clk: emmc-clk {
1174                                 rockchip,pins =
1175                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1176                         };
1177
1178                         emmc_cmd: emmc-cmd {
1179                                 rockchip,pins =
1180                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1181                         };
1182
1183                         emmc_pwren: emmc-pwren {
1184                                 rockchip,pins =
1185                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1186                         };
1187
1188                         emmc_rstnout: emmc-rstnout {
1189                                 rockchip,pins =
1190                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1191                         };
1192
1193                         emmc_bus1: emmc-bus1 {
1194                                 rockchip,pins =
1195                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1196                         };
1197
1198                         emmc_bus4: emmc-bus4 {
1199                                 rockchip,pins =
1200                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1201                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1202                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1203                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1204                         };
1205
1206                         emmc_bus8: emmc-bus8 {
1207                                 rockchip,pins =
1208                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1209                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1210                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1211                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1212                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1213                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1214                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1215                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1216                         };
1217                 };
1218
1219                 pwm0 {
1220                         pwm0_pin: pwm0-pin {
1221                                 rockchip,pins =
1222                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1223                         };
1224                 };
1225
1226                 pwm1 {
1227                         pwm1_pin: pwm1-pin {
1228                                 rockchip,pins =
1229                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1230                         };
1231                 };
1232
1233                 pwm2 {
1234                         pwm2_pin: pwm2-pin {
1235                                 rockchip,pins =
1236                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 pwmir {
1241                         pwmir_pin: pwmir-pin {
1242                                 rockchip,pins =
1243                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1244                         };
1245                 };
1246
1247                 gmac-0 {
1248                         rgmiim0_pins: rgmiim0-pins {
1249                                 rockchip,pins =
1250                                         /* mac_txclk */
1251                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1252                                         /* mac_rxclk */
1253                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1254                                         /* mac_mdio */
1255                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1256                                         /* mac_txen */
1257                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1258                                         /* mac_clk */
1259                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1260                                         /* mac_rxdv */
1261                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1262                                         /* mac_mdc */
1263                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1264                                         /* mac_rxd1 */
1265                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1266                                         /* mac_rxd0 */
1267                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1268                                         /* mac_txd1 */
1269                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1270                                         /* mac_txd0 */
1271                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1272                                         /* mac_rxd3 */
1273                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1274                                         /* mac_rxd2 */
1275                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1276                                         /* mac_txd3 */
1277                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1278                                         /* mac_txd2 */
1279                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1280                         };
1281
1282                         rmiim0_pins: rmiim0-pins {
1283                                 rockchip,pins =
1284                                         /* mac_mdio */
1285                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1286                                         /* mac_txen */
1287                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1288                                         /* mac_clk */
1289                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1290                                         /* mac_rxer */
1291                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1292                                         /* mac_rxdv */
1293                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1294                                         /* mac_mdc */
1295                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1296                                         /* mac_rxd1 */
1297                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1298                                         /* mac_rxd0 */
1299                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1300                                         /* mac_txd1 */
1301                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1302                                         /* mac_txd0 */
1303                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1304                         };
1305                 };
1306
1307                 gmac-1 {
1308                         rgmiim1_pins: rgmiim1-pins {
1309                                 rockchip,pins =
1310                                         /* mac_txclk */
1311                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1312                                         /* mac_rxclk */
1313                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1314                                         /* mac_mdio */
1315                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1316                                         /* mac_txen */
1317                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1318                                         /* mac_clk */
1319                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1320                                         /* mac_rxdv */
1321                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1322                                         /* mac_mdc */
1323                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1324                                         /* mac_rxd1 */
1325                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1326                                         /* mac_rxd0 */
1327                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1328                                         /* mac_txd1 */
1329                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1330                                         /* mac_txd0 */
1331                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1332                                         /* mac_rxd3 */
1333                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1334                                         /* mac_rxd2 */
1335                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1336                                         /* mac_txd3 */
1337                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1338                                         /* mac_txd2 */
1339                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1340
1341                                         /* mac_txclk */
1342                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1343                                         /* mac_txen */
1344                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1345                                         /* mac_clk */
1346                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1347                                         /* mac_txd1 */
1348                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1349                                         /* mac_txd0 */
1350                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1351                                         /* mac_txd3 */
1352                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1353                                         /* mac_txd2 */
1354                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1355                         };
1356
1357                         rmiim1_pins: rmiim1-pins {
1358                                 rockchip,pins =
1359                                         /* mac_mdio */
1360                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1361                                         /* mac_txen */
1362                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1363                                         /* mac_clk */
1364                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1365                                         /* mac_rxer */
1366                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1367                                         /* mac_rxdv */
1368                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1369                                         /* mac_mdc */
1370                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1371                                         /* mac_rxd1 */
1372                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1373                                         /* mac_rxd0 */
1374                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1375                                         /* mac_txd1 */
1376                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1377                                         /* mac_txd0 */
1378                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1379
1380                                         /* mac_mdio */
1381                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1382                                         /* mac_txen */
1383                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1384                                         /* mac_clk */
1385                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1386                                         /* mac_mdc */
1387                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1388                                         /* mac_txd1 */
1389                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1390                                         /* mac_txd0 */
1391                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1392                         };
1393                 };
1394
1395                 gmac2phy {
1396                         fephyled_speed100: fephyled-speed100 {
1397                                 rockchip,pins =
1398                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1399                         };
1400
1401                         fephyled_speed10: fephyled-speed10 {
1402                                 rockchip,pins =
1403                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1404                         };
1405
1406                         fephyled_duplex: fephyled-duplex {
1407                                 rockchip,pins =
1408                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1409                         };
1410
1411                         fephyled_rxm0: fephyled-rxm0 {
1412                                 rockchip,pins =
1413                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1414                         };
1415
1416                         fephyled_txm0: fephyled-txm0 {
1417                                 rockchip,pins =
1418                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1419                         };
1420
1421                         fephyled_linkm0: fephyled-linkm0 {
1422                                 rockchip,pins =
1423                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1424                         };
1425
1426                         fephyled_rxm1: fephyled-rxm1 {
1427                                 rockchip,pins =
1428                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1429                         };
1430
1431                         fephyled_txm1: fephyled-txm1 {
1432                                 rockchip,pins =
1433                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1434                         };
1435
1436                         fephyled_linkm1: fephyled-linkm1 {
1437                                 rockchip,pins =
1438                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1439                         };
1440                 };
1441
1442                 tsadc_pin {
1443                         tsadc_int: tsadc-int {
1444                                 rockchip,pins =
1445                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1446                         };
1447                         tsadc_gpio: tsadc-gpio {
1448                                 rockchip,pins =
1449                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 hdmi_pin {
1454                         hdmi_cec: hdmi-cec {
1455                                 rockchip,pins =
1456                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1457                         };
1458
1459                         hdmi_hpd: hdmi-hpd {
1460                                 rockchip,pins =
1461                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1462                         };
1463                 };
1464
1465                 cif-0 {
1466                         dvp_d2d9_m0:dvp-d2d9-m0 {
1467                                 rockchip,pins =
1468                                         /* cif_d0 */
1469                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1470                                         /* cif_d1 */
1471                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1472                                         /* cif_d2 */
1473                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1474                                         /* cif_d3 */
1475                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1476                                         /* cif_d4 */
1477                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1478                                         /* cif_d5m0 */
1479                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1480                                         /* cif_d6m0 */
1481                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1482                                         /* cif_d7m0 */
1483                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1484                                         /* cif_href */
1485                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1486                                         /* cif_vsync */
1487                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1488                                         /* cif_clkoutm0 */
1489                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1490                                         /* cif_clkin */
1491                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1492                         };
1493                 };
1494
1495                 cif-1 {
1496                         dvp_d2d9_m1:dvp-d2d9-m1 {
1497                                 rockchip,pins =
1498                                         /* cif_d0 */
1499                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1500                                         /* cif_d1 */
1501                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1502                                         /* cif_d2 */
1503                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1504                                         /* cif_d3 */
1505                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1506                                         /* cif_d4 */
1507                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1508                                         /* cif_d5m1 */
1509                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1510                                         /* cif_d6m1 */
1511                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1512                                         /* cif_d7m1 */
1513                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1514                                         /* cif_href */
1515                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1516                                         /* cif_vsync */
1517                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1518                                         /* cif_clkoutm1 */
1519                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1520                                         /* cif_clkin */
1521                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1522                         };
1523                 };
1524         };
1525 };