arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49
  50 / {
  51         compatible = "rockchip,rk3328";
  52
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 serial0 = &uart0;
  59                 serial1 = &uart1;
  60                 serial2 = &uart2;
  61                 i2c0 = &i2c0;
  62                 i2c1 = &i2c1;
  63                 i2c2 = &i2c2;
  64                 i2c3 = &i2c3;
  65         };
  66
  67         cpus {
  68                 #address-cells = <2>;
  69                 #size-cells = <0>;
  70
  71                 cpu0: cpu@0 {
  72                         device_type = "cpu";
  73                         compatible = "arm,cortex-a53", "arm,armv8";
  74                         reg = <0x0 0x0>;
  75                         enable-method = "psci";
  76 //                      clocks = <&cru ARMCLK>;
  77                         operating-points-v2 = <&cpu0_opp_table>;
  78                 };
  79                 cpu1: cpu@1 {
  80                         device_type = "cpu";
  81                         compatible = "arm,cortex-a53", "arm,armv8";
  82                         reg = <0x0 0x1>;
  83                         enable-method = "psci";
  84                 };
  85                 cpu2: cpu@2 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a53", "arm,armv8";
  88                         reg = <0x0 0x2>;
  89                         enable-method = "psci";
  90                 };
  91                 cpu3: cpu@3 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a53", "arm,armv8";
  94                         reg = <0x0 0x3>;
  95                         enable-method = "psci";
  96                 };
  97         };
  98
  99         cpu0_opp_table: opp_table0 {
 100                 compatible = "operating-points-v2";
 101                 opp-shared;
 102
 103                 opp@408000000 {
 104                         opp-hz = /bits/ 64 <408000000>;
 105                         opp-microvolt = <950000>;
 106                         clock-latency-ns = <40000>;
 107                         opp-suspend;
 108                 };
 109                 opp@600000000 {
 110                         opp-hz = /bits/ 64 <600000000>;
 111                         opp-microvolt = <950000>;
 112                         clock-latency-ns = <40000>;
 113                 };
 114                 opp@816000000 {
 115                         opp-hz = /bits/ 64 <816000000>;
 116                         opp-microvolt = <1000000>;
 117                         clock-latency-ns = <40000>;
 118                 };
 119                 opp@1008000000 {
 120                         opp-hz = /bits/ 64 <1008000000>;
 121                         opp-microvolt = <1100000>;
 122                         clock-latency-ns = <40000>;
 123                 };
 124                 opp@1200000000 {
 125                         opp-hz = /bits/ 64 <1200000000>;
 126                         opp-microvolt = <1225000>;
 127                         clock-latency-ns = <40000>;
 128                 };
 129                 opp@1296000000 {
 130                         opp-hz = /bits/ 64 <1296000000>;
 131                         opp-microvolt = <1300000>;
 132                         clock-latency-ns = <40000>;
 133                 };
 134         };
 135
 136         arm-pmu {
 137                 compatible = "arm,cortex-a53-pmu";
 138                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 139                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 142                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 143         };
 144
 145         psci {
 146                 compatible = "arm,psci-1.0";
 147                 method = "smc";
 148         };
 149
 150         timer {
 151                 compatible = "arm,armv8-timer";
 152                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 153                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 156         };
 157
 158         xin24m: xin24m {
 159                 compatible = "fixed-clock";
 160                 #clock-cells = <0>;
 161                 clock-frequency = <24000000>;
 162                 clock-output-names = "xin24m";
 163         };
 164
 165         i2s0: i2s@ff000000 {
 166                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 167                 reg = <0x0 0xff000000 0x0 0x1000>;
 168                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 169                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 170                 clock-names = "i2s_clk", "i2s_hclk";
 171                 dmas = <&dmac 11>, <&dmac 12>;
 172                 #dma-cells = <2>;
 173                 dma-names = "tx", "rx";
 174                 status = "disabled";
 175         };
 176
 177         i2s1: i2s@ff010000 {
 178                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 179                 reg = <0x0 0xff010000 0x0 0x1000>;
 180                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 181                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 182                 clock-names = "i2s_clk", "i2s_hclk";
 183                 dmas = <&dmac 14>, <&dmac 15>;
 184                 #dma-cells = <2>;
 185                 dma-names = "tx", "rx";
 186                 status = "disabled";
 187         };
 188
 189         i2s2: i2s@ff020000 {
 190                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 191                 reg = <0x0 0xff020000 0x0 0x1000>;
 192                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 193                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 194                 clock-names = "i2s_clk", "i2s_hclk";
 195                 dmas = <&dmac 0>, <&dmac 1>;
 196                 #dma-cells = <2>;
 197                 dma-names = "tx", "rx";
 198                 pinctrl-names = "default", "sleep";
 199                 pinctrl-0 = <&i2s2m0_mclk
 200                              &i2s2m0_sclk
 201                              &i2s2m0_lrcktx
 202                              &i2s2m0_lrckrx
 203                              &i2s2m0_sdo
 204                              &i2s2m0_sdi>;
 205                 pinctrl-1 = <&i2s2m0_sleep>;
 206                 status = "disabled";
 207         };
 208
 209         spdif: spdif@ff030000 {
 210                 compatible = "rockchip,rk3328-spdif";
 211                 reg = <0x0 0xff030000 0x0 0x1000>;
 212                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 213                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 214                 clock-names = "mclk", "hclk";
 215                 dmas = <&dmac 10>;
 216                 #dma-cells = <1>;
 217                 dma-names = "tx";
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&spdifm2_tx>;
 220                 status = "disabled";
 221         };
 222
 223         grf: syscon@ff100000 {
 224                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 225                 reg = <0x0 0xff100000 0x0 0x1000>;
 226                 #address-cells = <1>;
 227                 #size-cells = <1>;
 228
 229                 io_domains: io-domains {
 230                         compatible = "rockchip,rk3328-io-voltage-domain";
 231                         status = "disabled";
 232                 };
 233
 234                 reboot-mode {
 235                         compatible = "syscon-reboot-mode";
 236                         offset = <0x5c8>;
 237                         mode-bootloader = <BOOT_LOADER>;
 238                         mode-charge = <BOOT_CHARGING>;
 239                         mode-fastboot = <BOOT_FASTBOOT>;
 240                         mode-loader = <BOOT_LOADER>;
 241                         mode-normal = <BOOT_NORMAL>;
 242                         mode-recovery = <BOOT_RECOVERY>;
 243                         mode-ums = <BOOT_UMS>;
 244                 };
 245         };
 246
 247         uart0: serial@ff110000 {
 248                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 249                 reg = <0x0 0xff110000 0x0 0x100>;
 250                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 251                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 252                 clock-names = "baudclk", "apb_pclk";
 253                 reg-shift = <2>;
 254                 reg-io-width = <4>;
 255                 dmas = <&dmac 2>, <&dmac 3>;
 256                 #dma-cells = <2>;
 257                 pinctrl-names = "default";
 258                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 259                 status = "disabled";
 260         };
 261
 262         uart1: serial@ff120000 {
 263                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 264                 reg = <0x0 0xff120000 0x0 0x100>;
 265                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 266                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 267                 clock-names = "sclk_uart", "pclk_uart";
 268                 reg-shift = <2>;
 269                 reg-io-width = <4>;
 270                 dmas = <&dmac 4>, <&dmac 5>;
 271                 #dma-cells = <2>;
 272                 pinctrl-names = "default";
 273                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 274                 status = "disabled";
 275         };
 276
 277         uart2: serial@ff130000 {
 278                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 279                 reg = <0x0 0xff130000 0x0 0x100>;
 280                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 281                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 282                 clock-names = "baudclk", "apb_pclk";
 283                 reg-shift = <2>;
 284                 reg-io-width = <4>;
 285                 dmas = <&dmac 6>, <&dmac 7>;
 286                 #dma-cells = <2>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&uart2m1_xfer>;
 289                 status = "disabled";
 290         };
 291
 292         pmu: power-management@ff140000 {
 293                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 294                 reg = <0x0 0xff140000 0x0 0x1000>;
 295         };
 296
 297         i2c0: i2c@ff150000 {
 298                 compatible = "rockchip,rk3328-i2c";
 299                 reg = <0x0 0xff150000 0x0 0x1000>;
 300                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 304                 clock-names = "i2c", "pclk";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c0_xfer>;
 307                 status = "disabled";
 308         };
 309
 310         i2c1: i2c@ff160000 {
 311                 compatible = "rockchip,rk3328-i2c";
 312                 reg = <0x0 0xff160000 0x0 0x1000>;
 313                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 317                 clock-names = "i2c", "pclk";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&i2c1_xfer>;
 320                 status = "disabled";
 321         };
 322
 323         i2c2: i2c@ff170000 {
 324                 compatible = "rockchip,rk3328-i2c";
 325                 reg = <0x0 0xff170000 0x0 0x1000>;
 326                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 330                 clock-names = "i2c", "pclk";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&i2c2_xfer>;
 333                 status = "disabled";
 334         };
 335
 336         i2c3: i2c@ff180000 {
 337                 compatible = "rockchip,rk3328-i2c";
 338                 reg = <0x0 0xff180000 0x0 0x1000>;
 339                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 340                 #address-cells = <1>;
 341                 #size-cells = <0>;
 342                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 343                 clock-names = "i2c", "pclk";
 344                 pinctrl-names = "default";
 345                 pinctrl-0 = <&i2c3_xfer>;
 346                 status = "disabled";
 347         };
 348
 349         spi0: spi@ff190000 {
 350                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 351                 reg = <0x0 0xff190000 0x0 0x1000>;
 352                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 353                 #address-cells = <1>;
 354                 #size-cells = <0>;
 355                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 356                 clock-names = "spiclk", "apb_pclk";
 357                 dmas = <&dmac 8>, <&dmac 9>;
 358                 #dma-cells = <2>;
 359                 dma-names = "tx", "rx";
 360                 pinctrl-names = "default";
 361                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 362                 status = "disabled";
 363         };
 364
 365         wdt: watchdog@ff1a0000 {
 366                 compatible = "snps,dw-wdt";
 367                 reg = <0x0 0xff1a0000 0x0 0x100>;
 368                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 369                 status = "disabled";
 370         };
 371
 372         amba {
 373                 compatible = "simple-bus";
 374                 #address-cells = <2>;
 375                 #size-cells = <2>;
 376                 ranges;
 377
 378                 dmac: dmac@ff1f0000 {
 379                         compatible = "arm,pl330", "arm,primecell";
 380                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 381                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 382                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 383                         clocks = <&cru ACLK_DMAC>;
 384                         clock-names = "apb_pclk";
 385                         #dma-cells = <1>;
 386                 };
 387         };
 388
 389         saradc: saradc@ff280000 {
 390                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 391                 reg = <0x0 0xff280000 0x0 0x100>;
 392                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 393                 #io-channel-cells = <1>;
 394                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 395                 clock-names = "saradc", "apb_pclk";
 396                 resets = <&cru SRST_SARADC_P>;
 397                 reset-names = "saradc-apb";
 398                 status = "disabled";
 399         };
 400
 401         cru: clock-controller@ff440000 {
 402                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 403                 reg = <0x0 0xff440000 0x0 0x1000>;
 404                 rockchip,grf = <&grf>;
 405                 #clock-cells = <1>;
 406                 #reset-cells = <1>;
 407                 assigned-clocks =
 408                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 409                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 410                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 411                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 412                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 413                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 414                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 415                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 416                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 417                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 418                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 419                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 420                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 421                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 422                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 423                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 424                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 425                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 426                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 427                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 428                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 429                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 430                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 431                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 432                 assigned-clock-parents =
 433                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 434                         <&cru PLL_GPLL>, <&xin24m>,
 435                         <&xin24m>, <&xin24m>;
 436                 assigned-clock-rates =
 437                         <0>, <61440000>,
 438                         <0>, <24000000>,
 439                         <24000000>, <24000000>,
 440                         <15000000>, <15000000>,
 441                         <100000000>, <100000000>,
 442                         <100000000>, <100000000>,
 443                         <50000000>, <100000000>,
 444                         <100000000>, <100000000>,
 445                         <50000000>, <50000000>,
 446                         <50000000>, <50000000>,
 447                         <24000000>, <600000000>,
 448                         <491520000>, <1200000000>,
 449                         <150000000>, <75000000>,
 450                         <75000000>, <150000000>,
 451                         <75000000>, <75000000>,
 452                         <300000000>, <100000000>,
 453                         <300000000>, <200000000>,
 454                         <400000000>, <500000000>,
 455                         <200000000>, <300000000>,
 456                         <300000000>, <250000000>,
 457                         <200000000>, <100000000>,
 458                         <24000000>, <100000000>,
 459                         <150000000>, <50000000>,
 460                         <32768>, <32768>;
 461         };
 462
 463         gic: interrupt-controller@ff811000 {
 464                 compatible = "arm,gic-400";
 465                 #interrupt-cells = <3>;
 466                 #address-cells = <0>;
 467                 interrupt-controller;
 468                 reg = <0x0 0xff811000 0 0x1000>,
 469                       <0x0 0xff812000 0 0x2000>,
 470                       <0x0 0xff814000 0 0x2000>,
 471                       <0x0 0xff816000 0 0x2000>;
 472                 interrupts = <GIC_PPI 9
 473                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 474         };
 475
 476         pinctrl: pinctrl {
 477                 compatible = "rockchip,rk3328-pinctrl";
 478                 rockchip,grf = <&grf>;
 479                 #address-cells = <2>;
 480                 #size-cells = <2>;
 481                 ranges;
 482
 483                 gpio0: gpio0@ff210000 {
 484                         compatible = "rockchip,gpio-bank";
 485                         reg = <0x0 0xff210000 0x0 0x100>;
 486                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 487                         clocks = <&cru PCLK_GPIO0>;
 488
 489                         gpio-controller;
 490                         #gpio-cells = <2>;
 491
 492                         interrupt-controller;
 493                         #interrupt-cells = <2>;
 494                 };
 495
 496                 gpio1: gpio1@ff220000 {
 497                         compatible = "rockchip,gpio-bank";
 498                         reg = <0x0 0xff220000 0x0 0x100>;
 499                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 500                         clocks = <&cru PCLK_GPIO1>;
 501
 502                         gpio-controller;
 503                         #gpio-cells = <2>;
 504
 505                         interrupt-controller;
 506                         #interrupt-cells = <2>;
 507                 };
 508
 509                 gpio2: gpio2@ff230000 {
 510                         compatible = "rockchip,gpio-bank";
 511                         reg = <0x0 0xff230000 0x0 0x100>;
 512                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 513                         clocks = <&cru PCLK_GPIO2>;
 514
 515                         gpio-controller;
 516                         #gpio-cells = <2>;
 517
 518                         interrupt-controller;
 519                         #interrupt-cells = <2>;
 520                 };
 521
 522                 gpio3: gpio3@ff240000 {
 523                         compatible = "rockchip,gpio-bank";
 524                         reg = <0x0 0xff240000 0x0 0x100>;
 525                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&cru PCLK_GPIO3>;
 527
 528                         gpio-controller;
 529                         #gpio-cells = <2>;
 530
 531                         interrupt-controller;
 532                         #interrupt-cells = <2>;
 533                 };
 534
 535                 pcfg_pull_up: pcfg-pull-up {
 536                         bias-pull-up;
 537                 };
 538
 539                 pcfg_pull_down: pcfg-pull-down {
 540                         bias-pull-down;
 541                 };
 542
 543                 pcfg_pull_none: pcfg-pull-none {
 544                         bias-disable;
 545                 };
 546
 547                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 548                         bias-disable;
 549                         drive-strength = <2>;
 550                 };
 551
 552                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 553                         bias-pull-up;
 554                         drive-strength = <2>;
 555                 };
 556
 557                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 558                         bias-pull-up;
 559                         drive-strength = <4>;
 560                 };
 561
 562                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 563                         bias-disable;
 564                         drive-strength = <4>;
 565                 };
 566
 567                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 568                         bias-pull-down;
 569                         drive-strength = <4>;
 570                 };
 571
 572                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 573                         bias-disable;
 574                         drive-strength = <8>;
 575                 };
 576
 577                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 578                         bias-pull-up;
 579                         drive-strength = <8>;
 580                 };
 581
 582                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 583                         bias-disable;
 584                         drive-strength = <12>;
 585                 };
 586
 587                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 588                         bias-pull-up;
 589                         drive-strength = <12>;
 590                 };
 591
 592                 pcfg_output_high: pcfg-output-high {
 593                         output-high;
 594                 };
 595
 596                 pcfg_output_low: pcfg-output-low {
 597                         output-low;
 598                 };
 599
 600                 pcfg_input_high: pcfg-input-high {
 601                         bias-pull-up;
 602                         input-enable;
 603                 };
 604
 605                 pcfg_input: pcfg-input {
 606                         input-enable;
 607                 };
 608
 609                 i2c0 {
 610                         i2c0_xfer: i2c0-xfer {
 611                                 rockchip,pins =
 612                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 613                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 614                         };
 615                 };
 616
 617                 i2c1 {
 618                         i2c1_xfer: i2c1-xfer {
 619                                 rockchip,pins =
 620                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 621                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 622                         };
 623                 };
 624
 625                 i2c2 {
 626                         i2c2_xfer: i2c2-xfer {
 627                                 rockchip,pins =
 628                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 629                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 630                         };
 631                 };
 632
 633                 i2c3 {
 634                         i2c3_xfer: i2c3-xfer {
 635                                 rockchip,pins =
 636                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 637                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 638                         };
 639                         i2c3_gpio: i2c3-gpio {
 640                                 rockchip,pins =
 641                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 642                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 643                         };
 644                 };
 645
 646                 hdmi_i2c {
 647                         hdmii2c_xfer: hdmii2c-xfer {
 648                                 rockchip,pins =
 649                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 650                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 651                         };
 652                 };
 653
 654                 uart0 {
 655                         uart0_xfer: uart0-xfer {
 656                                 rockchip,pins =
 657                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 658                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 659                         };
 660
 661                         uart0_cts: uart0-cts {
 662                                 rockchip,pins =
 663                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 664                         };
 665
 666                         uart0_rts: uart0-rts {
 667                                 rockchip,pins =
 668                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 669                         };
 670
 671                         uart0_rts_gpio: uart0-rts-gpio {
 672                                 rockchip,pins =
 673                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 674                         };
 675                 };
 676
 677                 uart1 {
 678                         uart1_xfer: uart1-xfer {
 679                                 rockchip,pins =
 680                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 681                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 682                         };
 683
 684                         uart1_cts: uart1-cts {
 685                                 rockchip,pins =
 686                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 687                         };
 688
 689                         uart1_rts: uart1-rts {
 690                                 rockchip,pins =
 691                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 692                         };
 693
 694                         uart1_rts_gpio: uart1-rts-gpio {
 695                                 rockchip,pins =
 696                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 697                         };
 698                 };
 699
 700                 uart2-0 {
 701                         uart2m0_xfer: uart2m0-xfer {
 702                                 rockchip,pins =
 703                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 704                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 705                         };
 706                 };
 707
 708                 uart2-1 {
 709                         uart2m1_xfer: uart2m1-xfer {
 710                                 rockchip,pins =
 711                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 712                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 713                         };
 714                 };
 715
 716                 spi0-0 {
 717                         spi0m0_clk: spi0m0-clk {
 718                                 rockchip,pins =
 719                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 720                         };
 721
 722                         spi0m0_cs0: spi0m0-cs0 {
 723                                 rockchip,pins =
 724                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 725                         };
 726
 727                         spi0m0_tx: spi0m0-tx {
 728                                 rockchip,pins =
 729                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 730                         };
 731
 732                         spi0m0_rx: spi0m0-rx {
 733                                 rockchip,pins =
 734                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 735                         };
 736
 737                         spi0m0_cs1: spi0m0-cs1 {
 738                                 rockchip,pins =
 739                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 740                         };
 741                 };
 742
 743                 spi0-1 {
 744                         spi0m1_clk: spi0m1-clk {
 745                                 rockchip,pins =
 746                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 747                         };
 748
 749                         spi0m1_cs0: spi0m1-cs0 {
 750                                 rockchip,pins =
 751                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 752                         };
 753
 754                         spi0m1_tx: spi0m1-tx {
 755                                 rockchip,pins =
 756                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 757                         };
 758
 759                         spi0m1_rx: spi0m1-rx {
 760                                 rockchip,pins =
 761                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 762                         };
 763
 764                         spi0m1_cs1: spi0m1-cs1 {
 765                                 rockchip,pins =
 766                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 767                         };
 768                 };
 769
 770                 spi0-2 {
 771                         spi0m2_clk: spi0m2-clk {
 772                                 rockchip,pins =
 773                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 774                         };
 775
 776                         spi0m2_cs0: spi0m2-cs0 {
 777                                 rockchip,pins =
 778                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 779                         };
 780
 781                         spi0m2_tx: spi0m2-tx {
 782                                 rockchip,pins =
 783                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 784                         };
 785
 786                         spi0m2_rx: spi0m2-rx {
 787                                 rockchip,pins =
 788                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 789                         };
 790                 };
 791
 792                 i2s1 {
 793                         i2s1_mclk: i2s1-mclk {
 794                                 rockchip,pins =
 795                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 796                         };
 797
 798                         i2s1_sclk: i2s1-sclk {
 799                                 rockchip,pins =
 800                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 801                         };
 802
 803                         i2s1_lrckrx: i2s1-lrckrx {
 804                                 rockchip,pins =
 805                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 806                         };
 807
 808                         i2s1_lrcktx: i2s1-lrcktx {
 809                                 rockchip,pins =
 810                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 811                         };
 812
 813                         i2s1_sdi: i2s1-sdi {
 814                                 rockchip,pins =
 815                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 816                         };
 817
 818                         i2s1_sdo: i2s1-sdo {
 819                                 rockchip,pins =
 820                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 821                         };
 822
 823                         i2s1_sdio1: i2s1-sdio1 {
 824                                 rockchip,pins =
 825                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 826                         };
 827
 828                         i2s1_sdio2: i2s1-sdio2 {
 829                                 rockchip,pins =
 830                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
 831                         };
 832
 833                         i2s1_sdio3: i2s1-sdio3 {
 834                                 rockchip,pins =
 835                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
 836                         };
 837
 838                         i2s1_sleep: i2s1-sleep {
 839                                 rockchip,pins =
 840                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
 841                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
 842                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
 843                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
 844                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
 845                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
 846                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
 847                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
 848                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
 849                         };
 850                 };
 851
 852                 i2s2-0 {
 853                         i2s2m0_mclk: i2s2m0-mclk {
 854                                 rockchip,pins =
 855                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 856                         };
 857
 858                         i2s2m0_sclk: i2s2m0-sclk {
 859                                 rockchip,pins =
 860                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
 861                         };
 862
 863                         i2s2m0_lrckrx: i2s2m0-lrckrx {
 864                                 rockchip,pins =
 865                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
 866                         };
 867
 868                         i2s2m0_lrcktx: i2s2m0-lrcktx {
 869                                 rockchip,pins =
 870                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
 871                         };
 872
 873                         i2s2m0_sdi: i2s2m0-sdi {
 874                                 rockchip,pins =
 875                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
 876                         };
 877
 878                         i2s2m0_sdo: i2s2m0-sdo {
 879                                 rockchip,pins =
 880                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
 881                         };
 882
 883                         i2s2m0_sleep: i2s2m0-sleep {
 884                                 rockchip,pins =
 885                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 886                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
 887                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
 888                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
 889                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
 890                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
 891                         };
 892                 };
 893
 894                 i2s2-1 {
 895                         i2s2m1_mclk: i2s2m1-mclk {
 896                                 rockchip,pins =
 897                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
 898                         };
 899
 900                         i2s2m1_sclk: i2s2m1-sclk {
 901                                 rockchip,pins =
 902                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
 903                         };
 904
 905                         i2s2m1_lrckrx: i2sm1-lrckrx {
 906                                 rockchip,pins =
 907                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
 908                         };
 909
 910                         i2s2m1_lrcktx: i2s2m1-lrcktx {
 911                                 rockchip,pins =
 912                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
 913                         };
 914
 915                         i2s2m1_sdi: i2s2m1-sdi {
 916                                 rockchip,pins =
 917                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
 918                         };
 919
 920                         i2s2m1_sdo: i2s2m1-sdo {
 921                                 rockchip,pins =
 922                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
 923                         };
 924
 925                         i2s2m1_sleep: i2s2m1-sleep {
 926                                 rockchip,pins =
 927                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
 928                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
 929                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
 930                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
 931                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
 932                         };
 933                 };
 934
 935                 spdif-0 {
 936                         spdifm0_tx: spdifm0-tx {
 937                                 rockchip,pins =
 938                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
 939                         };
 940                 };
 941
 942                 spdif-1 {
 943                         spdifm1_tx: spdifm1-tx {
 944                                 rockchip,pins =
 945                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
 946                         };
 947                 };
 948
 949                 spdif-2 {
 950                         spdifm2_tx: spdifm2-tx {
 951                                 rockchip,pins =
 952                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 sdmmc0-0 {
 957                         sdmmc0m0_pwren: sdmmc0m0-pwren {
 958                                 rockchip,pins =
 959                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 960                         };
 961
 962                         sdmmc0m0_gpio: sdmmc0m0-gpio {
 963                                 rockchip,pins =
 964                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 965                         };
 966                 };
 967
 968                 sdmmc0-1 {
 969                         sdmmc0m1_pwren: sdmmc0m1-pwren {
 970                                 rockchip,pins =
 971                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
 972                         };
 973
 974                         sdmmc0m1_gpio: sdmmc0m1-gpio {
 975                                 rockchip,pins =
 976                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
 977                         };
 978                 };
 979
 980                 sdmmc0 {
 981                         sdmmc0_clk: sdmmc0-clk {
 982                                 rockchip,pins =
 983                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
 984                         };
 985
 986                         sdmmc0_cmd: sdmmc0-cmd {
 987                                 rockchip,pins =
 988                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
 989                         };
 990
 991                         sdmmc0_dectn: sdmmc0-dectn {
 992                                 rockchip,pins =
 993                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
 994                         };
 995
 996                         sdmmc0_wrprt: sdmmc0-wrprt {
 997                                 rockchip,pins =
 998                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
 999                         };
1000
1001                         sdmmc0_bus1: sdmmc0-bus1 {
1002                                 rockchip,pins =
1003                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1004                         };
1005
1006                         sdmmc0_bus4: sdmmc0-bus4 {
1007                                 rockchip,pins =
1008                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1009                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1010                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1011                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1012                         };
1013
1014                         sdmmc0_gpio: sdmmc0-gpio {
1015                                 rockchip,pins =
1016                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1017                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1018                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1019                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1020                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1021                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1022                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1023                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1024                         };
1025                 };
1026
1027                 sdmmc0ext {
1028                         sdmmc0ext_clk: sdmmc0ext-clk {
1029                                 rockchip,pins =
1030                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1031                         };
1032
1033                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1034                                 rockchip,pins =
1035                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1036                         };
1037
1038                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1039                                 rockchip,pins =
1040                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1041                         };
1042
1043                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1044                                 rockchip,pins =
1045                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1046                         };
1047
1048                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1049                                 rockchip,pins =
1050                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1051                         };
1052
1053                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1054                                 rockchip,pins =
1055                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1056                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1057                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1058                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1059                         };
1060
1061                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1062                                 rockchip,pins =
1063                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1064                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1065                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1066                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1067                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1068                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1069                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1070                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1071                         };
1072                 };
1073
1074                 sdmmc1 {
1075                         sdmmc1_clk: sdmmc1-clk {
1076                                 rockchip,pins =
1077                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1078                         };
1079
1080                         sdmmc1_cmd: sdmmc1-cmd {
1081                                 rockchip,pins =
1082                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1083                         };
1084
1085                         sdmmc1_pwren: sdmmc1-pwren {
1086                                 rockchip,pins =
1087                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1088                         };
1089
1090                         sdmmc1_wrprt: sdmmc1-wrprt {
1091                                 rockchip,pins =
1092                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1093                         };
1094
1095                         sdmmc1_dectn: sdmmc1-dectn {
1096                                 rockchip,pins =
1097                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1098                         };
1099
1100                         sdmmc1_bus1: sdmmc1-bus1 {
1101                                 rockchip,pins =
1102                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1103                         };
1104
1105                         sdmmc1_bus4: sdmmc1-bus4 {
1106                                 rockchip,pins =
1107                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1108                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1109                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1110                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1111                         };
1112
1113                         sdmmc1_gpio: sdmmc1-gpio {
1114                                 rockchip,pins =
1115                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1116                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1117                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1118                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1119                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1120                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1121                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1122                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1123                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1124                         };
1125                 };
1126
1127                 emmc {
1128                         emmc_clk: emmc-clk {
1129                                 rockchip,pins =
1130                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1131                         };
1132
1133                         emmc_cmd: emmc-cmd {
1134                                 rockchip,pins =
1135                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1136                         };
1137
1138                         emmc_pwren: emmc-pwren {
1139                                 rockchip,pins =
1140                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1141                         };
1142
1143                         emmc_rstnout: emmc-rstnout {
1144                                 rockchip,pins =
1145                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1146                         };
1147
1148                         emmc_bus1: emmc-bus1 {
1149                                 rockchip,pins =
1150                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1151                         };
1152
1153                         emmc_bus4: emmc-bus4 {
1154                                 rockchip,pins =
1155                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1156                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1157                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1158                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1159                         };
1160
1161                         emmc_bus8: emmc-bus8 {
1162                                 rockchip,pins =
1163                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1164                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1165                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1166                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1167                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1168                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1169                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1170                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1171                         };
1172                 };
1173
1174                 pwm0 {
1175                         pwm0_pin: pwm0-pin {
1176                                 rockchip,pins =
1177                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1178                         };
1179                 };
1180
1181                 pwm1 {
1182                         pwm1_pin: pwm1-pin {
1183                                 rockchip,pins =
1184                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 pwm2 {
1189                         pwm2_pin: pwm2-pin {
1190                                 rockchip,pins =
1191                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1192                         };
1193                 };
1194
1195                 pwmir {
1196                         pwmir_pin: pwmir-pin {
1197                                 rockchip,pins =
1198                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200                 };
1201
1202                 gmac-0 {
1203                         rgmiim0_pins: rgmiim0-pins {
1204                                 rockchip,pins =
1205                                         /* mac_txclk */
1206                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1207                                         /* mac_rxclk */
1208                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1209                                         /* mac_mdio */
1210                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1211                                         /* mac_txen */
1212                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1213                                         /* mac_clk */
1214                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1215                                         /* mac_rxdv */
1216                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1217                                         /* mac_mdc */
1218                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1219                                         /* mac_rxd1 */
1220                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1221                                         /* mac_rxd0 */
1222                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1223                                         /* mac_txd1 */
1224                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1225                                         /* mac_txd0 */
1226                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1227                                         /* mac_rxd3 */
1228                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1229                                         /* mac_rxd2 */
1230                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1231                                         /* mac_txd3 */
1232                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1233                                         /* mac_txd2 */
1234                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1235                         };
1236
1237                         rmiim0_pins: rmiim0-pins {
1238                                 rockchip,pins =
1239                                         /* mac_mdio */
1240                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1241                                         /* mac_txen */
1242                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1243                                         /* mac_clk */
1244                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1245                                         /* mac_rxer */
1246                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1247                                         /* mac_rxdv */
1248                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1249                                         /* mac_mdc */
1250                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1251                                         /* mac_rxd1 */
1252                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1253                                         /* mac_rxd0 */
1254                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1255                                         /* mac_txd1 */
1256                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1257                                         /* mac_txd0 */
1258                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1259                         };
1260                 };
1261
1262                 gmac-1 {
1263                         rgmiim1_pins: rgmiim1-pins {
1264                                 rockchip,pins =
1265                                         /* mac_txclk */
1266                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1267                                         /* mac_rxclk */
1268                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1269                                         /* mac_mdio */
1270                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1271                                         /* mac_txen */
1272                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1273                                         /* mac_clk */
1274                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1275                                         /* mac_rxdv */
1276                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1277                                         /* mac_mdc */
1278                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1279                                         /* mac_rxd1 */
1280                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1281                                         /* mac_rxd0 */
1282                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1283                                         /* mac_txd1 */
1284                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1285                                         /* mac_txd0 */
1286                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1287                                         /* mac_rxd3 */
1288                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1289                                         /* mac_rxd2 */
1290                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1291                                         /* mac_txd3 */
1292                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1293                                         /* mac_txd2 */
1294                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1295
1296                                         /* mac_txclk */
1297                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1298                                         /* mac_txen */
1299                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1300                                         /* mac_clk */
1301                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1302                                         /* mac_txd1 */
1303                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1304                                         /* mac_txd0 */
1305                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1306                                         /* mac_txd3 */
1307                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1308                                         /* mac_txd2 */
1309                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1310                         };
1311
1312                         rmiim1_pins: rmiim1-pins {
1313                                 rockchip,pins =
1314                                         /* mac_mdio */
1315                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1316                                         /* mac_txen */
1317                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1318                                         /* mac_clk */
1319                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1320                                         /* mac_rxer */
1321                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1322                                         /* mac_rxdv */
1323                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1324                                         /* mac_mdc */
1325                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1326                                         /* mac_rxd1 */
1327                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1328                                         /* mac_rxd0 */
1329                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1330                                         /* mac_txd1 */
1331                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1332                                         /* mac_txd0 */
1333                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1334
1335                                         /* mac_mdio */
1336                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1337                                         /* mac_txen */
1338                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1339                                         /* mac_clk */
1340                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1341                                         /* mac_mdc */
1342                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1343                                         /* mac_txd1 */
1344                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1345                                         /* mac_txd0 */
1346                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1347                         };
1348                 };
1349
1350                 gmac2phy {
1351                         fephyled_speed100: fephyled-speed100 {
1352                                 rockchip,pins =
1353                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1354                         };
1355
1356                         fephyled_speed10: fephyled-speed10 {
1357                                 rockchip,pins =
1358                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1359                         };
1360
1361                         fephyled_duplex: fephyled-duplex {
1362                                 rockchip,pins =
1363                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1364                         };
1365
1366                         fephyled_rxm0: fephyled-rxm0 {
1367                                 rockchip,pins =
1368                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370
1371                         fephyled_txm0: fephyled-txm0 {
1372                                 rockchip,pins =
1373                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1374                         };
1375
1376                         fephyled_linkm0: fephyled-linkm0 {
1377                                 rockchip,pins =
1378                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1379                         };
1380
1381                         fephyled_rxm1: fephyled-rxm1 {
1382                                 rockchip,pins =
1383                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1384                         };
1385
1386                         fephyled_txm1: fephyled-txm1 {
1387                                 rockchip,pins =
1388                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1389                         };
1390
1391                         fephyled_linkm1: fephyled-linkm1 {
1392                                 rockchip,pins =
1393                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1394                         };
1395                 };
1396
1397                 tsadc_pin {
1398                         tsadc_int: tsadc-int {
1399                                 rockchip,pins =
1400                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1401                         };
1402                         tsadc_gpio: tsadc-gpio {
1403                                 rockchip,pins =
1404                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1405                         };
1406                 };
1407
1408                 hdmi_pin {
1409                         hdmi_cec: hdmi-cec {
1410                                 rockchip,pins =
1411                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1412                         };
1413
1414                         hdmi_hpd: hdmi-hpd {
1415                                 rockchip,pins =
1416                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1417                         };
1418                 };
1419
1420                 cif-0 {
1421                         dvp_d2d9_m0:dvp-d2d9-m0 {
1422                                 rockchip,pins =
1423                                         /* cif_d0 */
1424                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1425                                         /* cif_d1 */
1426                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1427                                         /* cif_d2 */
1428                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1429                                         /* cif_d3 */
1430                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1431                                         /* cif_d4 */
1432                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1433                                         /* cif_d5m0 */
1434                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1435                                         /* cif_d6m0 */
1436                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1437                                         /* cif_d7m0 */
1438                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1439                                         /* cif_href */
1440                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1441                                         /* cif_vsync */
1442                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1443                                         /* cif_clkoutm0 */
1444                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1445                                         /* cif_clkin */
1446                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1447                         };
1448                 };
1449
1450                 cif-1 {
1451                         dvp_d2d9_m1:dvp-d2d9-m1 {
1452                                 rockchip,pins =
1453                                         /* cif_d0 */
1454                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1455                                         /* cif_d1 */
1456                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1457                                         /* cif_d2 */
1458                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1459                                         /* cif_d3 */
1460                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1461                                         /* cif_d4 */
1462                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1463                                         /* cif_d5m1 */
1464                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1465                                         /* cif_d6m1 */
1466                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1467                                         /* cif_d7m1 */
1468                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1469                                         /* cif_href */
1470                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1471                                         /* cif_vsync */
1472                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1473                                         /* cif_clkoutm1 */
1474                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1475                                         /* cif_clkin */
1476                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1477                         };
1478                 };
1479         };
1480 };