arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         psci {
 153                 compatible = "arm,psci-1.0";
 154                 method = "smc";
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         xin24m: xin24m {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency = <24000000>;
 169                 clock-output-names = "xin24m";
 170         };
 171
 172         i2s0: i2s@ff000000 {
 173                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 174                 reg = <0x0 0xff000000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 177                 clock-names = "i2s_clk", "i2s_hclk";
 178                 dmas = <&dmac 11>, <&dmac 12>;
 179                 #dma-cells = <2>;
 180                 dma-names = "tx", "rx";
 181                 status = "disabled";
 182         };
 183
 184         i2s1: i2s@ff010000 {
 185                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 186                 reg = <0x0 0xff010000 0x0 0x1000>;
 187                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 189                 clock-names = "i2s_clk", "i2s_hclk";
 190                 dmas = <&dmac 14>, <&dmac 15>;
 191                 #dma-cells = <2>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 #dma-cells = <2>;
 204                 dma-names = "tx", "rx";
 205                 pinctrl-names = "default", "sleep";
 206                 pinctrl-0 = <&i2s2m0_mclk
 207                              &i2s2m0_sclk
 208                              &i2s2m0_lrcktx
 209                              &i2s2m0_lrckrx
 210                              &i2s2m0_sdo
 211                              &i2s2m0_sdi>;
 212                 pinctrl-1 = <&i2s2m0_sleep>;
 213                 status = "disabled";
 214         };
 215
 216         spdif: spdif@ff030000 {
 217                 compatible = "rockchip,rk3328-spdif";
 218                 reg = <0x0 0xff030000 0x0 0x1000>;
 219                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 221                 clock-names = "mclk", "hclk";
 222                 dmas = <&dmac 10>;
 223                 #dma-cells = <1>;
 224                 dma-names = "tx";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&spdifm2_tx>;
 227                 status = "disabled";
 228         };
 229
 230         pdm: pdm@ff040000 {
 231                 compatible = "rockchip,pdm";
 232                 reg = <0x0 0xff040000 0x0 0x1000>;
 233                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 234                 clock-names = "pdm_clk", "pdm_hclk";
 235                 dmas = <&dmac 16>;
 236                 #dma-cells = <1>;
 237                 dma-names = "rx";
 238                 pinctrl-names = "default", "sleep";
 239                 pinctrl-0 = <&pdmm0_clk
 240                              &pdmm0_fsync
 241                              &pdmm0_sdi0
 242                              &pdmm0_sdi1
 243                              &pdmm0_sdi2
 244                              &pdmm0_sdi3>;
 245                 pinctrl-1 = <&pdmm0_sleep>;
 246                 status = "disabled";
 247         };
 248
 249         grf: syscon@ff100000 {
 250                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 251                 reg = <0x0 0xff100000 0x0 0x1000>;
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254
 255                 io_domains: io-domains {
 256                         compatible = "rockchip,rk3328-io-voltage-domain";
 257                         status = "disabled";
 258                 };
 259
 260                 power: power-controller {
 261                         compatible = "rockchip,rk3328-power-controller";
 262                         #power-domain-cells = <1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266
 267                         pd_hevc@RK3328_PD_HEVC {
 268                                 reg = <RK3328_PD_HEVC>;
 269                         };
 270                         pd_video@RK3328_PD_VIDEO {
 271                                 reg = <RK3328_PD_VIDEO>;
 272                         };
 273                         pd_vpu@RK3328_PD_VPU {
 274                                 reg = <RK3328_PD_VPU>;
 275                         };
 276                 };
 277
 278                 reboot-mode {
 279                         compatible = "syscon-reboot-mode";
 280                         offset = <0x5c8>;
 281                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 282                         mode-charge = <BOOT_CHARGING>;
 283                         mode-fastboot = <BOOT_FASTBOOT>;
 284                         mode-loader = <BOOT_BL_DOWNLOAD>;
 285                         mode-normal = <BOOT_NORMAL>;
 286                         mode-recovery = <BOOT_RECOVERY>;
 287                         mode-ums = <BOOT_UMS>;
 288                 };
 289         };
 290
 291         thermal-zones {
 292                 soc_thermal: soc-thermal {
 293                         polling-delay-passive = <20>; /* milliseconds */
 294                         polling-delay = <1000>; /* milliseconds */
 295                         sustainable-power = <1000>; /* milliwatts */
 296
 297                         thermal-sensors = <&tsadc 0>;
 298
 299                         trips {
 300                                 threshold: trip-point@0 {
 301                                         temperature = <70000>; /* millicelsius */
 302                                         hysteresis = <2000>; /* millicelsius */
 303                                         type = "passive";
 304                                 };
 305                                 target: trip-point@1 {
 306                                         temperature = <85000>; /* millicelsius */
 307                                         hysteresis = <2000>; /* millicelsius */
 308                                         type = "passive";
 309                                 };
 310                                 soc_crit: soc-crit {
 311                                         temperature = <95000>; /* millicelsius */
 312                                         hysteresis = <2000>; /* millicelsius */
 313                                         type = "critical";
 314                                 };
 315                         };
 316
 317                         cooling-maps {
 318                                 map0 {
 319                                         trip = <&target>;
 320                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 321                                         contribution = <4096>;
 322                                 };
 323                         };
 324                 };
 325
 326         };
 327
 328         tsadc: tsadc@ff250000 {
 329                 compatible = "rockchip,rk3328-tsadc";
 330                 reg = <0x0 0xff250000 0x0 0x100>;
 331                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 rockchip,grf = <&grf>;
 333                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 334                 clock-names = "tsadc", "apb_pclk";
 335                 assigned-clocks = <&cru SCLK_TSADC>;
 336                 assigned-clock-rates = <50000>;
 337                 resets = <&cru SRST_TSADC>;
 338                 reset-names = "tsadc-apb";
 339                 pinctrl-names = "init", "default", "sleep";
 340                 pinctrl-0 = <&otp_gpio>;
 341                 pinctrl-1 = <&otp_out>;
 342                 pinctrl-2 = <&otp_gpio>;
 343                 #thermal-sensor-cells = <1>;
 344                 rockchip,hw-tshut-temp = <100000>;
 345                 status = "disabled";
 346         };
 347
 348         uart0: serial@ff110000 {
 349                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 350                 reg = <0x0 0xff110000 0x0 0x100>;
 351                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 353                 clock-names = "baudclk", "apb_pclk";
 354                 reg-shift = <2>;
 355                 reg-io-width = <4>;
 356                 dmas = <&dmac 2>, <&dmac 3>;
 357                 #dma-cells = <2>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 360                 status = "disabled";
 361         };
 362
 363         uart1: serial@ff120000 {
 364                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 365                 reg = <0x0 0xff120000 0x0 0x100>;
 366                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 368                 clock-names = "sclk_uart", "pclk_uart";
 369                 reg-shift = <2>;
 370                 reg-io-width = <4>;
 371                 dmas = <&dmac 4>, <&dmac 5>;
 372                 #dma-cells = <2>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 375                 status = "disabled";
 376         };
 377
 378         uart2: serial@ff130000 {
 379                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 380                 reg = <0x0 0xff130000 0x0 0x100>;
 381                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 382                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 reg-shift = <2>;
 385                 reg-io-width = <4>;
 386                 dmas = <&dmac 6>, <&dmac 7>;
 387                 #dma-cells = <2>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&uart2m1_xfer>;
 390                 status = "disabled";
 391         };
 392
 393         pmu: power-management@ff140000 {
 394                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 395                 reg = <0x0 0xff140000 0x0 0x1000>;
 396         };
 397
 398         i2c0: i2c@ff150000 {
 399                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 400                 reg = <0x0 0xff150000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 405                 clock-names = "i2c", "pclk";
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c0_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c1: i2c@ff160000 {
 412                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 413                 reg = <0x0 0xff160000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 418                 clock-names = "i2c", "pclk";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c1_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c2: i2c@ff170000 {
 425                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 426                 reg = <0x0 0xff170000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 431                 clock-names = "i2c", "pclk";
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c2_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c3: i2c@ff180000 {
 438                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 439                 reg = <0x0 0xff180000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 444                 clock-names = "i2c", "pclk";
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c3_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         spi0: spi@ff190000 {
 451                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 452                 reg = <0x0 0xff190000 0x0 0x1000>;
 453                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 457                 clock-names = "spiclk", "apb_pclk";
 458                 dmas = <&dmac 8>, <&dmac 9>;
 459                 #dma-cells = <2>;
 460                 dma-names = "tx", "rx";
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 463                 status = "disabled";
 464         };
 465
 466         wdt: watchdog@ff1a0000 {
 467                 compatible = "snps,dw-wdt";
 468                 reg = <0x0 0xff1a0000 0x0 0x100>;
 469                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 470                 status = "disabled";
 471         };
 472
 473         pwm0: pwm@ff1b0000 {
 474                 compatible = "rockchip,rk3328-pwm";
 475                 reg = <0x0 0xff1b0000 0x0 0x10>;
 476                 #pwm-cells = <3>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&pwm0_pin>;
 479                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 480                 clock-names = "pwm", "pclk";
 481                 status = "disabled";
 482         };
 483
 484         pwm1: pwm@ff1b0010 {
 485                 compatible = "rockchip,rk3328-pwm";
 486                 reg = <0x0 0xff1b0010 0x0 0x10>;
 487                 #pwm-cells = <3>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&pwm1_pin>;
 490                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 491                 clock-names = "pwm", "pclk";
 492                 status = "disabled";
 493         };
 494
 495         pwm2: pwm@ff1b0020 {
 496                 compatible = "rockchip,rk3328-pwm";
 497                 reg = <0x0 0xff1b0020 0x0 0x10>;
 498                 #pwm-cells = <3>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&pwm2_pin>;
 501                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 502                 clock-names = "pwm", "pclk";
 503                 status = "disabled";
 504         };
 505
 506         pwm3: pwm@ff1b0030 {
 507                 compatible = "rockchip,rk3328-pwm";
 508                 reg = <0x0 0xff1b0030 0x0 0x10>;
 509                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 510                 #pwm-cells = <3>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&pwmir_pin>;
 513                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 514                 clock-names = "pwm", "pclk";
 515                 status = "disabled";
 516         };
 517
 518         amba {
 519                 compatible = "simple-bus";
 520                 #address-cells = <2>;
 521                 #size-cells = <2>;
 522                 ranges;
 523
 524                 dmac: dmac@ff1f0000 {
 525                         compatible = "arm,pl330", "arm,primecell";
 526                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 527                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&cru ACLK_DMAC>;
 530                         clock-names = "apb_pclk";
 531                         #dma-cells = <1>;
 532                 };
 533         };
 534
 535         efuse: efuse@ff260000 {
 536                 compatible = "rockchip,rk3328-efuse";
 537                 reg = <0x0 0xff260000 0x0 0x50>;
 538                 #address-cells = <1>;
 539                 #size-cells = <1>;
 540                 clocks = <&cru SCLK_EFUSE>;
 541                 clock-names = "pclk_efuse";
 542                 rockchip,efuse-size = <0x20>;
 543
 544                 /* Data cells */
 545                 efuse_id: id@7 {
 546                         reg = <0x07 0x10>;
 547                 };
 548                 cpu_leakage: cpu-leakage@17 {
 549                         reg = <0x17 0x1>;
 550                 };
 551                 logic_leakage: logic-leakage@19 {
 552                         reg = <0x19 0x1>;
 553                 };
 554         };
 555
 556         saradc: saradc@ff280000 {
 557                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 558                 reg = <0x0 0xff280000 0x0 0x100>;
 559                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 560                 #io-channel-cells = <1>;
 561                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 562                 clock-names = "saradc", "apb_pclk";
 563                 resets = <&cru SRST_SARADC_P>;
 564                 reset-names = "saradc-apb";
 565                 status = "disabled";
 566         };
 567
 568         gpu: gpu@ff300000 {
 569                 compatible = "arm,mali-450";
 570                 /* first item of 'reg' is dummy, to fit src code. */
 571                 reg = <0x0 0xff300000 0x0 0x40000>,
 572                       <0x0 0xff300000 0x0 0x40000>;
 573                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 574                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 575                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 576                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 577                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 578                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 579                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 580                 interrupt-names = "Mali_GP_IRQ",
 581                                   "Mali_GP_MMU_IRQ",
 582                                   "IRQPP",
 583                                   "Mali_PP0_IRQ",
 584                                   "Mali_PP0_MMU_IRQ",
 585                                   "Mali_PP1_IRQ",
 586                                   "Mali_PP1_MMU_IRQ";
 587                 clocks = <&cru ACLK_GPU>;
 588                 clock-names = "clk_mali";
 589                 operating-points-v2 = <&gpu_opp_table>;
 590                 status = "disabled";
 591         };
 592
 593         gpu_opp_table: opp-table2 {
 594                 compatible = "operating-points-v2";
 595
 596                 opp@200000000 {
 597                         opp-hz = /bits/ 64 <200000000>;
 598                         opp-microvolt = <1050000>;
 599                 };
 600                 opp@300000000 {
 601                         opp-hz = /bits/ 64 <300000000>;
 602                         opp-microvolt = <1050000>;
 603                 };
 604                 opp@400000000 {
 605                         opp-hz = /bits/ 64 <400000000>;
 606                         opp-microvolt = <1050000>;
 607                 };
 608                 opp@500000000 {
 609                         opp-hz = /bits/ 64 <500000000>;
 610                         opp-microvolt = <1100000>;
 611                 };
 612         };
 613
 614         vop: vop@ff370000 {
 615                 compatible = "rockchip,rk3328-vop";
 616                 reg = <0x0 0xff370000 0x0 0x3efc>;
 617                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 618                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 619                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 620                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 621                 reset-names = "axi", "ahb", "dclk";
 622                 iommus = <&vop_mmu>;
 623                 status = "disabled";
 624
 625                 vop_out: port {
 626                         #address-cells = <1>;
 627                         #size-cells = <0>;
 628                 };
 629         };
 630
 631         vop_mmu: iommu@ff373f00 {
 632                 compatible = "rockchip,iommu";
 633                 reg = <0x0 0xff373f00 0x0 0x100>;
 634                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 635                 interrupt-names = "vop_mmu";
 636                 #iommu-cells = <0>;
 637                 status = "disabled";
 638         };
 639
 640         display_subsystem: display-subsystem {
 641                 compatible = "rockchip,display-subsystem";
 642                 ports = <&vop_out>;
 643                 status = "disabled";
 644         };
 645
 646         cru: clock-controller@ff440000 {
 647                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 648                 reg = <0x0 0xff440000 0x0 0x1000>;
 649                 rockchip,grf = <&grf>;
 650                 #clock-cells = <1>;
 651                 #reset-cells = <1>;
 652                 assigned-clocks =
 653                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 654                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 655                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 656                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 657                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 658                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 659                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 660                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 661                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 662                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 663                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 664                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 665                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 666                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 667                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 668                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 669                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 670                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 671                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 672                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 673                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 674                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 675                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 676                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 677                 assigned-clock-parents =
 678                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 679                         <&cru PLL_GPLL>, <&xin24m>,
 680                         <&xin24m>, <&xin24m>;
 681                 assigned-clock-rates =
 682                         <0>, <61440000>,
 683                         <0>, <24000000>,
 684                         <24000000>, <24000000>,
 685                         <15000000>, <15000000>,
 686                         <100000000>, <100000000>,
 687                         <100000000>, <100000000>,
 688                         <50000000>, <100000000>,
 689                         <100000000>, <100000000>,
 690                         <50000000>, <50000000>,
 691                         <50000000>, <50000000>,
 692                         <24000000>, <600000000>,
 693                         <491520000>, <1200000000>,
 694                         <150000000>, <75000000>,
 695                         <75000000>, <150000000>,
 696                         <75000000>, <75000000>,
 697                         <300000000>, <100000000>,
 698                         <300000000>, <200000000>,
 699                         <400000000>, <500000000>,
 700                         <200000000>, <300000000>,
 701                         <300000000>, <250000000>,
 702                         <200000000>, <100000000>,
 703                         <24000000>, <100000000>,
 704                         <150000000>, <50000000>,
 705                         <32768>, <32768>;
 706         };
 707
 708         usb2phy_grf: syscon@ff450000 {
 709                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 710                              "simple-mfd";
 711                 reg = <0x0 0xff450000 0x0 0x10000>;
 712                 #address-cells = <1>;
 713                 #size-cells = <1>;
 714
 715                 u2phy: usb2-phy@100 {
 716                         compatible = "rockchip,rk3328-usb2phy";
 717                         reg = <0x100 0x10>;
 718                         clocks = <&xin24m>;
 719                         clock-names = "phyclk";
 720                         #clock-cells = <0>;
 721                         assigned-clocks = <&cru USB480M>;
 722                         assigned-clock-parents = <&u2phy>;
 723                         clock-output-names = "usb480m_phy";
 724                         status = "disabled";
 725
 726                         u2phy_host: host-port {
 727                                 #phy-cells = <0>;
 728                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 729                                 interrupt-names = "linestate";
 730                                 status = "disabled";
 731                         };
 732
 733                         u2phy_otg: otg-port {
 734                                 #phy-cells = <0>;
 735                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 736                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 737                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 738                                 interrupt-names = "otg-bvalid", "otg-id",
 739                                                   "linestate";
 740                                 status = "disabled";
 741                         };
 742                 };
 743         };
 744
 745         usb3phy_grf: syscon@ff460000 {
 746                 compatible = "rockchip,usb3phy-grf", "syscon";
 747                 reg = <0x0 0xff460000 0x0 0x1000>;
 748         };
 749
 750         u3phy: usb3-phy@ff470000 {
 751                 compatible = "rockchip,rk3328-u3phy";
 752                 reg = <0x0 0xff470000 0x0 0x0>;
 753                 rockchip,u3phygrf = <&usb3phy_grf>;
 754                 rockchip,grf = <&grf>;
 755                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 756                 interrupt-names = "linestate";
 757                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 758                 clock-names = "u3phy-otg", "u3phy-pipe";
 759                 resets = <&cru SRST_USB3PHY_U2>,
 760                          <&cru SRST_USB3PHY_U3>,
 761                          <&cru SRST_USB3PHY_PIPE>,
 762                          <&cru SRST_USB3OTG_UTMI>,
 763                          <&cru SRST_USB3PHY_OTG_P>,
 764                          <&cru SRST_USB3PHY_PIPE_P>;
 765                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 766                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 767                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 768                 #address-cells = <2>;
 769                 #size-cells = <2>;
 770                 ranges;
 771                 status = "disabled";
 772
 773                 u3phy_utmi: utmi@ff470000 {
 774                         reg = <0x0 0xff470000 0x0 0x8000>;
 775                         #phy-cells = <0>;
 776                         status = "disabled";
 777                 };
 778
 779                 u3phy_pipe: pipe@ff478000 {
 780                         reg = <0x0 0xff478000 0x0 0x8000>;
 781                         #phy-cells = <0>;
 782                         status = "disabled";
 783                 };
 784         };
 785
 786         sdmmc: rksdmmc@ff500000 {
 787                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 788                 reg = <0x0 0xff500000 0x0 0x4000>;
 789                 clock-freq-min-max = <400000 150000000>;
 790                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 791                 clock-names = "biu", "ciu";
 792                 fifo-depth = <0x100>;
 793                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 794                 status = "disabled";
 795         };
 796
 797         sdio: dwmmc@ff510000 {
 798                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 799                 reg = <0x0 0xff510000 0x0 0x4000>;
 800                 clock-freq-min-max = <400000 150000000>;
 801                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 802                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 803                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 804                 fifo-depth = <0x100>;
 805                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 806                 status = "disabled";
 807         };
 808
 809         emmc: rksdmmc@ff520000 {
 810                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 811                 reg = <0x0 0xff520000 0x0 0x4000>;
 812                 clock-freq-min-max = <400000 150000000>;
 813                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 814                 clock-names = "biu", "ciu";
 815                 fifo-depth = <0x100>;
 816                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 817                 status = "disabled";
 818         };
 819
 820         gmac2io: eth@ff540000 {
 821                 compatible = "rockchip,rk3328-gmac";
 822                 reg = <0x0 0xff540000 0x0 0x10000>;
 823                 rockchip,grf = <&grf>;
 824                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 825                 interrupt-names = "macirq";
 826                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 827                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 828                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 829                          <&cru PCLK_MAC2IO>;
 830                 clock-names = "stmmaceth", "mac_clk_rx",
 831                               "mac_clk_tx", "clk_mac_ref",
 832                               "clk_mac_refout", "aclk_mac",
 833                               "pclk_mac";
 834                 resets = <&cru SRST_GMAC2IO_A>;
 835                 reset-names = "stmmaceth";
 836                 status = "disabled";
 837         };
 838
 839         usb20_otg: usb@ff580000 {
 840                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 841                              "snps,dwc2";
 842                 reg = <0x0 0xff580000 0x0 0x40000>;
 843                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 844                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 845                 clock-names = "otg", "otg_pmu";
 846                 dr_mode = "otg";
 847                 g-np-tx-fifo-size = <16>;
 848                 g-rx-fifo-size = <275>;
 849                 g-tx-fifo-size = <256 128 128 64 64 32>;
 850                 g-use-dma;
 851                 phys = <&u2phy_otg>;
 852                 phy-names = "usb2-phy";
 853                 status = "disabled";
 854         };
 855
 856         usb_host0_ehci: usb@ff5c0000 {
 857                 compatible = "generic-ehci";
 858                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 859                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 860                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 861                          <&u2phy>;
 862                 clock-names = "usbhost", "arbiter", "utmi";
 863                 phys = <&u2phy_host>;
 864                 phy-names = "usb";
 865                 status = "disabled";
 866         };
 867
 868         usb_host0_ohci: usb@ff5d0000 {
 869                 compatible = "generic-ohci";
 870                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 871                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 872                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 873                          <&u2phy>;
 874                 clock-names = "usbhost", "arbiter", "utmi";
 875                 phys = <&u2phy_host>;
 876                 phy-names = "usb";
 877                 status = "disabled";
 878         };
 879
 880         sdmmc_ext: rksdmmc@ff5f0000 {
 881                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 882                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 883                 clock-freq-min-max = <400000 150000000>;
 884                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 885                 clock-names = "biu", "ciu";
 886                 fifo-depth = <0x100>;
 887                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 888                 status = "disabled";
 889         };
 890
 891         usbdrd3: usb@ff600000 {
 892                 compatible = "rockchip,rk3328-dwc3";
 893                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 894                          <&cru ACLK_USB3OTG>;
 895                 clock-names = "ref_clk", "suspend_clk",
 896                               "bus_clk";
 897                 #address-cells = <2>;
 898                 #size-cells = <2>;
 899                 ranges;
 900                 status = "disabled";
 901
 902                 usbdrd_dwc3: dwc3@ff600000 {
 903                         compatible = "snps,dwc3";
 904                         reg = <0x0 0xff600000 0x0 0x100000>;
 905                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 906                         dr_mode = "host";
 907                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 908                         phy-names = "usb2-phy", "usb3-phy";
 909                         phy_type = "utmi_wide";
 910                         snps,dis_enblslpm_quirk;
 911                         snps,dis-u2-freeclk-exists-quirk;
 912                         snps,dis_u2_susphy_quirk;
 913                         snps,dis-u3-autosuspend-quirk;
 914                         snps,dis_u3_susphy_quirk;
 915                         snps,dis-del-phy-power-chg-quirk;
 916                         status = "disabled";
 917                 };
 918         };
 919
 920         gic: interrupt-controller@ff811000 {
 921                 compatible = "arm,gic-400";
 922                 #interrupt-cells = <3>;
 923                 #address-cells = <0>;
 924                 interrupt-controller;
 925                 reg = <0x0 0xff811000 0 0x1000>,
 926                       <0x0 0xff812000 0 0x2000>,
 927                       <0x0 0xff814000 0 0x2000>,
 928                       <0x0 0xff816000 0 0x2000>;
 929                 interrupts = <GIC_PPI 9
 930                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 931         };
 932
 933         pinctrl: pinctrl {
 934                 compatible = "rockchip,rk3328-pinctrl";
 935                 rockchip,grf = <&grf>;
 936                 #address-cells = <2>;
 937                 #size-cells = <2>;
 938                 ranges;
 939
 940                 gpio0: gpio0@ff210000 {
 941                         compatible = "rockchip,gpio-bank";
 942                         reg = <0x0 0xff210000 0x0 0x100>;
 943                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 944                         clocks = <&cru PCLK_GPIO0>;
 945
 946                         gpio-controller;
 947                         #gpio-cells = <2>;
 948
 949                         interrupt-controller;
 950                         #interrupt-cells = <2>;
 951                 };
 952
 953                 gpio1: gpio1@ff220000 {
 954                         compatible = "rockchip,gpio-bank";
 955                         reg = <0x0 0xff220000 0x0 0x100>;
 956                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 957                         clocks = <&cru PCLK_GPIO1>;
 958
 959                         gpio-controller;
 960                         #gpio-cells = <2>;
 961
 962                         interrupt-controller;
 963                         #interrupt-cells = <2>;
 964                 };
 965
 966                 gpio2: gpio2@ff230000 {
 967                         compatible = "rockchip,gpio-bank";
 968                         reg = <0x0 0xff230000 0x0 0x100>;
 969                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 970                         clocks = <&cru PCLK_GPIO2>;
 971
 972                         gpio-controller;
 973                         #gpio-cells = <2>;
 974
 975                         interrupt-controller;
 976                         #interrupt-cells = <2>;
 977                 };
 978
 979                 gpio3: gpio3@ff240000 {
 980                         compatible = "rockchip,gpio-bank";
 981                         reg = <0x0 0xff240000 0x0 0x100>;
 982                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 983                         clocks = <&cru PCLK_GPIO3>;
 984
 985                         gpio-controller;
 986                         #gpio-cells = <2>;
 987
 988                         interrupt-controller;
 989                         #interrupt-cells = <2>;
 990                 };
 991
 992                 pcfg_pull_up: pcfg-pull-up {
 993                         bias-pull-up;
 994                 };
 995
 996                 pcfg_pull_down: pcfg-pull-down {
 997                         bias-pull-down;
 998                 };
 999
1000                 pcfg_pull_none: pcfg-pull-none {
1001                         bias-disable;
1002                 };
1003
1004                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1005                         bias-disable;
1006                         drive-strength = <2>;
1007                 };
1008
1009                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1010                         bias-pull-up;
1011                         drive-strength = <2>;
1012                 };
1013
1014                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1015                         bias-pull-up;
1016                         drive-strength = <4>;
1017                 };
1018
1019                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1020                         bias-disable;
1021                         drive-strength = <4>;
1022                 };
1023
1024                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1025                         bias-pull-down;
1026                         drive-strength = <4>;
1027                 };
1028
1029                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1030                         bias-disable;
1031                         drive-strength = <8>;
1032                 };
1033
1034                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1035                         bias-pull-up;
1036                         drive-strength = <8>;
1037                 };
1038
1039                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1040                         bias-disable;
1041                         drive-strength = <12>;
1042                 };
1043
1044                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1045                         bias-pull-up;
1046                         drive-strength = <12>;
1047                 };
1048
1049                 pcfg_output_high: pcfg-output-high {
1050                         output-high;
1051                 };
1052
1053                 pcfg_output_low: pcfg-output-low {
1054                         output-low;
1055                 };
1056
1057                 pcfg_input_high: pcfg-input-high {
1058                         bias-pull-up;
1059                         input-enable;
1060                 };
1061
1062                 pcfg_input: pcfg-input {
1063                         input-enable;
1064                 };
1065
1066                 i2c0 {
1067                         i2c0_xfer: i2c0-xfer {
1068                                 rockchip,pins =
1069                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1070                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072                 };
1073
1074                 i2c1 {
1075                         i2c1_xfer: i2c1-xfer {
1076                                 rockchip,pins =
1077                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1078                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 i2c2 {
1083                         i2c2_xfer: i2c2-xfer {
1084                                 rockchip,pins =
1085                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1086                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1087                         };
1088                 };
1089
1090                 i2c3 {
1091                         i2c3_xfer: i2c3-xfer {
1092                                 rockchip,pins =
1093                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1094                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1095                         };
1096                         i2c3_gpio: i2c3-gpio {
1097                                 rockchip,pins =
1098                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1099                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1100                         };
1101                 };
1102
1103                 hdmi_i2c {
1104                         hdmii2c_xfer: hdmii2c-xfer {
1105                                 rockchip,pins =
1106                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1107                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1108                         };
1109                 };
1110
1111                 tsadc {
1112                         otp_gpio: otp-gpio {
1113                                 rockchip,pins =
1114                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1115                         };
1116
1117                         otp_out: otp-out {
1118                                 rockchip,pins =
1119                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1120                         };
1121                 };
1122
1123                 uart0 {
1124                         uart0_xfer: uart0-xfer {
1125                                 rockchip,pins =
1126                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1127                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         uart0_cts: uart0-cts {
1131                                 rockchip,pins =
1132                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1133                         };
1134
1135                         uart0_rts: uart0-rts {
1136                                 rockchip,pins =
1137                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1138                         };
1139
1140                         uart0_rts_gpio: uart0-rts-gpio {
1141                                 rockchip,pins =
1142                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 uart1 {
1147                         uart1_xfer: uart1-xfer {
1148                                 rockchip,pins =
1149                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1150                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1151                         };
1152
1153                         uart1_cts: uart1-cts {
1154                                 rockchip,pins =
1155                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1156                         };
1157
1158                         uart1_rts: uart1-rts {
1159                                 rockchip,pins =
1160                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1161                         };
1162
1163                         uart1_rts_gpio: uart1-rts-gpio {
1164                                 rockchip,pins =
1165                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1166                         };
1167                 };
1168
1169                 uart2-0 {
1170                         uart2m0_xfer: uart2m0-xfer {
1171                                 rockchip,pins =
1172                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1173                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1174                         };
1175                 };
1176
1177                 uart2-1 {
1178                         uart2m1_xfer: uart2m1-xfer {
1179                                 rockchip,pins =
1180                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1181                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1182                         };
1183                 };
1184
1185                 spi0-0 {
1186                         spi0m0_clk: spi0m0-clk {
1187                                 rockchip,pins =
1188                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1189                         };
1190
1191                         spi0m0_cs0: spi0m0-cs0 {
1192                                 rockchip,pins =
1193                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1194                         };
1195
1196                         spi0m0_tx: spi0m0-tx {
1197                                 rockchip,pins =
1198                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1199                         };
1200
1201                         spi0m0_rx: spi0m0-rx {
1202                                 rockchip,pins =
1203                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1204                         };
1205
1206                         spi0m0_cs1: spi0m0-cs1 {
1207                                 rockchip,pins =
1208                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1209                         };
1210                 };
1211
1212                 spi0-1 {
1213                         spi0m1_clk: spi0m1-clk {
1214                                 rockchip,pins =
1215                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1216                         };
1217
1218                         spi0m1_cs0: spi0m1-cs0 {
1219                                 rockchip,pins =
1220                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1221                         };
1222
1223                         spi0m1_tx: spi0m1-tx {
1224                                 rockchip,pins =
1225                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1226                         };
1227
1228                         spi0m1_rx: spi0m1-rx {
1229                                 rockchip,pins =
1230                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1231                         };
1232
1233                         spi0m1_cs1: spi0m1-cs1 {
1234                                 rockchip,pins =
1235                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1236                         };
1237                 };
1238
1239                 spi0-2 {
1240                         spi0m2_clk: spi0m2-clk {
1241                                 rockchip,pins =
1242                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1243                         };
1244
1245                         spi0m2_cs0: spi0m2-cs0 {
1246                                 rockchip,pins =
1247                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1248                         };
1249
1250                         spi0m2_tx: spi0m2-tx {
1251                                 rockchip,pins =
1252                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1253                         };
1254
1255                         spi0m2_rx: spi0m2-rx {
1256                                 rockchip,pins =
1257                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1258                         };
1259                 };
1260
1261                 pdm-0 {
1262                         pdmm0_clk: pdmm0-clk {
1263                                 rockchip,pins =
1264                                         <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1265                         };
1266
1267                         pdmm0_fsync: pdmm0-fsync {
1268                                 rockchip,pins =
1269                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1270                         };
1271
1272                         pdmm0_sdi0: pdmm0-sdi0 {
1273                                 rockchip,pins =
1274                                         <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1275                         };
1276
1277                         pdmm0_sdi1: pdmm0-sdi1 {
1278                                 rockchip,pins =
1279                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1280                         };
1281
1282                         pdmm0_sdi2: pdmm0-sdi2 {
1283                                 rockchip,pins =
1284                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
1285                         };
1286
1287                         pdmm0_sdi3: pdmm0-sdi3 {
1288                                 rockchip,pins =
1289                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1290                         };
1291
1292                         pdmm0_sleep: pdmm0-sleep {
1293                                 rockchip,pins =
1294                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1295                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1296                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1297                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1298                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1299                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1300                         };
1301                 };
1302
1303                 i2s1 {
1304                         i2s1_mclk: i2s1-mclk {
1305                                 rockchip,pins =
1306                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1307                         };
1308
1309                         i2s1_sclk: i2s1-sclk {
1310                                 rockchip,pins =
1311                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1312                         };
1313
1314                         i2s1_lrckrx: i2s1-lrckrx {
1315                                 rockchip,pins =
1316                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1317                         };
1318
1319                         i2s1_lrcktx: i2s1-lrcktx {
1320                                 rockchip,pins =
1321                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323
1324                         i2s1_sdi: i2s1-sdi {
1325                                 rockchip,pins =
1326                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1327                         };
1328
1329                         i2s1_sdo: i2s1-sdo {
1330                                 rockchip,pins =
1331                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1332                         };
1333
1334                         i2s1_sdio1: i2s1-sdio1 {
1335                                 rockchip,pins =
1336                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338
1339                         i2s1_sdio2: i2s1-sdio2 {
1340                                 rockchip,pins =
1341                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1342                         };
1343
1344                         i2s1_sdio3: i2s1-sdio3 {
1345                                 rockchip,pins =
1346                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1347                         };
1348
1349                         i2s1_sleep: i2s1-sleep {
1350                                 rockchip,pins =
1351                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1352                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1353                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1354                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1355                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1356                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1357                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1358                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1359                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1360                         };
1361                 };
1362
1363                 i2s2-0 {
1364                         i2s2m0_mclk: i2s2m0-mclk {
1365                                 rockchip,pins =
1366                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1367                         };
1368
1369                         i2s2m0_sclk: i2s2m0-sclk {
1370                                 rockchip,pins =
1371                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1372                         };
1373
1374                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1375                                 rockchip,pins =
1376                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1377                         };
1378
1379                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1380                                 rockchip,pins =
1381                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1382                         };
1383
1384                         i2s2m0_sdi: i2s2m0-sdi {
1385                                 rockchip,pins =
1386                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1387                         };
1388
1389                         i2s2m0_sdo: i2s2m0-sdo {
1390                                 rockchip,pins =
1391                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1392                         };
1393
1394                         i2s2m0_sleep: i2s2m0-sleep {
1395                                 rockchip,pins =
1396                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1397                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1398                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1399                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1400                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1401                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1402                         };
1403                 };
1404
1405                 i2s2-1 {
1406                         i2s2m1_mclk: i2s2m1-mclk {
1407                                 rockchip,pins =
1408                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1409                         };
1410
1411                         i2s2m1_sclk: i2s2m1-sclk {
1412                                 rockchip,pins =
1413                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1414                         };
1415
1416                         i2s2m1_lrckrx: i2sm1-lrckrx {
1417                                 rockchip,pins =
1418                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1419                         };
1420
1421                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1422                                 rockchip,pins =
1423                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1424                         };
1425
1426                         i2s2m1_sdi: i2s2m1-sdi {
1427                                 rockchip,pins =
1428                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1429                         };
1430
1431                         i2s2m1_sdo: i2s2m1-sdo {
1432                                 rockchip,pins =
1433                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1434                         };
1435
1436                         i2s2m1_sleep: i2s2m1-sleep {
1437                                 rockchip,pins =
1438                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1439                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1440                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1441                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1442                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1443                         };
1444                 };
1445
1446                 spdif-0 {
1447                         spdifm0_tx: spdifm0-tx {
1448                                 rockchip,pins =
1449                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1450                         };
1451                 };
1452
1453                 spdif-1 {
1454                         spdifm1_tx: spdifm1-tx {
1455                                 rockchip,pins =
1456                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1457                         };
1458                 };
1459
1460                 spdif-2 {
1461                         spdifm2_tx: spdifm2-tx {
1462                                 rockchip,pins =
1463                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1464                         };
1465                 };
1466
1467                 sdmmc0-0 {
1468                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1469                                 rockchip,pins =
1470                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1471                         };
1472
1473                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1474                                 rockchip,pins =
1475                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1476                         };
1477                 };
1478
1479                 sdmmc0-1 {
1480                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1481                                 rockchip,pins =
1482                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1483                         };
1484
1485                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1486                                 rockchip,pins =
1487                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1488                         };
1489                 };
1490
1491                 sdmmc0 {
1492                         sdmmc0_clk: sdmmc0-clk {
1493                                 rockchip,pins =
1494                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1495                         };
1496
1497                         sdmmc0_cmd: sdmmc0-cmd {
1498                                 rockchip,pins =
1499                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1500                         };
1501
1502                         sdmmc0_dectn: sdmmc0-dectn {
1503                                 rockchip,pins =
1504                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1505                         };
1506
1507                         sdmmc0_wrprt: sdmmc0-wrprt {
1508                                 rockchip,pins =
1509                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1510                         };
1511
1512                         sdmmc0_bus1: sdmmc0-bus1 {
1513                                 rockchip,pins =
1514                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1515                         };
1516
1517                         sdmmc0_bus4: sdmmc0-bus4 {
1518                                 rockchip,pins =
1519                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1520                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1521                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1522                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1523                         };
1524
1525                         sdmmc0_gpio: sdmmc0-gpio {
1526                                 rockchip,pins =
1527                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1528                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1529                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1530                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1531                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1532                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1533                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1534                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1535                         };
1536                 };
1537
1538                 sdmmc0ext {
1539                         sdmmc0ext_clk: sdmmc0ext-clk {
1540                                 rockchip,pins =
1541                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1542                         };
1543
1544                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1545                                 rockchip,pins =
1546                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1547                         };
1548
1549                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1550                                 rockchip,pins =
1551                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1552                         };
1553
1554                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1555                                 rockchip,pins =
1556                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1557                         };
1558
1559                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1560                                 rockchip,pins =
1561                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1562                         };
1563
1564                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1565                                 rockchip,pins =
1566                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1567                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1568                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1569                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1570                         };
1571
1572                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1573                                 rockchip,pins =
1574                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1575                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1576                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1577                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1578                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1579                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1580                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1581                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1582                         };
1583                 };
1584
1585                 sdmmc1 {
1586                         sdmmc1_clk: sdmmc1-clk {
1587                                 rockchip,pins =
1588                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1589                         };
1590
1591                         sdmmc1_cmd: sdmmc1-cmd {
1592                                 rockchip,pins =
1593                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1594                         };
1595
1596                         sdmmc1_pwren: sdmmc1-pwren {
1597                                 rockchip,pins =
1598                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1599                         };
1600
1601                         sdmmc1_wrprt: sdmmc1-wrprt {
1602                                 rockchip,pins =
1603                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1604                         };
1605
1606                         sdmmc1_dectn: sdmmc1-dectn {
1607                                 rockchip,pins =
1608                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1609                         };
1610
1611                         sdmmc1_bus1: sdmmc1-bus1 {
1612                                 rockchip,pins =
1613                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1614                         };
1615
1616                         sdmmc1_bus4: sdmmc1-bus4 {
1617                                 rockchip,pins =
1618                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
1619                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
1620                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1621                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1622                         };
1623
1624                         sdmmc1_gpio: sdmmc1-gpio {
1625                                 rockchip,pins =
1626                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1627                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1628                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1629                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1630                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1631                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1632                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1633                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1634                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1635                         };
1636                 };
1637
1638                 emmc {
1639                         emmc_clk: emmc-clk {
1640                                 rockchip,pins =
1641                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1642                         };
1643
1644                         emmc_cmd: emmc-cmd {
1645                                 rockchip,pins =
1646                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1647                         };
1648
1649                         emmc_pwren: emmc-pwren {
1650                                 rockchip,pins =
1651                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1652                         };
1653
1654                         emmc_rstnout: emmc-rstnout {
1655                                 rockchip,pins =
1656                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1657                         };
1658
1659                         emmc_bus1: emmc-bus1 {
1660                                 rockchip,pins =
1661                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1662                         };
1663
1664                         emmc_bus4: emmc-bus4 {
1665                                 rockchip,pins =
1666                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1667                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1668                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1669                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1670                         };
1671
1672                         emmc_bus8: emmc-bus8 {
1673                                 rockchip,pins =
1674                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1675                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1676                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1677                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1678                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1679                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1680                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1681                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1682                         };
1683                 };
1684
1685                 pwm0 {
1686                         pwm0_pin: pwm0-pin {
1687                                 rockchip,pins =
1688                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1689                         };
1690                 };
1691
1692                 pwm1 {
1693                         pwm1_pin: pwm1-pin {
1694                                 rockchip,pins =
1695                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1696                         };
1697                 };
1698
1699                 pwm2 {
1700                         pwm2_pin: pwm2-pin {
1701                                 rockchip,pins =
1702                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1703                         };
1704                 };
1705
1706                 pwmir {
1707                         pwmir_pin: pwmir-pin {
1708                                 rockchip,pins =
1709                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711                 };
1712
1713                 gmac-1 {
1714                         rgmiim1_pins: rgmiim1-pins {
1715                                 rockchip,pins =
1716                                         /* mac_txclk */
1717                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1718                                         /* mac_rxclk */
1719                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1720                                         /* mac_mdio */
1721                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1722                                         /* mac_txen */
1723                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1724                                         /* mac_clk */
1725                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1726                                         /* mac_rxdv */
1727                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1728                                         /* mac_mdc */
1729                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1730                                         /* mac_rxd1 */
1731                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1732                                         /* mac_rxd0 */
1733                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1734                                         /* mac_txd1 */
1735                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1736                                         /* mac_txd0 */
1737                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1738                                         /* mac_rxd3 */
1739                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1740                                         /* mac_rxd2 */
1741                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1742                                         /* mac_txd3 */
1743                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1744                                         /* mac_txd2 */
1745                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1746
1747                                         /* mac_txclk */
1748                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1749                                         /* mac_txen */
1750                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1751                                         /* mac_clk */
1752                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1753                                         /* mac_txd1 */
1754                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1755                                         /* mac_txd0 */
1756                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1757                                         /* mac_txd3 */
1758                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1759                                         /* mac_txd2 */
1760                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1761                         };
1762
1763                         rmiim1_pins: rmiim1-pins {
1764                                 rockchip,pins =
1765                                         /* mac_mdio */
1766                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1767                                         /* mac_txen */
1768                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1769                                         /* mac_clk */
1770                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1771                                         /* mac_rxer */
1772                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1773                                         /* mac_rxdv */
1774                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1775                                         /* mac_mdc */
1776                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1777                                         /* mac_rxd1 */
1778                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1779                                         /* mac_rxd0 */
1780                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1781                                         /* mac_txd1 */
1782                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1783                                         /* mac_txd0 */
1784                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1785
1786                                         /* mac_mdio */
1787                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1788                                         /* mac_txen */
1789                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1790                                         /* mac_clk */
1791                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1792                                         /* mac_mdc */
1793                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1794                                         /* mac_txd1 */
1795                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1796                                         /* mac_txd0 */
1797                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1798                         };
1799                 };
1800
1801                 gmac2phy {
1802                         fephyled_speed100: fephyled-speed100 {
1803                                 rockchip,pins =
1804                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1805                         };
1806
1807                         fephyled_speed10: fephyled-speed10 {
1808                                 rockchip,pins =
1809                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1810                         };
1811
1812                         fephyled_duplex: fephyled-duplex {
1813                                 rockchip,pins =
1814                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1815                         };
1816
1817                         fephyled_rxm0: fephyled-rxm0 {
1818                                 rockchip,pins =
1819                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1820                         };
1821
1822                         fephyled_txm0: fephyled-txm0 {
1823                                 rockchip,pins =
1824                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1825                         };
1826
1827                         fephyled_linkm0: fephyled-linkm0 {
1828                                 rockchip,pins =
1829                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831
1832                         fephyled_rxm1: fephyled-rxm1 {
1833                                 rockchip,pins =
1834                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1835                         };
1836
1837                         fephyled_txm1: fephyled-txm1 {
1838                                 rockchip,pins =
1839                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1840                         };
1841
1842                         fephyled_linkm1: fephyled-linkm1 {
1843                                 rockchip,pins =
1844                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1845                         };
1846                 };
1847
1848                 tsadc_pin {
1849                         tsadc_int: tsadc-int {
1850                                 rockchip,pins =
1851                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1852                         };
1853                         tsadc_gpio: tsadc-gpio {
1854                                 rockchip,pins =
1855                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1856                         };
1857                 };
1858
1859                 hdmi_pin {
1860                         hdmi_cec: hdmi-cec {
1861                                 rockchip,pins =
1862                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1863                         };
1864
1865                         hdmi_hpd: hdmi-hpd {
1866                                 rockchip,pins =
1867                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1868                         };
1869                 };
1870
1871                 cif-0 {
1872                         dvp_d2d9_m0:dvp-d2d9-m0 {
1873                                 rockchip,pins =
1874                                         /* cif_d0 */
1875                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1876                                         /* cif_d1 */
1877                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1878                                         /* cif_d2 */
1879                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1880                                         /* cif_d3 */
1881                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1882                                         /* cif_d4 */
1883                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1884                                         /* cif_d5m0 */
1885                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1886                                         /* cif_d6m0 */
1887                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1888                                         /* cif_d7m0 */
1889                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1890                                         /* cif_href */
1891                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1892                                         /* cif_vsync */
1893                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1894                                         /* cif_clkoutm0 */
1895                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1896                                         /* cif_clkin */
1897                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1898                         };
1899                 };
1900
1901                 cif-1 {
1902                         dvp_d2d9_m1:dvp-d2d9-m1 {
1903                                 rockchip,pins =
1904                                         /* cif_d0 */
1905                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1906                                         /* cif_d1 */
1907                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1908                                         /* cif_d2 */
1909                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1910                                         /* cif_d3 */
1911                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1912                                         /* cif_d4 */
1913                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1914                                         /* cif_d5m1 */
1915                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1916                                         /* cif_d6m1 */
1917                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1918                                         /* cif_d7m1 */
1919                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1920                                         /* cif_href */
1921                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1922                                         /* cif_vsync */
1923                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1924                                         /* cif_clkoutm1 */
1925                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1926                                         /* cif_clkin */
1927                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1928                         };
1929                 };
1930         };
1931 };