2 * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/power/rk3328-power.h>
52 compatible = "rockchip,rk3328";
54 interrupt-parent = <&gic>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 // clocks = <&cru ARMCLK>;
78 operating-points-v2 = <&cpu0_opp_table>;
82 compatible = "arm,cortex-a53", "arm,armv8";
84 enable-method = "psci";
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
94 compatible = "arm,cortex-a53", "arm,armv8";
96 enable-method = "psci";
100 cpu0_opp_table: opp_table0 {
101 compatible = "operating-points-v2";
105 opp-hz = /bits/ 64 <408000000>;
106 opp-microvolt = <950000>;
107 clock-latency-ns = <40000>;
111 opp-hz = /bits/ 64 <600000000>;
112 opp-microvolt = <950000>;
113 clock-latency-ns = <40000>;
116 opp-hz = /bits/ 64 <816000000>;
117 opp-microvolt = <1000000>;
118 clock-latency-ns = <40000>;
121 opp-hz = /bits/ 64 <1008000000>;
122 opp-microvolt = <1100000>;
123 clock-latency-ns = <40000>;
126 opp-hz = /bits/ 64 <1200000000>;
127 opp-microvolt = <1225000>;
128 clock-latency-ns = <40000>;
131 opp-hz = /bits/ 64 <1296000000>;
132 opp-microvolt = <1300000>;
133 clock-latency-ns = <40000>;
138 compatible = "arm,cortex-a53-pmu";
139 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
143 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
147 compatible = "arm,psci-1.0";
152 compatible = "arm,armv8-timer";
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
160 compatible = "fixed-clock";
162 clock-frequency = <24000000>;
163 clock-output-names = "xin24m";
167 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
168 reg = <0x0 0xff000000 0x0 0x1000>;
169 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
170 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
171 clock-names = "i2s_clk", "i2s_hclk";
172 dmas = <&dmac 11>, <&dmac 12>;
174 dma-names = "tx", "rx";
179 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
180 reg = <0x0 0xff010000 0x0 0x1000>;
181 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
182 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
183 clock-names = "i2s_clk", "i2s_hclk";
184 dmas = <&dmac 14>, <&dmac 15>;
186 dma-names = "tx", "rx";
191 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
192 reg = <0x0 0xff020000 0x0 0x1000>;
193 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
195 clock-names = "i2s_clk", "i2s_hclk";
196 dmas = <&dmac 0>, <&dmac 1>;
198 dma-names = "tx", "rx";
199 pinctrl-names = "default", "sleep";
200 pinctrl-0 = <&i2s2m0_mclk
206 pinctrl-1 = <&i2s2m0_sleep>;
210 spdif: spdif@ff030000 {
211 compatible = "rockchip,rk3328-spdif";
212 reg = <0x0 0xff030000 0x0 0x1000>;
213 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
215 clock-names = "mclk", "hclk";
219 pinctrl-names = "default";
220 pinctrl-0 = <&spdifm2_tx>;
224 grf: syscon@ff100000 {
225 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
226 reg = <0x0 0xff100000 0x0 0x1000>;
227 #address-cells = <1>;
230 io_domains: io-domains {
231 compatible = "rockchip,rk3328-io-voltage-domain";
235 power: power-controller {
236 compatible = "rockchip,rk3328-power-controller";
237 #power-domain-cells = <1>;
238 #address-cells = <1>;
242 pd_hevc@RK3328_PD_HEVC {
243 reg = <RK3328_PD_HEVC>;
245 pd_video@RK3328_PD_VIDEO {
246 reg = <RK3328_PD_VIDEO>;
248 pd_vpu@RK3328_PD_VPU {
249 reg = <RK3328_PD_VPU>;
254 compatible = "syscon-reboot-mode";
256 mode-bootloader = <BOOT_BL_DOWNLOAD>;
257 mode-charge = <BOOT_CHARGING>;
258 mode-fastboot = <BOOT_FASTBOOT>;
259 mode-loader = <BOOT_BL_DOWNLOAD>;
260 mode-normal = <BOOT_NORMAL>;
261 mode-recovery = <BOOT_RECOVERY>;
262 mode-ums = <BOOT_UMS>;
266 uart0: serial@ff110000 {
267 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
268 reg = <0x0 0xff110000 0x0 0x100>;
269 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
271 clock-names = "baudclk", "apb_pclk";
274 dmas = <&dmac 2>, <&dmac 3>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
281 uart1: serial@ff120000 {
282 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
283 reg = <0x0 0xff120000 0x0 0x100>;
284 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
286 clock-names = "sclk_uart", "pclk_uart";
289 dmas = <&dmac 4>, <&dmac 5>;
291 pinctrl-names = "default";
292 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
296 uart2: serial@ff130000 {
297 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
298 reg = <0x0 0xff130000 0x0 0x100>;
299 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
301 clock-names = "baudclk", "apb_pclk";
304 dmas = <&dmac 6>, <&dmac 7>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&uart2m1_xfer>;
311 pmu: power-management@ff140000 {
312 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
313 reg = <0x0 0xff140000 0x0 0x1000>;
317 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
318 reg = <0x0 0xff150000 0x0 0x1000>;
319 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
322 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
323 clock-names = "i2c", "pclk";
324 pinctrl-names = "default";
325 pinctrl-0 = <&i2c0_xfer>;
330 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
331 reg = <0x0 0xff160000 0x0 0x1000>;
332 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
333 #address-cells = <1>;
335 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
336 clock-names = "i2c", "pclk";
337 pinctrl-names = "default";
338 pinctrl-0 = <&i2c1_xfer>;
343 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
344 reg = <0x0 0xff170000 0x0 0x1000>;
345 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
348 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
349 clock-names = "i2c", "pclk";
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c2_xfer>;
356 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
357 reg = <0x0 0xff180000 0x0 0x1000>;
358 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
361 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
362 clock-names = "i2c", "pclk";
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c3_xfer>;
369 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
370 reg = <0x0 0xff190000 0x0 0x1000>;
371 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
374 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
375 clock-names = "spiclk", "apb_pclk";
376 dmas = <&dmac 8>, <&dmac 9>;
378 dma-names = "tx", "rx";
379 pinctrl-names = "default";
380 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
384 wdt: watchdog@ff1a0000 {
385 compatible = "snps,dw-wdt";
386 reg = <0x0 0xff1a0000 0x0 0x100>;
387 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
392 compatible = "rockchip,rk3328-pwm";
393 reg = <0x0 0xff1b0000 0x0 0x10>;
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm0_pin>;
397 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
398 clock-names = "pwm", "pclk";
403 compatible = "rockchip,rk3328-pwm";
404 reg = <0x0 0xff1b0010 0x0 0x10>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&pwm1_pin>;
408 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
409 clock-names = "pwm", "pclk";
414 compatible = "rockchip,rk3328-pwm";
415 reg = <0x0 0xff1b0020 0x0 0x10>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pwm2_pin>;
419 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
420 clock-names = "pwm", "pclk";
425 compatible = "rockchip,rk3328-pwm";
426 reg = <0x0 0xff1b0030 0x0 0x10>;
427 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
429 pinctrl-names = "default";
430 pinctrl-0 = <&pwmir_pin>;
431 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
432 clock-names = "pwm", "pclk";
437 compatible = "simple-bus";
438 #address-cells = <2>;
442 dmac: dmac@ff1f0000 {
443 compatible = "arm,pl330", "arm,primecell";
444 reg = <0x0 0xff1f0000 0x0 0x4000>;
445 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&cru ACLK_DMAC>;
448 clock-names = "apb_pclk";
453 saradc: saradc@ff280000 {
454 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
455 reg = <0x0 0xff280000 0x0 0x100>;
456 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
457 #io-channel-cells = <1>;
458 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
459 clock-names = "saradc", "apb_pclk";
460 resets = <&cru SRST_SARADC_P>;
461 reset-names = "saradc-apb";
465 cru: clock-controller@ff440000 {
466 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
467 reg = <0x0 0xff440000 0x0 0x1000>;
468 rockchip,grf = <&grf>;
472 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
473 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
474 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
475 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
476 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
477 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
478 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
479 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
480 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
481 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
482 <&cru SCLK_WIFI>, <&cru ARMCLK>,
483 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
484 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
485 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
486 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
487 <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
488 <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
489 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
490 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
491 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
492 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
493 <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
494 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
495 <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
496 assigned-clock-parents =
497 <&cru HDMIPHY>, <&cru PLL_APLL>,
498 <&cru PLL_GPLL>, <&xin24m>,
499 <&xin24m>, <&xin24m>;
500 assigned-clock-rates =
503 <24000000>, <24000000>,
504 <15000000>, <15000000>,
505 <100000000>, <100000000>,
506 <100000000>, <100000000>,
507 <50000000>, <100000000>,
508 <100000000>, <100000000>,
509 <50000000>, <50000000>,
510 <50000000>, <50000000>,
511 <24000000>, <600000000>,
512 <491520000>, <1200000000>,
513 <150000000>, <75000000>,
514 <75000000>, <150000000>,
515 <75000000>, <75000000>,
516 <300000000>, <100000000>,
517 <300000000>, <200000000>,
518 <400000000>, <500000000>,
519 <200000000>, <300000000>,
520 <300000000>, <250000000>,
521 <200000000>, <100000000>,
522 <24000000>, <100000000>,
523 <150000000>, <50000000>,
527 usb2phy_grf: syscon@ff450000 {
528 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
530 reg = <0x0 0xff450000 0x0 0x10000>;
531 #address-cells = <1>;
534 u2phy: usb2-phy@100 {
535 compatible = "rockchip,rk3328-usb2phy";
538 clock-names = "phyclk";
540 assigned-clocks = <&cru USB480M>;
541 assigned-clock-parents = <&u2phy>;
542 clock-output-names = "usb480m_phy";
545 u2phy_host: host-port {
547 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "linestate";
552 u2phy_otg: otg-port {
554 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
557 interrupt-names = "otg-bvalid", "otg-id",
564 usb3phy_grf: syscon@ff460000 {
565 compatible = "rockchip,usb3phy-grf", "syscon";
566 reg = <0x0 0xff460000 0x0 0x1000>;
569 u3phy: usb3-phy@ff470000 {
570 compatible = "rockchip,rk3328-u3phy";
571 reg = <0x0 0xff470000 0x0 0x0>;
572 rockchip,u3phygrf = <&usb3phy_grf>;
573 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "linestate";
575 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
576 clock-names = "u3phy-otg", "u3phy-pipe";
577 resets = <&cru SRST_USB3PHY_U2>,
578 <&cru SRST_USB3PHY_U3>,
579 <&cru SRST_USB3PHY_PIPE>,
580 <&cru SRST_USB3OTG_UTMI>,
581 <&cru SRST_USB3PHY_OTG_P>,
582 <&cru SRST_USB3PHY_PIPE_P>;
583 reset-names = "u3phy-u2-por", "u3phy-u3-por",
584 "u3phy-pipe-mac", "u3phy-utmi-mac",
585 "u3phy-utmi-apb", "u3phy-pipe-apb";
586 #address-cells = <2>;
591 u3phy_utmi: utmi@ff470000 {
592 reg = <0x0 0xff470000 0x0 0x8000>;
597 u3phy_pipe: pipe@ff478000 {
598 reg = <0x0 0xff478000 0x0 0x8000>;
604 sdmmc: rksdmmc@ff500000 {
605 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
606 reg = <0x0 0xff500000 0x0 0x4000>;
607 clock-freq-min-max = <400000 150000000>;
608 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
609 clock-names = "biu", "ciu";
610 fifo-depth = <0x100>;
611 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
615 sdio: dwmmc@ff510000 {
616 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
617 reg = <0x0 0xff510000 0x0 0x4000>;
618 clock-freq-min-max = <400000 150000000>;
619 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
620 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
621 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
622 fifo-depth = <0x100>;
623 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
627 emmc: rksdmmc@ff520000 {
628 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
629 reg = <0x0 0xff520000 0x0 0x4000>;
630 clock-freq-min-max = <400000 150000000>;
631 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
632 clock-names = "biu", "ciu";
633 fifo-depth = <0x100>;
634 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
638 gmac2io: eth@ff540000 {
639 compatible = "rockchip,rk3328-gmac";
640 reg = <0x0 0xff540000 0x0 0x10000>;
641 rockchip,grf = <&grf>;
642 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
643 interrupt-names = "macirq";
644 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
645 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
646 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
648 clock-names = "stmmaceth", "mac_clk_rx",
649 "mac_clk_tx", "clk_mac_ref",
650 "clk_mac_refout", "aclk_mac",
652 resets = <&cru SRST_GMAC2IO_A>;
653 reset-names = "stmmaceth";
657 usb20_otg: usb@ff580000 {
658 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
660 reg = <0x0 0xff580000 0x0 0x40000>;
661 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
662 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
663 clock-names = "otg", "otg_pmu";
665 g-np-tx-fifo-size = <16>;
666 g-rx-fifo-size = <275>;
667 g-tx-fifo-size = <256 128 128 64 64 32>;
670 phy-names = "usb2-phy";
674 usb_host0_ehci: usb@ff5c0000 {
675 compatible = "generic-ehci";
676 reg = <0x0 0xff5c0000 0x0 0x10000>;
677 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
678 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
680 clock-names = "usbhost", "arbiter", "utmi";
681 phys = <&u2phy_host>;
686 usb_host0_ohci: usb@ff5d0000 {
687 compatible = "generic-ohci";
688 reg = <0x0 0xff5d0000 0x0 0x10000>;
689 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
692 clock-names = "usbhost", "arbiter", "utmi";
693 phys = <&u2phy_host>;
698 sdmmc_ext: rksdmmc@ff5f0000 {
699 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
700 reg = <0x0 0xff5f0000 0x0 0x4000>;
701 clock-freq-min-max = <400000 150000000>;
702 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
703 clock-names = "biu", "ciu";
704 fifo-depth = <0x100>;
705 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
709 usbdrd3: usb@ff600000 {
710 compatible = "rockchip,rk3328-dwc3";
711 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
713 clock-names = "ref_clk", "suspend_clk",
715 #address-cells = <2>;
720 usbdrd_dwc3: dwc3@ff600000 {
721 compatible = "snps,dwc3";
722 reg = <0x0 0xff600000 0x0 0x100000>;
723 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
725 phys = <&u3phy_utmi>, <&u3phy_pipe>;
726 phy-names = "usb2-phy", "usb3-phy";
727 phy_type = "utmi_wide";
728 snps,dis_enblslpm_quirk;
729 snps,dis-u2-freeclk-exists-quirk;
730 snps,dis_u2_susphy_quirk;
731 snps,dis-u3-autosuspend-quirk;
732 snps,dis_u3_susphy_quirk;
733 snps,dis-del-phy-power-chg-quirk;
738 gic: interrupt-controller@ff811000 {
739 compatible = "arm,gic-400";
740 #interrupt-cells = <3>;
741 #address-cells = <0>;
742 interrupt-controller;
743 reg = <0x0 0xff811000 0 0x1000>,
744 <0x0 0xff812000 0 0x2000>,
745 <0x0 0xff814000 0 0x2000>,
746 <0x0 0xff816000 0 0x2000>;
747 interrupts = <GIC_PPI 9
748 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
752 compatible = "rockchip,rk3328-pinctrl";
753 rockchip,grf = <&grf>;
754 #address-cells = <2>;
758 gpio0: gpio0@ff210000 {
759 compatible = "rockchip,gpio-bank";
760 reg = <0x0 0xff210000 0x0 0x100>;
761 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&cru PCLK_GPIO0>;
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 gpio1: gpio1@ff220000 {
772 compatible = "rockchip,gpio-bank";
773 reg = <0x0 0xff220000 0x0 0x100>;
774 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&cru PCLK_GPIO1>;
780 interrupt-controller;
781 #interrupt-cells = <2>;
784 gpio2: gpio2@ff230000 {
785 compatible = "rockchip,gpio-bank";
786 reg = <0x0 0xff230000 0x0 0x100>;
787 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru PCLK_GPIO2>;
793 interrupt-controller;
794 #interrupt-cells = <2>;
797 gpio3: gpio3@ff240000 {
798 compatible = "rockchip,gpio-bank";
799 reg = <0x0 0xff240000 0x0 0x100>;
800 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru PCLK_GPIO3>;
806 interrupt-controller;
807 #interrupt-cells = <2>;
810 pcfg_pull_up: pcfg-pull-up {
814 pcfg_pull_down: pcfg-pull-down {
818 pcfg_pull_none: pcfg-pull-none {
822 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
824 drive-strength = <2>;
827 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
829 drive-strength = <2>;
832 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
834 drive-strength = <4>;
837 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
839 drive-strength = <4>;
842 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
844 drive-strength = <4>;
847 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
849 drive-strength = <8>;
852 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
854 drive-strength = <8>;
857 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
859 drive-strength = <12>;
862 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
864 drive-strength = <12>;
867 pcfg_output_high: pcfg-output-high {
871 pcfg_output_low: pcfg-output-low {
875 pcfg_input_high: pcfg-input-high {
880 pcfg_input: pcfg-input {
885 i2c0_xfer: i2c0-xfer {
887 <2 24 RK_FUNC_1 &pcfg_pull_none>,
888 <2 25 RK_FUNC_1 &pcfg_pull_none>;
893 i2c1_xfer: i2c1-xfer {
895 <2 4 RK_FUNC_2 &pcfg_pull_none>,
896 <2 5 RK_FUNC_2 &pcfg_pull_none>;
901 i2c2_xfer: i2c2-xfer {
903 <2 13 RK_FUNC_1 &pcfg_pull_none>,
904 <2 14 RK_FUNC_1 &pcfg_pull_none>;
909 i2c3_xfer: i2c3-xfer {
911 <0 5 RK_FUNC_2 &pcfg_pull_none>,
912 <0 6 RK_FUNC_2 &pcfg_pull_none>;
914 i2c3_gpio: i2c3-gpio {
916 <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
917 <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
922 hdmii2c_xfer: hdmii2c-xfer {
924 <0 5 RK_FUNC_1 &pcfg_pull_none>,
925 <0 6 RK_FUNC_1 &pcfg_pull_none>;
930 uart0_xfer: uart0-xfer {
932 <1 9 RK_FUNC_1 &pcfg_pull_up>,
933 <1 8 RK_FUNC_1 &pcfg_pull_none>;
936 uart0_cts: uart0-cts {
938 <1 11 RK_FUNC_1 &pcfg_pull_none>;
941 uart0_rts: uart0-rts {
943 <1 10 RK_FUNC_1 &pcfg_pull_none>;
946 uart0_rts_gpio: uart0-rts-gpio {
948 <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
953 uart1_xfer: uart1-xfer {
955 <3 4 RK_FUNC_4 &pcfg_pull_up>,
956 <3 6 RK_FUNC_4 &pcfg_pull_none>;
959 uart1_cts: uart1-cts {
961 <3 7 RK_FUNC_4 &pcfg_pull_none>;
964 uart1_rts: uart1-rts {
966 <3 5 RK_FUNC_4 &pcfg_pull_none>;
969 uart1_rts_gpio: uart1-rts-gpio {
971 <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
976 uart2m0_xfer: uart2m0-xfer {
978 <1 0 RK_FUNC_2 &pcfg_pull_up>,
979 <1 1 RK_FUNC_2 &pcfg_pull_none>;
984 uart2m1_xfer: uart2m1-xfer {
986 <2 0 RK_FUNC_1 &pcfg_pull_up>,
987 <2 1 RK_FUNC_1 &pcfg_pull_none>;
992 spi0m0_clk: spi0m0-clk {
994 <2 8 RK_FUNC_1 &pcfg_pull_up>;
997 spi0m0_cs0: spi0m0-cs0 {
999 <2 11 RK_FUNC_1 &pcfg_pull_up>;
1002 spi0m0_tx: spi0m0-tx {
1004 <2 9 RK_FUNC_1 &pcfg_pull_up>;
1007 spi0m0_rx: spi0m0-rx {
1009 <2 10 RK_FUNC_1 &pcfg_pull_up>;
1012 spi0m0_cs1: spi0m0-cs1 {
1014 <2 12 RK_FUNC_1 &pcfg_pull_up>;
1019 spi0m1_clk: spi0m1-clk {
1021 <3 23 RK_FUNC_2 &pcfg_pull_up>;
1024 spi0m1_cs0: spi0m1-cs0 {
1026 <3 26 RK_FUNC_2 &pcfg_pull_up>;
1029 spi0m1_tx: spi0m1-tx {
1031 <3 25 RK_FUNC_2 &pcfg_pull_up>;
1034 spi0m1_rx: spi0m1-rx {
1036 <3 24 RK_FUNC_2 &pcfg_pull_up>;
1039 spi0m1_cs1: spi0m1-cs1 {
1041 <3 27 RK_FUNC_2 &pcfg_pull_up>;
1046 spi0m2_clk: spi0m2-clk {
1048 <3 0 RK_FUNC_4 &pcfg_pull_up>;
1051 spi0m2_cs0: spi0m2-cs0 {
1053 <3 8 RK_FUNC_3 &pcfg_pull_up>;
1056 spi0m2_tx: spi0m2-tx {
1058 <3 1 RK_FUNC_4 &pcfg_pull_up>;
1061 spi0m2_rx: spi0m2-rx {
1063 <3 2 RK_FUNC_4 &pcfg_pull_up>;
1068 i2s1_mclk: i2s1-mclk {
1070 <2 15 RK_FUNC_1 &pcfg_pull_none>;
1073 i2s1_sclk: i2s1-sclk {
1075 <2 18 RK_FUNC_1 &pcfg_pull_none>;
1078 i2s1_lrckrx: i2s1-lrckrx {
1080 <2 16 RK_FUNC_1 &pcfg_pull_none>;
1083 i2s1_lrcktx: i2s1-lrcktx {
1085 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1088 i2s1_sdi: i2s1-sdi {
1090 <2 19 RK_FUNC_1 &pcfg_pull_none>;
1093 i2s1_sdo: i2s1-sdo {
1095 <2 23 RK_FUNC_1 &pcfg_pull_none>;
1098 i2s1_sdio1: i2s1-sdio1 {
1100 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1103 i2s1_sdio2: i2s1-sdio2 {
1105 <2 21 RK_FUNC_1 &pcfg_pull_none>;
1108 i2s1_sdio3: i2s1-sdio3 {
1110 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1113 i2s1_sleep: i2s1-sleep {
1115 <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1116 <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1117 <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1118 <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1119 <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1120 <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1121 <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1122 <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1123 <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1128 i2s2m0_mclk: i2s2m0-mclk {
1130 <1 21 RK_FUNC_1 &pcfg_pull_none>;
1133 i2s2m0_sclk: i2s2m0-sclk {
1135 <1 22 RK_FUNC_1 &pcfg_pull_none>;
1138 i2s2m0_lrckrx: i2s2m0-lrckrx {
1140 <1 26 RK_FUNC_1 &pcfg_pull_none>;
1143 i2s2m0_lrcktx: i2s2m0-lrcktx {
1145 <1 23 RK_FUNC_1 &pcfg_pull_none>;
1148 i2s2m0_sdi: i2s2m0-sdi {
1150 <1 24 RK_FUNC_1 &pcfg_pull_none>;
1153 i2s2m0_sdo: i2s2m0-sdo {
1155 <1 25 RK_FUNC_1 &pcfg_pull_none>;
1158 i2s2m0_sleep: i2s2m0-sleep {
1160 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1161 <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1162 <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1163 <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1164 <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1165 <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1170 i2s2m1_mclk: i2s2m1-mclk {
1172 <1 21 RK_FUNC_1 &pcfg_pull_none>;
1175 i2s2m1_sclk: i2s2m1-sclk {
1177 <3 0 RK_FUNC_6 &pcfg_pull_none>;
1180 i2s2m1_lrckrx: i2sm1-lrckrx {
1182 <3 8 RK_FUNC_6 &pcfg_pull_none>;
1185 i2s2m1_lrcktx: i2s2m1-lrcktx {
1187 <3 8 RK_FUNC_4 &pcfg_pull_none>;
1190 i2s2m1_sdi: i2s2m1-sdi {
1192 <3 2 RK_FUNC_6 &pcfg_pull_none>;
1195 i2s2m1_sdo: i2s2m1-sdo {
1197 <3 1 RK_FUNC_6 &pcfg_pull_none>;
1200 i2s2m1_sleep: i2s2m1-sleep {
1202 <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1203 <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1204 <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1205 <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1206 <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1211 spdifm0_tx: spdifm0-tx {
1213 <0 27 RK_FUNC_1 &pcfg_pull_none>;
1218 spdifm1_tx: spdifm1-tx {
1220 <2 17 RK_FUNC_2 &pcfg_pull_none>;
1225 spdifm2_tx: spdifm2-tx {
1227 <0 2 RK_FUNC_2 &pcfg_pull_none>;
1232 sdmmc0m0_pwren: sdmmc0m0-pwren {
1234 <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1237 sdmmc0m0_gpio: sdmmc0m0-gpio {
1239 <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1244 sdmmc0m1_pwren: sdmmc0m1-pwren {
1246 <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1249 sdmmc0m1_gpio: sdmmc0m1-gpio {
1251 <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1256 sdmmc0_clk: sdmmc0-clk {
1258 <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1261 sdmmc0_cmd: sdmmc0-cmd {
1263 <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1266 sdmmc0_dectn: sdmmc0-dectn {
1268 <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1271 sdmmc0_wrprt: sdmmc0-wrprt {
1273 <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1276 sdmmc0_bus1: sdmmc0-bus1 {
1278 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1281 sdmmc0_bus4: sdmmc0-bus4 {
1283 <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1284 <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1285 <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1286 <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1289 sdmmc0_gpio: sdmmc0-gpio {
1291 <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1292 <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1293 <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1294 <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1295 <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1296 <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1297 <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1298 <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1303 sdmmc0ext_clk: sdmmc0ext-clk {
1305 <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1308 sdmmc0ext_cmd: sdmmc0ext-cmd {
1310 <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1313 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1315 <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1318 sdmmc0ext_dectn: sdmmc0ext-dectn {
1320 <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1323 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1325 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1328 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1330 <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1331 <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1332 <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1333 <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1336 sdmmc0ext_gpio: sdmmc0ext-gpio {
1338 <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1339 <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1340 <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1341 <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1342 <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1343 <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1344 <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1345 <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1350 sdmmc1_clk: sdmmc1-clk {
1352 <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1355 sdmmc1_cmd: sdmmc1-cmd {
1357 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1360 sdmmc1_pwren: sdmmc1-pwren {
1362 <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1365 sdmmc1_wrprt: sdmmc1-wrprt {
1367 <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1370 sdmmc1_dectn: sdmmc1-dectn {
1372 <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1375 sdmmc1_bus1: sdmmc1-bus1 {
1377 <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1380 sdmmc1_bus4: sdmmc1-bus4 {
1382 <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1383 <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1384 <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1385 <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1388 sdmmc1_gpio: sdmmc1-gpio {
1390 <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1391 <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1392 <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1393 <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1394 <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1395 <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1396 <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1397 <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1398 <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1403 emmc_clk: emmc-clk {
1405 <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1408 emmc_cmd: emmc-cmd {
1410 <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1413 emmc_pwren: emmc-pwren {
1415 <3 22 RK_FUNC_2 &pcfg_pull_none>;
1418 emmc_rstnout: emmc-rstnout {
1420 <3 20 RK_FUNC_2 &pcfg_pull_none>;
1423 emmc_bus1: emmc-bus1 {
1425 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1428 emmc_bus4: emmc-bus4 {
1430 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1431 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1432 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1433 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1436 emmc_bus8: emmc-bus8 {
1438 <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1439 <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1440 <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1441 <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1442 <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1443 <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1444 <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1445 <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1450 pwm0_pin: pwm0-pin {
1452 <2 4 RK_FUNC_1 &pcfg_pull_none>;
1457 pwm1_pin: pwm1-pin {
1459 <2 5 RK_FUNC_1 &pcfg_pull_none>;
1464 pwm2_pin: pwm2-pin {
1466 <2 6 RK_FUNC_1 &pcfg_pull_none>;
1471 pwmir_pin: pwmir-pin {
1473 <2 2 RK_FUNC_1 &pcfg_pull_none>;
1478 rgmiim0_pins: rgmiim0-pins {
1481 <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1483 <0 10 RK_FUNC_1 &pcfg_pull_none>,
1485 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1487 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1489 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1491 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1493 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1495 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1497 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1499 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1501 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1503 <0 20 RK_FUNC_1 &pcfg_pull_none>,
1505 <0 21 RK_FUNC_1 &pcfg_pull_none>,
1507 <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1509 <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1512 rmiim0_pins: rmiim0-pins {
1515 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1517 <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1519 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1521 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1523 <0 25 RK_FUNC_1 &pcfg_pull_none>,
1525 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1527 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1529 <0 15 RK_FUNC_1 &pcfg_pull_none>,
1531 <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1533 <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1538 rgmiim1_pins: rgmiim1-pins {
1541 <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1543 <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1545 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1547 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1549 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1551 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1553 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1555 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1557 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1559 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1561 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1563 <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1565 <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1567 <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1569 <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1572 <0 8 RK_FUNC_1 &pcfg_pull_none>,
1574 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1576 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1578 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1580 <0 17 RK_FUNC_1 &pcfg_pull_none>,
1582 <0 23 RK_FUNC_1 &pcfg_pull_none>,
1584 <0 22 RK_FUNC_1 &pcfg_pull_none>;
1587 rmiim1_pins: rmiim1-pins {
1590 <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1592 <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1594 <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1596 <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1598 <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1600 <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1602 <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1604 <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1606 <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1608 <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1611 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1613 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1615 <0 24 RK_FUNC_1 &pcfg_pull_none>,
1617 <0 19 RK_FUNC_1 &pcfg_pull_none>,
1619 <0 16 RK_FUNC_1 &pcfg_pull_none>,
1621 <0 17 RK_FUNC_1 &pcfg_pull_none>;
1626 fephyled_speed100: fephyled-speed100 {
1628 <0 31 RK_FUNC_1 &pcfg_pull_none>;
1631 fephyled_speed10: fephyled-speed10 {
1633 <0 30 RK_FUNC_1 &pcfg_pull_none>;
1636 fephyled_duplex: fephyled-duplex {
1638 <0 30 RK_FUNC_2 &pcfg_pull_none>;
1641 fephyled_rxm0: fephyled-rxm0 {
1643 <0 29 RK_FUNC_1 &pcfg_pull_none>;
1646 fephyled_txm0: fephyled-txm0 {
1648 <0 29 RK_FUNC_2 &pcfg_pull_none>;
1651 fephyled_linkm0: fephyled-linkm0 {
1653 <0 28 RK_FUNC_1 &pcfg_pull_none>;
1656 fephyled_rxm1: fephyled-rxm1 {
1658 <2 25 RK_FUNC_2 &pcfg_pull_none>;
1661 fephyled_txm1: fephyled-txm1 {
1663 <2 25 RK_FUNC_3 &pcfg_pull_none>;
1666 fephyled_linkm1: fephyled-linkm1 {
1668 <2 24 RK_FUNC_2 &pcfg_pull_none>;
1673 tsadc_int: tsadc-int {
1675 <2 13 RK_FUNC_2 &pcfg_pull_none>;
1677 tsadc_gpio: tsadc-gpio {
1679 <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1684 hdmi_cec: hdmi-cec {
1686 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1689 hdmi_hpd: hdmi-hpd {
1691 <0 4 RK_FUNC_1 &pcfg_pull_down>;
1696 dvp_d2d9_m0:dvp-d2d9-m0 {
1699 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1701 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1703 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1705 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1707 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1709 <3 9 RK_FUNC_2 &pcfg_pull_none>,
1711 <3 10 RK_FUNC_2 &pcfg_pull_none>,
1713 <3 11 RK_FUNC_2 &pcfg_pull_none>,
1715 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1717 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1719 <3 3 RK_FUNC_2 &pcfg_pull_none>,
1721 <3 2 RK_FUNC_2 &pcfg_pull_none>;
1726 dvp_d2d9_m1:dvp-d2d9-m1 {
1729 <3 4 RK_FUNC_2 &pcfg_pull_none>,
1731 <3 5 RK_FUNC_2 &pcfg_pull_none>,
1733 <3 6 RK_FUNC_2 &pcfg_pull_none>,
1735 <3 7 RK_FUNC_2 &pcfg_pull_none>,
1737 <3 8 RK_FUNC_2 &pcfg_pull_none>,
1739 <2 16 RK_FUNC_4 &pcfg_pull_none>,
1741 <2 17 RK_FUNC_4 &pcfg_pull_none>,
1743 <2 18 RK_FUNC_4 &pcfg_pull_none>,
1745 <3 1 RK_FUNC_2 &pcfg_pull_none>,
1747 <3 0 RK_FUNC_2 &pcfg_pull_none>,
1749 <2 15 RK_FUNC_4 &pcfg_pull_none>,
1751 <3 2 RK_FUNC_2 &pcfg_pull_none>;