arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         psci {
 153                 compatible = "arm,psci-1.0";
 154                 method = "smc";
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         xin24m: xin24m {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency = <24000000>;
 169                 clock-output-names = "xin24m";
 170         };
 171
 172         i2s0: i2s@ff000000 {
 173                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 174                 reg = <0x0 0xff000000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 177                 clock-names = "i2s_clk", "i2s_hclk";
 178                 dmas = <&dmac 11>, <&dmac 12>;
 179                 #dma-cells = <2>;
 180                 dma-names = "tx", "rx";
 181                 status = "disabled";
 182         };
 183
 184         i2s1: i2s@ff010000 {
 185                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 186                 reg = <0x0 0xff010000 0x0 0x1000>;
 187                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 189                 clock-names = "i2s_clk", "i2s_hclk";
 190                 dmas = <&dmac 14>, <&dmac 15>;
 191                 #dma-cells = <2>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 #dma-cells = <2>;
 204                 dma-names = "tx", "rx";
 205                 pinctrl-names = "default", "sleep";
 206                 pinctrl-0 = <&i2s2m0_mclk
 207                              &i2s2m0_sclk
 208                              &i2s2m0_lrcktx
 209                              &i2s2m0_lrckrx
 210                              &i2s2m0_sdo
 211                              &i2s2m0_sdi>;
 212                 pinctrl-1 = <&i2s2m0_sleep>;
 213                 status = "disabled";
 214         };
 215
 216         spdif: spdif@ff030000 {
 217                 compatible = "rockchip,rk3328-spdif";
 218                 reg = <0x0 0xff030000 0x0 0x1000>;
 219                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 221                 clock-names = "mclk", "hclk";
 222                 dmas = <&dmac 10>;
 223                 #dma-cells = <1>;
 224                 dma-names = "tx";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&spdifm2_tx>;
 227                 status = "disabled";
 228         };
 229
 230         pdm: pdm@ff040000 {
 231                 compatible = "rockchip,pdm";
 232                 reg = <0x0 0xff040000 0x0 0x1000>;
 233                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
 234                 clock-names = "pdm_clk", "pdm_hclk";
 235                 dmas = <&dmac 16>;
 236                 #dma-cells = <1>;
 237                 dma-names = "rx";
 238                 pinctrl-names = "default", "sleep";
 239                 pinctrl-0 = <&pdmm0_clk
 240                              &pdmm0_fsync
 241                              &pdmm0_sdi0
 242                              &pdmm0_sdi1
 243                              &pdmm0_sdi2
 244                              &pdmm0_sdi3>;
 245                 pinctrl-1 = <&pdmm0_sleep>;
 246                 status = "disabled";
 247         };
 248
 249         grf: syscon@ff100000 {
 250                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 251                 reg = <0x0 0xff100000 0x0 0x1000>;
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254
 255                 io_domains: io-domains {
 256                         compatible = "rockchip,rk3328-io-voltage-domain";
 257                         status = "disabled";
 258                 };
 259
 260                 power: power-controller {
 261                         compatible = "rockchip,rk3328-power-controller";
 262                         #power-domain-cells = <1>;
 263                         #address-cells = <1>;
 264                         #size-cells = <0>;
 265                         status = "disabled";
 266
 267                         pd_hevc@RK3328_PD_HEVC {
 268                                 reg = <RK3328_PD_HEVC>;
 269                         };
 270                         pd_video@RK3328_PD_VIDEO {
 271                                 reg = <RK3328_PD_VIDEO>;
 272                         };
 273                         pd_vpu@RK3328_PD_VPU {
 274                                 reg = <RK3328_PD_VPU>;
 275                         };
 276                 };
 277
 278                 reboot-mode {
 279                         compatible = "syscon-reboot-mode";
 280                         offset = <0x5c8>;
 281                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 282                         mode-charge = <BOOT_CHARGING>;
 283                         mode-fastboot = <BOOT_FASTBOOT>;
 284                         mode-loader = <BOOT_BL_DOWNLOAD>;
 285                         mode-normal = <BOOT_NORMAL>;
 286                         mode-recovery = <BOOT_RECOVERY>;
 287                         mode-ums = <BOOT_UMS>;
 288                 };
 289         };
 290
 291         thermal-zones {
 292                 soc_thermal: soc-thermal {
 293                         polling-delay-passive = <20>; /* milliseconds */
 294                         polling-delay = <1000>; /* milliseconds */
 295                         sustainable-power = <1000>; /* milliwatts */
 296
 297                         thermal-sensors = <&tsadc 0>;
 298
 299                         trips {
 300                                 threshold: trip-point@0 {
 301                                         temperature = <70000>; /* millicelsius */
 302                                         hysteresis = <2000>; /* millicelsius */
 303                                         type = "passive";
 304                                 };
 305                                 target: trip-point@1 {
 306                                         temperature = <85000>; /* millicelsius */
 307                                         hysteresis = <2000>; /* millicelsius */
 308                                         type = "passive";
 309                                 };
 310                                 soc_crit: soc-crit {
 311                                         temperature = <95000>; /* millicelsius */
 312                                         hysteresis = <2000>; /* millicelsius */
 313                                         type = "critical";
 314                                 };
 315                         };
 316
 317                         cooling-maps {
 318                                 map0 {
 319                                         trip = <&target>;
 320                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 321                                         contribution = <4096>;
 322                                 };
 323                         };
 324                 };
 325
 326         };
 327
 328         tsadc: tsadc@ff250000 {
 329                 compatible = "rockchip,rk3328-tsadc";
 330                 reg = <0x0 0xff250000 0x0 0x100>;
 331                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 332                 rockchip,grf = <&grf>;
 333                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 334                 clock-names = "tsadc", "apb_pclk";
 335                 assigned-clocks = <&cru SCLK_TSADC>;
 336                 assigned-clock-rates = <50000>;
 337                 resets = <&cru SRST_TSADC>;
 338                 reset-names = "tsadc-apb";
 339                 pinctrl-names = "init", "default", "sleep";
 340                 pinctrl-0 = <&otp_gpio>;
 341                 pinctrl-1 = <&otp_out>;
 342                 pinctrl-2 = <&otp_gpio>;
 343                 #thermal-sensor-cells = <1>;
 344                 rockchip,hw-tshut-temp = <100000>;
 345                 status = "disabled";
 346         };
 347
 348         uart0: serial@ff110000 {
 349                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 350                 reg = <0x0 0xff110000 0x0 0x100>;
 351                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 352                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 353                 clock-names = "baudclk", "apb_pclk";
 354                 reg-shift = <2>;
 355                 reg-io-width = <4>;
 356                 dmas = <&dmac 2>, <&dmac 3>;
 357                 #dma-cells = <2>;
 358                 pinctrl-names = "default";
 359                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 360                 status = "disabled";
 361         };
 362
 363         uart1: serial@ff120000 {
 364                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 365                 reg = <0x0 0xff120000 0x0 0x100>;
 366                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 367                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 368                 clock-names = "sclk_uart", "pclk_uart";
 369                 reg-shift = <2>;
 370                 reg-io-width = <4>;
 371                 dmas = <&dmac 4>, <&dmac 5>;
 372                 #dma-cells = <2>;
 373                 pinctrl-names = "default";
 374                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 375                 status = "disabled";
 376         };
 377
 378         uart2: serial@ff130000 {
 379                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 380                 reg = <0x0 0xff130000 0x0 0x100>;
 381                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 382                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 383                 clock-names = "baudclk", "apb_pclk";
 384                 reg-shift = <2>;
 385                 reg-io-width = <4>;
 386                 dmas = <&dmac 6>, <&dmac 7>;
 387                 #dma-cells = <2>;
 388                 pinctrl-names = "default";
 389                 pinctrl-0 = <&uart2m1_xfer>;
 390                 status = "disabled";
 391         };
 392
 393         pmu: power-management@ff140000 {
 394                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 395                 reg = <0x0 0xff140000 0x0 0x1000>;
 396         };
 397
 398         i2c0: i2c@ff150000 {
 399                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 400                 reg = <0x0 0xff150000 0x0 0x1000>;
 401                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 405                 clock-names = "i2c", "pclk";
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&i2c0_xfer>;
 408                 status = "disabled";
 409         };
 410
 411         i2c1: i2c@ff160000 {
 412                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 413                 reg = <0x0 0xff160000 0x0 0x1000>;
 414                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 415                 #address-cells = <1>;
 416                 #size-cells = <0>;
 417                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 418                 clock-names = "i2c", "pclk";
 419                 pinctrl-names = "default";
 420                 pinctrl-0 = <&i2c1_xfer>;
 421                 status = "disabled";
 422         };
 423
 424         i2c2: i2c@ff170000 {
 425                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 426                 reg = <0x0 0xff170000 0x0 0x1000>;
 427                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 431                 clock-names = "i2c", "pclk";
 432                 pinctrl-names = "default";
 433                 pinctrl-0 = <&i2c2_xfer>;
 434                 status = "disabled";
 435         };
 436
 437         i2c3: i2c@ff180000 {
 438                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 439                 reg = <0x0 0xff180000 0x0 0x1000>;
 440                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 441                 #address-cells = <1>;
 442                 #size-cells = <0>;
 443                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 444                 clock-names = "i2c", "pclk";
 445                 pinctrl-names = "default";
 446                 pinctrl-0 = <&i2c3_xfer>;
 447                 status = "disabled";
 448         };
 449
 450         spi0: spi@ff190000 {
 451                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 452                 reg = <0x0 0xff190000 0x0 0x1000>;
 453                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 454                 #address-cells = <1>;
 455                 #size-cells = <0>;
 456                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 457                 clock-names = "spiclk", "apb_pclk";
 458                 dmas = <&dmac 8>, <&dmac 9>;
 459                 #dma-cells = <2>;
 460                 dma-names = "tx", "rx";
 461                 pinctrl-names = "default";
 462                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 463                 status = "disabled";
 464         };
 465
 466         wdt: watchdog@ff1a0000 {
 467                 compatible = "snps,dw-wdt";
 468                 reg = <0x0 0xff1a0000 0x0 0x100>;
 469                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 470                 status = "disabled";
 471         };
 472
 473         pwm0: pwm@ff1b0000 {
 474                 compatible = "rockchip,rk3328-pwm";
 475                 reg = <0x0 0xff1b0000 0x0 0x10>;
 476                 #pwm-cells = <3>;
 477                 pinctrl-names = "default";
 478                 pinctrl-0 = <&pwm0_pin>;
 479                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 480                 clock-names = "pwm", "pclk";
 481                 status = "disabled";
 482         };
 483
 484         pwm1: pwm@ff1b0010 {
 485                 compatible = "rockchip,rk3328-pwm";
 486                 reg = <0x0 0xff1b0010 0x0 0x10>;
 487                 #pwm-cells = <3>;
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&pwm1_pin>;
 490                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 491                 clock-names = "pwm", "pclk";
 492                 status = "disabled";
 493         };
 494
 495         pwm2: pwm@ff1b0020 {
 496                 compatible = "rockchip,rk3328-pwm";
 497                 reg = <0x0 0xff1b0020 0x0 0x10>;
 498                 #pwm-cells = <3>;
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&pwm2_pin>;
 501                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 502                 clock-names = "pwm", "pclk";
 503                 status = "disabled";
 504         };
 505
 506         pwm3: pwm@ff1b0030 {
 507                 compatible = "rockchip,rk3328-pwm";
 508                 reg = <0x0 0xff1b0030 0x0 0x10>;
 509                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 510                 #pwm-cells = <3>;
 511                 pinctrl-names = "default";
 512                 pinctrl-0 = <&pwmir_pin>;
 513                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 514                 clock-names = "pwm", "pclk";
 515                 status = "disabled";
 516         };
 517
 518         amba {
 519                 compatible = "simple-bus";
 520                 #address-cells = <2>;
 521                 #size-cells = <2>;
 522                 ranges;
 523
 524                 dmac: dmac@ff1f0000 {
 525                         compatible = "arm,pl330", "arm,primecell";
 526                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 527                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 528                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&cru ACLK_DMAC>;
 530                         clock-names = "apb_pclk";
 531                         #dma-cells = <1>;
 532                 };
 533         };
 534
 535         saradc: saradc@ff280000 {
 536                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 537                 reg = <0x0 0xff280000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 539                 #io-channel-cells = <1>;
 540                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 541                 clock-names = "saradc", "apb_pclk";
 542                 resets = <&cru SRST_SARADC_P>;
 543                 reset-names = "saradc-apb";
 544                 status = "disabled";
 545         };
 546
 547         gpu: gpu@ff300000 {
 548                 compatible = "arm,mali-450";
 549                 /* first item of 'reg' is dummy, to fit src code. */
 550                 reg = <0x0 0xff300000 0x0 0x40000>,
 551                       <0x0 0xff300000 0x0 0x40000>;
 552                 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 553                              <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 554                              <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
 555                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 556                              <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
 557                              <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 558                              <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 559                 interrupt-names = "Mali_GP_IRQ",
 560                                   "Mali_GP_MMU_IRQ",
 561                                   "IRQPP",
 562                                   "Mali_PP0_IRQ",
 563                                   "Mali_PP0_MMU_IRQ",
 564                                   "Mali_PP1_IRQ",
 565                                   "Mali_PP1_MMU_IRQ";
 566                 clocks = <&cru ACLK_GPU>;
 567                 clock-names = "clk_mali";
 568                 operating-points-v2 = <&gpu_opp_table>;
 569                 status = "disabled";
 570         };
 571
 572         gpu_opp_table: opp-table2 {
 573                 compatible = "operating-points-v2";
 574
 575                 opp@200000000 {
 576                         opp-hz = /bits/ 64 <200000000>;
 577                         opp-microvolt = <1050000>;
 578                 };
 579                 opp@300000000 {
 580                         opp-hz = /bits/ 64 <300000000>;
 581                         opp-microvolt = <1050000>;
 582                 };
 583                 opp@400000000 {
 584                         opp-hz = /bits/ 64 <400000000>;
 585                         opp-microvolt = <1050000>;
 586                 };
 587                 opp@500000000 {
 588                         opp-hz = /bits/ 64 <500000000>;
 589                         opp-microvolt = <1100000>;
 590                 };
 591         };
 592
 593         vop: vop@ff370000 {
 594                 compatible = "rockchip,rk3328-vop";
 595                 reg = <0x0 0xff370000 0x0 0x3efc>;
 596                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 597                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 598                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 599                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 600                 reset-names = "axi", "ahb", "dclk";
 601                 iommus = <&vop_mmu>;
 602                 status = "disabled";
 603
 604                 vop_out: port {
 605                         #address-cells = <1>;
 606                         #size-cells = <0>;
 607                 };
 608         };
 609
 610         vop_mmu: iommu@ff373f00 {
 611                 compatible = "rockchip,iommu";
 612                 reg = <0x0 0xff373f00 0x0 0x100>;
 613                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 614                 interrupt-names = "vop_mmu";
 615                 #iommu-cells = <0>;
 616                 status = "disabled";
 617         };
 618
 619         display_subsystem: display-subsystem {
 620                 compatible = "rockchip,display-subsystem";
 621                 ports = <&vop_out>;
 622                 status = "disabled";
 623         };
 624
 625         cru: clock-controller@ff440000 {
 626                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 627                 reg = <0x0 0xff440000 0x0 0x1000>;
 628                 rockchip,grf = <&grf>;
 629                 #clock-cells = <1>;
 630                 #reset-cells = <1>;
 631                 assigned-clocks =
 632                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 633                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 634                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 635                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 636                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 637                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 638                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 639                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 640                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 641                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 642                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 643                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 644                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 645                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 646                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 647                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 648                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 649                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 650                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 651                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 652                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 653                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 654                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 655                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 656                 assigned-clock-parents =
 657                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 658                         <&cru PLL_GPLL>, <&xin24m>,
 659                         <&xin24m>, <&xin24m>;
 660                 assigned-clock-rates =
 661                         <0>, <61440000>,
 662                         <0>, <24000000>,
 663                         <24000000>, <24000000>,
 664                         <15000000>, <15000000>,
 665                         <100000000>, <100000000>,
 666                         <100000000>, <100000000>,
 667                         <50000000>, <100000000>,
 668                         <100000000>, <100000000>,
 669                         <50000000>, <50000000>,
 670                         <50000000>, <50000000>,
 671                         <24000000>, <600000000>,
 672                         <491520000>, <1200000000>,
 673                         <150000000>, <75000000>,
 674                         <75000000>, <150000000>,
 675                         <75000000>, <75000000>,
 676                         <300000000>, <100000000>,
 677                         <300000000>, <200000000>,
 678                         <400000000>, <500000000>,
 679                         <200000000>, <300000000>,
 680                         <300000000>, <250000000>,
 681                         <200000000>, <100000000>,
 682                         <24000000>, <100000000>,
 683                         <150000000>, <50000000>,
 684                         <32768>, <32768>;
 685         };
 686
 687         usb2phy_grf: syscon@ff450000 {
 688                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 689                              "simple-mfd";
 690                 reg = <0x0 0xff450000 0x0 0x10000>;
 691                 #address-cells = <1>;
 692                 #size-cells = <1>;
 693
 694                 u2phy: usb2-phy@100 {
 695                         compatible = "rockchip,rk3328-usb2phy";
 696                         reg = <0x100 0x10>;
 697                         clocks = <&xin24m>;
 698                         clock-names = "phyclk";
 699                         #clock-cells = <0>;
 700                         assigned-clocks = <&cru USB480M>;
 701                         assigned-clock-parents = <&u2phy>;
 702                         clock-output-names = "usb480m_phy";
 703                         status = "disabled";
 704
 705                         u2phy_host: host-port {
 706                                 #phy-cells = <0>;
 707                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 708                                 interrupt-names = "linestate";
 709                                 status = "disabled";
 710                         };
 711
 712                         u2phy_otg: otg-port {
 713                                 #phy-cells = <0>;
 714                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 715                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 716                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 717                                 interrupt-names = "otg-bvalid", "otg-id",
 718                                                   "linestate";
 719                                 status = "disabled";
 720                         };
 721                 };
 722         };
 723
 724         usb3phy_grf: syscon@ff460000 {
 725                 compatible = "rockchip,usb3phy-grf", "syscon";
 726                 reg = <0x0 0xff460000 0x0 0x1000>;
 727         };
 728
 729         u3phy: usb3-phy@ff470000 {
 730                 compatible = "rockchip,rk3328-u3phy";
 731                 reg = <0x0 0xff470000 0x0 0x0>;
 732                 rockchip,u3phygrf = <&usb3phy_grf>;
 733                 rockchip,grf = <&grf>;
 734                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 735                 interrupt-names = "linestate";
 736                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 737                 clock-names = "u3phy-otg", "u3phy-pipe";
 738                 resets = <&cru SRST_USB3PHY_U2>,
 739                          <&cru SRST_USB3PHY_U3>,
 740                          <&cru SRST_USB3PHY_PIPE>,
 741                          <&cru SRST_USB3OTG_UTMI>,
 742                          <&cru SRST_USB3PHY_OTG_P>,
 743                          <&cru SRST_USB3PHY_PIPE_P>;
 744                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 745                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 746                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 747                 #address-cells = <2>;
 748                 #size-cells = <2>;
 749                 ranges;
 750                 status = "disabled";
 751
 752                 u3phy_utmi: utmi@ff470000 {
 753                         reg = <0x0 0xff470000 0x0 0x8000>;
 754                         #phy-cells = <0>;
 755                         status = "disabled";
 756                 };
 757
 758                 u3phy_pipe: pipe@ff478000 {
 759                         reg = <0x0 0xff478000 0x0 0x8000>;
 760                         #phy-cells = <0>;
 761                         status = "disabled";
 762                 };
 763         };
 764
 765         sdmmc: rksdmmc@ff500000 {
 766                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 767                 reg = <0x0 0xff500000 0x0 0x4000>;
 768                 clock-freq-min-max = <400000 150000000>;
 769                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 770                 clock-names = "biu", "ciu";
 771                 fifo-depth = <0x100>;
 772                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 773                 status = "disabled";
 774         };
 775
 776         sdio: dwmmc@ff510000 {
 777                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 778                 reg = <0x0 0xff510000 0x0 0x4000>;
 779                 clock-freq-min-max = <400000 150000000>;
 780                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 781                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 782                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 783                 fifo-depth = <0x100>;
 784                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 785                 status = "disabled";
 786         };
 787
 788         emmc: rksdmmc@ff520000 {
 789                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 790                 reg = <0x0 0xff520000 0x0 0x4000>;
 791                 clock-freq-min-max = <400000 150000000>;
 792                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 793                 clock-names = "biu", "ciu";
 794                 fifo-depth = <0x100>;
 795                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 796                 status = "disabled";
 797         };
 798
 799         gmac2io: eth@ff540000 {
 800                 compatible = "rockchip,rk3328-gmac";
 801                 reg = <0x0 0xff540000 0x0 0x10000>;
 802                 rockchip,grf = <&grf>;
 803                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 804                 interrupt-names = "macirq";
 805                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 806                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 807                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 808                          <&cru PCLK_MAC2IO>;
 809                 clock-names = "stmmaceth", "mac_clk_rx",
 810                               "mac_clk_tx", "clk_mac_ref",
 811                               "clk_mac_refout", "aclk_mac",
 812                               "pclk_mac";
 813                 resets = <&cru SRST_GMAC2IO_A>;
 814                 reset-names = "stmmaceth";
 815                 status = "disabled";
 816         };
 817
 818         usb20_otg: usb@ff580000 {
 819                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 820                              "snps,dwc2";
 821                 reg = <0x0 0xff580000 0x0 0x40000>;
 822                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 823                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 824                 clock-names = "otg", "otg_pmu";
 825                 dr_mode = "otg";
 826                 g-np-tx-fifo-size = <16>;
 827                 g-rx-fifo-size = <275>;
 828                 g-tx-fifo-size = <256 128 128 64 64 32>;
 829                 g-use-dma;
 830                 phys = <&u2phy_otg>;
 831                 phy-names = "usb2-phy";
 832                 status = "disabled";
 833         };
 834
 835         usb_host0_ehci: usb@ff5c0000 {
 836                 compatible = "generic-ehci";
 837                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 838                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 839                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 840                          <&u2phy>;
 841                 clock-names = "usbhost", "arbiter", "utmi";
 842                 phys = <&u2phy_host>;
 843                 phy-names = "usb";
 844                 status = "disabled";
 845         };
 846
 847         usb_host0_ohci: usb@ff5d0000 {
 848                 compatible = "generic-ohci";
 849                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 850                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 851                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 852                          <&u2phy>;
 853                 clock-names = "usbhost", "arbiter", "utmi";
 854                 phys = <&u2phy_host>;
 855                 phy-names = "usb";
 856                 status = "disabled";
 857         };
 858
 859         sdmmc_ext: rksdmmc@ff5f0000 {
 860                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 861                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 862                 clock-freq-min-max = <400000 150000000>;
 863                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 864                 clock-names = "biu", "ciu";
 865                 fifo-depth = <0x100>;
 866                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 867                 status = "disabled";
 868         };
 869
 870         usbdrd3: usb@ff600000 {
 871                 compatible = "rockchip,rk3328-dwc3";
 872                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 873                          <&cru ACLK_USB3OTG>;
 874                 clock-names = "ref_clk", "suspend_clk",
 875                               "bus_clk";
 876                 #address-cells = <2>;
 877                 #size-cells = <2>;
 878                 ranges;
 879                 status = "disabled";
 880
 881                 usbdrd_dwc3: dwc3@ff600000 {
 882                         compatible = "snps,dwc3";
 883                         reg = <0x0 0xff600000 0x0 0x100000>;
 884                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 885                         dr_mode = "host";
 886                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 887                         phy-names = "usb2-phy", "usb3-phy";
 888                         phy_type = "utmi_wide";
 889                         snps,dis_enblslpm_quirk;
 890                         snps,dis-u2-freeclk-exists-quirk;
 891                         snps,dis_u2_susphy_quirk;
 892                         snps,dis-u3-autosuspend-quirk;
 893                         snps,dis_u3_susphy_quirk;
 894                         snps,dis-del-phy-power-chg-quirk;
 895                         status = "disabled";
 896                 };
 897         };
 898
 899         gic: interrupt-controller@ff811000 {
 900                 compatible = "arm,gic-400";
 901                 #interrupt-cells = <3>;
 902                 #address-cells = <0>;
 903                 interrupt-controller;
 904                 reg = <0x0 0xff811000 0 0x1000>,
 905                       <0x0 0xff812000 0 0x2000>,
 906                       <0x0 0xff814000 0 0x2000>,
 907                       <0x0 0xff816000 0 0x2000>;
 908                 interrupts = <GIC_PPI 9
 909                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 910         };
 911
 912         pinctrl: pinctrl {
 913                 compatible = "rockchip,rk3328-pinctrl";
 914                 rockchip,grf = <&grf>;
 915                 #address-cells = <2>;
 916                 #size-cells = <2>;
 917                 ranges;
 918
 919                 gpio0: gpio0@ff210000 {
 920                         compatible = "rockchip,gpio-bank";
 921                         reg = <0x0 0xff210000 0x0 0x100>;
 922                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 923                         clocks = <&cru PCLK_GPIO0>;
 924
 925                         gpio-controller;
 926                         #gpio-cells = <2>;
 927
 928                         interrupt-controller;
 929                         #interrupt-cells = <2>;
 930                 };
 931
 932                 gpio1: gpio1@ff220000 {
 933                         compatible = "rockchip,gpio-bank";
 934                         reg = <0x0 0xff220000 0x0 0x100>;
 935                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 936                         clocks = <&cru PCLK_GPIO1>;
 937
 938                         gpio-controller;
 939                         #gpio-cells = <2>;
 940
 941                         interrupt-controller;
 942                         #interrupt-cells = <2>;
 943                 };
 944
 945                 gpio2: gpio2@ff230000 {
 946                         compatible = "rockchip,gpio-bank";
 947                         reg = <0x0 0xff230000 0x0 0x100>;
 948                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 949                         clocks = <&cru PCLK_GPIO2>;
 950
 951                         gpio-controller;
 952                         #gpio-cells = <2>;
 953
 954                         interrupt-controller;
 955                         #interrupt-cells = <2>;
 956                 };
 957
 958                 gpio3: gpio3@ff240000 {
 959                         compatible = "rockchip,gpio-bank";
 960                         reg = <0x0 0xff240000 0x0 0x100>;
 961                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 962                         clocks = <&cru PCLK_GPIO3>;
 963
 964                         gpio-controller;
 965                         #gpio-cells = <2>;
 966
 967                         interrupt-controller;
 968                         #interrupt-cells = <2>;
 969                 };
 970
 971                 pcfg_pull_up: pcfg-pull-up {
 972                         bias-pull-up;
 973                 };
 974
 975                 pcfg_pull_down: pcfg-pull-down {
 976                         bias-pull-down;
 977                 };
 978
 979                 pcfg_pull_none: pcfg-pull-none {
 980                         bias-disable;
 981                 };
 982
 983                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 984                         bias-disable;
 985                         drive-strength = <2>;
 986                 };
 987
 988                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 989                         bias-pull-up;
 990                         drive-strength = <2>;
 991                 };
 992
 993                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 994                         bias-pull-up;
 995                         drive-strength = <4>;
 996                 };
 997
 998                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 999                         bias-disable;
1000                         drive-strength = <4>;
1001                 };
1002
1003                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1004                         bias-pull-down;
1005                         drive-strength = <4>;
1006                 };
1007
1008                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1009                         bias-disable;
1010                         drive-strength = <8>;
1011                 };
1012
1013                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1014                         bias-pull-up;
1015                         drive-strength = <8>;
1016                 };
1017
1018                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1019                         bias-disable;
1020                         drive-strength = <12>;
1021                 };
1022
1023                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1024                         bias-pull-up;
1025                         drive-strength = <12>;
1026                 };
1027
1028                 pcfg_output_high: pcfg-output-high {
1029                         output-high;
1030                 };
1031
1032                 pcfg_output_low: pcfg-output-low {
1033                         output-low;
1034                 };
1035
1036                 pcfg_input_high: pcfg-input-high {
1037                         bias-pull-up;
1038                         input-enable;
1039                 };
1040
1041                 pcfg_input: pcfg-input {
1042                         input-enable;
1043                 };
1044
1045                 i2c0 {
1046                         i2c0_xfer: i2c0-xfer {
1047                                 rockchip,pins =
1048                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1049                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1050                         };
1051                 };
1052
1053                 i2c1 {
1054                         i2c1_xfer: i2c1-xfer {
1055                                 rockchip,pins =
1056                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1057                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
1058                         };
1059                 };
1060
1061                 i2c2 {
1062                         i2c2_xfer: i2c2-xfer {
1063                                 rockchip,pins =
1064                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1065                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1066                         };
1067                 };
1068
1069                 i2c3 {
1070                         i2c3_xfer: i2c3-xfer {
1071                                 rockchip,pins =
1072                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1073                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1074                         };
1075                         i2c3_gpio: i2c3-gpio {
1076                                 rockchip,pins =
1077                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1078                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1079                         };
1080                 };
1081
1082                 hdmi_i2c {
1083                         hdmii2c_xfer: hdmii2c-xfer {
1084                                 rockchip,pins =
1085                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1086                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1087                         };
1088                 };
1089
1090                 tsadc {
1091                         otp_gpio: otp-gpio {
1092                                 rockchip,pins =
1093                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1094                         };
1095
1096                         otp_out: otp-out {
1097                                 rockchip,pins =
1098                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1099                         };
1100                 };
1101
1102                 uart0 {
1103                         uart0_xfer: uart0-xfer {
1104                                 rockchip,pins =
1105                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1106                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1107                         };
1108
1109                         uart0_cts: uart0-cts {
1110                                 rockchip,pins =
1111                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1112                         };
1113
1114                         uart0_rts: uart0-rts {
1115                                 rockchip,pins =
1116                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1117                         };
1118
1119                         uart0_rts_gpio: uart0-rts-gpio {
1120                                 rockchip,pins =
1121                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1122                         };
1123                 };
1124
1125                 uart1 {
1126                         uart1_xfer: uart1-xfer {
1127                                 rockchip,pins =
1128                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1129                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1130                         };
1131
1132                         uart1_cts: uart1-cts {
1133                                 rockchip,pins =
1134                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1135                         };
1136
1137                         uart1_rts: uart1-rts {
1138                                 rockchip,pins =
1139                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1140                         };
1141
1142                         uart1_rts_gpio: uart1-rts-gpio {
1143                                 rockchip,pins =
1144                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1145                         };
1146                 };
1147
1148                 uart2-0 {
1149                         uart2m0_xfer: uart2m0-xfer {
1150                                 rockchip,pins =
1151                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1152                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1153                         };
1154                 };
1155
1156                 uart2-1 {
1157                         uart2m1_xfer: uart2m1-xfer {
1158                                 rockchip,pins =
1159                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1160                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 spi0-0 {
1165                         spi0m0_clk: spi0m0-clk {
1166                                 rockchip,pins =
1167                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1168                         };
1169
1170                         spi0m0_cs0: spi0m0-cs0 {
1171                                 rockchip,pins =
1172                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1173                         };
1174
1175                         spi0m0_tx: spi0m0-tx {
1176                                 rockchip,pins =
1177                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1178                         };
1179
1180                         spi0m0_rx: spi0m0-rx {
1181                                 rockchip,pins =
1182                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1183                         };
1184
1185                         spi0m0_cs1: spi0m0-cs1 {
1186                                 rockchip,pins =
1187                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1188                         };
1189                 };
1190
1191                 spi0-1 {
1192                         spi0m1_clk: spi0m1-clk {
1193                                 rockchip,pins =
1194                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1195                         };
1196
1197                         spi0m1_cs0: spi0m1-cs0 {
1198                                 rockchip,pins =
1199                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1200                         };
1201
1202                         spi0m1_tx: spi0m1-tx {
1203                                 rockchip,pins =
1204                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1205                         };
1206
1207                         spi0m1_rx: spi0m1-rx {
1208                                 rockchip,pins =
1209                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1210                         };
1211
1212                         spi0m1_cs1: spi0m1-cs1 {
1213                                 rockchip,pins =
1214                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1215                         };
1216                 };
1217
1218                 spi0-2 {
1219                         spi0m2_clk: spi0m2-clk {
1220                                 rockchip,pins =
1221                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1222                         };
1223
1224                         spi0m2_cs0: spi0m2-cs0 {
1225                                 rockchip,pins =
1226                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1227                         };
1228
1229                         spi0m2_tx: spi0m2-tx {
1230                                 rockchip,pins =
1231                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1232                         };
1233
1234                         spi0m2_rx: spi0m2-rx {
1235                                 rockchip,pins =
1236                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1237                         };
1238                 };
1239
1240                 pdm-0 {
1241                         pdmm0_clk: pdmm0-clk {
1242                                 rockchip,pins =
1243                                         <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1244                         };
1245
1246                         pdmm0_fsync: pdmm0-fsync {
1247                                 rockchip,pins =
1248                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1249                         };
1250
1251                         pdmm0_sdi0: pdmm0-sdi0 {
1252                                 rockchip,pins =
1253                                         <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1254                         };
1255
1256                         pdmm0_sdi1: pdmm0-sdi1 {
1257                                 rockchip,pins =
1258                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1259                         };
1260
1261                         pdmm0_sdi2: pdmm0-sdi2 {
1262                                 rockchip,pins =
1263                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
1264                         };
1265
1266                         pdmm0_sdi3: pdmm0-sdi3 {
1267                                 rockchip,pins =
1268                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1269                         };
1270
1271                         pdmm0_sleep: pdmm0-sleep {
1272                                 rockchip,pins =
1273                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1274                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1275                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1276                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1277                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1278                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1279                         };
1280                 };
1281
1282                 i2s1 {
1283                         i2s1_mclk: i2s1-mclk {
1284                                 rockchip,pins =
1285                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287
1288                         i2s1_sclk: i2s1-sclk {
1289                                 rockchip,pins =
1290                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1291                         };
1292
1293                         i2s1_lrckrx: i2s1-lrckrx {
1294                                 rockchip,pins =
1295                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297
1298                         i2s1_lrcktx: i2s1-lrcktx {
1299                                 rockchip,pins =
1300                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1301                         };
1302
1303                         i2s1_sdi: i2s1-sdi {
1304                                 rockchip,pins =
1305                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1306                         };
1307
1308                         i2s1_sdo: i2s1-sdo {
1309                                 rockchip,pins =
1310                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1311                         };
1312
1313                         i2s1_sdio1: i2s1-sdio1 {
1314                                 rockchip,pins =
1315                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1316                         };
1317
1318                         i2s1_sdio2: i2s1-sdio2 {
1319                                 rockchip,pins =
1320                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1321                         };
1322
1323                         i2s1_sdio3: i2s1-sdio3 {
1324                                 rockchip,pins =
1325                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1326                         };
1327
1328                         i2s1_sleep: i2s1-sleep {
1329                                 rockchip,pins =
1330                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1331                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1332                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1333                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1334                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1335                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1336                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1337                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1338                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1339                         };
1340                 };
1341
1342                 i2s2-0 {
1343                         i2s2m0_mclk: i2s2m0-mclk {
1344                                 rockchip,pins =
1345                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1346                         };
1347
1348                         i2s2m0_sclk: i2s2m0-sclk {
1349                                 rockchip,pins =
1350                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352
1353                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1354                                 rockchip,pins =
1355                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1356                         };
1357
1358                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1359                                 rockchip,pins =
1360                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1361                         };
1362
1363                         i2s2m0_sdi: i2s2m0-sdi {
1364                                 rockchip,pins =
1365                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1366                         };
1367
1368                         i2s2m0_sdo: i2s2m0-sdo {
1369                                 rockchip,pins =
1370                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1371                         };
1372
1373                         i2s2m0_sleep: i2s2m0-sleep {
1374                                 rockchip,pins =
1375                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1376                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1377                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1378                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1379                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1380                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1381                         };
1382                 };
1383
1384                 i2s2-1 {
1385                         i2s2m1_mclk: i2s2m1-mclk {
1386                                 rockchip,pins =
1387                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1388                         };
1389
1390                         i2s2m1_sclk: i2s2m1-sclk {
1391                                 rockchip,pins =
1392                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1393                         };
1394
1395                         i2s2m1_lrckrx: i2sm1-lrckrx {
1396                                 rockchip,pins =
1397                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1398                         };
1399
1400                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1401                                 rockchip,pins =
1402                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1403                         };
1404
1405                         i2s2m1_sdi: i2s2m1-sdi {
1406                                 rockchip,pins =
1407                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1408                         };
1409
1410                         i2s2m1_sdo: i2s2m1-sdo {
1411                                 rockchip,pins =
1412                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1413                         };
1414
1415                         i2s2m1_sleep: i2s2m1-sleep {
1416                                 rockchip,pins =
1417                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1418                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1419                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1420                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1421                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1422                         };
1423                 };
1424
1425                 spdif-0 {
1426                         spdifm0_tx: spdifm0-tx {
1427                                 rockchip,pins =
1428                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1429                         };
1430                 };
1431
1432                 spdif-1 {
1433                         spdifm1_tx: spdifm1-tx {
1434                                 rockchip,pins =
1435                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1436                         };
1437                 };
1438
1439                 spdif-2 {
1440                         spdifm2_tx: spdifm2-tx {
1441                                 rockchip,pins =
1442                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1443                         };
1444                 };
1445
1446                 sdmmc0-0 {
1447                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1448                                 rockchip,pins =
1449                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1450                         };
1451
1452                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1453                                 rockchip,pins =
1454                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1455                         };
1456                 };
1457
1458                 sdmmc0-1 {
1459                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1460                                 rockchip,pins =
1461                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1462                         };
1463
1464                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1465                                 rockchip,pins =
1466                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1467                         };
1468                 };
1469
1470                 sdmmc0 {
1471                         sdmmc0_clk: sdmmc0-clk {
1472                                 rockchip,pins =
1473                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1474                         };
1475
1476                         sdmmc0_cmd: sdmmc0-cmd {
1477                                 rockchip,pins =
1478                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1479                         };
1480
1481                         sdmmc0_dectn: sdmmc0-dectn {
1482                                 rockchip,pins =
1483                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1484                         };
1485
1486                         sdmmc0_wrprt: sdmmc0-wrprt {
1487                                 rockchip,pins =
1488                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1489                         };
1490
1491                         sdmmc0_bus1: sdmmc0-bus1 {
1492                                 rockchip,pins =
1493                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1494                         };
1495
1496                         sdmmc0_bus4: sdmmc0-bus4 {
1497                                 rockchip,pins =
1498                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1499                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1500                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1501                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1502                         };
1503
1504                         sdmmc0_gpio: sdmmc0-gpio {
1505                                 rockchip,pins =
1506                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1507                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1509                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1510                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1511                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1512                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1513                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1514                         };
1515                 };
1516
1517                 sdmmc0ext {
1518                         sdmmc0ext_clk: sdmmc0ext-clk {
1519                                 rockchip,pins =
1520                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1521                         };
1522
1523                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1524                                 rockchip,pins =
1525                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1526                         };
1527
1528                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1529                                 rockchip,pins =
1530                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1531                         };
1532
1533                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1534                                 rockchip,pins =
1535                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1536                         };
1537
1538                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1539                                 rockchip,pins =
1540                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1541                         };
1542
1543                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1544                                 rockchip,pins =
1545                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1546                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1547                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1548                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1549                         };
1550
1551                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1552                                 rockchip,pins =
1553                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1554                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1555                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1556                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1557                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1558                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1559                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1560                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1561                         };
1562                 };
1563
1564                 sdmmc1 {
1565                         sdmmc1_clk: sdmmc1-clk {
1566                                 rockchip,pins =
1567                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1568                         };
1569
1570                         sdmmc1_cmd: sdmmc1-cmd {
1571                                 rockchip,pins =
1572                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1573                         };
1574
1575                         sdmmc1_pwren: sdmmc1-pwren {
1576                                 rockchip,pins =
1577                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1578                         };
1579
1580                         sdmmc1_wrprt: sdmmc1-wrprt {
1581                                 rockchip,pins =
1582                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1583                         };
1584
1585                         sdmmc1_dectn: sdmmc1-dectn {
1586                                 rockchip,pins =
1587                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1588                         };
1589
1590                         sdmmc1_bus1: sdmmc1-bus1 {
1591                                 rockchip,pins =
1592                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1593                         };
1594
1595                         sdmmc1_bus4: sdmmc1-bus4 {
1596                                 rockchip,pins =
1597                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>,
1598                                         <1 RK_PB7 RK_FUNC_1 &pcfg_pull_up_8ma>,
1599                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1600                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1601                         };
1602
1603                         sdmmc1_gpio: sdmmc1-gpio {
1604                                 rockchip,pins =
1605                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1606                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1607                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1608                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1609                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1610                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1611                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1612                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1613                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1614                         };
1615                 };
1616
1617                 emmc {
1618                         emmc_clk: emmc-clk {
1619                                 rockchip,pins =
1620                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1621                         };
1622
1623                         emmc_cmd: emmc-cmd {
1624                                 rockchip,pins =
1625                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1626                         };
1627
1628                         emmc_pwren: emmc-pwren {
1629                                 rockchip,pins =
1630                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1631                         };
1632
1633                         emmc_rstnout: emmc-rstnout {
1634                                 rockchip,pins =
1635                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1636                         };
1637
1638                         emmc_bus1: emmc-bus1 {
1639                                 rockchip,pins =
1640                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1641                         };
1642
1643                         emmc_bus4: emmc-bus4 {
1644                                 rockchip,pins =
1645                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1646                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1647                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1648                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1649                         };
1650
1651                         emmc_bus8: emmc-bus8 {
1652                                 rockchip,pins =
1653                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1654                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1655                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1656                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1657                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1658                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1659                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1660                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1661                         };
1662                 };
1663
1664                 pwm0 {
1665                         pwm0_pin: pwm0-pin {
1666                                 rockchip,pins =
1667                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 pwm1 {
1672                         pwm1_pin: pwm1-pin {
1673                                 rockchip,pins =
1674                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1675                         };
1676                 };
1677
1678                 pwm2 {
1679                         pwm2_pin: pwm2-pin {
1680                                 rockchip,pins =
1681                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1682                         };
1683                 };
1684
1685                 pwmir {
1686                         pwmir_pin: pwmir-pin {
1687                                 rockchip,pins =
1688                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1689                         };
1690                 };
1691
1692                 gmac-1 {
1693                         rgmiim1_pins: rgmiim1-pins {
1694                                 rockchip,pins =
1695                                         /* mac_txclk */
1696                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1697                                         /* mac_rxclk */
1698                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1699                                         /* mac_mdio */
1700                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1701                                         /* mac_txen */
1702                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1703                                         /* mac_clk */
1704                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1705                                         /* mac_rxdv */
1706                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1707                                         /* mac_mdc */
1708                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1709                                         /* mac_rxd1 */
1710                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1711                                         /* mac_rxd0 */
1712                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1713                                         /* mac_txd1 */
1714                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1715                                         /* mac_txd0 */
1716                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1717                                         /* mac_rxd3 */
1718                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1719                                         /* mac_rxd2 */
1720                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1721                                         /* mac_txd3 */
1722                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1723                                         /* mac_txd2 */
1724                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1725
1726                                         /* mac_txclk */
1727                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1728                                         /* mac_txen */
1729                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1730                                         /* mac_clk */
1731                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1732                                         /* mac_txd1 */
1733                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1734                                         /* mac_txd0 */
1735                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1736                                         /* mac_txd3 */
1737                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1738                                         /* mac_txd2 */
1739                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1740                         };
1741
1742                         rmiim1_pins: rmiim1-pins {
1743                                 rockchip,pins =
1744                                         /* mac_mdio */
1745                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1746                                         /* mac_txen */
1747                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1748                                         /* mac_clk */
1749                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1750                                         /* mac_rxer */
1751                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1752                                         /* mac_rxdv */
1753                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1754                                         /* mac_mdc */
1755                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1756                                         /* mac_rxd1 */
1757                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1758                                         /* mac_rxd0 */
1759                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1760                                         /* mac_txd1 */
1761                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1762                                         /* mac_txd0 */
1763                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1764
1765                                         /* mac_mdio */
1766                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1767                                         /* mac_txen */
1768                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1769                                         /* mac_clk */
1770                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1771                                         /* mac_mdc */
1772                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1773                                         /* mac_txd1 */
1774                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1775                                         /* mac_txd0 */
1776                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 gmac2phy {
1781                         fephyled_speed100: fephyled-speed100 {
1782                                 rockchip,pins =
1783                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1784                         };
1785
1786                         fephyled_speed10: fephyled-speed10 {
1787                                 rockchip,pins =
1788                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1789                         };
1790
1791                         fephyled_duplex: fephyled-duplex {
1792                                 rockchip,pins =
1793                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1794                         };
1795
1796                         fephyled_rxm0: fephyled-rxm0 {
1797                                 rockchip,pins =
1798                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1799                         };
1800
1801                         fephyled_txm0: fephyled-txm0 {
1802                                 rockchip,pins =
1803                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1804                         };
1805
1806                         fephyled_linkm0: fephyled-linkm0 {
1807                                 rockchip,pins =
1808                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1809                         };
1810
1811                         fephyled_rxm1: fephyled-rxm1 {
1812                                 rockchip,pins =
1813                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1814                         };
1815
1816                         fephyled_txm1: fephyled-txm1 {
1817                                 rockchip,pins =
1818                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1819                         };
1820
1821                         fephyled_linkm1: fephyled-linkm1 {
1822                                 rockchip,pins =
1823                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 tsadc_pin {
1828                         tsadc_int: tsadc-int {
1829                                 rockchip,pins =
1830                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832                         tsadc_gpio: tsadc-gpio {
1833                                 rockchip,pins =
1834                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1835                         };
1836                 };
1837
1838                 hdmi_pin {
1839                         hdmi_cec: hdmi-cec {
1840                                 rockchip,pins =
1841                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1842                         };
1843
1844                         hdmi_hpd: hdmi-hpd {
1845                                 rockchip,pins =
1846                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1847                         };
1848                 };
1849
1850                 cif-0 {
1851                         dvp_d2d9_m0:dvp-d2d9-m0 {
1852                                 rockchip,pins =
1853                                         /* cif_d0 */
1854                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1855                                         /* cif_d1 */
1856                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1857                                         /* cif_d2 */
1858                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1859                                         /* cif_d3 */
1860                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1861                                         /* cif_d4 */
1862                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1863                                         /* cif_d5m0 */
1864                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1865                                         /* cif_d6m0 */
1866                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1867                                         /* cif_d7m0 */
1868                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1869                                         /* cif_href */
1870                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1871                                         /* cif_vsync */
1872                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1873                                         /* cif_clkoutm0 */
1874                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1875                                         /* cif_clkin */
1876                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1877                         };
1878                 };
1879
1880                 cif-1 {
1881                         dvp_d2d9_m1:dvp-d2d9-m1 {
1882                                 rockchip,pins =
1883                                         /* cif_d0 */
1884                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1885                                         /* cif_d1 */
1886                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1887                                         /* cif_d2 */
1888                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1889                                         /* cif_d3 */
1890                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1891                                         /* cif_d4 */
1892                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1893                                         /* cif_d5m1 */
1894                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1895                                         /* cif_d6m1 */
1896                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1897                                         /* cif_d7m1 */
1898                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1899                                         /* cif_href */
1900                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1901                                         /* cif_vsync */
1902                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1903                                         /* cif_clkoutm1 */
1904                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1905                                         /* cif_clkin */
1906                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1907                         };
1908                 };
1909         };
1910 };