arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77 //                      clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x2>;
  90                         enable-method = "psci";
  91                 };
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x3>;
  96                         enable-method = "psci";
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp_table0 {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp@408000000 {
 105                         opp-hz = /bits/ 64 <408000000>;
 106                         opp-microvolt = <950000>;
 107                         clock-latency-ns = <40000>;
 108                         opp-suspend;
 109                 };
 110                 opp@600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                 };
 115                 opp@816000000 {
 116                         opp-hz = /bits/ 64 <816000000>;
 117                         opp-microvolt = <1000000>;
 118                         clock-latency-ns = <40000>;
 119                 };
 120                 opp@1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1100000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp@1200000000 {
 126                         opp-hz = /bits/ 64 <1200000000>;
 127                         opp-microvolt = <1225000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp@1296000000 {
 131                         opp-hz = /bits/ 64 <1296000000>;
 132                         opp-microvolt = <1300000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135         };
 136
 137         arm-pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 143                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         i2s0: i2s@ff000000 {
 167                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 168                 reg = <0x0 0xff000000 0x0 0x1000>;
 169                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 171                 clock-names = "i2s_clk", "i2s_hclk";
 172                 dmas = <&dmac 11>, <&dmac 12>;
 173                 #dma-cells = <2>;
 174                 dma-names = "tx", "rx";
 175                 status = "disabled";
 176         };
 177
 178         i2s1: i2s@ff010000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff010000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 14>, <&dmac 15>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s2: i2s@ff020000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff020000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 0>, <&dmac 1>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 pinctrl-names = "default", "sleep";
 200                 pinctrl-0 = <&i2s2m0_mclk
 201                              &i2s2m0_sclk
 202                              &i2s2m0_lrcktx
 203                              &i2s2m0_lrckrx
 204                              &i2s2m0_sdo
 205                              &i2s2m0_sdi>;
 206                 pinctrl-1 = <&i2s2m0_sleep>;
 207                 status = "disabled";
 208         };
 209
 210         spdif: spdif@ff030000 {
 211                 compatible = "rockchip,rk3328-spdif";
 212                 reg = <0x0 0xff030000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 215                 clock-names = "mclk", "hclk";
 216                 dmas = <&dmac 10>;
 217                 #dma-cells = <1>;
 218                 dma-names = "tx";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&spdifm2_tx>;
 221                 status = "disabled";
 222         };
 223
 224         grf: syscon@ff100000 {
 225                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff100000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229
 230                 io_domains: io-domains {
 231                         compatible = "rockchip,rk3328-io-voltage-domain";
 232                         status = "disabled";
 233                 };
 234
 235                 power: power-controller {
 236                         compatible = "rockchip,rk3328-power-controller";
 237                         #power-domain-cells = <1>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241
 242                         pd_hevc@RK3328_PD_HEVC {
 243                                 reg = <RK3328_PD_HEVC>;
 244                         };
 245                         pd_video@RK3328_PD_VIDEO {
 246                                 reg = <RK3328_PD_VIDEO>;
 247                         };
 248                         pd_vpu@RK3328_PD_VPU {
 249                                 reg = <RK3328_PD_VPU>;
 250                         };
 251                 };
 252
 253                 reboot-mode {
 254                         compatible = "syscon-reboot-mode";
 255                         offset = <0x5c8>;
 256                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 257                         mode-charge = <BOOT_CHARGING>;
 258                         mode-fastboot = <BOOT_FASTBOOT>;
 259                         mode-loader = <BOOT_BL_DOWNLOAD>;
 260                         mode-normal = <BOOT_NORMAL>;
 261                         mode-recovery = <BOOT_RECOVERY>;
 262                         mode-ums = <BOOT_UMS>;
 263                 };
 264         };
 265
 266         uart0: serial@ff110000 {
 267                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 268                 reg = <0x0 0xff110000 0x0 0x100>;
 269                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 reg-shift = <2>;
 273                 reg-io-width = <4>;
 274                 dmas = <&dmac 2>, <&dmac 3>;
 275                 #dma-cells = <2>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 278                 status = "disabled";
 279         };
 280
 281         uart1: serial@ff120000 {
 282                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 283                 reg = <0x0 0xff120000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 286                 clock-names = "sclk_uart", "pclk_uart";
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 dmas = <&dmac 4>, <&dmac 5>;
 290                 #dma-cells = <2>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 293                 status = "disabled";
 294         };
 295
 296         uart2: serial@ff130000 {
 297                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff130000 0x0 0x100>;
 299                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 301                 clock-names = "baudclk", "apb_pclk";
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 dmas = <&dmac 6>, <&dmac 7>;
 305                 #dma-cells = <2>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&uart2m1_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         pmu: power-management@ff140000 {
 312                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314         };
 315
 316         i2c0: i2c@ff150000 {
 317                 compatible = "rockchip,rk3328-i2c";
 318                 reg = <0x0 0xff150000 0x0 0x1000>;
 319                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 323                 clock-names = "i2c", "pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff160000 {
 330                 compatible = "rockchip,rk3328-i2c";
 331                 reg = <0x0 0xff160000 0x0 0x1000>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 336                 clock-names = "i2c", "pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@ff170000 {
 343                 compatible = "rockchip,rk3328-i2c";
 344                 reg = <0x0 0xff170000 0x0 0x1000>;
 345                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 349                 clock-names = "i2c", "pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff180000 {
 356                 compatible = "rockchip,rk3328-i2c";
 357                 reg = <0x0 0xff180000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 362                 clock-names = "i2c", "pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff190000 {
 369                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff190000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac 8>, <&dmac 9>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 381                 status = "disabled";
 382         };
 383
 384         wdt: watchdog@ff1a0000 {
 385                 compatible = "snps,dw-wdt";
 386                 reg = <0x0 0xff1a0000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 388                 status = "disabled";
 389         };
 390
 391         amba {
 392                 compatible = "simple-bus";
 393                 #address-cells = <2>;
 394                 #size-cells = <2>;
 395                 ranges;
 396
 397                 dmac: dmac@ff1f0000 {
 398                         compatible = "arm,pl330", "arm,primecell";
 399                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 400                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 401                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 402                         clocks = <&cru ACLK_DMAC>;
 403                         clock-names = "apb_pclk";
 404                         #dma-cells = <1>;
 405                 };
 406         };
 407
 408         saradc: saradc@ff280000 {
 409                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 410                 reg = <0x0 0xff280000 0x0 0x100>;
 411                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 412                 #io-channel-cells = <1>;
 413                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 414                 clock-names = "saradc", "apb_pclk";
 415                 resets = <&cru SRST_SARADC_P>;
 416                 reset-names = "saradc-apb";
 417                 status = "disabled";
 418         };
 419
 420         cru: clock-controller@ff440000 {
 421                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 422                 reg = <0x0 0xff440000 0x0 0x1000>;
 423                 rockchip,grf = <&grf>;
 424                 #clock-cells = <1>;
 425                 #reset-cells = <1>;
 426                 assigned-clocks =
 427                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 428                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 429                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 430                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 431                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 432                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 433                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 434                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 435                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 436                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 437                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 438                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 439                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 440                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 441                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 442                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 443                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 444                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 445                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 446                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 447                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 448                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 449                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 450                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 451                 assigned-clock-parents =
 452                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 453                         <&cru PLL_GPLL>, <&xin24m>,
 454                         <&xin24m>, <&xin24m>;
 455                 assigned-clock-rates =
 456                         <0>, <61440000>,
 457                         <0>, <24000000>,
 458                         <24000000>, <24000000>,
 459                         <15000000>, <15000000>,
 460                         <100000000>, <100000000>,
 461                         <100000000>, <100000000>,
 462                         <50000000>, <100000000>,
 463                         <100000000>, <100000000>,
 464                         <50000000>, <50000000>,
 465                         <50000000>, <50000000>,
 466                         <24000000>, <600000000>,
 467                         <491520000>, <1200000000>,
 468                         <150000000>, <75000000>,
 469                         <75000000>, <150000000>,
 470                         <75000000>, <75000000>,
 471                         <300000000>, <100000000>,
 472                         <300000000>, <200000000>,
 473                         <400000000>, <500000000>,
 474                         <200000000>, <300000000>,
 475                         <300000000>, <250000000>,
 476                         <200000000>, <100000000>,
 477                         <24000000>, <100000000>,
 478                         <150000000>, <50000000>,
 479                         <32768>, <32768>;
 480         };
 481
 482         usb2phy_grf: syscon@ff450000 {
 483                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 484                              "simple-mfd";
 485                 reg = <0x0 0xff450000 0x0 0x10000>;
 486                 #address-cells = <1>;
 487                 #size-cells = <1>;
 488
 489                 u2phy: usb2-phy@100 {
 490                         compatible = "rockchip,rk3328-usb2phy";
 491                         reg = <0x100 0x10>;
 492                         clocks = <&xin24m>;
 493                         clock-names = "phyclk";
 494                         #clock-cells = <0>;
 495                         assigned-clocks = <&cru USB480M>;
 496                         assigned-clock-parents = <&u2phy>;
 497                         clock-output-names = "usb480m_phy";
 498                         status = "disabled";
 499
 500                         u2phy_host: host-port {
 501                                 #phy-cells = <0>;
 502                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 503                                 interrupt-names = "linestate";
 504                                 status = "disabled";
 505                         };
 506                 };
 507         };
 508
 509         usb3phy_grf: syscon@ff460000 {
 510                 compatible = "rockchip,usb3phy-grf", "syscon";
 511                 reg = <0x0 0xff460000 0x0 0x1000>;
 512         };
 513
 514         u3phy: usb3-phy@ff470000 {
 515                 compatible = "rockchip,rk3328-u3phy";
 516                 reg = <0x0 0xff470000 0x0 0x0>;
 517                 rockchip,u3phygrf = <&usb3phy_grf>;
 518                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 519                 interrupt-names = "linestate";
 520                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 521                 clock-names = "u3phy-otg", "u3phy-pipe";
 522                 resets = <&cru SRST_USB3PHY_U2>,
 523                          <&cru SRST_USB3PHY_U3>,
 524                          <&cru SRST_USB3PHY_PIPE>,
 525                          <&cru SRST_USB3OTG_UTMI>,
 526                          <&cru SRST_USB3PHY_OTG_P>,
 527                          <&cru SRST_USB3PHY_PIPE_P>;
 528                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 529                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 530                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 531                 #address-cells = <2>;
 532                 #size-cells = <2>;
 533                 ranges;
 534                 status = "disabled";
 535
 536                 u3phy_utmi: utmi@ff470000 {
 537                         reg = <0x0 0xff470000 0x0 0x8000>;
 538                         #phy-cells = <0>;
 539                         status = "disabled";
 540                 };
 541
 542                 u3phy_pipe: pipe@ff478000 {
 543                         reg = <0x0 0xff478000 0x0 0x8000>;
 544                         #phy-cells = <0>;
 545                         status = "disabled";
 546                 };
 547         };
 548
 549         sdmmc: rksdmmc@ff500000 {
 550                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 551                 reg = <0x0 0xff500000 0x0 0x4000>;
 552                 clock-freq-min-max = <400000 150000000>;
 553                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 554                 clock-names = "biu", "ciu";
 555                 fifo-depth = <0x100>;
 556                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 557                 status = "disabled";
 558         };
 559
 560         sdio: dwmmc@ff510000 {
 561                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 562                 reg = <0x0 0xff510000 0x0 0x4000>;
 563                 clock-freq-min-max = <400000 150000000>;
 564                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 565                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 566                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 567                 fifo-depth = <0x100>;
 568                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 569                 status = "disabled";
 570         };
 571
 572         emmc: rksdmmc@ff520000 {
 573                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 574                 reg = <0x0 0xff520000 0x0 0x4000>;
 575                 clock-freq-min-max = <400000 150000000>;
 576                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 577                 clock-names = "biu", "ciu";
 578                 fifo-depth = <0x100>;
 579                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 580                 status = "disabled";
 581         };
 582
 583         usb20_otg: usb@ff580000 {
 584                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 585                              "snps,dwc2";
 586                 reg = <0x0 0xff580000 0x0 0x40000>;
 587                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 588                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 589                 clock-names = "otg", "otg_pmu";
 590                 dr_mode = "otg";
 591                 g-np-tx-fifo-size = <16>;
 592                 g-rx-fifo-size = <275>;
 593                 g-tx-fifo-size = <256 128 128 64 64 32>;
 594                 g-use-dma;
 595                 status = "disabled";
 596         };
 597
 598         usb_host0_ehci: usb@ff5c0000 {
 599                 compatible = "generic-ehci";
 600                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 601                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 602                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 603                          <&u2phy>;
 604                 clock-names = "usbhost", "arbiter", "utmi";
 605                 phys = <&u2phy_host>;
 606                 phy-names = "usb";
 607                 status = "disabled";
 608         };
 609
 610         usb_host0_ohci: usb@ff5d0000 {
 611                 compatible = "generic-ohci";
 612                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 613                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 614                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 615                          <&u2phy>;
 616                 clock-names = "usbhost", "arbiter", "utmi";
 617                 phys = <&u2phy_host>;
 618                 phy-names = "usb";
 619                 status = "disabled";
 620         };
 621
 622         sdmmc_ext: rksdmmc@ff5f0000 {
 623                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 624                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 625                 clock-freq-min-max = <400000 150000000>;
 626                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 627                 clock-names = "biu", "ciu";
 628                 fifo-depth = <0x100>;
 629                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 630                 status = "disabled";
 631         };
 632
 633         gic: interrupt-controller@ff811000 {
 634                 compatible = "arm,gic-400";
 635                 #interrupt-cells = <3>;
 636                 #address-cells = <0>;
 637                 interrupt-controller;
 638                 reg = <0x0 0xff811000 0 0x1000>,
 639                       <0x0 0xff812000 0 0x2000>,
 640                       <0x0 0xff814000 0 0x2000>,
 641                       <0x0 0xff816000 0 0x2000>;
 642                 interrupts = <GIC_PPI 9
 643                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 644         };
 645
 646         pinctrl: pinctrl {
 647                 compatible = "rockchip,rk3328-pinctrl";
 648                 rockchip,grf = <&grf>;
 649                 #address-cells = <2>;
 650                 #size-cells = <2>;
 651                 ranges;
 652
 653                 gpio0: gpio0@ff210000 {
 654                         compatible = "rockchip,gpio-bank";
 655                         reg = <0x0 0xff210000 0x0 0x100>;
 656                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 657                         clocks = <&cru PCLK_GPIO0>;
 658
 659                         gpio-controller;
 660                         #gpio-cells = <2>;
 661
 662                         interrupt-controller;
 663                         #interrupt-cells = <2>;
 664                 };
 665
 666                 gpio1: gpio1@ff220000 {
 667                         compatible = "rockchip,gpio-bank";
 668                         reg = <0x0 0xff220000 0x0 0x100>;
 669                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 670                         clocks = <&cru PCLK_GPIO1>;
 671
 672                         gpio-controller;
 673                         #gpio-cells = <2>;
 674
 675                         interrupt-controller;
 676                         #interrupt-cells = <2>;
 677                 };
 678
 679                 gpio2: gpio2@ff230000 {
 680                         compatible = "rockchip,gpio-bank";
 681                         reg = <0x0 0xff230000 0x0 0x100>;
 682                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 683                         clocks = <&cru PCLK_GPIO2>;
 684
 685                         gpio-controller;
 686                         #gpio-cells = <2>;
 687
 688                         interrupt-controller;
 689                         #interrupt-cells = <2>;
 690                 };
 691
 692                 gpio3: gpio3@ff240000 {
 693                         compatible = "rockchip,gpio-bank";
 694                         reg = <0x0 0xff240000 0x0 0x100>;
 695                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 696                         clocks = <&cru PCLK_GPIO3>;
 697
 698                         gpio-controller;
 699                         #gpio-cells = <2>;
 700
 701                         interrupt-controller;
 702                         #interrupt-cells = <2>;
 703                 };
 704
 705                 pcfg_pull_up: pcfg-pull-up {
 706                         bias-pull-up;
 707                 };
 708
 709                 pcfg_pull_down: pcfg-pull-down {
 710                         bias-pull-down;
 711                 };
 712
 713                 pcfg_pull_none: pcfg-pull-none {
 714                         bias-disable;
 715                 };
 716
 717                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 718                         bias-disable;
 719                         drive-strength = <2>;
 720                 };
 721
 722                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 723                         bias-pull-up;
 724                         drive-strength = <2>;
 725                 };
 726
 727                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 728                         bias-pull-up;
 729                         drive-strength = <4>;
 730                 };
 731
 732                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 733                         bias-disable;
 734                         drive-strength = <4>;
 735                 };
 736
 737                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 738                         bias-pull-down;
 739                         drive-strength = <4>;
 740                 };
 741
 742                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 743                         bias-disable;
 744                         drive-strength = <8>;
 745                 };
 746
 747                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 748                         bias-pull-up;
 749                         drive-strength = <8>;
 750                 };
 751
 752                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 753                         bias-disable;
 754                         drive-strength = <12>;
 755                 };
 756
 757                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 758                         bias-pull-up;
 759                         drive-strength = <12>;
 760                 };
 761
 762                 pcfg_output_high: pcfg-output-high {
 763                         output-high;
 764                 };
 765
 766                 pcfg_output_low: pcfg-output-low {
 767                         output-low;
 768                 };
 769
 770                 pcfg_input_high: pcfg-input-high {
 771                         bias-pull-up;
 772                         input-enable;
 773                 };
 774
 775                 pcfg_input: pcfg-input {
 776                         input-enable;
 777                 };
 778
 779                 i2c0 {
 780                         i2c0_xfer: i2c0-xfer {
 781                                 rockchip,pins =
 782                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 783                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 784                         };
 785                 };
 786
 787                 i2c1 {
 788                         i2c1_xfer: i2c1-xfer {
 789                                 rockchip,pins =
 790                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 791                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 792                         };
 793                 };
 794
 795                 i2c2 {
 796                         i2c2_xfer: i2c2-xfer {
 797                                 rockchip,pins =
 798                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 799                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 800                         };
 801                 };
 802
 803                 i2c3 {
 804                         i2c3_xfer: i2c3-xfer {
 805                                 rockchip,pins =
 806                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 807                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 808                         };
 809                         i2c3_gpio: i2c3-gpio {
 810                                 rockchip,pins =
 811                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 812                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 813                         };
 814                 };
 815
 816                 hdmi_i2c {
 817                         hdmii2c_xfer: hdmii2c-xfer {
 818                                 rockchip,pins =
 819                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 820                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 821                         };
 822                 };
 823
 824                 uart0 {
 825                         uart0_xfer: uart0-xfer {
 826                                 rockchip,pins =
 827                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 828                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 829                         };
 830
 831                         uart0_cts: uart0-cts {
 832                                 rockchip,pins =
 833                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 834                         };
 835
 836                         uart0_rts: uart0-rts {
 837                                 rockchip,pins =
 838                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 839                         };
 840
 841                         uart0_rts_gpio: uart0-rts-gpio {
 842                                 rockchip,pins =
 843                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 844                         };
 845                 };
 846
 847                 uart1 {
 848                         uart1_xfer: uart1-xfer {
 849                                 rockchip,pins =
 850                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 851                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 852                         };
 853
 854                         uart1_cts: uart1-cts {
 855                                 rockchip,pins =
 856                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 857                         };
 858
 859                         uart1_rts: uart1-rts {
 860                                 rockchip,pins =
 861                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 862                         };
 863
 864                         uart1_rts_gpio: uart1-rts-gpio {
 865                                 rockchip,pins =
 866                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 867                         };
 868                 };
 869
 870                 uart2-0 {
 871                         uart2m0_xfer: uart2m0-xfer {
 872                                 rockchip,pins =
 873                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 874                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 875                         };
 876                 };
 877
 878                 uart2-1 {
 879                         uart2m1_xfer: uart2m1-xfer {
 880                                 rockchip,pins =
 881                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 882                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 883                         };
 884                 };
 885
 886                 spi0-0 {
 887                         spi0m0_clk: spi0m0-clk {
 888                                 rockchip,pins =
 889                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 890                         };
 891
 892                         spi0m0_cs0: spi0m0-cs0 {
 893                                 rockchip,pins =
 894                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 895                         };
 896
 897                         spi0m0_tx: spi0m0-tx {
 898                                 rockchip,pins =
 899                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 900                         };
 901
 902                         spi0m0_rx: spi0m0-rx {
 903                                 rockchip,pins =
 904                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 905                         };
 906
 907                         spi0m0_cs1: spi0m0-cs1 {
 908                                 rockchip,pins =
 909                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
 910                         };
 911                 };
 912
 913                 spi0-1 {
 914                         spi0m1_clk: spi0m1-clk {
 915                                 rockchip,pins =
 916                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
 917                         };
 918
 919                         spi0m1_cs0: spi0m1-cs0 {
 920                                 rockchip,pins =
 921                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
 922                         };
 923
 924                         spi0m1_tx: spi0m1-tx {
 925                                 rockchip,pins =
 926                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
 927                         };
 928
 929                         spi0m1_rx: spi0m1-rx {
 930                                 rockchip,pins =
 931                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
 932                         };
 933
 934                         spi0m1_cs1: spi0m1-cs1 {
 935                                 rockchip,pins =
 936                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
 937                         };
 938                 };
 939
 940                 spi0-2 {
 941                         spi0m2_clk: spi0m2-clk {
 942                                 rockchip,pins =
 943                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
 944                         };
 945
 946                         spi0m2_cs0: spi0m2-cs0 {
 947                                 rockchip,pins =
 948                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
 949                         };
 950
 951                         spi0m2_tx: spi0m2-tx {
 952                                 rockchip,pins =
 953                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
 954                         };
 955
 956                         spi0m2_rx: spi0m2-rx {
 957                                 rockchip,pins =
 958                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
 959                         };
 960                 };
 961
 962                 i2s1 {
 963                         i2s1_mclk: i2s1-mclk {
 964                                 rockchip,pins =
 965                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
 966                         };
 967
 968                         i2s1_sclk: i2s1-sclk {
 969                                 rockchip,pins =
 970                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
 971                         };
 972
 973                         i2s1_lrckrx: i2s1-lrckrx {
 974                                 rockchip,pins =
 975                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
 976                         };
 977
 978                         i2s1_lrcktx: i2s1-lrcktx {
 979                                 rockchip,pins =
 980                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
 981                         };
 982
 983                         i2s1_sdi: i2s1-sdi {
 984                                 rockchip,pins =
 985                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
 986                         };
 987
 988                         i2s1_sdo: i2s1-sdo {
 989                                 rockchip,pins =
 990                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         i2s1_sdio1: i2s1-sdio1 {
 994                                 rockchip,pins =
 995                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
 996                         };
 997
 998                         i2s1_sdio2: i2s1-sdio2 {
 999                                 rockchip,pins =
1000                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002
1003                         i2s1_sdio3: i2s1-sdio3 {
1004                                 rockchip,pins =
1005                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1006                         };
1007
1008                         i2s1_sleep: i2s1-sleep {
1009                                 rockchip,pins =
1010                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1011                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1012                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1013                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1014                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1015                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1016                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1017                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1018                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1019                         };
1020                 };
1021
1022                 i2s2-0 {
1023                         i2s2m0_mclk: i2s2m0-mclk {
1024                                 rockchip,pins =
1025                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1026                         };
1027
1028                         i2s2m0_sclk: i2s2m0-sclk {
1029                                 rockchip,pins =
1030                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1031                         };
1032
1033                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1034                                 rockchip,pins =
1035                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1036                         };
1037
1038                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1039                                 rockchip,pins =
1040                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1041                         };
1042
1043                         i2s2m0_sdi: i2s2m0-sdi {
1044                                 rockchip,pins =
1045                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1046                         };
1047
1048                         i2s2m0_sdo: i2s2m0-sdo {
1049                                 rockchip,pins =
1050                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1051                         };
1052
1053                         i2s2m0_sleep: i2s2m0-sleep {
1054                                 rockchip,pins =
1055                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1056                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1057                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1058                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1059                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1060                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1061                         };
1062                 };
1063
1064                 i2s2-1 {
1065                         i2s2m1_mclk: i2s2m1-mclk {
1066                                 rockchip,pins =
1067                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069
1070                         i2s2m1_sclk: i2s2m1-sclk {
1071                                 rockchip,pins =
1072                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1073                         };
1074
1075                         i2s2m1_lrckrx: i2sm1-lrckrx {
1076                                 rockchip,pins =
1077                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1078                         };
1079
1080                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1081                                 rockchip,pins =
1082                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1083                         };
1084
1085                         i2s2m1_sdi: i2s2m1-sdi {
1086                                 rockchip,pins =
1087                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1088                         };
1089
1090                         i2s2m1_sdo: i2s2m1-sdo {
1091                                 rockchip,pins =
1092                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1093                         };
1094
1095                         i2s2m1_sleep: i2s2m1-sleep {
1096                                 rockchip,pins =
1097                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1098                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1099                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1100                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1101                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1102                         };
1103                 };
1104
1105                 spdif-0 {
1106                         spdifm0_tx: spdifm0-tx {
1107                                 rockchip,pins =
1108                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1109                         };
1110                 };
1111
1112                 spdif-1 {
1113                         spdifm1_tx: spdifm1-tx {
1114                                 rockchip,pins =
1115                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1116                         };
1117                 };
1118
1119                 spdif-2 {
1120                         spdifm2_tx: spdifm2-tx {
1121                                 rockchip,pins =
1122                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1123                         };
1124                 };
1125
1126                 sdmmc0-0 {
1127                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1128                                 rockchip,pins =
1129                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1130                         };
1131
1132                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1133                                 rockchip,pins =
1134                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1135                         };
1136                 };
1137
1138                 sdmmc0-1 {
1139                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1140                                 rockchip,pins =
1141                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1142                         };
1143
1144                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1145                                 rockchip,pins =
1146                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1147                         };
1148                 };
1149
1150                 sdmmc0 {
1151                         sdmmc0_clk: sdmmc0-clk {
1152                                 rockchip,pins =
1153                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1154                         };
1155
1156                         sdmmc0_cmd: sdmmc0-cmd {
1157                                 rockchip,pins =
1158                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1159                         };
1160
1161                         sdmmc0_dectn: sdmmc0-dectn {
1162                                 rockchip,pins =
1163                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1164                         };
1165
1166                         sdmmc0_wrprt: sdmmc0-wrprt {
1167                                 rockchip,pins =
1168                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1169                         };
1170
1171                         sdmmc0_bus1: sdmmc0-bus1 {
1172                                 rockchip,pins =
1173                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1174                         };
1175
1176                         sdmmc0_bus4: sdmmc0-bus4 {
1177                                 rockchip,pins =
1178                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1179                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1180                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1181                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1182                         };
1183
1184                         sdmmc0_gpio: sdmmc0-gpio {
1185                                 rockchip,pins =
1186                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1187                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1188                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1189                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1190                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1191                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1192                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1193                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1194                         };
1195                 };
1196
1197                 sdmmc0ext {
1198                         sdmmc0ext_clk: sdmmc0ext-clk {
1199                                 rockchip,pins =
1200                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1201                         };
1202
1203                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1204                                 rockchip,pins =
1205                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1206                         };
1207
1208                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1209                                 rockchip,pins =
1210                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1211                         };
1212
1213                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1214                                 rockchip,pins =
1215                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1216                         };
1217
1218                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1219                                 rockchip,pins =
1220                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1221                         };
1222
1223                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1224                                 rockchip,pins =
1225                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1226                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1227                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1228                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1229                         };
1230
1231                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1232                                 rockchip,pins =
1233                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1234                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1235                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1236                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1237                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1238                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1239                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1240                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1241                         };
1242                 };
1243
1244                 sdmmc1 {
1245                         sdmmc1_clk: sdmmc1-clk {
1246                                 rockchip,pins =
1247                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1248                         };
1249
1250                         sdmmc1_cmd: sdmmc1-cmd {
1251                                 rockchip,pins =
1252                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1253                         };
1254
1255                         sdmmc1_pwren: sdmmc1-pwren {
1256                                 rockchip,pins =
1257                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1258                         };
1259
1260                         sdmmc1_wrprt: sdmmc1-wrprt {
1261                                 rockchip,pins =
1262                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1263                         };
1264
1265                         sdmmc1_dectn: sdmmc1-dectn {
1266                                 rockchip,pins =
1267                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1268                         };
1269
1270                         sdmmc1_bus1: sdmmc1-bus1 {
1271                                 rockchip,pins =
1272                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1273                         };
1274
1275                         sdmmc1_bus4: sdmmc1-bus4 {
1276                                 rockchip,pins =
1277                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1278                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1279                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1280                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1281                         };
1282
1283                         sdmmc1_gpio: sdmmc1-gpio {
1284                                 rockchip,pins =
1285                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1286                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1287                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1288                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1289                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1290                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1291                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1292                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1293                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1294                         };
1295                 };
1296
1297                 emmc {
1298                         emmc_clk: emmc-clk {
1299                                 rockchip,pins =
1300                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1301                         };
1302
1303                         emmc_cmd: emmc-cmd {
1304                                 rockchip,pins =
1305                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1306                         };
1307
1308                         emmc_pwren: emmc-pwren {
1309                                 rockchip,pins =
1310                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1311                         };
1312
1313                         emmc_rstnout: emmc-rstnout {
1314                                 rockchip,pins =
1315                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1316                         };
1317
1318                         emmc_bus1: emmc-bus1 {
1319                                 rockchip,pins =
1320                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1321                         };
1322
1323                         emmc_bus4: emmc-bus4 {
1324                                 rockchip,pins =
1325                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1326                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1327                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1328                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1329                         };
1330
1331                         emmc_bus8: emmc-bus8 {
1332                                 rockchip,pins =
1333                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1334                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1335                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1336                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1337                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1338                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1339                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1340                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1341                         };
1342                 };
1343
1344                 pwm0 {
1345                         pwm0_pin: pwm0-pin {
1346                                 rockchip,pins =
1347                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1348                         };
1349                 };
1350
1351                 pwm1 {
1352                         pwm1_pin: pwm1-pin {
1353                                 rockchip,pins =
1354                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1355                         };
1356                 };
1357
1358                 pwm2 {
1359                         pwm2_pin: pwm2-pin {
1360                                 rockchip,pins =
1361                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1362                         };
1363                 };
1364
1365                 pwmir {
1366                         pwmir_pin: pwmir-pin {
1367                                 rockchip,pins =
1368                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370                 };
1371
1372                 gmac-0 {
1373                         rgmiim0_pins: rgmiim0-pins {
1374                                 rockchip,pins =
1375                                         /* mac_txclk */
1376                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1377                                         /* mac_rxclk */
1378                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1379                                         /* mac_mdio */
1380                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1381                                         /* mac_txen */
1382                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1383                                         /* mac_clk */
1384                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1385                                         /* mac_rxdv */
1386                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1387                                         /* mac_mdc */
1388                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1389                                         /* mac_rxd1 */
1390                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1391                                         /* mac_rxd0 */
1392                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1393                                         /* mac_txd1 */
1394                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1395                                         /* mac_txd0 */
1396                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1397                                         /* mac_rxd3 */
1398                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1399                                         /* mac_rxd2 */
1400                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1401                                         /* mac_txd3 */
1402                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1403                                         /* mac_txd2 */
1404                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1405                         };
1406
1407                         rmiim0_pins: rmiim0-pins {
1408                                 rockchip,pins =
1409                                         /* mac_mdio */
1410                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1411                                         /* mac_txen */
1412                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1413                                         /* mac_clk */
1414                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1415                                         /* mac_rxer */
1416                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1417                                         /* mac_rxdv */
1418                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1419                                         /* mac_mdc */
1420                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1421                                         /* mac_rxd1 */
1422                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1423                                         /* mac_rxd0 */
1424                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1425                                         /* mac_txd1 */
1426                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1427                                         /* mac_txd0 */
1428                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1429                         };
1430                 };
1431
1432                 gmac-1 {
1433                         rgmiim1_pins: rgmiim1-pins {
1434                                 rockchip,pins =
1435                                         /* mac_txclk */
1436                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1437                                         /* mac_rxclk */
1438                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1439                                         /* mac_mdio */
1440                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1441                                         /* mac_txen */
1442                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1443                                         /* mac_clk */
1444                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1445                                         /* mac_rxdv */
1446                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1447                                         /* mac_mdc */
1448                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1449                                         /* mac_rxd1 */
1450                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1451                                         /* mac_rxd0 */
1452                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1453                                         /* mac_txd1 */
1454                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1455                                         /* mac_txd0 */
1456                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1457                                         /* mac_rxd3 */
1458                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1459                                         /* mac_rxd2 */
1460                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1461                                         /* mac_txd3 */
1462                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1463                                         /* mac_txd2 */
1464                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1465
1466                                         /* mac_txclk */
1467                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1468                                         /* mac_txen */
1469                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1470                                         /* mac_clk */
1471                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1472                                         /* mac_txd1 */
1473                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1474                                         /* mac_txd0 */
1475                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1476                                         /* mac_txd3 */
1477                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1478                                         /* mac_txd2 */
1479                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481
1482                         rmiim1_pins: rmiim1-pins {
1483                                 rockchip,pins =
1484                                         /* mac_mdio */
1485                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1486                                         /* mac_txen */
1487                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1488                                         /* mac_clk */
1489                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1490                                         /* mac_rxer */
1491                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1492                                         /* mac_rxdv */
1493                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1494                                         /* mac_mdc */
1495                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1496                                         /* mac_rxd1 */
1497                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1498                                         /* mac_rxd0 */
1499                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1500                                         /* mac_txd1 */
1501                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1502                                         /* mac_txd0 */
1503                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1504
1505                                         /* mac_mdio */
1506                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1507                                         /* mac_txen */
1508                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1509                                         /* mac_clk */
1510                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1511                                         /* mac_mdc */
1512                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1513                                         /* mac_txd1 */
1514                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_txd0 */
1516                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 gmac2phy {
1521                         fephyled_speed100: fephyled-speed100 {
1522                                 rockchip,pins =
1523                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1524                         };
1525
1526                         fephyled_speed10: fephyled-speed10 {
1527                                 rockchip,pins =
1528                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1529                         };
1530
1531                         fephyled_duplex: fephyled-duplex {
1532                                 rockchip,pins =
1533                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1534                         };
1535
1536                         fephyled_rxm0: fephyled-rxm0 {
1537                                 rockchip,pins =
1538                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1539                         };
1540
1541                         fephyled_txm0: fephyled-txm0 {
1542                                 rockchip,pins =
1543                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1544                         };
1545
1546                         fephyled_linkm0: fephyled-linkm0 {
1547                                 rockchip,pins =
1548                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1549                         };
1550
1551                         fephyled_rxm1: fephyled-rxm1 {
1552                                 rockchip,pins =
1553                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1554                         };
1555
1556                         fephyled_txm1: fephyled-txm1 {
1557                                 rockchip,pins =
1558                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1559                         };
1560
1561                         fephyled_linkm1: fephyled-linkm1 {
1562                                 rockchip,pins =
1563                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1564                         };
1565                 };
1566
1567                 tsadc_pin {
1568                         tsadc_int: tsadc-int {
1569                                 rockchip,pins =
1570                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1571                         };
1572                         tsadc_gpio: tsadc-gpio {
1573                                 rockchip,pins =
1574                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1575                         };
1576                 };
1577
1578                 hdmi_pin {
1579                         hdmi_cec: hdmi-cec {
1580                                 rockchip,pins =
1581                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1582                         };
1583
1584                         hdmi_hpd: hdmi-hpd {
1585                                 rockchip,pins =
1586                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1587                         };
1588                 };
1589
1590                 cif-0 {
1591                         dvp_d2d9_m0:dvp-d2d9-m0 {
1592                                 rockchip,pins =
1593                                         /* cif_d0 */
1594                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1595                                         /* cif_d1 */
1596                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1597                                         /* cif_d2 */
1598                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1599                                         /* cif_d3 */
1600                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1601                                         /* cif_d4 */
1602                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1603                                         /* cif_d5m0 */
1604                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1605                                         /* cif_d6m0 */
1606                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1607                                         /* cif_d7m0 */
1608                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1609                                         /* cif_href */
1610                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1611                                         /* cif_vsync */
1612                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1613                                         /* cif_clkoutm0 */
1614                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1615                                         /* cif_clkin */
1616                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1617                         };
1618                 };
1619
1620                 cif-1 {
1621                         dvp_d2d9_m1:dvp-d2d9-m1 {
1622                                 rockchip,pins =
1623                                         /* cif_d0 */
1624                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1625                                         /* cif_d1 */
1626                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1627                                         /* cif_d2 */
1628                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1629                                         /* cif_d3 */
1630                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1631                                         /* cif_d4 */
1632                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1633                                         /* cif_d5m1 */
1634                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1635                                         /* cif_d6m1 */
1636                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1637                                         /* cif_d7m1 */
1638                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1639                                         /* cif_href */
1640                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1641                                         /* cif_vsync */
1642                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1643                                         /* cif_clkoutm1 */
1644                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1645                                         /* cif_clkin */
1646                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1647                         };
1648                 };
1649         };
1650 };