ARM64: dts: rk3328: add pdm node
[firefly-linux-kernel-4.4.55.git] / arch / arm64 / boot / dts / rockchip / rk3328.dtsi
1 /*
2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * This file is dual-licensed: you can use it either under the terms
5  * of the GPL or the X11 license, at your option. Note that this dual
6  * licensing only applies to this file, and not this project as a
7  * whole.
8  *
9  *  a) This library is free software; you can redistribute it and/or
10  *     modify it under the terms of the GNU General Public License as
11  *     published by the Free Software Foundation; either version 2 of the
12  *     License, or (at your option) any later version.
13  *
14  *     This library is distributed in the hope that it will be useful,
15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17  *     GNU General Public License for more details.
18  *
19  * Or, alternatively,
20  *
21  *  b) Permission is hereby granted, free of charge, to any person
22  *     obtaining a copy of this software and associated documentation
23  *     files (the "Software"), to deal in the Software without
24  *     restriction, including without limitation the rights to use,
25  *     copy, modify, merge, publish, distribute, sublicense, and/or
26  *     sell copies of the Software, and to permit persons to whom the
27  *     Software is furnished to do so, subject to the following
28  *     conditions:
29  *
30  *     The above copyright notice and this permission notice shall be
31  *     included in all copies or substantial portions of the Software.
32  *
33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40  *     OTHER DEALINGS IN THE SOFTWARE.
41  */
42
43 #include <dt-bindings/clock/rk3328-cru.h>
44 #include <dt-bindings/gpio/gpio.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/interrupt-controller/irq.h>
47 #include <dt-bindings/pinctrl/rockchip.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/power/rk3328-power.h>
50 #include <dt-bindings/thermal/thermal.h>
51
52 / {
53         compatible = "rockchip,rk3328";
54
55         interrupt-parent = <&gic>;
56         #address-cells = <2>;
57         #size-cells = <2>;
58
59         aliases {
60                 serial0 = &uart0;
61                 serial1 = &uart1;
62                 serial2 = &uart2;
63                 i2c0 = &i2c0;
64                 i2c1 = &i2c1;
65                 i2c2 = &i2c2;
66                 i2c3 = &i2c3;
67         };
68
69         cpus {
70                 #address-cells = <2>;
71                 #size-cells = <0>;
72
73                 cpu0: cpu@0 {
74                         device_type = "cpu";
75                         compatible = "arm,cortex-a53", "arm,armv8";
76                         reg = <0x0 0x0>;
77                         enable-method = "psci";
78                         clocks = <&cru ARMCLK>;
79                         #cooling-cells = <2>; /* min followed by max */
80                         dynamic-power-coefficient = <120>;
81                         operating-points-v2 = <&cpu0_opp_table>;
82                 };
83                 cpu1: cpu@1 {
84                         device_type = "cpu";
85                         compatible = "arm,cortex-a53", "arm,armv8";
86                         reg = <0x0 0x1>;
87                         enable-method = "psci";
88                         operating-points-v2 = <&cpu0_opp_table>;
89                 };
90                 cpu2: cpu@2 {
91                         device_type = "cpu";
92                         compatible = "arm,cortex-a53", "arm,armv8";
93                         reg = <0x0 0x2>;
94                         enable-method = "psci";
95                         operating-points-v2 = <&cpu0_opp_table>;
96                 };
97                 cpu3: cpu@3 {
98                         device_type = "cpu";
99                         compatible = "arm,cortex-a53", "arm,armv8";
100                         reg = <0x0 0x3>;
101                         enable-method = "psci";
102                         operating-points-v2 = <&cpu0_opp_table>;
103                 };
104         };
105
106         cpu0_opp_table: opp_table0 {
107                 compatible = "operating-points-v2";
108                 opp-shared;
109
110                 opp@408000000 {
111                         opp-hz = /bits/ 64 <408000000>;
112                         opp-microvolt = <950000>;
113                         clock-latency-ns = <40000>;
114                         opp-suspend;
115                 };
116                 opp@600000000 {
117                         opp-hz = /bits/ 64 <600000000>;
118                         opp-microvolt = <950000>;
119                         clock-latency-ns = <40000>;
120                 };
121                 opp@816000000 {
122                         opp-hz = /bits/ 64 <816000000>;
123                         opp-microvolt = <1000000>;
124                         clock-latency-ns = <40000>;
125                 };
126                 opp@1008000000 {
127                         opp-hz = /bits/ 64 <1008000000>;
128                         opp-microvolt = <1100000>;
129                         clock-latency-ns = <40000>;
130                 };
131                 opp@1200000000 {
132                         opp-hz = /bits/ 64 <1200000000>;
133                         opp-microvolt = <1225000>;
134                         clock-latency-ns = <40000>;
135                 };
136                 opp@1296000000 {
137                         opp-hz = /bits/ 64 <1296000000>;
138                         opp-microvolt = <1300000>;
139                         clock-latency-ns = <40000>;
140                 };
141         };
142
143         arm-pmu {
144                 compatible = "arm,cortex-a53-pmu";
145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
150         };
151
152         psci {
153                 compatible = "arm,psci-1.0";
154                 method = "smc";
155         };
156
157         timer {
158                 compatible = "arm,armv8-timer";
159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
163         };
164
165         xin24m: xin24m {
166                 compatible = "fixed-clock";
167                 #clock-cells = <0>;
168                 clock-frequency = <24000000>;
169                 clock-output-names = "xin24m";
170         };
171
172         i2s0: i2s@ff000000 {
173                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
174                 reg = <0x0 0xff000000 0x0 0x1000>;
175                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
176                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
177                 clock-names = "i2s_clk", "i2s_hclk";
178                 dmas = <&dmac 11>, <&dmac 12>;
179                 #dma-cells = <2>;
180                 dma-names = "tx", "rx";
181                 status = "disabled";
182         };
183
184         i2s1: i2s@ff010000 {
185                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
186                 reg = <0x0 0xff010000 0x0 0x1000>;
187                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
189                 clock-names = "i2s_clk", "i2s_hclk";
190                 dmas = <&dmac 14>, <&dmac 15>;
191                 #dma-cells = <2>;
192                 dma-names = "tx", "rx";
193                 status = "disabled";
194         };
195
196         i2s2: i2s@ff020000 {
197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
198                 reg = <0x0 0xff020000 0x0 0x1000>;
199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
201                 clock-names = "i2s_clk", "i2s_hclk";
202                 dmas = <&dmac 0>, <&dmac 1>;
203                 #dma-cells = <2>;
204                 dma-names = "tx", "rx";
205                 pinctrl-names = "default", "sleep";
206                 pinctrl-0 = <&i2s2m0_mclk
207                              &i2s2m0_sclk
208                              &i2s2m0_lrcktx
209                              &i2s2m0_lrckrx
210                              &i2s2m0_sdo
211                              &i2s2m0_sdi>;
212                 pinctrl-1 = <&i2s2m0_sleep>;
213                 status = "disabled";
214         };
215
216         spdif: spdif@ff030000 {
217                 compatible = "rockchip,rk3328-spdif";
218                 reg = <0x0 0xff030000 0x0 0x1000>;
219                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
220                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
221                 clock-names = "mclk", "hclk";
222                 dmas = <&dmac 10>;
223                 #dma-cells = <1>;
224                 dma-names = "tx";
225                 pinctrl-names = "default";
226                 pinctrl-0 = <&spdifm2_tx>;
227                 status = "disabled";
228         };
229
230         pdm: pdm@ff040000 {
231                 compatible = "rockchip,pdm";
232                 reg = <0x0 0xff040000 0x0 0x1000>;
233                 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
234                 clock-names = "pdm_clk", "pdm_hclk";
235                 dmas = <&dmac 16>;
236                 #dma-cells = <1>;
237                 dma-names = "rx";
238                 pinctrl-names = "default", "sleep";
239                 pinctrl-0 = <&pdmm0_clk
240                              &pdmm0_fsync
241                              &pdmm0_sdi0
242                              &pdmm0_sdi1
243                              &pdmm0_sdi2
244                              &pdmm0_sdi3>;
245                 pinctrl-1 = <&pdmm0_sleep>;
246                 status = "disabled";
247         };
248
249         grf: syscon@ff100000 {
250                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
251                 reg = <0x0 0xff100000 0x0 0x1000>;
252                 #address-cells = <1>;
253                 #size-cells = <1>;
254
255                 io_domains: io-domains {
256                         compatible = "rockchip,rk3328-io-voltage-domain";
257                         status = "disabled";
258                 };
259
260                 power: power-controller {
261                         compatible = "rockchip,rk3328-power-controller";
262                         #power-domain-cells = <1>;
263                         #address-cells = <1>;
264                         #size-cells = <0>;
265                         status = "disabled";
266
267                         pd_hevc@RK3328_PD_HEVC {
268                                 reg = <RK3328_PD_HEVC>;
269                         };
270                         pd_video@RK3328_PD_VIDEO {
271                                 reg = <RK3328_PD_VIDEO>;
272                         };
273                         pd_vpu@RK3328_PD_VPU {
274                                 reg = <RK3328_PD_VPU>;
275                         };
276                 };
277
278                 reboot-mode {
279                         compatible = "syscon-reboot-mode";
280                         offset = <0x5c8>;
281                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
282                         mode-charge = <BOOT_CHARGING>;
283                         mode-fastboot = <BOOT_FASTBOOT>;
284                         mode-loader = <BOOT_BL_DOWNLOAD>;
285                         mode-normal = <BOOT_NORMAL>;
286                         mode-recovery = <BOOT_RECOVERY>;
287                         mode-ums = <BOOT_UMS>;
288                 };
289         };
290
291         thermal-zones {
292                 soc_thermal: soc-thermal {
293                         polling-delay-passive = <20>; /* milliseconds */
294                         polling-delay = <1000>; /* milliseconds */
295                         sustainable-power = <1000>; /* milliwatts */
296
297                         thermal-sensors = <&tsadc 0>;
298
299                         trips {
300                                 threshold: trip-point@0 {
301                                         temperature = <70000>; /* millicelsius */
302                                         hysteresis = <2000>; /* millicelsius */
303                                         type = "passive";
304                                 };
305                                 target: trip-point@1 {
306                                         temperature = <85000>; /* millicelsius */
307                                         hysteresis = <2000>; /* millicelsius */
308                                         type = "passive";
309                                 };
310                                 soc_crit: soc-crit {
311                                         temperature = <95000>; /* millicelsius */
312                                         hysteresis = <2000>; /* millicelsius */
313                                         type = "critical";
314                                 };
315                         };
316
317                         cooling-maps {
318                                 map0 {
319                                         trip = <&target>;
320                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
321                                         contribution = <4096>;
322                                 };
323                         };
324                 };
325
326         };
327
328         tsadc: tsadc@ff250000 {
329                 compatible = "rockchip,rk3328-tsadc";
330                 reg = <0x0 0xff250000 0x0 0x100>;
331                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
332                 rockchip,grf = <&grf>;
333                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
334                 clock-names = "tsadc", "apb_pclk";
335                 assigned-clocks = <&cru SCLK_TSADC>;
336                 assigned-clock-rates = <50000>;
337                 resets = <&cru SRST_TSADC>;
338                 reset-names = "tsadc-apb";
339                 pinctrl-names = "init", "default", "sleep";
340                 pinctrl-0 = <&otp_gpio>;
341                 pinctrl-1 = <&otp_out>;
342                 pinctrl-2 = <&otp_gpio>;
343                 #thermal-sensor-cells = <1>;
344                 rockchip,hw-tshut-temp = <100000>;
345                 status = "disabled";
346         };
347
348         uart0: serial@ff110000 {
349                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
350                 reg = <0x0 0xff110000 0x0 0x100>;
351                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
352                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
353                 clock-names = "baudclk", "apb_pclk";
354                 reg-shift = <2>;
355                 reg-io-width = <4>;
356                 dmas = <&dmac 2>, <&dmac 3>;
357                 #dma-cells = <2>;
358                 pinctrl-names = "default";
359                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
360                 status = "disabled";
361         };
362
363         uart1: serial@ff120000 {
364                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
365                 reg = <0x0 0xff120000 0x0 0x100>;
366                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
367                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
368                 clock-names = "sclk_uart", "pclk_uart";
369                 reg-shift = <2>;
370                 reg-io-width = <4>;
371                 dmas = <&dmac 4>, <&dmac 5>;
372                 #dma-cells = <2>;
373                 pinctrl-names = "default";
374                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
375                 status = "disabled";
376         };
377
378         uart2: serial@ff130000 {
379                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
380                 reg = <0x0 0xff130000 0x0 0x100>;
381                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
382                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
383                 clock-names = "baudclk", "apb_pclk";
384                 reg-shift = <2>;
385                 reg-io-width = <4>;
386                 dmas = <&dmac 6>, <&dmac 7>;
387                 #dma-cells = <2>;
388                 pinctrl-names = "default";
389                 pinctrl-0 = <&uart2m1_xfer>;
390                 status = "disabled";
391         };
392
393         pmu: power-management@ff140000 {
394                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
395                 reg = <0x0 0xff140000 0x0 0x1000>;
396         };
397
398         i2c0: i2c@ff150000 {
399                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
400                 reg = <0x0 0xff150000 0x0 0x1000>;
401                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
402                 #address-cells = <1>;
403                 #size-cells = <0>;
404                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
405                 clock-names = "i2c", "pclk";
406                 pinctrl-names = "default";
407                 pinctrl-0 = <&i2c0_xfer>;
408                 status = "disabled";
409         };
410
411         i2c1: i2c@ff160000 {
412                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
413                 reg = <0x0 0xff160000 0x0 0x1000>;
414                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
415                 #address-cells = <1>;
416                 #size-cells = <0>;
417                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
418                 clock-names = "i2c", "pclk";
419                 pinctrl-names = "default";
420                 pinctrl-0 = <&i2c1_xfer>;
421                 status = "disabled";
422         };
423
424         i2c2: i2c@ff170000 {
425                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
426                 reg = <0x0 0xff170000 0x0 0x1000>;
427                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
428                 #address-cells = <1>;
429                 #size-cells = <0>;
430                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
431                 clock-names = "i2c", "pclk";
432                 pinctrl-names = "default";
433                 pinctrl-0 = <&i2c2_xfer>;
434                 status = "disabled";
435         };
436
437         i2c3: i2c@ff180000 {
438                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
439                 reg = <0x0 0xff180000 0x0 0x1000>;
440                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
441                 #address-cells = <1>;
442                 #size-cells = <0>;
443                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
444                 clock-names = "i2c", "pclk";
445                 pinctrl-names = "default";
446                 pinctrl-0 = <&i2c3_xfer>;
447                 status = "disabled";
448         };
449
450         spi0: spi@ff190000 {
451                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
452                 reg = <0x0 0xff190000 0x0 0x1000>;
453                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
454                 #address-cells = <1>;
455                 #size-cells = <0>;
456                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
457                 clock-names = "spiclk", "apb_pclk";
458                 dmas = <&dmac 8>, <&dmac 9>;
459                 #dma-cells = <2>;
460                 dma-names = "tx", "rx";
461                 pinctrl-names = "default";
462                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
463                 status = "disabled";
464         };
465
466         wdt: watchdog@ff1a0000 {
467                 compatible = "snps,dw-wdt";
468                 reg = <0x0 0xff1a0000 0x0 0x100>;
469                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
470                 status = "disabled";
471         };
472
473         pwm0: pwm@ff1b0000 {
474                 compatible = "rockchip,rk3328-pwm";
475                 reg = <0x0 0xff1b0000 0x0 0x10>;
476                 #pwm-cells = <3>;
477                 pinctrl-names = "default";
478                 pinctrl-0 = <&pwm0_pin>;
479                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
480                 clock-names = "pwm", "pclk";
481                 status = "disabled";
482         };
483
484         pwm1: pwm@ff1b0010 {
485                 compatible = "rockchip,rk3328-pwm";
486                 reg = <0x0 0xff1b0010 0x0 0x10>;
487                 #pwm-cells = <3>;
488                 pinctrl-names = "default";
489                 pinctrl-0 = <&pwm1_pin>;
490                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
491                 clock-names = "pwm", "pclk";
492                 status = "disabled";
493         };
494
495         pwm2: pwm@ff1b0020 {
496                 compatible = "rockchip,rk3328-pwm";
497                 reg = <0x0 0xff1b0020 0x0 0x10>;
498                 #pwm-cells = <3>;
499                 pinctrl-names = "default";
500                 pinctrl-0 = <&pwm2_pin>;
501                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
502                 clock-names = "pwm", "pclk";
503                 status = "disabled";
504         };
505
506         pwm3: pwm@ff1b0030 {
507                 compatible = "rockchip,rk3328-pwm";
508                 reg = <0x0 0xff1b0030 0x0 0x10>;
509                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
510                 #pwm-cells = <3>;
511                 pinctrl-names = "default";
512                 pinctrl-0 = <&pwmir_pin>;
513                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
514                 clock-names = "pwm", "pclk";
515                 status = "disabled";
516         };
517
518         amba {
519                 compatible = "simple-bus";
520                 #address-cells = <2>;
521                 #size-cells = <2>;
522                 ranges;
523
524                 dmac: dmac@ff1f0000 {
525                         compatible = "arm,pl330", "arm,primecell";
526                         reg = <0x0 0xff1f0000 0x0 0x4000>;
527                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
528                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
529                         clocks = <&cru ACLK_DMAC>;
530                         clock-names = "apb_pclk";
531                         #dma-cells = <1>;
532                 };
533         };
534
535         saradc: saradc@ff280000 {
536                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
537                 reg = <0x0 0xff280000 0x0 0x100>;
538                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
539                 #io-channel-cells = <1>;
540                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
541                 clock-names = "saradc", "apb_pclk";
542                 resets = <&cru SRST_SARADC_P>;
543                 reset-names = "saradc-apb";
544                 status = "disabled";
545         };
546
547         vop: vop@ff370000 {
548                 compatible = "rockchip,rk3328-vop";
549                 reg = <0x0 0xff370000 0x0 0x3efc>;
550                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
551                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
552                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
553                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
554                 reset-names = "axi", "ahb", "dclk";
555                 iommus = <&vop_mmu>;
556                 status = "disabled";
557
558                 vop_out: port {
559                         #address-cells = <1>;
560                         #size-cells = <0>;
561                 };
562         };
563
564         vop_mmu: iommu@ff373f00 {
565                 compatible = "rockchip,iommu";
566                 reg = <0x0 0xff373f00 0x0 0x100>;
567                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
568                 interrupt-names = "vop_mmu";
569                 #iommu-cells = <0>;
570                 status = "disabled";
571         };
572
573         display_subsystem: display-subsystem {
574                 compatible = "rockchip,display-subsystem";
575                 ports = <&vop_out>;
576                 status = "disabled";
577         };
578
579         cru: clock-controller@ff440000 {
580                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
581                 reg = <0x0 0xff440000 0x0 0x1000>;
582                 rockchip,grf = <&grf>;
583                 #clock-cells = <1>;
584                 #reset-cells = <1>;
585                 assigned-clocks =
586                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
587                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
588                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
589                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
590                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
591                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
592                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
593                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
594                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
595                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
596                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
597                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
598                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
599                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
600                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
601                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
602                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
603                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
604                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
605                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
606                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
607                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
608                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
609                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
610                 assigned-clock-parents =
611                         <&cru HDMIPHY>, <&cru PLL_APLL>,
612                         <&cru PLL_GPLL>, <&xin24m>,
613                         <&xin24m>, <&xin24m>;
614                 assigned-clock-rates =
615                         <0>, <61440000>,
616                         <0>, <24000000>,
617                         <24000000>, <24000000>,
618                         <15000000>, <15000000>,
619                         <100000000>, <100000000>,
620                         <100000000>, <100000000>,
621                         <50000000>, <100000000>,
622                         <100000000>, <100000000>,
623                         <50000000>, <50000000>,
624                         <50000000>, <50000000>,
625                         <24000000>, <600000000>,
626                         <491520000>, <1200000000>,
627                         <150000000>, <75000000>,
628                         <75000000>, <150000000>,
629                         <75000000>, <75000000>,
630                         <300000000>, <100000000>,
631                         <300000000>, <200000000>,
632                         <400000000>, <500000000>,
633                         <200000000>, <300000000>,
634                         <300000000>, <250000000>,
635                         <200000000>, <100000000>,
636                         <24000000>, <100000000>,
637                         <150000000>, <50000000>,
638                         <32768>, <32768>;
639         };
640
641         usb2phy_grf: syscon@ff450000 {
642                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
643                              "simple-mfd";
644                 reg = <0x0 0xff450000 0x0 0x10000>;
645                 #address-cells = <1>;
646                 #size-cells = <1>;
647
648                 u2phy: usb2-phy@100 {
649                         compatible = "rockchip,rk3328-usb2phy";
650                         reg = <0x100 0x10>;
651                         clocks = <&xin24m>;
652                         clock-names = "phyclk";
653                         #clock-cells = <0>;
654                         assigned-clocks = <&cru USB480M>;
655                         assigned-clock-parents = <&u2phy>;
656                         clock-output-names = "usb480m_phy";
657                         status = "disabled";
658
659                         u2phy_host: host-port {
660                                 #phy-cells = <0>;
661                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
662                                 interrupt-names = "linestate";
663                                 status = "disabled";
664                         };
665
666                         u2phy_otg: otg-port {
667                                 #phy-cells = <0>;
668                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
669                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
670                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
671                                 interrupt-names = "otg-bvalid", "otg-id",
672                                                   "linestate";
673                                 status = "disabled";
674                         };
675                 };
676         };
677
678         usb3phy_grf: syscon@ff460000 {
679                 compatible = "rockchip,usb3phy-grf", "syscon";
680                 reg = <0x0 0xff460000 0x0 0x1000>;
681         };
682
683         u3phy: usb3-phy@ff470000 {
684                 compatible = "rockchip,rk3328-u3phy";
685                 reg = <0x0 0xff470000 0x0 0x0>;
686                 rockchip,u3phygrf = <&usb3phy_grf>;
687                 rockchip,grf = <&grf>;
688                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
689                 interrupt-names = "linestate";
690                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
691                 clock-names = "u3phy-otg", "u3phy-pipe";
692                 resets = <&cru SRST_USB3PHY_U2>,
693                          <&cru SRST_USB3PHY_U3>,
694                          <&cru SRST_USB3PHY_PIPE>,
695                          <&cru SRST_USB3OTG_UTMI>,
696                          <&cru SRST_USB3PHY_OTG_P>,
697                          <&cru SRST_USB3PHY_PIPE_P>;
698                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
699                               "u3phy-pipe-mac", "u3phy-utmi-mac",
700                               "u3phy-utmi-apb", "u3phy-pipe-apb";
701                 #address-cells = <2>;
702                 #size-cells = <2>;
703                 ranges;
704                 status = "disabled";
705
706                 u3phy_utmi: utmi@ff470000 {
707                         reg = <0x0 0xff470000 0x0 0x8000>;
708                         #phy-cells = <0>;
709                         status = "disabled";
710                 };
711
712                 u3phy_pipe: pipe@ff478000 {
713                         reg = <0x0 0xff478000 0x0 0x8000>;
714                         #phy-cells = <0>;
715                         status = "disabled";
716                 };
717         };
718
719         sdmmc: rksdmmc@ff500000 {
720                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
721                 reg = <0x0 0xff500000 0x0 0x4000>;
722                 clock-freq-min-max = <400000 150000000>;
723                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
724                 clock-names = "biu", "ciu";
725                 fifo-depth = <0x100>;
726                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
727                 status = "disabled";
728         };
729
730         sdio: dwmmc@ff510000 {
731                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
732                 reg = <0x0 0xff510000 0x0 0x4000>;
733                 clock-freq-min-max = <400000 150000000>;
734                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
735                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
736                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
737                 fifo-depth = <0x100>;
738                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
739                 status = "disabled";
740         };
741
742         emmc: rksdmmc@ff520000 {
743                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
744                 reg = <0x0 0xff520000 0x0 0x4000>;
745                 clock-freq-min-max = <400000 150000000>;
746                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
747                 clock-names = "biu", "ciu";
748                 fifo-depth = <0x100>;
749                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
750                 status = "disabled";
751         };
752
753         gmac2io: eth@ff540000 {
754                 compatible = "rockchip,rk3328-gmac";
755                 reg = <0x0 0xff540000 0x0 0x10000>;
756                 rockchip,grf = <&grf>;
757                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
758                 interrupt-names = "macirq";
759                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
760                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
761                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
762                          <&cru PCLK_MAC2IO>;
763                 clock-names = "stmmaceth", "mac_clk_rx",
764                               "mac_clk_tx", "clk_mac_ref",
765                               "clk_mac_refout", "aclk_mac",
766                               "pclk_mac";
767                 resets = <&cru SRST_GMAC2IO_A>;
768                 reset-names = "stmmaceth";
769                 status = "disabled";
770         };
771
772         usb20_otg: usb@ff580000 {
773                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
774                              "snps,dwc2";
775                 reg = <0x0 0xff580000 0x0 0x40000>;
776                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
777                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
778                 clock-names = "otg", "otg_pmu";
779                 dr_mode = "otg";
780                 g-np-tx-fifo-size = <16>;
781                 g-rx-fifo-size = <275>;
782                 g-tx-fifo-size = <256 128 128 64 64 32>;
783                 g-use-dma;
784                 phys = <&u2phy_otg>;
785                 phy-names = "usb2-phy";
786                 status = "disabled";
787         };
788
789         usb_host0_ehci: usb@ff5c0000 {
790                 compatible = "generic-ehci";
791                 reg = <0x0 0xff5c0000 0x0 0x10000>;
792                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
793                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
794                          <&u2phy>;
795                 clock-names = "usbhost", "arbiter", "utmi";
796                 phys = <&u2phy_host>;
797                 phy-names = "usb";
798                 status = "disabled";
799         };
800
801         usb_host0_ohci: usb@ff5d0000 {
802                 compatible = "generic-ohci";
803                 reg = <0x0 0xff5d0000 0x0 0x10000>;
804                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
805                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
806                          <&u2phy>;
807                 clock-names = "usbhost", "arbiter", "utmi";
808                 phys = <&u2phy_host>;
809                 phy-names = "usb";
810                 status = "disabled";
811         };
812
813         sdmmc_ext: rksdmmc@ff5f0000 {
814                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
815                 reg = <0x0 0xff5f0000 0x0 0x4000>;
816                 clock-freq-min-max = <400000 150000000>;
817                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
818                 clock-names = "biu", "ciu";
819                 fifo-depth = <0x100>;
820                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
821                 status = "disabled";
822         };
823
824         usbdrd3: usb@ff600000 {
825                 compatible = "rockchip,rk3328-dwc3";
826                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
827                          <&cru ACLK_USB3OTG>;
828                 clock-names = "ref_clk", "suspend_clk",
829                               "bus_clk";
830                 #address-cells = <2>;
831                 #size-cells = <2>;
832                 ranges;
833                 status = "disabled";
834
835                 usbdrd_dwc3: dwc3@ff600000 {
836                         compatible = "snps,dwc3";
837                         reg = <0x0 0xff600000 0x0 0x100000>;
838                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
839                         dr_mode = "host";
840                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
841                         phy-names = "usb2-phy", "usb3-phy";
842                         phy_type = "utmi_wide";
843                         snps,dis_enblslpm_quirk;
844                         snps,dis-u2-freeclk-exists-quirk;
845                         snps,dis_u2_susphy_quirk;
846                         snps,dis-u3-autosuspend-quirk;
847                         snps,dis_u3_susphy_quirk;
848                         snps,dis-del-phy-power-chg-quirk;
849                         status = "disabled";
850                 };
851         };
852
853         gic: interrupt-controller@ff811000 {
854                 compatible = "arm,gic-400";
855                 #interrupt-cells = <3>;
856                 #address-cells = <0>;
857                 interrupt-controller;
858                 reg = <0x0 0xff811000 0 0x1000>,
859                       <0x0 0xff812000 0 0x2000>,
860                       <0x0 0xff814000 0 0x2000>,
861                       <0x0 0xff816000 0 0x2000>;
862                 interrupts = <GIC_PPI 9
863                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
864         };
865
866         pinctrl: pinctrl {
867                 compatible = "rockchip,rk3328-pinctrl";
868                 rockchip,grf = <&grf>;
869                 #address-cells = <2>;
870                 #size-cells = <2>;
871                 ranges;
872
873                 gpio0: gpio0@ff210000 {
874                         compatible = "rockchip,gpio-bank";
875                         reg = <0x0 0xff210000 0x0 0x100>;
876                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
877                         clocks = <&cru PCLK_GPIO0>;
878
879                         gpio-controller;
880                         #gpio-cells = <2>;
881
882                         interrupt-controller;
883                         #interrupt-cells = <2>;
884                 };
885
886                 gpio1: gpio1@ff220000 {
887                         compatible = "rockchip,gpio-bank";
888                         reg = <0x0 0xff220000 0x0 0x100>;
889                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
890                         clocks = <&cru PCLK_GPIO1>;
891
892                         gpio-controller;
893                         #gpio-cells = <2>;
894
895                         interrupt-controller;
896                         #interrupt-cells = <2>;
897                 };
898
899                 gpio2: gpio2@ff230000 {
900                         compatible = "rockchip,gpio-bank";
901                         reg = <0x0 0xff230000 0x0 0x100>;
902                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
903                         clocks = <&cru PCLK_GPIO2>;
904
905                         gpio-controller;
906                         #gpio-cells = <2>;
907
908                         interrupt-controller;
909                         #interrupt-cells = <2>;
910                 };
911
912                 gpio3: gpio3@ff240000 {
913                         compatible = "rockchip,gpio-bank";
914                         reg = <0x0 0xff240000 0x0 0x100>;
915                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
916                         clocks = <&cru PCLK_GPIO3>;
917
918                         gpio-controller;
919                         #gpio-cells = <2>;
920
921                         interrupt-controller;
922                         #interrupt-cells = <2>;
923                 };
924
925                 pcfg_pull_up: pcfg-pull-up {
926                         bias-pull-up;
927                 };
928
929                 pcfg_pull_down: pcfg-pull-down {
930                         bias-pull-down;
931                 };
932
933                 pcfg_pull_none: pcfg-pull-none {
934                         bias-disable;
935                 };
936
937                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
938                         bias-disable;
939                         drive-strength = <2>;
940                 };
941
942                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
943                         bias-pull-up;
944                         drive-strength = <2>;
945                 };
946
947                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
948                         bias-pull-up;
949                         drive-strength = <4>;
950                 };
951
952                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
953                         bias-disable;
954                         drive-strength = <4>;
955                 };
956
957                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
958                         bias-pull-down;
959                         drive-strength = <4>;
960                 };
961
962                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
963                         bias-disable;
964                         drive-strength = <8>;
965                 };
966
967                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
968                         bias-pull-up;
969                         drive-strength = <8>;
970                 };
971
972                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
973                         bias-disable;
974                         drive-strength = <12>;
975                 };
976
977                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
978                         bias-pull-up;
979                         drive-strength = <12>;
980                 };
981
982                 pcfg_output_high: pcfg-output-high {
983                         output-high;
984                 };
985
986                 pcfg_output_low: pcfg-output-low {
987                         output-low;
988                 };
989
990                 pcfg_input_high: pcfg-input-high {
991                         bias-pull-up;
992                         input-enable;
993                 };
994
995                 pcfg_input: pcfg-input {
996                         input-enable;
997                 };
998
999                 i2c0 {
1000                         i2c0_xfer: i2c0-xfer {
1001                                 rockchip,pins =
1002                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1003                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1004                         };
1005                 };
1006
1007                 i2c1 {
1008                         i2c1_xfer: i2c1-xfer {
1009                                 rockchip,pins =
1010                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1011                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
1012                         };
1013                 };
1014
1015                 i2c2 {
1016                         i2c2_xfer: i2c2-xfer {
1017                                 rockchip,pins =
1018                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1019                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1020                         };
1021                 };
1022
1023                 i2c3 {
1024                         i2c3_xfer: i2c3-xfer {
1025                                 rockchip,pins =
1026                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1027                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1028                         };
1029                         i2c3_gpio: i2c3-gpio {
1030                                 rockchip,pins =
1031                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1032                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1033                         };
1034                 };
1035
1036                 hdmi_i2c {
1037                         hdmii2c_xfer: hdmii2c-xfer {
1038                                 rockchip,pins =
1039                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1040                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1041                         };
1042                 };
1043
1044                 tsadc {
1045                         otp_gpio: otp-gpio {
1046                                 rockchip,pins =
1047                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1048                         };
1049
1050                         otp_out: otp-out {
1051                                 rockchip,pins =
1052                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1053                         };
1054                 };
1055
1056                 uart0 {
1057                         uart0_xfer: uart0-xfer {
1058                                 rockchip,pins =
1059                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1060                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1061                         };
1062
1063                         uart0_cts: uart0-cts {
1064                                 rockchip,pins =
1065                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1066                         };
1067
1068                         uart0_rts: uart0-rts {
1069                                 rockchip,pins =
1070                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1071                         };
1072
1073                         uart0_rts_gpio: uart0-rts-gpio {
1074                                 rockchip,pins =
1075                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 uart1 {
1080                         uart1_xfer: uart1-xfer {
1081                                 rockchip,pins =
1082                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1083                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1084                         };
1085
1086                         uart1_cts: uart1-cts {
1087                                 rockchip,pins =
1088                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1089                         };
1090
1091                         uart1_rts: uart1-rts {
1092                                 rockchip,pins =
1093                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1094                         };
1095
1096                         uart1_rts_gpio: uart1-rts-gpio {
1097                                 rockchip,pins =
1098                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1099                         };
1100                 };
1101
1102                 uart2-0 {
1103                         uart2m0_xfer: uart2m0-xfer {
1104                                 rockchip,pins =
1105                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1106                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1107                         };
1108                 };
1109
1110                 uart2-1 {
1111                         uart2m1_xfer: uart2m1-xfer {
1112                                 rockchip,pins =
1113                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1114                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1115                         };
1116                 };
1117
1118                 spi0-0 {
1119                         spi0m0_clk: spi0m0-clk {
1120                                 rockchip,pins =
1121                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1122                         };
1123
1124                         spi0m0_cs0: spi0m0-cs0 {
1125                                 rockchip,pins =
1126                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1127                         };
1128
1129                         spi0m0_tx: spi0m0-tx {
1130                                 rockchip,pins =
1131                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1132                         };
1133
1134                         spi0m0_rx: spi0m0-rx {
1135                                 rockchip,pins =
1136                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1137                         };
1138
1139                         spi0m0_cs1: spi0m0-cs1 {
1140                                 rockchip,pins =
1141                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1142                         };
1143                 };
1144
1145                 spi0-1 {
1146                         spi0m1_clk: spi0m1-clk {
1147                                 rockchip,pins =
1148                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1149                         };
1150
1151                         spi0m1_cs0: spi0m1-cs0 {
1152                                 rockchip,pins =
1153                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1154                         };
1155
1156                         spi0m1_tx: spi0m1-tx {
1157                                 rockchip,pins =
1158                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1159                         };
1160
1161                         spi0m1_rx: spi0m1-rx {
1162                                 rockchip,pins =
1163                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1164                         };
1165
1166                         spi0m1_cs1: spi0m1-cs1 {
1167                                 rockchip,pins =
1168                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1169                         };
1170                 };
1171
1172                 spi0-2 {
1173                         spi0m2_clk: spi0m2-clk {
1174                                 rockchip,pins =
1175                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1176                         };
1177
1178                         spi0m2_cs0: spi0m2-cs0 {
1179                                 rockchip,pins =
1180                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1181                         };
1182
1183                         spi0m2_tx: spi0m2-tx {
1184                                 rockchip,pins =
1185                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1186                         };
1187
1188                         spi0m2_rx: spi0m2-rx {
1189                                 rockchip,pins =
1190                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1191                         };
1192                 };
1193
1194                 pdm-0 {
1195                         pdmm0_clk: pdmm0-clk {
1196                                 rockchip,pins =
1197                                         <2 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
1198                         };
1199
1200                         pdmm0_fsync: pdmm0-fsync {
1201                                 rockchip,pins =
1202                                         <2 RK_PC7 RK_FUNC_2 &pcfg_pull_none>;
1203                         };
1204
1205                         pdmm0_sdi0: pdmm0-sdi0 {
1206                                 rockchip,pins =
1207                                         <2 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
1208                         };
1209
1210                         pdmm0_sdi1: pdmm0-sdi1 {
1211                                 rockchip,pins =
1212                                         <2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1213                         };
1214
1215                         pdmm0_sdi2: pdmm0-sdi2 {
1216                                 rockchip,pins =
1217                                         <2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>;
1218                         };
1219
1220                         pdmm0_sdi3: pdmm0-sdi3 {
1221                                 rockchip,pins =
1222                                         <2 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1223                         };
1224
1225                         pdmm0_sleep: pdmm0-sleep {
1226                                 rockchip,pins =
1227                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1228                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1229                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1230                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1231                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1232                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1233                         };
1234                 };
1235
1236                 i2s1 {
1237                         i2s1_mclk: i2s1-mclk {
1238                                 rockchip,pins =
1239                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1240                         };
1241
1242                         i2s1_sclk: i2s1-sclk {
1243                                 rockchip,pins =
1244                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1245                         };
1246
1247                         i2s1_lrckrx: i2s1-lrckrx {
1248                                 rockchip,pins =
1249                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1250                         };
1251
1252                         i2s1_lrcktx: i2s1-lrcktx {
1253                                 rockchip,pins =
1254                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1255                         };
1256
1257                         i2s1_sdi: i2s1-sdi {
1258                                 rockchip,pins =
1259                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1260                         };
1261
1262                         i2s1_sdo: i2s1-sdo {
1263                                 rockchip,pins =
1264                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1265                         };
1266
1267                         i2s1_sdio1: i2s1-sdio1 {
1268                                 rockchip,pins =
1269                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1270                         };
1271
1272                         i2s1_sdio2: i2s1-sdio2 {
1273                                 rockchip,pins =
1274                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1275                         };
1276
1277                         i2s1_sdio3: i2s1-sdio3 {
1278                                 rockchip,pins =
1279                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1280                         };
1281
1282                         i2s1_sleep: i2s1-sleep {
1283                                 rockchip,pins =
1284                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1285                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1286                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1287                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1288                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1289                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1290                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1291                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1292                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1293                         };
1294                 };
1295
1296                 i2s2-0 {
1297                         i2s2m0_mclk: i2s2m0-mclk {
1298                                 rockchip,pins =
1299                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1300                         };
1301
1302                         i2s2m0_sclk: i2s2m0-sclk {
1303                                 rockchip,pins =
1304                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1305                         };
1306
1307                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1308                                 rockchip,pins =
1309                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1310                         };
1311
1312                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1313                                 rockchip,pins =
1314                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1315                         };
1316
1317                         i2s2m0_sdi: i2s2m0-sdi {
1318                                 rockchip,pins =
1319                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1320                         };
1321
1322                         i2s2m0_sdo: i2s2m0-sdo {
1323                                 rockchip,pins =
1324                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1325                         };
1326
1327                         i2s2m0_sleep: i2s2m0-sleep {
1328                                 rockchip,pins =
1329                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1330                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1331                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1332                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1333                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1334                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1335                         };
1336                 };
1337
1338                 i2s2-1 {
1339                         i2s2m1_mclk: i2s2m1-mclk {
1340                                 rockchip,pins =
1341                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1342                         };
1343
1344                         i2s2m1_sclk: i2s2m1-sclk {
1345                                 rockchip,pins =
1346                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1347                         };
1348
1349                         i2s2m1_lrckrx: i2sm1-lrckrx {
1350                                 rockchip,pins =
1351                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1352                         };
1353
1354                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1355                                 rockchip,pins =
1356                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1357                         };
1358
1359                         i2s2m1_sdi: i2s2m1-sdi {
1360                                 rockchip,pins =
1361                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1362                         };
1363
1364                         i2s2m1_sdo: i2s2m1-sdo {
1365                                 rockchip,pins =
1366                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1367                         };
1368
1369                         i2s2m1_sleep: i2s2m1-sleep {
1370                                 rockchip,pins =
1371                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1372                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1373                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1374                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1375                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1376                         };
1377                 };
1378
1379                 spdif-0 {
1380                         spdifm0_tx: spdifm0-tx {
1381                                 rockchip,pins =
1382                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1383                         };
1384                 };
1385
1386                 spdif-1 {
1387                         spdifm1_tx: spdifm1-tx {
1388                                 rockchip,pins =
1389                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1390                         };
1391                 };
1392
1393                 spdif-2 {
1394                         spdifm2_tx: spdifm2-tx {
1395                                 rockchip,pins =
1396                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1397                         };
1398                 };
1399
1400                 sdmmc0-0 {
1401                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1402                                 rockchip,pins =
1403                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1404                         };
1405
1406                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1407                                 rockchip,pins =
1408                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1409                         };
1410                 };
1411
1412                 sdmmc0-1 {
1413                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1414                                 rockchip,pins =
1415                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1416                         };
1417
1418                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1419                                 rockchip,pins =
1420                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1421                         };
1422                 };
1423
1424                 sdmmc0 {
1425                         sdmmc0_clk: sdmmc0-clk {
1426                                 rockchip,pins =
1427                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1428                         };
1429
1430                         sdmmc0_cmd: sdmmc0-cmd {
1431                                 rockchip,pins =
1432                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1433                         };
1434
1435                         sdmmc0_dectn: sdmmc0-dectn {
1436                                 rockchip,pins =
1437                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1438                         };
1439
1440                         sdmmc0_wrprt: sdmmc0-wrprt {
1441                                 rockchip,pins =
1442                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1443                         };
1444
1445                         sdmmc0_bus1: sdmmc0-bus1 {
1446                                 rockchip,pins =
1447                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1448                         };
1449
1450                         sdmmc0_bus4: sdmmc0-bus4 {
1451                                 rockchip,pins =
1452                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1453                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1454                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1455                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1456                         };
1457
1458                         sdmmc0_gpio: sdmmc0-gpio {
1459                                 rockchip,pins =
1460                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1461                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1462                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1463                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1464                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1465                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1466                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1467                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1468                         };
1469                 };
1470
1471                 sdmmc0ext {
1472                         sdmmc0ext_clk: sdmmc0ext-clk {
1473                                 rockchip,pins =
1474                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1475                         };
1476
1477                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1478                                 rockchip,pins =
1479                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1480                         };
1481
1482                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1483                                 rockchip,pins =
1484                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1485                         };
1486
1487                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1488                                 rockchip,pins =
1489                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1490                         };
1491
1492                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1493                                 rockchip,pins =
1494                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1495                         };
1496
1497                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1498                                 rockchip,pins =
1499                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1500                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1501                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1502                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1503                         };
1504
1505                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1506                                 rockchip,pins =
1507                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1508                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1509                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1510                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1511                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1512                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1513                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1514                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1515                         };
1516                 };
1517
1518                 sdmmc1 {
1519                         sdmmc1_clk: sdmmc1-clk {
1520                                 rockchip,pins =
1521                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1522                         };
1523
1524                         sdmmc1_cmd: sdmmc1-cmd {
1525                                 rockchip,pins =
1526                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1527                         };
1528
1529                         sdmmc1_pwren: sdmmc1-pwren {
1530                                 rockchip,pins =
1531                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1532                         };
1533
1534                         sdmmc1_wrprt: sdmmc1-wrprt {
1535                                 rockchip,pins =
1536                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1537                         };
1538
1539                         sdmmc1_dectn: sdmmc1-dectn {
1540                                 rockchip,pins =
1541                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1542                         };
1543
1544                         sdmmc1_bus1: sdmmc1-bus1 {
1545                                 rockchip,pins =
1546                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1547                         };
1548
1549                         sdmmc1_bus4: sdmmc1-bus4 {
1550                                 rockchip,pins =
1551                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_up_8ma>,
1552                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>,
1553                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1554                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1555                         };
1556
1557                         sdmmc1_gpio: sdmmc1-gpio {
1558                                 rockchip,pins =
1559                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1560                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1561                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1562                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1563                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1564                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1565                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1566                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1567                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1568                         };
1569                 };
1570
1571                 emmc {
1572                         emmc_clk: emmc-clk {
1573                                 rockchip,pins =
1574                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1575                         };
1576
1577                         emmc_cmd: emmc-cmd {
1578                                 rockchip,pins =
1579                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1580                         };
1581
1582                         emmc_pwren: emmc-pwren {
1583                                 rockchip,pins =
1584                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1585                         };
1586
1587                         emmc_rstnout: emmc-rstnout {
1588                                 rockchip,pins =
1589                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1590                         };
1591
1592                         emmc_bus1: emmc-bus1 {
1593                                 rockchip,pins =
1594                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1595                         };
1596
1597                         emmc_bus4: emmc-bus4 {
1598                                 rockchip,pins =
1599                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1600                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1601                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1602                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1603                         };
1604
1605                         emmc_bus8: emmc-bus8 {
1606                                 rockchip,pins =
1607                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1608                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1609                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1610                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1611                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1612                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1613                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1614                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1615                         };
1616                 };
1617
1618                 pwm0 {
1619                         pwm0_pin: pwm0-pin {
1620                                 rockchip,pins =
1621                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1622                         };
1623                 };
1624
1625                 pwm1 {
1626                         pwm1_pin: pwm1-pin {
1627                                 rockchip,pins =
1628                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1629                         };
1630                 };
1631
1632                 pwm2 {
1633                         pwm2_pin: pwm2-pin {
1634                                 rockchip,pins =
1635                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1636                         };
1637                 };
1638
1639                 pwmir {
1640                         pwmir_pin: pwmir-pin {
1641                                 rockchip,pins =
1642                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1643                         };
1644                 };
1645
1646                 gmac-1 {
1647                         rgmiim1_pins: rgmiim1-pins {
1648                                 rockchip,pins =
1649                                         /* mac_txclk */
1650                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1651                                         /* mac_rxclk */
1652                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1653                                         /* mac_mdio */
1654                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1655                                         /* mac_txen */
1656                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1657                                         /* mac_clk */
1658                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1659                                         /* mac_rxdv */
1660                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1661                                         /* mac_mdc */
1662                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1663                                         /* mac_rxd1 */
1664                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1665                                         /* mac_rxd0 */
1666                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1667                                         /* mac_txd1 */
1668                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1669                                         /* mac_txd0 */
1670                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1671                                         /* mac_rxd3 */
1672                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1673                                         /* mac_rxd2 */
1674                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1675                                         /* mac_txd3 */
1676                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1677                                         /* mac_txd2 */
1678                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1679
1680                                         /* mac_txclk */
1681                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1682                                         /* mac_txen */
1683                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1684                                         /* mac_clk */
1685                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1686                                         /* mac_txd1 */
1687                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1688                                         /* mac_txd0 */
1689                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1690                                         /* mac_txd3 */
1691                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1692                                         /* mac_txd2 */
1693                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1694                         };
1695
1696                         rmiim1_pins: rmiim1-pins {
1697                                 rockchip,pins =
1698                                         /* mac_mdio */
1699                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1700                                         /* mac_txen */
1701                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1702                                         /* mac_clk */
1703                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1704                                         /* mac_rxer */
1705                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1706                                         /* mac_rxdv */
1707                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1708                                         /* mac_mdc */
1709                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1710                                         /* mac_rxd1 */
1711                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1712                                         /* mac_rxd0 */
1713                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1714                                         /* mac_txd1 */
1715                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1716                                         /* mac_txd0 */
1717                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1718
1719                                         /* mac_mdio */
1720                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1721                                         /* mac_txen */
1722                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1723                                         /* mac_clk */
1724                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1725                                         /* mac_mdc */
1726                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1727                                         /* mac_txd1 */
1728                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1729                                         /* mac_txd0 */
1730                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1731                         };
1732                 };
1733
1734                 gmac2phy {
1735                         fephyled_speed100: fephyled-speed100 {
1736                                 rockchip,pins =
1737                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1738                         };
1739
1740                         fephyled_speed10: fephyled-speed10 {
1741                                 rockchip,pins =
1742                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1743                         };
1744
1745                         fephyled_duplex: fephyled-duplex {
1746                                 rockchip,pins =
1747                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1748                         };
1749
1750                         fephyled_rxm0: fephyled-rxm0 {
1751                                 rockchip,pins =
1752                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1753                         };
1754
1755                         fephyled_txm0: fephyled-txm0 {
1756                                 rockchip,pins =
1757                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1758                         };
1759
1760                         fephyled_linkm0: fephyled-linkm0 {
1761                                 rockchip,pins =
1762                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1763                         };
1764
1765                         fephyled_rxm1: fephyled-rxm1 {
1766                                 rockchip,pins =
1767                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1768                         };
1769
1770                         fephyled_txm1: fephyled-txm1 {
1771                                 rockchip,pins =
1772                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1773                         };
1774
1775                         fephyled_linkm1: fephyled-linkm1 {
1776                                 rockchip,pins =
1777                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1778                         };
1779                 };
1780
1781                 tsadc_pin {
1782                         tsadc_int: tsadc-int {
1783                                 rockchip,pins =
1784                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1785                         };
1786                         tsadc_gpio: tsadc-gpio {
1787                                 rockchip,pins =
1788                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1789                         };
1790                 };
1791
1792                 hdmi_pin {
1793                         hdmi_cec: hdmi-cec {
1794                                 rockchip,pins =
1795                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1796                         };
1797
1798                         hdmi_hpd: hdmi-hpd {
1799                                 rockchip,pins =
1800                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1801                         };
1802                 };
1803
1804                 cif-0 {
1805                         dvp_d2d9_m0:dvp-d2d9-m0 {
1806                                 rockchip,pins =
1807                                         /* cif_d0 */
1808                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1809                                         /* cif_d1 */
1810                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1811                                         /* cif_d2 */
1812                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1813                                         /* cif_d3 */
1814                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1815                                         /* cif_d4 */
1816                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1817                                         /* cif_d5m0 */
1818                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1819                                         /* cif_d6m0 */
1820                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1821                                         /* cif_d7m0 */
1822                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1823                                         /* cif_href */
1824                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1825                                         /* cif_vsync */
1826                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1827                                         /* cif_clkoutm0 */
1828                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1829                                         /* cif_clkin */
1830                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1831                         };
1832                 };
1833
1834                 cif-1 {
1835                         dvp_d2d9_m1:dvp-d2d9-m1 {
1836                                 rockchip,pins =
1837                                         /* cif_d0 */
1838                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1839                                         /* cif_d1 */
1840                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1841                                         /* cif_d2 */
1842                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1843                                         /* cif_d3 */
1844                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1845                                         /* cif_d4 */
1846                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1847                                         /* cif_d5m1 */
1848                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1849                                         /* cif_d6m1 */
1850                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1851                                         /* cif_d7m1 */
1852                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1853                                         /* cif_href */
1854                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1855                                         /* cif_vsync */
1856                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1857                                         /* cif_clkoutm1 */
1858                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1859                                         /* cif_clkin */
1860                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1861                         };
1862                 };
1863         };
1864 };