arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77 //                      clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x2>;
  90                         enable-method = "psci";
  91                 };
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x3>;
  96                         enable-method = "psci";
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp_table0 {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp@408000000 {
 105                         opp-hz = /bits/ 64 <408000000>;
 106                         opp-microvolt = <950000>;
 107                         clock-latency-ns = <40000>;
 108                         opp-suspend;
 109                 };
 110                 opp@600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                 };
 115                 opp@816000000 {
 116                         opp-hz = /bits/ 64 <816000000>;
 117                         opp-microvolt = <1000000>;
 118                         clock-latency-ns = <40000>;
 119                 };
 120                 opp@1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1100000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp@1200000000 {
 126                         opp-hz = /bits/ 64 <1200000000>;
 127                         opp-microvolt = <1225000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp@1296000000 {
 131                         opp-hz = /bits/ 64 <1296000000>;
 132                         opp-microvolt = <1300000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135         };
 136
 137         arm-pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 143                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         i2s0: i2s@ff000000 {
 167                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 168                 reg = <0x0 0xff000000 0x0 0x1000>;
 169                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 171                 clock-names = "i2s_clk", "i2s_hclk";
 172                 dmas = <&dmac 11>, <&dmac 12>;
 173                 #dma-cells = <2>;
 174                 dma-names = "tx", "rx";
 175                 status = "disabled";
 176         };
 177
 178         i2s1: i2s@ff010000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff010000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 14>, <&dmac 15>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s2: i2s@ff020000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff020000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 0>, <&dmac 1>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 pinctrl-names = "default", "sleep";
 200                 pinctrl-0 = <&i2s2m0_mclk
 201                              &i2s2m0_sclk
 202                              &i2s2m0_lrcktx
 203                              &i2s2m0_lrckrx
 204                              &i2s2m0_sdo
 205                              &i2s2m0_sdi>;
 206                 pinctrl-1 = <&i2s2m0_sleep>;
 207                 status = "disabled";
 208         };
 209
 210         spdif: spdif@ff030000 {
 211                 compatible = "rockchip,rk3328-spdif";
 212                 reg = <0x0 0xff030000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 215                 clock-names = "mclk", "hclk";
 216                 dmas = <&dmac 10>;
 217                 #dma-cells = <1>;
 218                 dma-names = "tx";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&spdifm2_tx>;
 221                 status = "disabled";
 222         };
 223
 224         grf: syscon@ff100000 {
 225                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff100000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229
 230                 io_domains: io-domains {
 231                         compatible = "rockchip,rk3328-io-voltage-domain";
 232                         status = "disabled";
 233                 };
 234
 235                 power: power-controller {
 236                         compatible = "rockchip,rk3328-power-controller";
 237                         #power-domain-cells = <1>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241
 242                         pd_hevc@RK3328_PD_HEVC {
 243                                 reg = <RK3328_PD_HEVC>;
 244                         };
 245                         pd_video@RK3328_PD_VIDEO {
 246                                 reg = <RK3328_PD_VIDEO>;
 247                         };
 248                         pd_vpu@RK3328_PD_VPU {
 249                                 reg = <RK3328_PD_VPU>;
 250                         };
 251                 };
 252
 253                 reboot-mode {
 254                         compatible = "syscon-reboot-mode";
 255                         offset = <0x5c8>;
 256                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 257                         mode-charge = <BOOT_CHARGING>;
 258                         mode-fastboot = <BOOT_FASTBOOT>;
 259                         mode-loader = <BOOT_BL_DOWNLOAD>;
 260                         mode-normal = <BOOT_NORMAL>;
 261                         mode-recovery = <BOOT_RECOVERY>;
 262                         mode-ums = <BOOT_UMS>;
 263                 };
 264         };
 265
 266         uart0: serial@ff110000 {
 267                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 268                 reg = <0x0 0xff110000 0x0 0x100>;
 269                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 reg-shift = <2>;
 273                 reg-io-width = <4>;
 274                 dmas = <&dmac 2>, <&dmac 3>;
 275                 #dma-cells = <2>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 278                 status = "disabled";
 279         };
 280
 281         uart1: serial@ff120000 {
 282                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 283                 reg = <0x0 0xff120000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 286                 clock-names = "sclk_uart", "pclk_uart";
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 dmas = <&dmac 4>, <&dmac 5>;
 290                 #dma-cells = <2>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 293                 status = "disabled";
 294         };
 295
 296         uart2: serial@ff130000 {
 297                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff130000 0x0 0x100>;
 299                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 301                 clock-names = "baudclk", "apb_pclk";
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 dmas = <&dmac 6>, <&dmac 7>;
 305                 #dma-cells = <2>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&uart2m1_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         pmu: power-management@ff140000 {
 312                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314         };
 315
 316         i2c0: i2c@ff150000 {
 317                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 318                 reg = <0x0 0xff150000 0x0 0x1000>;
 319                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 323                 clock-names = "i2c", "pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff160000 {
 330                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 331                 reg = <0x0 0xff160000 0x0 0x1000>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 336                 clock-names = "i2c", "pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@ff170000 {
 343                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 344                 reg = <0x0 0xff170000 0x0 0x1000>;
 345                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 349                 clock-names = "i2c", "pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff180000 {
 356                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 357                 reg = <0x0 0xff180000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 362                 clock-names = "i2c", "pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff190000 {
 369                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff190000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac 8>, <&dmac 9>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 381                 status = "disabled";
 382         };
 383
 384         wdt: watchdog@ff1a0000 {
 385                 compatible = "snps,dw-wdt";
 386                 reg = <0x0 0xff1a0000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 388                 status = "disabled";
 389         };
 390
 391         pwm0: pwm@ff1b0000 {
 392                 compatible = "rockchip,rk3328-pwm";
 393                 reg = <0x0 0xff1b0000 0x0 0x10>;
 394                 #pwm-cells = <3>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pwm0_pin>;
 397                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 398                 clock-names = "pwm", "pclk";
 399                 status = "disabled";
 400         };
 401
 402         pwm1: pwm@ff1b0010 {
 403                 compatible = "rockchip,rk3328-pwm";
 404                 reg = <0x0 0xff1b0010 0x0 0x10>;
 405                 #pwm-cells = <3>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&pwm1_pin>;
 408                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 409                 clock-names = "pwm", "pclk";
 410                 status = "disabled";
 411         };
 412
 413         pwm2: pwm@ff1b0020 {
 414                 compatible = "rockchip,rk3328-pwm";
 415                 reg = <0x0 0xff1b0020 0x0 0x10>;
 416                 #pwm-cells = <3>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&pwm2_pin>;
 419                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 420                 clock-names = "pwm", "pclk";
 421                 status = "disabled";
 422         };
 423
 424         pwm3: pwm@ff1b0030 {
 425                 compatible = "rockchip,rk3328-pwm";
 426                 reg = <0x0 0xff1b0030 0x0 0x10>;
 427                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 428                 #pwm-cells = <3>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&pwmir_pin>;
 431                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 432                 clock-names = "pwm", "pclk";
 433                 status = "disabled";
 434         };
 435
 436         amba {
 437                 compatible = "simple-bus";
 438                 #address-cells = <2>;
 439                 #size-cells = <2>;
 440                 ranges;
 441
 442                 dmac: dmac@ff1f0000 {
 443                         compatible = "arm,pl330", "arm,primecell";
 444                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 445                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 446                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&cru ACLK_DMAC>;
 448                         clock-names = "apb_pclk";
 449                         #dma-cells = <1>;
 450                 };
 451         };
 452
 453         saradc: saradc@ff280000 {
 454                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 455                 reg = <0x0 0xff280000 0x0 0x100>;
 456                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 457                 #io-channel-cells = <1>;
 458                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 459                 clock-names = "saradc", "apb_pclk";
 460                 resets = <&cru SRST_SARADC_P>;
 461                 reset-names = "saradc-apb";
 462                 status = "disabled";
 463         };
 464
 465         cru: clock-controller@ff440000 {
 466                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 467                 reg = <0x0 0xff440000 0x0 0x1000>;
 468                 rockchip,grf = <&grf>;
 469                 #clock-cells = <1>;
 470                 #reset-cells = <1>;
 471                 assigned-clocks =
 472                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 473                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 474                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 475                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 476                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 477                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 478                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 479                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 480                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 481                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 482                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 483                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 484                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 485                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 486                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 487                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 488                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 489                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 490                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 491                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 492                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 493                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 494                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 495                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 496                 assigned-clock-parents =
 497                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 498                         <&cru PLL_GPLL>, <&xin24m>,
 499                         <&xin24m>, <&xin24m>;
 500                 assigned-clock-rates =
 501                         <0>, <61440000>,
 502                         <0>, <24000000>,
 503                         <24000000>, <24000000>,
 504                         <15000000>, <15000000>,
 505                         <100000000>, <100000000>,
 506                         <100000000>, <100000000>,
 507                         <50000000>, <100000000>,
 508                         <100000000>, <100000000>,
 509                         <50000000>, <50000000>,
 510                         <50000000>, <50000000>,
 511                         <24000000>, <600000000>,
 512                         <491520000>, <1200000000>,
 513                         <150000000>, <75000000>,
 514                         <75000000>, <150000000>,
 515                         <75000000>, <75000000>,
 516                         <300000000>, <100000000>,
 517                         <300000000>, <200000000>,
 518                         <400000000>, <500000000>,
 519                         <200000000>, <300000000>,
 520                         <300000000>, <250000000>,
 521                         <200000000>, <100000000>,
 522                         <24000000>, <100000000>,
 523                         <150000000>, <50000000>,
 524                         <32768>, <32768>;
 525         };
 526
 527         usb2phy_grf: syscon@ff450000 {
 528                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 529                              "simple-mfd";
 530                 reg = <0x0 0xff450000 0x0 0x10000>;
 531                 #address-cells = <1>;
 532                 #size-cells = <1>;
 533
 534                 u2phy: usb2-phy@100 {
 535                         compatible = "rockchip,rk3328-usb2phy";
 536                         reg = <0x100 0x10>;
 537                         clocks = <&xin24m>;
 538                         clock-names = "phyclk";
 539                         #clock-cells = <0>;
 540                         assigned-clocks = <&cru USB480M>;
 541                         assigned-clock-parents = <&u2phy>;
 542                         clock-output-names = "usb480m_phy";
 543                         status = "disabled";
 544
 545                         u2phy_host: host-port {
 546                                 #phy-cells = <0>;
 547                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 548                                 interrupt-names = "linestate";
 549                                 status = "disabled";
 550                         };
 551
 552                         u2phy_otg: otg-port {
 553                                 #phy-cells = <0>;
 554                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 555                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 556                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 557                                 interrupt-names = "otg-bvalid", "otg-id",
 558                                                   "linestate";
 559                                 status = "disabled";
 560                         };
 561                 };
 562         };
 563
 564         usb3phy_grf: syscon@ff460000 {
 565                 compatible = "rockchip,usb3phy-grf", "syscon";
 566                 reg = <0x0 0xff460000 0x0 0x1000>;
 567         };
 568
 569         u3phy: usb3-phy@ff470000 {
 570                 compatible = "rockchip,rk3328-u3phy";
 571                 reg = <0x0 0xff470000 0x0 0x0>;
 572                 rockchip,u3phygrf = <&usb3phy_grf>;
 573                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 574                 interrupt-names = "linestate";
 575                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 576                 clock-names = "u3phy-otg", "u3phy-pipe";
 577                 resets = <&cru SRST_USB3PHY_U2>,
 578                          <&cru SRST_USB3PHY_U3>,
 579                          <&cru SRST_USB3PHY_PIPE>,
 580                          <&cru SRST_USB3OTG_UTMI>,
 581                          <&cru SRST_USB3PHY_OTG_P>,
 582                          <&cru SRST_USB3PHY_PIPE_P>;
 583                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 584                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 585                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 586                 #address-cells = <2>;
 587                 #size-cells = <2>;
 588                 ranges;
 589                 status = "disabled";
 590
 591                 u3phy_utmi: utmi@ff470000 {
 592                         reg = <0x0 0xff470000 0x0 0x8000>;
 593                         #phy-cells = <0>;
 594                         status = "disabled";
 595                 };
 596
 597                 u3phy_pipe: pipe@ff478000 {
 598                         reg = <0x0 0xff478000 0x0 0x8000>;
 599                         #phy-cells = <0>;
 600                         status = "disabled";
 601                 };
 602         };
 603
 604         sdmmc: rksdmmc@ff500000 {
 605                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 606                 reg = <0x0 0xff500000 0x0 0x4000>;
 607                 clock-freq-min-max = <400000 150000000>;
 608                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 609                 clock-names = "biu", "ciu";
 610                 fifo-depth = <0x100>;
 611                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 612                 status = "disabled";
 613         };
 614
 615         sdio: dwmmc@ff510000 {
 616                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 617                 reg = <0x0 0xff510000 0x0 0x4000>;
 618                 clock-freq-min-max = <400000 150000000>;
 619                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 620                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 621                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 622                 fifo-depth = <0x100>;
 623                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 624                 status = "disabled";
 625         };
 626
 627         emmc: rksdmmc@ff520000 {
 628                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 629                 reg = <0x0 0xff520000 0x0 0x4000>;
 630                 clock-freq-min-max = <400000 150000000>;
 631                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 632                 clock-names = "biu", "ciu";
 633                 fifo-depth = <0x100>;
 634                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 635                 status = "disabled";
 636         };
 637
 638         gmac2io: eth@ff540000 {
 639                 compatible = "rockchip,rk3328-gmac";
 640                 reg = <0x0 0xff540000 0x0 0x10000>;
 641                 rockchip,grf = <&grf>;
 642                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 643                 interrupt-names = "macirq";
 644                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 645                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 646                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 647                          <&cru PCLK_MAC2IO>;
 648                 clock-names = "stmmaceth", "mac_clk_rx",
 649                               "mac_clk_tx", "clk_mac_ref",
 650                               "clk_mac_refout", "aclk_mac",
 651                               "pclk_mac";
 652                 resets = <&cru SRST_GMAC2IO_A>;
 653                 reset-names = "stmmaceth";
 654                 status = "disabled";
 655         };
 656
 657         usb20_otg: usb@ff580000 {
 658                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 659                              "snps,dwc2";
 660                 reg = <0x0 0xff580000 0x0 0x40000>;
 661                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 662                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 663                 clock-names = "otg", "otg_pmu";
 664                 dr_mode = "otg";
 665                 g-np-tx-fifo-size = <16>;
 666                 g-rx-fifo-size = <275>;
 667                 g-tx-fifo-size = <256 128 128 64 64 32>;
 668                 g-use-dma;
 669                 phys = <&u2phy_otg>;
 670                 phy-names = "usb2-phy";
 671                 status = "disabled";
 672         };
 673
 674         usb_host0_ehci: usb@ff5c0000 {
 675                 compatible = "generic-ehci";
 676                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 677                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 679                          <&u2phy>;
 680                 clock-names = "usbhost", "arbiter", "utmi";
 681                 phys = <&u2phy_host>;
 682                 phy-names = "usb";
 683                 status = "disabled";
 684         };
 685
 686         usb_host0_ohci: usb@ff5d0000 {
 687                 compatible = "generic-ohci";
 688                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 689                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 690                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 691                          <&u2phy>;
 692                 clock-names = "usbhost", "arbiter", "utmi";
 693                 phys = <&u2phy_host>;
 694                 phy-names = "usb";
 695                 status = "disabled";
 696         };
 697
 698         sdmmc_ext: rksdmmc@ff5f0000 {
 699                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 700                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 701                 clock-freq-min-max = <400000 150000000>;
 702                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 703                 clock-names = "biu", "ciu";
 704                 fifo-depth = <0x100>;
 705                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 706                 status = "disabled";
 707         };
 708
 709         usbdrd3: usb@ff600000 {
 710                 compatible = "rockchip,rk3328-dwc3";
 711                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 712                          <&cru ACLK_USB3OTG>;
 713                 clock-names = "ref_clk", "suspend_clk",
 714                               "bus_clk";
 715                 #address-cells = <2>;
 716                 #size-cells = <2>;
 717                 ranges;
 718                 status = "disabled";
 719
 720                 usbdrd_dwc3: dwc3@ff600000 {
 721                         compatible = "snps,dwc3";
 722                         reg = <0x0 0xff600000 0x0 0x100000>;
 723                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 724                         dr_mode = "host";
 725                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 726                         phy-names = "usb2-phy", "usb3-phy";
 727                         phy_type = "utmi_wide";
 728                         snps,dis_enblslpm_quirk;
 729                         snps,dis-u2-freeclk-exists-quirk;
 730                         snps,dis_u2_susphy_quirk;
 731                         snps,dis_u3_susphy_quirk;
 732                         snps,dis-del-phy-power-chg-quirk;
 733                         status = "disabled";
 734                 };
 735         };
 736
 737         gic: interrupt-controller@ff811000 {
 738                 compatible = "arm,gic-400";
 739                 #interrupt-cells = <3>;
 740                 #address-cells = <0>;
 741                 interrupt-controller;
 742                 reg = <0x0 0xff811000 0 0x1000>,
 743                       <0x0 0xff812000 0 0x2000>,
 744                       <0x0 0xff814000 0 0x2000>,
 745                       <0x0 0xff816000 0 0x2000>;
 746                 interrupts = <GIC_PPI 9
 747                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 748         };
 749
 750         pinctrl: pinctrl {
 751                 compatible = "rockchip,rk3328-pinctrl";
 752                 rockchip,grf = <&grf>;
 753                 #address-cells = <2>;
 754                 #size-cells = <2>;
 755                 ranges;
 756
 757                 gpio0: gpio0@ff210000 {
 758                         compatible = "rockchip,gpio-bank";
 759                         reg = <0x0 0xff210000 0x0 0x100>;
 760                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&cru PCLK_GPIO0>;
 762
 763                         gpio-controller;
 764                         #gpio-cells = <2>;
 765
 766                         interrupt-controller;
 767                         #interrupt-cells = <2>;
 768                 };
 769
 770                 gpio1: gpio1@ff220000 {
 771                         compatible = "rockchip,gpio-bank";
 772                         reg = <0x0 0xff220000 0x0 0x100>;
 773                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 774                         clocks = <&cru PCLK_GPIO1>;
 775
 776                         gpio-controller;
 777                         #gpio-cells = <2>;
 778
 779                         interrupt-controller;
 780                         #interrupt-cells = <2>;
 781                 };
 782
 783                 gpio2: gpio2@ff230000 {
 784                         compatible = "rockchip,gpio-bank";
 785                         reg = <0x0 0xff230000 0x0 0x100>;
 786                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 787                         clocks = <&cru PCLK_GPIO2>;
 788
 789                         gpio-controller;
 790                         #gpio-cells = <2>;
 791
 792                         interrupt-controller;
 793                         #interrupt-cells = <2>;
 794                 };
 795
 796                 gpio3: gpio3@ff240000 {
 797                         compatible = "rockchip,gpio-bank";
 798                         reg = <0x0 0xff240000 0x0 0x100>;
 799                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 800                         clocks = <&cru PCLK_GPIO3>;
 801
 802                         gpio-controller;
 803                         #gpio-cells = <2>;
 804
 805                         interrupt-controller;
 806                         #interrupt-cells = <2>;
 807                 };
 808
 809                 pcfg_pull_up: pcfg-pull-up {
 810                         bias-pull-up;
 811                 };
 812
 813                 pcfg_pull_down: pcfg-pull-down {
 814                         bias-pull-down;
 815                 };
 816
 817                 pcfg_pull_none: pcfg-pull-none {
 818                         bias-disable;
 819                 };
 820
 821                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 822                         bias-disable;
 823                         drive-strength = <2>;
 824                 };
 825
 826                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 827                         bias-pull-up;
 828                         drive-strength = <2>;
 829                 };
 830
 831                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 832                         bias-pull-up;
 833                         drive-strength = <4>;
 834                 };
 835
 836                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 837                         bias-disable;
 838                         drive-strength = <4>;
 839                 };
 840
 841                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 842                         bias-pull-down;
 843                         drive-strength = <4>;
 844                 };
 845
 846                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 847                         bias-disable;
 848                         drive-strength = <8>;
 849                 };
 850
 851                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 852                         bias-pull-up;
 853                         drive-strength = <8>;
 854                 };
 855
 856                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 857                         bias-disable;
 858                         drive-strength = <12>;
 859                 };
 860
 861                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 862                         bias-pull-up;
 863                         drive-strength = <12>;
 864                 };
 865
 866                 pcfg_output_high: pcfg-output-high {
 867                         output-high;
 868                 };
 869
 870                 pcfg_output_low: pcfg-output-low {
 871                         output-low;
 872                 };
 873
 874                 pcfg_input_high: pcfg-input-high {
 875                         bias-pull-up;
 876                         input-enable;
 877                 };
 878
 879                 pcfg_input: pcfg-input {
 880                         input-enable;
 881                 };
 882
 883                 i2c0 {
 884                         i2c0_xfer: i2c0-xfer {
 885                                 rockchip,pins =
 886                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 887                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 888                         };
 889                 };
 890
 891                 i2c1 {
 892                         i2c1_xfer: i2c1-xfer {
 893                                 rockchip,pins =
 894                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 895                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 896                         };
 897                 };
 898
 899                 i2c2 {
 900                         i2c2_xfer: i2c2-xfer {
 901                                 rockchip,pins =
 902                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 903                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 904                         };
 905                 };
 906
 907                 i2c3 {
 908                         i2c3_xfer: i2c3-xfer {
 909                                 rockchip,pins =
 910                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 911                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 912                         };
 913                         i2c3_gpio: i2c3-gpio {
 914                                 rockchip,pins =
 915                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 916                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 917                         };
 918                 };
 919
 920                 hdmi_i2c {
 921                         hdmii2c_xfer: hdmii2c-xfer {
 922                                 rockchip,pins =
 923                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 924                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 925                         };
 926                 };
 927
 928                 uart0 {
 929                         uart0_xfer: uart0-xfer {
 930                                 rockchip,pins =
 931                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 932                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 933                         };
 934
 935                         uart0_cts: uart0-cts {
 936                                 rockchip,pins =
 937                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 938                         };
 939
 940                         uart0_rts: uart0-rts {
 941                                 rockchip,pins =
 942                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 943                         };
 944
 945                         uart0_rts_gpio: uart0-rts-gpio {
 946                                 rockchip,pins =
 947                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 948                         };
 949                 };
 950
 951                 uart1 {
 952                         uart1_xfer: uart1-xfer {
 953                                 rockchip,pins =
 954                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 955                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 956                         };
 957
 958                         uart1_cts: uart1-cts {
 959                                 rockchip,pins =
 960                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 961                         };
 962
 963                         uart1_rts: uart1-rts {
 964                                 rockchip,pins =
 965                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 966                         };
 967
 968                         uart1_rts_gpio: uart1-rts-gpio {
 969                                 rockchip,pins =
 970                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 uart2-0 {
 975                         uart2m0_xfer: uart2m0-xfer {
 976                                 rockchip,pins =
 977                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 978                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 979                         };
 980                 };
 981
 982                 uart2-1 {
 983                         uart2m1_xfer: uart2m1-xfer {
 984                                 rockchip,pins =
 985                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 986                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 987                         };
 988                 };
 989
 990                 spi0-0 {
 991                         spi0m0_clk: spi0m0-clk {
 992                                 rockchip,pins =
 993                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 994                         };
 995
 996                         spi0m0_cs0: spi0m0-cs0 {
 997                                 rockchip,pins =
 998                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 999                         };
1000
1001                         spi0m0_tx: spi0m0-tx {
1002                                 rockchip,pins =
1003                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
1004                         };
1005
1006                         spi0m0_rx: spi0m0-rx {
1007                                 rockchip,pins =
1008                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
1009                         };
1010
1011                         spi0m0_cs1: spi0m0-cs1 {
1012                                 rockchip,pins =
1013                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1014                         };
1015                 };
1016
1017                 spi0-1 {
1018                         spi0m1_clk: spi0m1-clk {
1019                                 rockchip,pins =
1020                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
1021                         };
1022
1023                         spi0m1_cs0: spi0m1-cs0 {
1024                                 rockchip,pins =
1025                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
1026                         };
1027
1028                         spi0m1_tx: spi0m1-tx {
1029                                 rockchip,pins =
1030                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
1031                         };
1032
1033                         spi0m1_rx: spi0m1-rx {
1034                                 rockchip,pins =
1035                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
1036                         };
1037
1038                         spi0m1_cs1: spi0m1-cs1 {
1039                                 rockchip,pins =
1040                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
1041                         };
1042                 };
1043
1044                 spi0-2 {
1045                         spi0m2_clk: spi0m2-clk {
1046                                 rockchip,pins =
1047                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
1048                         };
1049
1050                         spi0m2_cs0: spi0m2-cs0 {
1051                                 rockchip,pins =
1052                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
1053                         };
1054
1055                         spi0m2_tx: spi0m2-tx {
1056                                 rockchip,pins =
1057                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
1058                         };
1059
1060                         spi0m2_rx: spi0m2-rx {
1061                                 rockchip,pins =
1062                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
1063                         };
1064                 };
1065
1066                 i2s1 {
1067                         i2s1_mclk: i2s1-mclk {
1068                                 rockchip,pins =
1069                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
1070                         };
1071
1072                         i2s1_sclk: i2s1-sclk {
1073                                 rockchip,pins =
1074                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1075                         };
1076
1077                         i2s1_lrckrx: i2s1-lrckrx {
1078                                 rockchip,pins =
1079                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1080                         };
1081
1082                         i2s1_lrcktx: i2s1-lrcktx {
1083                                 rockchip,pins =
1084                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1085                         };
1086
1087                         i2s1_sdi: i2s1-sdi {
1088                                 rockchip,pins =
1089                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1090                         };
1091
1092                         i2s1_sdo: i2s1-sdo {
1093                                 rockchip,pins =
1094                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1095                         };
1096
1097                         i2s1_sdio1: i2s1-sdio1 {
1098                                 rockchip,pins =
1099                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1100                         };
1101
1102                         i2s1_sdio2: i2s1-sdio2 {
1103                                 rockchip,pins =
1104                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1105                         };
1106
1107                         i2s1_sdio3: i2s1-sdio3 {
1108                                 rockchip,pins =
1109                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1110                         };
1111
1112                         i2s1_sleep: i2s1-sleep {
1113                                 rockchip,pins =
1114                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1115                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1116                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1117                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1118                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1119                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1120                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1121                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1122                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1123                         };
1124                 };
1125
1126                 i2s2-0 {
1127                         i2s2m0_mclk: i2s2m0-mclk {
1128                                 rockchip,pins =
1129                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1130                         };
1131
1132                         i2s2m0_sclk: i2s2m0-sclk {
1133                                 rockchip,pins =
1134                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1135                         };
1136
1137                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1138                                 rockchip,pins =
1139                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1140                         };
1141
1142                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1143                                 rockchip,pins =
1144                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1145                         };
1146
1147                         i2s2m0_sdi: i2s2m0-sdi {
1148                                 rockchip,pins =
1149                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1150                         };
1151
1152                         i2s2m0_sdo: i2s2m0-sdo {
1153                                 rockchip,pins =
1154                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156
1157                         i2s2m0_sleep: i2s2m0-sleep {
1158                                 rockchip,pins =
1159                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1160                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1161                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1162                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1163                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1164                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1165                         };
1166                 };
1167
1168                 i2s2-1 {
1169                         i2s2m1_mclk: i2s2m1-mclk {
1170                                 rockchip,pins =
1171                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1172                         };
1173
1174                         i2s2m1_sclk: i2s2m1-sclk {
1175                                 rockchip,pins =
1176                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1177                         };
1178
1179                         i2s2m1_lrckrx: i2sm1-lrckrx {
1180                                 rockchip,pins =
1181                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1182                         };
1183
1184                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1185                                 rockchip,pins =
1186                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1187                         };
1188
1189                         i2s2m1_sdi: i2s2m1-sdi {
1190                                 rockchip,pins =
1191                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1192                         };
1193
1194                         i2s2m1_sdo: i2s2m1-sdo {
1195                                 rockchip,pins =
1196                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1197                         };
1198
1199                         i2s2m1_sleep: i2s2m1-sleep {
1200                                 rockchip,pins =
1201                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1202                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1203                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1204                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1205                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1206                         };
1207                 };
1208
1209                 spdif-0 {
1210                         spdifm0_tx: spdifm0-tx {
1211                                 rockchip,pins =
1212                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1213                         };
1214                 };
1215
1216                 spdif-1 {
1217                         spdifm1_tx: spdifm1-tx {
1218                                 rockchip,pins =
1219                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1220                         };
1221                 };
1222
1223                 spdif-2 {
1224                         spdifm2_tx: spdifm2-tx {
1225                                 rockchip,pins =
1226                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 sdmmc0-0 {
1231                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1232                                 rockchip,pins =
1233                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1234                         };
1235
1236                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1237                                 rockchip,pins =
1238                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1239                         };
1240                 };
1241
1242                 sdmmc0-1 {
1243                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1244                                 rockchip,pins =
1245                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1246                         };
1247
1248                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1249                                 rockchip,pins =
1250                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1251                         };
1252                 };
1253
1254                 sdmmc0 {
1255                         sdmmc0_clk: sdmmc0-clk {
1256                                 rockchip,pins =
1257                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1258                         };
1259
1260                         sdmmc0_cmd: sdmmc0-cmd {
1261                                 rockchip,pins =
1262                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1263                         };
1264
1265                         sdmmc0_dectn: sdmmc0-dectn {
1266                                 rockchip,pins =
1267                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1268                         };
1269
1270                         sdmmc0_wrprt: sdmmc0-wrprt {
1271                                 rockchip,pins =
1272                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1273                         };
1274
1275                         sdmmc0_bus1: sdmmc0-bus1 {
1276                                 rockchip,pins =
1277                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1278                         };
1279
1280                         sdmmc0_bus4: sdmmc0-bus4 {
1281                                 rockchip,pins =
1282                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1283                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1284                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1285                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1286                         };
1287
1288                         sdmmc0_gpio: sdmmc0-gpio {
1289                                 rockchip,pins =
1290                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1291                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1292                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1293                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1294                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1295                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1296                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1297                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1298                         };
1299                 };
1300
1301                 sdmmc0ext {
1302                         sdmmc0ext_clk: sdmmc0ext-clk {
1303                                 rockchip,pins =
1304                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1305                         };
1306
1307                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1308                                 rockchip,pins =
1309                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1310                         };
1311
1312                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1313                                 rockchip,pins =
1314                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1315                         };
1316
1317                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1318                                 rockchip,pins =
1319                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1320                         };
1321
1322                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1323                                 rockchip,pins =
1324                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1325                         };
1326
1327                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1328                                 rockchip,pins =
1329                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1330                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1331                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1332                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1333                         };
1334
1335                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1336                                 rockchip,pins =
1337                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1338                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1339                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1340                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1341                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1342                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1343                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1344                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1345                         };
1346                 };
1347
1348                 sdmmc1 {
1349                         sdmmc1_clk: sdmmc1-clk {
1350                                 rockchip,pins =
1351                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1352                         };
1353
1354                         sdmmc1_cmd: sdmmc1-cmd {
1355                                 rockchip,pins =
1356                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1357                         };
1358
1359                         sdmmc1_pwren: sdmmc1-pwren {
1360                                 rockchip,pins =
1361                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1362                         };
1363
1364                         sdmmc1_wrprt: sdmmc1-wrprt {
1365                                 rockchip,pins =
1366                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1367                         };
1368
1369                         sdmmc1_dectn: sdmmc1-dectn {
1370                                 rockchip,pins =
1371                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1372                         };
1373
1374                         sdmmc1_bus1: sdmmc1-bus1 {
1375                                 rockchip,pins =
1376                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1377                         };
1378
1379                         sdmmc1_bus4: sdmmc1-bus4 {
1380                                 rockchip,pins =
1381                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1382                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1383                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1384                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1385                         };
1386
1387                         sdmmc1_gpio: sdmmc1-gpio {
1388                                 rockchip,pins =
1389                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1390                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1391                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1392                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1393                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1394                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1395                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1396                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1397                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1398                         };
1399                 };
1400
1401                 emmc {
1402                         emmc_clk: emmc-clk {
1403                                 rockchip,pins =
1404                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1405                         };
1406
1407                         emmc_cmd: emmc-cmd {
1408                                 rockchip,pins =
1409                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1410                         };
1411
1412                         emmc_pwren: emmc-pwren {
1413                                 rockchip,pins =
1414                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1415                         };
1416
1417                         emmc_rstnout: emmc-rstnout {
1418                                 rockchip,pins =
1419                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1420                         };
1421
1422                         emmc_bus1: emmc-bus1 {
1423                                 rockchip,pins =
1424                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1425                         };
1426
1427                         emmc_bus4: emmc-bus4 {
1428                                 rockchip,pins =
1429                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1430                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1431                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1432                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1433                         };
1434
1435                         emmc_bus8: emmc-bus8 {
1436                                 rockchip,pins =
1437                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1438                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1439                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1440                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1441                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1442                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1443                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1444                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1445                         };
1446                 };
1447
1448                 pwm0 {
1449                         pwm0_pin: pwm0-pin {
1450                                 rockchip,pins =
1451                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1452                         };
1453                 };
1454
1455                 pwm1 {
1456                         pwm1_pin: pwm1-pin {
1457                                 rockchip,pins =
1458                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1459                         };
1460                 };
1461
1462                 pwm2 {
1463                         pwm2_pin: pwm2-pin {
1464                                 rockchip,pins =
1465                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1466                         };
1467                 };
1468
1469                 pwmir {
1470                         pwmir_pin: pwmir-pin {
1471                                 rockchip,pins =
1472                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1473                         };
1474                 };
1475
1476                 gmac-0 {
1477                         rgmiim0_pins: rgmiim0-pins {
1478                                 rockchip,pins =
1479                                         /* mac_txclk */
1480                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1481                                         /* mac_rxclk */
1482                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1483                                         /* mac_mdio */
1484                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1485                                         /* mac_txen */
1486                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1487                                         /* mac_clk */
1488                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1489                                         /* mac_rxdv */
1490                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1491                                         /* mac_mdc */
1492                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1493                                         /* mac_rxd1 */
1494                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1495                                         /* mac_rxd0 */
1496                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1497                                         /* mac_txd1 */
1498                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1499                                         /* mac_txd0 */
1500                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1501                                         /* mac_rxd3 */
1502                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1503                                         /* mac_rxd2 */
1504                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1505                                         /* mac_txd3 */
1506                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1507                                         /* mac_txd2 */
1508                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1509                         };
1510
1511                         rmiim0_pins: rmiim0-pins {
1512                                 rockchip,pins =
1513                                         /* mac_mdio */
1514                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_txen */
1516                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1517                                         /* mac_clk */
1518                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1519                                         /* mac_rxer */
1520                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1521                                         /* mac_rxdv */
1522                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1523                                         /* mac_mdc */
1524                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1525                                         /* mac_rxd1 */
1526                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1527                                         /* mac_rxd0 */
1528                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1529                                         /* mac_txd1 */
1530                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1531                                         /* mac_txd0 */
1532                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1533                         };
1534                 };
1535
1536                 gmac-1 {
1537                         rgmiim1_pins: rgmiim1-pins {
1538                                 rockchip,pins =
1539                                         /* mac_txclk */
1540                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1541                                         /* mac_rxclk */
1542                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1543                                         /* mac_mdio */
1544                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1545                                         /* mac_txen */
1546                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1547                                         /* mac_clk */
1548                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1549                                         /* mac_rxdv */
1550                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1551                                         /* mac_mdc */
1552                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1553                                         /* mac_rxd1 */
1554                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1555                                         /* mac_rxd0 */
1556                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1557                                         /* mac_txd1 */
1558                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1559                                         /* mac_txd0 */
1560                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1561                                         /* mac_rxd3 */
1562                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1563                                         /* mac_rxd2 */
1564                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1565                                         /* mac_txd3 */
1566                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1567                                         /* mac_txd2 */
1568                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1569
1570                                         /* mac_txclk */
1571                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1572                                         /* mac_txen */
1573                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1574                                         /* mac_clk */
1575                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1576                                         /* mac_txd1 */
1577                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1578                                         /* mac_txd0 */
1579                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1580                                         /* mac_txd3 */
1581                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1582                                         /* mac_txd2 */
1583                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1584                         };
1585
1586                         rmiim1_pins: rmiim1-pins {
1587                                 rockchip,pins =
1588                                         /* mac_mdio */
1589                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1590                                         /* mac_txen */
1591                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1592                                         /* mac_clk */
1593                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1594                                         /* mac_rxer */
1595                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1596                                         /* mac_rxdv */
1597                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1598                                         /* mac_mdc */
1599                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1600                                         /* mac_rxd1 */
1601                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1602                                         /* mac_rxd0 */
1603                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1604                                         /* mac_txd1 */
1605                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1606                                         /* mac_txd0 */
1607                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1608
1609                                         /* mac_mdio */
1610                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1611                                         /* mac_txen */
1612                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1613                                         /* mac_clk */
1614                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1615                                         /* mac_mdc */
1616                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1617                                         /* mac_txd1 */
1618                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1619                                         /* mac_txd0 */
1620                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 gmac2phy {
1625                         fephyled_speed100: fephyled-speed100 {
1626                                 rockchip,pins =
1627                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1628                         };
1629
1630                         fephyled_speed10: fephyled-speed10 {
1631                                 rockchip,pins =
1632                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         fephyled_duplex: fephyled-duplex {
1636                                 rockchip,pins =
1637                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1638                         };
1639
1640                         fephyled_rxm0: fephyled-rxm0 {
1641                                 rockchip,pins =
1642                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1643                         };
1644
1645                         fephyled_txm0: fephyled-txm0 {
1646                                 rockchip,pins =
1647                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1648                         };
1649
1650                         fephyled_linkm0: fephyled-linkm0 {
1651                                 rockchip,pins =
1652                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654
1655                         fephyled_rxm1: fephyled-rxm1 {
1656                                 rockchip,pins =
1657                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1658                         };
1659
1660                         fephyled_txm1: fephyled-txm1 {
1661                                 rockchip,pins =
1662                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1663                         };
1664
1665                         fephyled_linkm1: fephyled-linkm1 {
1666                                 rockchip,pins =
1667                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1668                         };
1669                 };
1670
1671                 tsadc_pin {
1672                         tsadc_int: tsadc-int {
1673                                 rockchip,pins =
1674                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1675                         };
1676                         tsadc_gpio: tsadc-gpio {
1677                                 rockchip,pins =
1678                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1679                         };
1680                 };
1681
1682                 hdmi_pin {
1683                         hdmi_cec: hdmi-cec {
1684                                 rockchip,pins =
1685                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1686                         };
1687
1688                         hdmi_hpd: hdmi-hpd {
1689                                 rockchip,pins =
1690                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1691                         };
1692                 };
1693
1694                 cif-0 {
1695                         dvp_d2d9_m0:dvp-d2d9-m0 {
1696                                 rockchip,pins =
1697                                         /* cif_d0 */
1698                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1699                                         /* cif_d1 */
1700                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1701                                         /* cif_d2 */
1702                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1703                                         /* cif_d3 */
1704                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1705                                         /* cif_d4 */
1706                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1707                                         /* cif_d5m0 */
1708                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1709                                         /* cif_d6m0 */
1710                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1711                                         /* cif_d7m0 */
1712                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1713                                         /* cif_href */
1714                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1715                                         /* cif_vsync */
1716                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1717                                         /* cif_clkoutm0 */
1718                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1719                                         /* cif_clkin */
1720                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1721                         };
1722                 };
1723
1724                 cif-1 {
1725                         dvp_d2d9_m1:dvp-d2d9-m1 {
1726                                 rockchip,pins =
1727                                         /* cif_d0 */
1728                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1729                                         /* cif_d1 */
1730                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1731                                         /* cif_d2 */
1732                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1733                                         /* cif_d3 */
1734                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1735                                         /* cif_d4 */
1736                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1737                                         /* cif_d5m1 */
1738                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1739                                         /* cif_d6m1 */
1740                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1741                                         /* cif_d7m1 */
1742                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1743                                         /* cif_href */
1744                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1745                                         /* cif_vsync */
1746                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1747                                         /* cif_clkoutm1 */
1748                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1749                                         /* cif_clkin */
1750                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1751                         };
1752                 };
1753         };
1754 };