arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50 #include <dt-bindings/thermal/thermal.h>
  51
  52 / {
  53         compatible = "rockchip,rk3328";
  54
  55         interrupt-parent = <&gic>;
  56         #address-cells = <2>;
  57         #size-cells = <2>;
  58
  59         aliases {
  60                 serial0 = &uart0;
  61                 serial1 = &uart1;
  62                 serial2 = &uart2;
  63                 i2c0 = &i2c0;
  64                 i2c1 = &i2c1;
  65                 i2c2 = &i2c2;
  66                 i2c3 = &i2c3;
  67         };
  68
  69         cpus {
  70                 #address-cells = <2>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         device_type = "cpu";
  75                         compatible = "arm,cortex-a53", "arm,armv8";
  76                         reg = <0x0 0x0>;
  77                         enable-method = "psci";
  78                         clocks = <&cru ARMCLK>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <120>;
  81                         operating-points-v2 = <&cpu0_opp_table>;
  82                 };
  83                 cpu1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a53", "arm,armv8";
  86                         reg = <0x0 0x1>;
  87                         enable-method = "psci";
  88                         operating-points-v2 = <&cpu0_opp_table>;
  89                 };
  90                 cpu2: cpu@2 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a53", "arm,armv8";
  93                         reg = <0x0 0x2>;
  94                         enable-method = "psci";
  95                         operating-points-v2 = <&cpu0_opp_table>;
  96                 };
  97                 cpu3: cpu@3 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a53", "arm,armv8";
 100                         reg = <0x0 0x3>;
 101                         enable-method = "psci";
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                 };
 104         };
 105
 106         cpu0_opp_table: opp_table0 {
 107                 compatible = "operating-points-v2";
 108                 opp-shared;
 109
 110                 opp@408000000 {
 111                         opp-hz = /bits/ 64 <408000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                         opp-suspend;
 115                 };
 116                 opp@600000000 {
 117                         opp-hz = /bits/ 64 <600000000>;
 118                         opp-microvolt = <950000>;
 119                         clock-latency-ns = <40000>;
 120                 };
 121                 opp@816000000 {
 122                         opp-hz = /bits/ 64 <816000000>;
 123                         opp-microvolt = <1000000>;
 124                         clock-latency-ns = <40000>;
 125                 };
 126                 opp@1008000000 {
 127                         opp-hz = /bits/ 64 <1008000000>;
 128                         opp-microvolt = <1100000>;
 129                         clock-latency-ns = <40000>;
 130                 };
 131                 opp@1200000000 {
 132                         opp-hz = /bits/ 64 <1200000000>;
 133                         opp-microvolt = <1225000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@1296000000 {
 137                         opp-hz = /bits/ 64 <1296000000>;
 138                         opp-microvolt = <1300000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141         };
 142
 143         arm-pmu {
 144                 compatible = "arm,cortex-a53-pmu";
 145                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 146                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 147                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 148                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 149                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 150         };
 151
 152         psci {
 153                 compatible = "arm,psci-1.0";
 154                 method = "smc";
 155         };
 156
 157         timer {
 158                 compatible = "arm,armv8-timer";
 159                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 160                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 161                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 162                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 163         };
 164
 165         xin24m: xin24m {
 166                 compatible = "fixed-clock";
 167                 #clock-cells = <0>;
 168                 clock-frequency = <24000000>;
 169                 clock-output-names = "xin24m";
 170         };
 171
 172         i2s0: i2s@ff000000 {
 173                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 174                 reg = <0x0 0xff000000 0x0 0x1000>;
 175                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 177                 clock-names = "i2s_clk", "i2s_hclk";
 178                 dmas = <&dmac 11>, <&dmac 12>;
 179                 #dma-cells = <2>;
 180                 dma-names = "tx", "rx";
 181                 status = "disabled";
 182         };
 183
 184         i2s1: i2s@ff010000 {
 185                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 186                 reg = <0x0 0xff010000 0x0 0x1000>;
 187                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 188                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 189                 clock-names = "i2s_clk", "i2s_hclk";
 190                 dmas = <&dmac 14>, <&dmac 15>;
 191                 #dma-cells = <2>;
 192                 dma-names = "tx", "rx";
 193                 status = "disabled";
 194         };
 195
 196         i2s2: i2s@ff020000 {
 197                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 198                 reg = <0x0 0xff020000 0x0 0x1000>;
 199                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 200                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 201                 clock-names = "i2s_clk", "i2s_hclk";
 202                 dmas = <&dmac 0>, <&dmac 1>;
 203                 #dma-cells = <2>;
 204                 dma-names = "tx", "rx";
 205                 pinctrl-names = "default", "sleep";
 206                 pinctrl-0 = <&i2s2m0_mclk
 207                              &i2s2m0_sclk
 208                              &i2s2m0_lrcktx
 209                              &i2s2m0_lrckrx
 210                              &i2s2m0_sdo
 211                              &i2s2m0_sdi>;
 212                 pinctrl-1 = <&i2s2m0_sleep>;
 213                 status = "disabled";
 214         };
 215
 216         spdif: spdif@ff030000 {
 217                 compatible = "rockchip,rk3328-spdif";
 218                 reg = <0x0 0xff030000 0x0 0x1000>;
 219                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 220                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 221                 clock-names = "mclk", "hclk";
 222                 dmas = <&dmac 10>;
 223                 #dma-cells = <1>;
 224                 dma-names = "tx";
 225                 pinctrl-names = "default";
 226                 pinctrl-0 = <&spdifm2_tx>;
 227                 status = "disabled";
 228         };
 229
 230         grf: syscon@ff100000 {
 231                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 232                 reg = <0x0 0xff100000 0x0 0x1000>;
 233                 #address-cells = <1>;
 234                 #size-cells = <1>;
 235
 236                 io_domains: io-domains {
 237                         compatible = "rockchip,rk3328-io-voltage-domain";
 238                         status = "disabled";
 239                 };
 240
 241                 power: power-controller {
 242                         compatible = "rockchip,rk3328-power-controller";
 243                         #power-domain-cells = <1>;
 244                         #address-cells = <1>;
 245                         #size-cells = <0>;
 246                         status = "disabled";
 247
 248                         pd_hevc@RK3328_PD_HEVC {
 249                                 reg = <RK3328_PD_HEVC>;
 250                         };
 251                         pd_video@RK3328_PD_VIDEO {
 252                                 reg = <RK3328_PD_VIDEO>;
 253                         };
 254                         pd_vpu@RK3328_PD_VPU {
 255                                 reg = <RK3328_PD_VPU>;
 256                         };
 257                 };
 258
 259                 reboot-mode {
 260                         compatible = "syscon-reboot-mode";
 261                         offset = <0x5c8>;
 262                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 263                         mode-charge = <BOOT_CHARGING>;
 264                         mode-fastboot = <BOOT_FASTBOOT>;
 265                         mode-loader = <BOOT_BL_DOWNLOAD>;
 266                         mode-normal = <BOOT_NORMAL>;
 267                         mode-recovery = <BOOT_RECOVERY>;
 268                         mode-ums = <BOOT_UMS>;
 269                 };
 270         };
 271
 272         thermal-zones {
 273                 soc_thermal: soc-thermal {
 274                         polling-delay-passive = <20>; /* milliseconds */
 275                         polling-delay = <1000>; /* milliseconds */
 276                         sustainable-power = <1000>; /* milliwatts */
 277
 278                         thermal-sensors = <&tsadc 0>;
 279
 280                         trips {
 281                                 threshold: trip-point@0 {
 282                                         temperature = <70000>; /* millicelsius */
 283                                         hysteresis = <2000>; /* millicelsius */
 284                                         type = "passive";
 285                                 };
 286                                 target: trip-point@1 {
 287                                         temperature = <85000>; /* millicelsius */
 288                                         hysteresis = <2000>; /* millicelsius */
 289                                         type = "passive";
 290                                 };
 291                                 soc_crit: soc-crit {
 292                                         temperature = <95000>; /* millicelsius */
 293                                         hysteresis = <2000>; /* millicelsius */
 294                                         type = "critical";
 295                                 };
 296                         };
 297
 298                         cooling-maps {
 299                                 map0 {
 300                                         trip = <&target>;
 301                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 302                                         contribution = <4096>;
 303                                 };
 304                         };
 305                 };
 306
 307         };
 308
 309         tsadc: tsadc@ff250000 {
 310                 compatible = "rockchip,rk3328-tsadc";
 311                 reg = <0x0 0xff250000 0x0 0x100>;
 312                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
 313                 rockchip,grf = <&grf>;
 314                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 315                 clock-names = "tsadc", "apb_pclk";
 316                 assigned-clocks = <&cru SCLK_TSADC>;
 317                 assigned-clock-rates = <50000>;
 318                 resets = <&cru SRST_TSADC>;
 319                 reset-names = "tsadc-apb";
 320                 pinctrl-names = "init", "default", "sleep";
 321                 pinctrl-0 = <&otp_gpio>;
 322                 pinctrl-1 = <&otp_out>;
 323                 pinctrl-2 = <&otp_gpio>;
 324                 #thermal-sensor-cells = <1>;
 325                 rockchip,hw-tshut-temp = <100000>;
 326                 status = "disabled";
 327         };
 328
 329         uart0: serial@ff110000 {
 330                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 331                 reg = <0x0 0xff110000 0x0 0x100>;
 332                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 334                 clock-names = "baudclk", "apb_pclk";
 335                 reg-shift = <2>;
 336                 reg-io-width = <4>;
 337                 dmas = <&dmac 2>, <&dmac 3>;
 338                 #dma-cells = <2>;
 339                 pinctrl-names = "default";
 340                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 341                 status = "disabled";
 342         };
 343
 344         uart1: serial@ff120000 {
 345                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 346                 reg = <0x0 0xff120000 0x0 0x100>;
 347                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 348                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 349                 clock-names = "sclk_uart", "pclk_uart";
 350                 reg-shift = <2>;
 351                 reg-io-width = <4>;
 352                 dmas = <&dmac 4>, <&dmac 5>;
 353                 #dma-cells = <2>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 356                 status = "disabled";
 357         };
 358
 359         uart2: serial@ff130000 {
 360                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 361                 reg = <0x0 0xff130000 0x0 0x100>;
 362                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 364                 clock-names = "baudclk", "apb_pclk";
 365                 reg-shift = <2>;
 366                 reg-io-width = <4>;
 367                 dmas = <&dmac 6>, <&dmac 7>;
 368                 #dma-cells = <2>;
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&uart2m1_xfer>;
 371                 status = "disabled";
 372         };
 373
 374         pmu: power-management@ff140000 {
 375                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 376                 reg = <0x0 0xff140000 0x0 0x1000>;
 377         };
 378
 379         i2c0: i2c@ff150000 {
 380                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 381                 reg = <0x0 0xff150000 0x0 0x1000>;
 382                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 383                 #address-cells = <1>;
 384                 #size-cells = <0>;
 385                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 386                 clock-names = "i2c", "pclk";
 387                 pinctrl-names = "default";
 388                 pinctrl-0 = <&i2c0_xfer>;
 389                 status = "disabled";
 390         };
 391
 392         i2c1: i2c@ff160000 {
 393                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 394                 reg = <0x0 0xff160000 0x0 0x1000>;
 395                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 399                 clock-names = "i2c", "pclk";
 400                 pinctrl-names = "default";
 401                 pinctrl-0 = <&i2c1_xfer>;
 402                 status = "disabled";
 403         };
 404
 405         i2c2: i2c@ff170000 {
 406                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 407                 reg = <0x0 0xff170000 0x0 0x1000>;
 408                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 409                 #address-cells = <1>;
 410                 #size-cells = <0>;
 411                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 412                 clock-names = "i2c", "pclk";
 413                 pinctrl-names = "default";
 414                 pinctrl-0 = <&i2c2_xfer>;
 415                 status = "disabled";
 416         };
 417
 418         i2c3: i2c@ff180000 {
 419                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 420                 reg = <0x0 0xff180000 0x0 0x1000>;
 421                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 422                 #address-cells = <1>;
 423                 #size-cells = <0>;
 424                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 425                 clock-names = "i2c", "pclk";
 426                 pinctrl-names = "default";
 427                 pinctrl-0 = <&i2c3_xfer>;
 428                 status = "disabled";
 429         };
 430
 431         spi0: spi@ff190000 {
 432                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 433                 reg = <0x0 0xff190000 0x0 0x1000>;
 434                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 435                 #address-cells = <1>;
 436                 #size-cells = <0>;
 437                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 438                 clock-names = "spiclk", "apb_pclk";
 439                 dmas = <&dmac 8>, <&dmac 9>;
 440                 #dma-cells = <2>;
 441                 dma-names = "tx", "rx";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 444                 status = "disabled";
 445         };
 446
 447         wdt: watchdog@ff1a0000 {
 448                 compatible = "snps,dw-wdt";
 449                 reg = <0x0 0xff1a0000 0x0 0x100>;
 450                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 451                 status = "disabled";
 452         };
 453
 454         pwm0: pwm@ff1b0000 {
 455                 compatible = "rockchip,rk3328-pwm";
 456                 reg = <0x0 0xff1b0000 0x0 0x10>;
 457                 #pwm-cells = <3>;
 458                 pinctrl-names = "default";
 459                 pinctrl-0 = <&pwm0_pin>;
 460                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 461                 clock-names = "pwm", "pclk";
 462                 status = "disabled";
 463         };
 464
 465         pwm1: pwm@ff1b0010 {
 466                 compatible = "rockchip,rk3328-pwm";
 467                 reg = <0x0 0xff1b0010 0x0 0x10>;
 468                 #pwm-cells = <3>;
 469                 pinctrl-names = "default";
 470                 pinctrl-0 = <&pwm1_pin>;
 471                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 472                 clock-names = "pwm", "pclk";
 473                 status = "disabled";
 474         };
 475
 476         pwm2: pwm@ff1b0020 {
 477                 compatible = "rockchip,rk3328-pwm";
 478                 reg = <0x0 0xff1b0020 0x0 0x10>;
 479                 #pwm-cells = <3>;
 480                 pinctrl-names = "default";
 481                 pinctrl-0 = <&pwm2_pin>;
 482                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 483                 clock-names = "pwm", "pclk";
 484                 status = "disabled";
 485         };
 486
 487         pwm3: pwm@ff1b0030 {
 488                 compatible = "rockchip,rk3328-pwm";
 489                 reg = <0x0 0xff1b0030 0x0 0x10>;
 490                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 491                 #pwm-cells = <3>;
 492                 pinctrl-names = "default";
 493                 pinctrl-0 = <&pwmir_pin>;
 494                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 495                 clock-names = "pwm", "pclk";
 496                 status = "disabled";
 497         };
 498
 499         amba {
 500                 compatible = "simple-bus";
 501                 #address-cells = <2>;
 502                 #size-cells = <2>;
 503                 ranges;
 504
 505                 dmac: dmac@ff1f0000 {
 506                         compatible = "arm,pl330", "arm,primecell";
 507                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 508                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 509                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 510                         clocks = <&cru ACLK_DMAC>;
 511                         clock-names = "apb_pclk";
 512                         #dma-cells = <1>;
 513                 };
 514         };
 515
 516         saradc: saradc@ff280000 {
 517                 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
 518                 reg = <0x0 0xff280000 0x0 0x100>;
 519                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 520                 #io-channel-cells = <1>;
 521                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 522                 clock-names = "saradc", "apb_pclk";
 523                 resets = <&cru SRST_SARADC_P>;
 524                 reset-names = "saradc-apb";
 525                 status = "disabled";
 526         };
 527
 528         vop: vop@ff370000 {
 529                 compatible = "rockchip,rk3328-vop";
 530                 reg = <0x0 0xff370000 0x0 0x3efc>;
 531                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 532                 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
 533                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 534                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 535                 reset-names = "axi", "ahb", "dclk";
 536                 iommus = <&vop_mmu>;
 537                 status = "disabled";
 538
 539                 vop_out: port {
 540                         #address-cells = <1>;
 541                         #size-cells = <0>;
 542                 };
 543         };
 544
 545         vop_mmu: iommu@ff373f00 {
 546                 compatible = "rockchip,iommu";
 547                 reg = <0x0 0xff373f00 0x0 0x100>;
 548                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 549                 interrupt-names = "vop_mmu";
 550                 #iommu-cells = <0>;
 551                 status = "disabled";
 552         };
 553
 554         display_subsystem: display-subsystem {
 555                 compatible = "rockchip,display-subsystem";
 556                 ports = <&vop_out>;
 557                 status = "disabled";
 558         };
 559
 560         cru: clock-controller@ff440000 {
 561                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 562                 reg = <0x0 0xff440000 0x0 0x1000>;
 563                 rockchip,grf = <&grf>;
 564                 #clock-cells = <1>;
 565                 #reset-cells = <1>;
 566                 assigned-clocks =
 567                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 568                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 569                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 570                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 571                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 572                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 573                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 574                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 575                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 576                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 577                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 578                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 579                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 580                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 581                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 582                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 583                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 584                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 585                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 586                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 587                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 588                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 589                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 590                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 591                 assigned-clock-parents =
 592                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 593                         <&cru PLL_GPLL>, <&xin24m>,
 594                         <&xin24m>, <&xin24m>;
 595                 assigned-clock-rates =
 596                         <0>, <61440000>,
 597                         <0>, <24000000>,
 598                         <24000000>, <24000000>,
 599                         <15000000>, <15000000>,
 600                         <100000000>, <100000000>,
 601                         <100000000>, <100000000>,
 602                         <50000000>, <100000000>,
 603                         <100000000>, <100000000>,
 604                         <50000000>, <50000000>,
 605                         <50000000>, <50000000>,
 606                         <24000000>, <600000000>,
 607                         <491520000>, <1200000000>,
 608                         <150000000>, <75000000>,
 609                         <75000000>, <150000000>,
 610                         <75000000>, <75000000>,
 611                         <300000000>, <100000000>,
 612                         <300000000>, <200000000>,
 613                         <400000000>, <500000000>,
 614                         <200000000>, <300000000>,
 615                         <300000000>, <250000000>,
 616                         <200000000>, <100000000>,
 617                         <24000000>, <100000000>,
 618                         <150000000>, <50000000>,
 619                         <32768>, <32768>;
 620         };
 621
 622         usb2phy_grf: syscon@ff450000 {
 623                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 624                              "simple-mfd";
 625                 reg = <0x0 0xff450000 0x0 0x10000>;
 626                 #address-cells = <1>;
 627                 #size-cells = <1>;
 628
 629                 u2phy: usb2-phy@100 {
 630                         compatible = "rockchip,rk3328-usb2phy";
 631                         reg = <0x100 0x10>;
 632                         clocks = <&xin24m>;
 633                         clock-names = "phyclk";
 634                         #clock-cells = <0>;
 635                         assigned-clocks = <&cru USB480M>;
 636                         assigned-clock-parents = <&u2phy>;
 637                         clock-output-names = "usb480m_phy";
 638                         status = "disabled";
 639
 640                         u2phy_host: host-port {
 641                                 #phy-cells = <0>;
 642                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 643                                 interrupt-names = "linestate";
 644                                 status = "disabled";
 645                         };
 646
 647                         u2phy_otg: otg-port {
 648                                 #phy-cells = <0>;
 649                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 650                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 651                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 652                                 interrupt-names = "otg-bvalid", "otg-id",
 653                                                   "linestate";
 654                                 status = "disabled";
 655                         };
 656                 };
 657         };
 658
 659         usb3phy_grf: syscon@ff460000 {
 660                 compatible = "rockchip,usb3phy-grf", "syscon";
 661                 reg = <0x0 0xff460000 0x0 0x1000>;
 662         };
 663
 664         u3phy: usb3-phy@ff470000 {
 665                 compatible = "rockchip,rk3328-u3phy";
 666                 reg = <0x0 0xff470000 0x0 0x0>;
 667                 rockchip,u3phygrf = <&usb3phy_grf>;
 668                 rockchip,grf = <&grf>;
 669                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 670                 interrupt-names = "linestate";
 671                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 672                 clock-names = "u3phy-otg", "u3phy-pipe";
 673                 resets = <&cru SRST_USB3PHY_U2>,
 674                          <&cru SRST_USB3PHY_U3>,
 675                          <&cru SRST_USB3PHY_PIPE>,
 676                          <&cru SRST_USB3OTG_UTMI>,
 677                          <&cru SRST_USB3PHY_OTG_P>,
 678                          <&cru SRST_USB3PHY_PIPE_P>;
 679                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 680                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 681                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 682                 #address-cells = <2>;
 683                 #size-cells = <2>;
 684                 ranges;
 685                 status = "disabled";
 686
 687                 u3phy_utmi: utmi@ff470000 {
 688                         reg = <0x0 0xff470000 0x0 0x8000>;
 689                         #phy-cells = <0>;
 690                         status = "disabled";
 691                 };
 692
 693                 u3phy_pipe: pipe@ff478000 {
 694                         reg = <0x0 0xff478000 0x0 0x8000>;
 695                         #phy-cells = <0>;
 696                         status = "disabled";
 697                 };
 698         };
 699
 700         sdmmc: rksdmmc@ff500000 {
 701                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 702                 reg = <0x0 0xff500000 0x0 0x4000>;
 703                 clock-freq-min-max = <400000 150000000>;
 704                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 705                 clock-names = "biu", "ciu";
 706                 fifo-depth = <0x100>;
 707                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 708                 status = "disabled";
 709         };
 710
 711         sdio: dwmmc@ff510000 {
 712                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 713                 reg = <0x0 0xff510000 0x0 0x4000>;
 714                 clock-freq-min-max = <400000 150000000>;
 715                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 716                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 717                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 718                 fifo-depth = <0x100>;
 719                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 720                 status = "disabled";
 721         };
 722
 723         emmc: rksdmmc@ff520000 {
 724                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 725                 reg = <0x0 0xff520000 0x0 0x4000>;
 726                 clock-freq-min-max = <400000 150000000>;
 727                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 728                 clock-names = "biu", "ciu";
 729                 fifo-depth = <0x100>;
 730                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 731                 status = "disabled";
 732         };
 733
 734         gmac2io: eth@ff540000 {
 735                 compatible = "rockchip,rk3328-gmac";
 736                 reg = <0x0 0xff540000 0x0 0x10000>;
 737                 rockchip,grf = <&grf>;
 738                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 739                 interrupt-names = "macirq";
 740                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 741                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 742                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 743                          <&cru PCLK_MAC2IO>;
 744                 clock-names = "stmmaceth", "mac_clk_rx",
 745                               "mac_clk_tx", "clk_mac_ref",
 746                               "clk_mac_refout", "aclk_mac",
 747                               "pclk_mac";
 748                 resets = <&cru SRST_GMAC2IO_A>;
 749                 reset-names = "stmmaceth";
 750                 status = "disabled";
 751         };
 752
 753         usb20_otg: usb@ff580000 {
 754                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 755                              "snps,dwc2";
 756                 reg = <0x0 0xff580000 0x0 0x40000>;
 757                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 758                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 759                 clock-names = "otg", "otg_pmu";
 760                 dr_mode = "otg";
 761                 g-np-tx-fifo-size = <16>;
 762                 g-rx-fifo-size = <275>;
 763                 g-tx-fifo-size = <256 128 128 64 64 32>;
 764                 g-use-dma;
 765                 phys = <&u2phy_otg>;
 766                 phy-names = "usb2-phy";
 767                 status = "disabled";
 768         };
 769
 770         usb_host0_ehci: usb@ff5c0000 {
 771                 compatible = "generic-ehci";
 772                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 773                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 774                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 775                          <&u2phy>;
 776                 clock-names = "usbhost", "arbiter", "utmi";
 777                 phys = <&u2phy_host>;
 778                 phy-names = "usb";
 779                 status = "disabled";
 780         };
 781
 782         usb_host0_ohci: usb@ff5d0000 {
 783                 compatible = "generic-ohci";
 784                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 785                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 786                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 787                          <&u2phy>;
 788                 clock-names = "usbhost", "arbiter", "utmi";
 789                 phys = <&u2phy_host>;
 790                 phy-names = "usb";
 791                 status = "disabled";
 792         };
 793
 794         sdmmc_ext: rksdmmc@ff5f0000 {
 795                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 796                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 797                 clock-freq-min-max = <400000 150000000>;
 798                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 799                 clock-names = "biu", "ciu";
 800                 fifo-depth = <0x100>;
 801                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 802                 status = "disabled";
 803         };
 804
 805         usbdrd3: usb@ff600000 {
 806                 compatible = "rockchip,rk3328-dwc3";
 807                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 808                          <&cru ACLK_USB3OTG>;
 809                 clock-names = "ref_clk", "suspend_clk",
 810                               "bus_clk";
 811                 #address-cells = <2>;
 812                 #size-cells = <2>;
 813                 ranges;
 814                 status = "disabled";
 815
 816                 usbdrd_dwc3: dwc3@ff600000 {
 817                         compatible = "snps,dwc3";
 818                         reg = <0x0 0xff600000 0x0 0x100000>;
 819                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 820                         dr_mode = "host";
 821                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 822                         phy-names = "usb2-phy", "usb3-phy";
 823                         phy_type = "utmi_wide";
 824                         snps,dis_enblslpm_quirk;
 825                         snps,dis-u2-freeclk-exists-quirk;
 826                         snps,dis_u2_susphy_quirk;
 827                         snps,dis-u3-autosuspend-quirk;
 828                         snps,dis_u3_susphy_quirk;
 829                         snps,dis-del-phy-power-chg-quirk;
 830                         status = "disabled";
 831                 };
 832         };
 833
 834         gic: interrupt-controller@ff811000 {
 835                 compatible = "arm,gic-400";
 836                 #interrupt-cells = <3>;
 837                 #address-cells = <0>;
 838                 interrupt-controller;
 839                 reg = <0x0 0xff811000 0 0x1000>,
 840                       <0x0 0xff812000 0 0x2000>,
 841                       <0x0 0xff814000 0 0x2000>,
 842                       <0x0 0xff816000 0 0x2000>;
 843                 interrupts = <GIC_PPI 9
 844                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 845         };
 846
 847         pinctrl: pinctrl {
 848                 compatible = "rockchip,rk3328-pinctrl";
 849                 rockchip,grf = <&grf>;
 850                 #address-cells = <2>;
 851                 #size-cells = <2>;
 852                 ranges;
 853
 854                 gpio0: gpio0@ff210000 {
 855                         compatible = "rockchip,gpio-bank";
 856                         reg = <0x0 0xff210000 0x0 0x100>;
 857                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 858                         clocks = <&cru PCLK_GPIO0>;
 859
 860                         gpio-controller;
 861                         #gpio-cells = <2>;
 862
 863                         interrupt-controller;
 864                         #interrupt-cells = <2>;
 865                 };
 866
 867                 gpio1: gpio1@ff220000 {
 868                         compatible = "rockchip,gpio-bank";
 869                         reg = <0x0 0xff220000 0x0 0x100>;
 870                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 871                         clocks = <&cru PCLK_GPIO1>;
 872
 873                         gpio-controller;
 874                         #gpio-cells = <2>;
 875
 876                         interrupt-controller;
 877                         #interrupt-cells = <2>;
 878                 };
 879
 880                 gpio2: gpio2@ff230000 {
 881                         compatible = "rockchip,gpio-bank";
 882                         reg = <0x0 0xff230000 0x0 0x100>;
 883                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 884                         clocks = <&cru PCLK_GPIO2>;
 885
 886                         gpio-controller;
 887                         #gpio-cells = <2>;
 888
 889                         interrupt-controller;
 890                         #interrupt-cells = <2>;
 891                 };
 892
 893                 gpio3: gpio3@ff240000 {
 894                         compatible = "rockchip,gpio-bank";
 895                         reg = <0x0 0xff240000 0x0 0x100>;
 896                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 897                         clocks = <&cru PCLK_GPIO3>;
 898
 899                         gpio-controller;
 900                         #gpio-cells = <2>;
 901
 902                         interrupt-controller;
 903                         #interrupt-cells = <2>;
 904                 };
 905
 906                 pcfg_pull_up: pcfg-pull-up {
 907                         bias-pull-up;
 908                 };
 909
 910                 pcfg_pull_down: pcfg-pull-down {
 911                         bias-pull-down;
 912                 };
 913
 914                 pcfg_pull_none: pcfg-pull-none {
 915                         bias-disable;
 916                 };
 917
 918                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 919                         bias-disable;
 920                         drive-strength = <2>;
 921                 };
 922
 923                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 924                         bias-pull-up;
 925                         drive-strength = <2>;
 926                 };
 927
 928                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 929                         bias-pull-up;
 930                         drive-strength = <4>;
 931                 };
 932
 933                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 934                         bias-disable;
 935                         drive-strength = <4>;
 936                 };
 937
 938                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 939                         bias-pull-down;
 940                         drive-strength = <4>;
 941                 };
 942
 943                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 944                         bias-disable;
 945                         drive-strength = <8>;
 946                 };
 947
 948                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 949                         bias-pull-up;
 950                         drive-strength = <8>;
 951                 };
 952
 953                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 954                         bias-disable;
 955                         drive-strength = <12>;
 956                 };
 957
 958                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 959                         bias-pull-up;
 960                         drive-strength = <12>;
 961                 };
 962
 963                 pcfg_output_high: pcfg-output-high {
 964                         output-high;
 965                 };
 966
 967                 pcfg_output_low: pcfg-output-low {
 968                         output-low;
 969                 };
 970
 971                 pcfg_input_high: pcfg-input-high {
 972                         bias-pull-up;
 973                         input-enable;
 974                 };
 975
 976                 pcfg_input: pcfg-input {
 977                         input-enable;
 978                 };
 979
 980                 i2c0 {
 981                         i2c0_xfer: i2c0-xfer {
 982                                 rockchip,pins =
 983                                         <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
 984                                         <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
 985                         };
 986                 };
 987
 988                 i2c1 {
 989                         i2c1_xfer: i2c1-xfer {
 990                                 rockchip,pins =
 991                                         <2 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
 992                                         <2 RK_PA5 RK_FUNC_2 &pcfg_pull_none>;
 993                         };
 994                 };
 995
 996                 i2c2 {
 997                         i2c2_xfer: i2c2-xfer {
 998                                 rockchip,pins =
 999                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
1000                                         <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>;
1001                         };
1002                 };
1003
1004                 i2c3 {
1005                         i2c3_xfer: i2c3-xfer {
1006                                 rockchip,pins =
1007                                         <0 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1008                                         <0 RK_PA6 RK_FUNC_2 &pcfg_pull_none>;
1009                         };
1010                         i2c3_gpio: i2c3-gpio {
1011                                 rockchip,pins =
1012                                         <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1013                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1014                         };
1015                 };
1016
1017                 hdmi_i2c {
1018                         hdmii2c_xfer: hdmii2c-xfer {
1019                                 rockchip,pins =
1020                                         <0 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,
1021                                         <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1022                         };
1023                 };
1024
1025                 tsadc {
1026                         otp_gpio: otp-gpio {
1027                                 rockchip,pins =
1028                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1029                         };
1030
1031                         otp_out: otp-out {
1032                                 rockchip,pins =
1033                                         <2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>;
1034                         };
1035                 };
1036
1037                 uart0 {
1038                         uart0_xfer: uart0-xfer {
1039                                 rockchip,pins =
1040                                         <1 RK_PB1 RK_FUNC_1 &pcfg_pull_up>,
1041                                         <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
1042                         };
1043
1044                         uart0_cts: uart0-cts {
1045                                 rockchip,pins =
1046                                         <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
1047                         };
1048
1049                         uart0_rts: uart0-rts {
1050                                 rockchip,pins =
1051                                         <1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
1052                         };
1053
1054                         uart0_rts_gpio: uart0-rts-gpio {
1055                                 rockchip,pins =
1056                                         <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1057                         };
1058                 };
1059
1060                 uart1 {
1061                         uart1_xfer: uart1-xfer {
1062                                 rockchip,pins =
1063                                         <3 RK_PA4 RK_FUNC_4 &pcfg_pull_up>,
1064                                         <3 RK_PA6 RK_FUNC_4 &pcfg_pull_none>;
1065                         };
1066
1067                         uart1_cts: uart1-cts {
1068                                 rockchip,pins =
1069                                         <3 RK_PA7 RK_FUNC_4 &pcfg_pull_none>;
1070                         };
1071
1072                         uart1_rts: uart1-rts {
1073                                 rockchip,pins =
1074                                         <3 RK_PA5 RK_FUNC_4 &pcfg_pull_none>;
1075                         };
1076
1077                         uart1_rts_gpio: uart1-rts-gpio {
1078                                 rockchip,pins =
1079                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1080                         };
1081                 };
1082
1083                 uart2-0 {
1084                         uart2m0_xfer: uart2m0-xfer {
1085                                 rockchip,pins =
1086                                         <1 RK_PA0 RK_FUNC_2 &pcfg_pull_up>,
1087                                         <1 RK_PA1 RK_FUNC_2 &pcfg_pull_none>;
1088                         };
1089                 };
1090
1091                 uart2-1 {
1092                         uart2m1_xfer: uart2m1-xfer {
1093                                 rockchip,pins =
1094                                         <2 RK_PA0 RK_FUNC_1 &pcfg_pull_up>,
1095                                         <2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
1096                         };
1097                 };
1098
1099                 spi0-0 {
1100                         spi0m0_clk: spi0m0-clk {
1101                                 rockchip,pins =
1102                                         <2 RK_PB0 RK_FUNC_1 &pcfg_pull_up>;
1103                         };
1104
1105                         spi0m0_cs0: spi0m0-cs0 {
1106                                 rockchip,pins =
1107                                         <2 RK_PB3 RK_FUNC_1 &pcfg_pull_up>;
1108                         };
1109
1110                         spi0m0_tx: spi0m0-tx {
1111                                 rockchip,pins =
1112                                         <2 RK_PB1 RK_FUNC_1 &pcfg_pull_up>;
1113                         };
1114
1115                         spi0m0_rx: spi0m0-rx {
1116                                 rockchip,pins =
1117                                         <2 RK_PB2 RK_FUNC_1 &pcfg_pull_up>;
1118                         };
1119
1120                         spi0m0_cs1: spi0m0-cs1 {
1121                                 rockchip,pins =
1122                                         <2 RK_PB4 RK_FUNC_1 &pcfg_pull_up>;
1123                         };
1124                 };
1125
1126                 spi0-1 {
1127                         spi0m1_clk: spi0m1-clk {
1128                                 rockchip,pins =
1129                                         <3 RK_PC7 RK_FUNC_2 &pcfg_pull_up>;
1130                         };
1131
1132                         spi0m1_cs0: spi0m1-cs0 {
1133                                 rockchip,pins =
1134                                         <3 RK_PD2 RK_FUNC_2 &pcfg_pull_up>;
1135                         };
1136
1137                         spi0m1_tx: spi0m1-tx {
1138                                 rockchip,pins =
1139                                         <3 RK_PD1 RK_FUNC_2 &pcfg_pull_up>;
1140                         };
1141
1142                         spi0m1_rx: spi0m1-rx {
1143                                 rockchip,pins =
1144                                         <3 RK_PD0 RK_FUNC_2 &pcfg_pull_up>;
1145                         };
1146
1147                         spi0m1_cs1: spi0m1-cs1 {
1148                                 rockchip,pins =
1149                                         <3 RK_PD3 RK_FUNC_2 &pcfg_pull_up>;
1150                         };
1151                 };
1152
1153                 spi0-2 {
1154                         spi0m2_clk: spi0m2-clk {
1155                                 rockchip,pins =
1156                                         <3 RK_PA0 RK_FUNC_4 &pcfg_pull_up>;
1157                         };
1158
1159                         spi0m2_cs0: spi0m2-cs0 {
1160                                 rockchip,pins =
1161                                         <3 RK_PB0 RK_FUNC_3 &pcfg_pull_up>;
1162                         };
1163
1164                         spi0m2_tx: spi0m2-tx {
1165                                 rockchip,pins =
1166                                         <3 RK_PA1 RK_FUNC_4 &pcfg_pull_up>;
1167                         };
1168
1169                         spi0m2_rx: spi0m2-rx {
1170                                 rockchip,pins =
1171                                         <3 RK_PA2 RK_FUNC_4 &pcfg_pull_up>;
1172                         };
1173                 };
1174
1175                 i2s1 {
1176                         i2s1_mclk: i2s1-mclk {
1177                                 rockchip,pins =
1178                                         <2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
1179                         };
1180
1181                         i2s1_sclk: i2s1-sclk {
1182                                 rockchip,pins =
1183                                         <2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>;
1184                         };
1185
1186                         i2s1_lrckrx: i2s1-lrckrx {
1187                                 rockchip,pins =
1188                                         <2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
1189                         };
1190
1191                         i2s1_lrcktx: i2s1-lrcktx {
1192                                 rockchip,pins =
1193                                         <2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195
1196                         i2s1_sdi: i2s1-sdi {
1197                                 rockchip,pins =
1198                                         <2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200
1201                         i2s1_sdo: i2s1-sdo {
1202                                 rockchip,pins =
1203                                         <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1204                         };
1205
1206                         i2s1_sdio1: i2s1-sdio1 {
1207                                 rockchip,pins =
1208                                         <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
1209                         };
1210
1211                         i2s1_sdio2: i2s1-sdio2 {
1212                                 rockchip,pins =
1213                                         <2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1214                         };
1215
1216                         i2s1_sdio3: i2s1-sdio3 {
1217                                 rockchip,pins =
1218                                         <2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1219                         };
1220
1221                         i2s1_sleep: i2s1-sleep {
1222                                 rockchip,pins =
1223                                         <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1224                                         <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1225                                         <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1226                                         <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1227                                         <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1228                                         <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1229                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1230                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1231                                         <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1232                         };
1233                 };
1234
1235                 i2s2-0 {
1236                         i2s2m0_mclk: i2s2m0-mclk {
1237                                 rockchip,pins =
1238                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1239                         };
1240
1241                         i2s2m0_sclk: i2s2m0-sclk {
1242                                 rockchip,pins =
1243                                         <1 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1244                         };
1245
1246                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1247                                 rockchip,pins =
1248                                         <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
1249                         };
1250
1251                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1252                                 rockchip,pins =
1253                                         <1 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1254                         };
1255
1256                         i2s2m0_sdi: i2s2m0-sdi {
1257                                 rockchip,pins =
1258                                         <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
1259                         };
1260
1261                         i2s2m0_sdo: i2s2m0-sdo {
1262                                 rockchip,pins =
1263                                         <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
1264                         };
1265
1266                         i2s2m0_sleep: i2s2m0-sleep {
1267                                 rockchip,pins =
1268                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1269                                         <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1270                                         <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1271                                         <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1272                                         <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1273                                         <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1274                         };
1275                 };
1276
1277                 i2s2-1 {
1278                         i2s2m1_mclk: i2s2m1-mclk {
1279                                 rockchip,pins =
1280                                         <1 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
1281                         };
1282
1283                         i2s2m1_sclk: i2s2m1-sclk {
1284                                 rockchip,pins =
1285                                         <3 RK_PA0 RK_FUNC_6 &pcfg_pull_none>;
1286                         };
1287
1288                         i2s2m1_lrckrx: i2sm1-lrckrx {
1289                                 rockchip,pins =
1290                                         <3 RK_PB0 RK_FUNC_6 &pcfg_pull_none>;
1291                         };
1292
1293                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1294                                 rockchip,pins =
1295                                         <3 RK_PB0 RK_FUNC_4 &pcfg_pull_none>;
1296                         };
1297
1298                         i2s2m1_sdi: i2s2m1-sdi {
1299                                 rockchip,pins =
1300                                         <3 RK_PA2 RK_FUNC_6 &pcfg_pull_none>;
1301                         };
1302
1303                         i2s2m1_sdo: i2s2m1-sdo {
1304                                 rockchip,pins =
1305                                         <3 RK_PA1 RK_FUNC_6 &pcfg_pull_none>;
1306                         };
1307
1308                         i2s2m1_sleep: i2s2m1-sleep {
1309                                 rockchip,pins =
1310                                         <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1311                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1312                                         <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1313                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1314                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1315                         };
1316                 };
1317
1318                 spdif-0 {
1319                         spdifm0_tx: spdifm0-tx {
1320                                 rockchip,pins =
1321                                         <0 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 spdif-1 {
1326                         spdifm1_tx: spdifm1-tx {
1327                                 rockchip,pins =
1328                                         <2 RK_PC1 RK_FUNC_2 &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 spdif-2 {
1333                         spdifm2_tx: spdifm2-tx {
1334                                 rockchip,pins =
1335                                         <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1336                         };
1337                 };
1338
1339                 sdmmc0-0 {
1340                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1341                                 rockchip,pins =
1342                                         <2 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1343                         };
1344
1345                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1346                                 rockchip,pins =
1347                                         <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1348                         };
1349                 };
1350
1351                 sdmmc0-1 {
1352                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1353                                 rockchip,pins =
1354                                         <0 RK_PD6 RK_FUNC_3 &pcfg_pull_up_4ma>;
1355                         };
1356
1357                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1358                                 rockchip,pins =
1359                                         <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1360                         };
1361                 };
1362
1363                 sdmmc0 {
1364                         sdmmc0_clk: sdmmc0-clk {
1365                                 rockchip,pins =
1366                                         <1 RK_PA6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1367                         };
1368
1369                         sdmmc0_cmd: sdmmc0-cmd {
1370                                 rockchip,pins =
1371                                         <1 RK_PA4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1372                         };
1373
1374                         sdmmc0_dectn: sdmmc0-dectn {
1375                                 rockchip,pins =
1376                                         <1 RK_PA5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1377                         };
1378
1379                         sdmmc0_wrprt: sdmmc0-wrprt {
1380                                 rockchip,pins =
1381                                         <1 RK_PA7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1382                         };
1383
1384                         sdmmc0_bus1: sdmmc0-bus1 {
1385                                 rockchip,pins =
1386                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1387                         };
1388
1389                         sdmmc0_bus4: sdmmc0-bus4 {
1390                                 rockchip,pins =
1391                                         <1 RK_PA0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1392                                         <1 RK_PA1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1393                                         <1 RK_PA2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1394                                         <1 RK_PA3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1395                         };
1396
1397                         sdmmc0_gpio: sdmmc0-gpio {
1398                                 rockchip,pins =
1399                                         <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1400                                         <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1401                                         <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1402                                         <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1403                                         <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1404                                         <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1405                                         <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1406                                         <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1407                         };
1408                 };
1409
1410                 sdmmc0ext {
1411                         sdmmc0ext_clk: sdmmc0ext-clk {
1412                                 rockchip,pins =
1413                                         <3 RK_PA2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1414                         };
1415
1416                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1417                                 rockchip,pins =
1418                                         <3 RK_PA0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1419                         };
1420
1421                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1422                                 rockchip,pins =
1423                                         <3 RK_PA3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1424                         };
1425
1426                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1427                                 rockchip,pins =
1428                                         <3 RK_PA1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1429                         };
1430
1431                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1432                                 rockchip,pins =
1433                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1434                         };
1435
1436                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1437                                 rockchip,pins =
1438                                         <3 RK_PA4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1439                                         <3 RK_PA5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1440                                         <3 RK_PA6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1441                                         <3 RK_PA7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1442                         };
1443
1444                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1445                                 rockchip,pins =
1446                                         <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1447                                         <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1448                                         <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1449                                         <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1450                                         <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1451                                         <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1452                                         <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1453                                         <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1454                         };
1455                 };
1456
1457                 sdmmc1 {
1458                         sdmmc1_clk: sdmmc1-clk {
1459                                 rockchip,pins =
1460                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_none_8ma>;
1461                         };
1462
1463                         sdmmc1_cmd: sdmmc1-cmd {
1464                                 rockchip,pins =
1465                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>;
1466                         };
1467
1468                         sdmmc1_pwren: sdmmc1-pwren {
1469                                 rockchip,pins =
1470                                         <1 RK_PC2 RK_FUNC_1 &pcfg_pull_up_8ma>;
1471                         };
1472
1473                         sdmmc1_wrprt: sdmmc1-wrprt {
1474                                 rockchip,pins =
1475                                         <1 RK_PC4 RK_FUNC_1 &pcfg_pull_up_8ma>;
1476                         };
1477
1478                         sdmmc1_dectn: sdmmc1-dectn {
1479                                 rockchip,pins =
1480                                         <1 RK_PC3 RK_FUNC_1 &pcfg_pull_up_8ma>;
1481                         };
1482
1483                         sdmmc1_bus1: sdmmc1-bus1 {
1484                                 rockchip,pins =
1485                                         <1 RK_PB6 RK_FUNC_1 &pcfg_pull_up_8ma>;
1486                         };
1487
1488                         sdmmc1_bus4: sdmmc1-bus4 {
1489                                 rockchip,pins =
1490                                         <1 RK_PB4 RK_FUNC_1 &pcfg_pull_up_8ma>,
1491                                         <1 RK_PB5 RK_FUNC_1 &pcfg_pull_up_8ma>,
1492                                         <1 RK_PC0 RK_FUNC_1 &pcfg_pull_up_8ma>,
1493                                         <1 RK_PC1 RK_FUNC_1 &pcfg_pull_up_8ma>;
1494                         };
1495
1496                         sdmmc1_gpio: sdmmc1-gpio {
1497                                 rockchip,pins =
1498                                         <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1499                                         <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1500                                         <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1501                                         <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1502                                         <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1503                                         <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1504                                         <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1505                                         <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1506                                         <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1507                         };
1508                 };
1509
1510                 emmc {
1511                         emmc_clk: emmc-clk {
1512                                 rockchip,pins =
1513                                         <3 RK_PC5 RK_FUNC_2 &pcfg_pull_none_12ma>;
1514                         };
1515
1516                         emmc_cmd: emmc-cmd {
1517                                 rockchip,pins =
1518                                         <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up_12ma>;
1519                         };
1520
1521                         emmc_pwren: emmc-pwren {
1522                                 rockchip,pins =
1523                                         <3 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
1524                         };
1525
1526                         emmc_rstnout: emmc-rstnout {
1527                                 rockchip,pins =
1528                                         <3 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
1529                         };
1530
1531                         emmc_bus1: emmc-bus1 {
1532                                 rockchip,pins =
1533                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1534                         };
1535
1536                         emmc_bus4: emmc-bus4 {
1537                                 rockchip,pins =
1538                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1539                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1540                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1541                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>;
1542                         };
1543
1544                         emmc_bus8: emmc-bus8 {
1545                                 rockchip,pins =
1546                                         <0 RK_PA7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1547                                         <2 RK_PD4 RK_FUNC_2 &pcfg_pull_up_12ma>,
1548                                         <2 RK_PD5 RK_FUNC_2 &pcfg_pull_up_12ma>,
1549                                         <2 RK_PD6 RK_FUNC_2 &pcfg_pull_up_12ma>,
1550                                         <2 RK_PD7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1551                                         <3 RK_PC0 RK_FUNC_2 &pcfg_pull_up_12ma>,
1552                                         <3 RK_PC1 RK_FUNC_2 &pcfg_pull_up_12ma>,
1553                                         <3 RK_PC2 RK_FUNC_2 &pcfg_pull_up_12ma>;
1554                         };
1555                 };
1556
1557                 pwm0 {
1558                         pwm0_pin: pwm0-pin {
1559                                 rockchip,pins =
1560                                         <2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
1561                         };
1562                 };
1563
1564                 pwm1 {
1565                         pwm1_pin: pwm1-pin {
1566                                 rockchip,pins =
1567                                         <2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 pwm2 {
1572                         pwm2_pin: pwm2-pin {
1573                                 rockchip,pins =
1574                                         <2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>;
1575                         };
1576                 };
1577
1578                 pwmir {
1579                         pwmir_pin: pwmir-pin {
1580                                 rockchip,pins =
1581                                         <2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>;
1582                         };
1583                 };
1584
1585                 gmac-1 {
1586                         rgmiim1_pins: rgmiim1-pins {
1587                                 rockchip,pins =
1588                                         /* mac_txclk */
1589                                         <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none_12ma>,
1590                                         /* mac_rxclk */
1591                                         <1 RK_PB5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1592                                         /* mac_mdio */
1593                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1594                                         /* mac_txen */
1595                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1596                                         /* mac_clk */
1597                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1598                                         /* mac_rxdv */
1599                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1600                                         /* mac_mdc */
1601                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1602                                         /* mac_rxd1 */
1603                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1604                                         /* mac_rxd0 */
1605                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1606                                         /* mac_txd1 */
1607                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1608                                         /* mac_txd0 */
1609                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1610                                         /* mac_rxd3 */
1611                                         <1 RK_PB6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1612                                         /* mac_rxd2 */
1613                                         <1 RK_PB7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1614                                         /* mac_txd3 */
1615                                         <1 RK_PC0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1616                                         /* mac_txd2 */
1617                                         <1 RK_PC1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1618
1619                                         /* mac_txclk */
1620                                         <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
1621                                         /* mac_txen */
1622                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1623                                         /* mac_clk */
1624                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1625                                         /* mac_txd1 */
1626                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1627                                         /* mac_txd0 */
1628                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
1629                                         /* mac_txd3 */
1630                                         <0 RK_PC7 RK_FUNC_1 &pcfg_pull_none>,
1631                                         /* mac_txd2 */
1632                                         <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
1633                         };
1634
1635                         rmiim1_pins: rmiim1-pins {
1636                                 rockchip,pins =
1637                                         /* mac_mdio */
1638                                         <1 RK_PC3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1639                                         /* mac_txen */
1640                                         <1 RK_PD1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1641                                         /* mac_clk */
1642                                         <1 RK_PC5 RK_FUNC_2 &pcfg_pull_none_2ma>,
1643                                         /* mac_rxer */
1644                                         <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none_2ma>,
1645                                         /* mac_rxdv */
1646                                         <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none_2ma>,
1647                                         /* mac_mdc */
1648                                         <1 RK_PC7 RK_FUNC_2 &pcfg_pull_none_2ma>,
1649                                         /* mac_rxd1 */
1650                                         <1 RK_PB2 RK_FUNC_2 &pcfg_pull_none_2ma>,
1651                                         /* mac_rxd0 */
1652                                         <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none_2ma>,
1653                                         /* mac_txd1 */
1654                                         <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none_12ma>,
1655                                         /* mac_txd0 */
1656                                         <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none_12ma>,
1657
1658                                         /* mac_mdio */
1659                                         <0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
1660                                         /* mac_txen */
1661                                         <0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
1662                                         /* mac_clk */
1663                                         <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>,
1664                                         /* mac_mdc */
1665                                         <0 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,
1666                                         /* mac_txd1 */
1667                                         <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
1668                                         /* mac_txd0 */
1669                                         <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
1670                         };
1671                 };
1672
1673                 gmac2phy {
1674                         fephyled_speed100: fephyled-speed100 {
1675                                 rockchip,pins =
1676                                         <0 RK_PD7 RK_FUNC_1 &pcfg_pull_none>;
1677                         };
1678
1679                         fephyled_speed10: fephyled-speed10 {
1680                                 rockchip,pins =
1681                                         <0 RK_PD6 RK_FUNC_1 &pcfg_pull_none>;
1682                         };
1683
1684                         fephyled_duplex: fephyled-duplex {
1685                                 rockchip,pins =
1686                                         <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
1687                         };
1688
1689                         fephyled_rxm0: fephyled-rxm0 {
1690                                 rockchip,pins =
1691                                         <0 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
1692                         };
1693
1694                         fephyled_txm0: fephyled-txm0 {
1695                                 rockchip,pins =
1696                                         <0 RK_PD5 RK_FUNC_2 &pcfg_pull_none>;
1697                         };
1698
1699                         fephyled_linkm0: fephyled-linkm0 {
1700                                 rockchip,pins =
1701                                         <0 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         fephyled_rxm1: fephyled-rxm1 {
1705                                 rockchip,pins =
1706                                         <2 RK_PD1 RK_FUNC_2 &pcfg_pull_none>;
1707                         };
1708
1709                         fephyled_txm1: fephyled-txm1 {
1710                                 rockchip,pins =
1711                                         <2 RK_PD1 RK_FUNC_3 &pcfg_pull_none>;
1712                         };
1713
1714                         fephyled_linkm1: fephyled-linkm1 {
1715                                 rockchip,pins =
1716                                         <2 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
1717                         };
1718                 };
1719
1720                 tsadc_pin {
1721                         tsadc_int: tsadc-int {
1722                                 rockchip,pins =
1723                                         <2 RK_PB5 RK_FUNC_2 &pcfg_pull_none>;
1724                         };
1725                         tsadc_gpio: tsadc-gpio {
1726                                 rockchip,pins =
1727                                         <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1728                         };
1729                 };
1730
1731                 hdmi_pin {
1732                         hdmi_cec: hdmi-cec {
1733                                 rockchip,pins =
1734                                         <0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
1735                         };
1736
1737                         hdmi_hpd: hdmi-hpd {
1738                                 rockchip,pins =
1739                                         <0 RK_PA4 RK_FUNC_1 &pcfg_pull_down>;
1740                         };
1741                 };
1742
1743                 cif-0 {
1744                         dvp_d2d9_m0:dvp-d2d9-m0 {
1745                                 rockchip,pins =
1746                                         /* cif_d0 */
1747                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1748                                         /* cif_d1 */
1749                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1750                                         /* cif_d2 */
1751                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1752                                         /* cif_d3 */
1753                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1754                                         /* cif_d4 */
1755                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1756                                         /* cif_d5m0 */
1757                                         <3 RK_PB1 RK_FUNC_2 &pcfg_pull_none>,
1758                                         /* cif_d6m0 */
1759                                         <3 RK_PB2 RK_FUNC_2 &pcfg_pull_none>,
1760                                         /* cif_d7m0 */
1761                                         <3 RK_PB3 RK_FUNC_2 &pcfg_pull_none>,
1762                                         /* cif_href */
1763                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1764                                         /* cif_vsync */
1765                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1766                                         /* cif_clkoutm0 */
1767                                         <3 RK_PA3 RK_FUNC_2 &pcfg_pull_none>,
1768                                         /* cif_clkin */
1769                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1770                         };
1771                 };
1772
1773                 cif-1 {
1774                         dvp_d2d9_m1:dvp-d2d9-m1 {
1775                                 rockchip,pins =
1776                                         /* cif_d0 */
1777                                         <3 RK_PA4 RK_FUNC_2 &pcfg_pull_none>,
1778                                         /* cif_d1 */
1779                                         <3 RK_PA5 RK_FUNC_2 &pcfg_pull_none>,
1780                                         /* cif_d2 */
1781                                         <3 RK_PA6 RK_FUNC_2 &pcfg_pull_none>,
1782                                         /* cif_d3 */
1783                                         <3 RK_PA7 RK_FUNC_2 &pcfg_pull_none>,
1784                                         /* cif_d4 */
1785                                         <3 RK_PB0 RK_FUNC_2 &pcfg_pull_none>,
1786                                         /* cif_d5m1 */
1787                                         <2 RK_PC0 RK_FUNC_4 &pcfg_pull_none>,
1788                                         /* cif_d6m1 */
1789                                         <2 RK_PC1 RK_FUNC_4 &pcfg_pull_none>,
1790                                         /* cif_d7m1 */
1791                                         <2 RK_PC2 RK_FUNC_4 &pcfg_pull_none>,
1792                                         /* cif_href */
1793                                         <3 RK_PA1 RK_FUNC_2 &pcfg_pull_none>,
1794                                         /* cif_vsync */
1795                                         <3 RK_PA0 RK_FUNC_2 &pcfg_pull_none>,
1796                                         /* cif_clkoutm1 */
1797                                         <2 RK_PB7 RK_FUNC_4 &pcfg_pull_none>,
1798                                         /* cif_clkin */
1799                                         <3 RK_PA2 RK_FUNC_2 &pcfg_pull_none>;
1800                         };
1801                 };
1802         };
1803 };