arch/arm64/boot/dts/rockchip/rk3328.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3328-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/arm-gic.h>
  46 #include <dt-bindings/interrupt-controller/irq.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/power/rk3328-power.h>
  50
  51 / {
  52         compatible = "rockchip,rk3328";
  53
  54         interrupt-parent = <&gic>;
  55         #address-cells = <2>;
  56         #size-cells = <2>;
  57
  58         aliases {
  59                 serial0 = &uart0;
  60                 serial1 = &uart1;
  61                 serial2 = &uart2;
  62                 i2c0 = &i2c0;
  63                 i2c1 = &i2c1;
  64                 i2c2 = &i2c2;
  65                 i2c3 = &i2c3;
  66         };
  67
  68         cpus {
  69                 #address-cells = <2>;
  70                 #size-cells = <0>;
  71
  72                 cpu0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53", "arm,armv8";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77 //                      clocks = <&cru ARMCLK>;
  78                         operating-points-v2 = <&cpu0_opp_table>;
  79                 };
  80                 cpu1: cpu@1 {
  81                         device_type = "cpu";
  82                         compatible = "arm,cortex-a53", "arm,armv8";
  83                         reg = <0x0 0x1>;
  84                         enable-method = "psci";
  85                 };
  86                 cpu2: cpu@2 {
  87                         device_type = "cpu";
  88                         compatible = "arm,cortex-a53", "arm,armv8";
  89                         reg = <0x0 0x2>;
  90                         enable-method = "psci";
  91                 };
  92                 cpu3: cpu@3 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a53", "arm,armv8";
  95                         reg = <0x0 0x3>;
  96                         enable-method = "psci";
  97                 };
  98         };
  99
 100         cpu0_opp_table: opp_table0 {
 101                 compatible = "operating-points-v2";
 102                 opp-shared;
 103
 104                 opp@408000000 {
 105                         opp-hz = /bits/ 64 <408000000>;
 106                         opp-microvolt = <950000>;
 107                         clock-latency-ns = <40000>;
 108                         opp-suspend;
 109                 };
 110                 opp@600000000 {
 111                         opp-hz = /bits/ 64 <600000000>;
 112                         opp-microvolt = <950000>;
 113                         clock-latency-ns = <40000>;
 114                 };
 115                 opp@816000000 {
 116                         opp-hz = /bits/ 64 <816000000>;
 117                         opp-microvolt = <1000000>;
 118                         clock-latency-ns = <40000>;
 119                 };
 120                 opp@1008000000 {
 121                         opp-hz = /bits/ 64 <1008000000>;
 122                         opp-microvolt = <1100000>;
 123                         clock-latency-ns = <40000>;
 124                 };
 125                 opp@1200000000 {
 126                         opp-hz = /bits/ 64 <1200000000>;
 127                         opp-microvolt = <1225000>;
 128                         clock-latency-ns = <40000>;
 129                 };
 130                 opp@1296000000 {
 131                         opp-hz = /bits/ 64 <1296000000>;
 132                         opp-microvolt = <1300000>;
 133                         clock-latency-ns = <40000>;
 134                 };
 135         };
 136
 137         arm-pmu {
 138                 compatible = "arm,cortex-a53-pmu";
 139                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 140                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
 141                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 142                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 143                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 144         };
 145
 146         psci {
 147                 compatible = "arm,psci-1.0";
 148                 method = "smc";
 149         };
 150
 151         timer {
 152                 compatible = "arm,armv8-timer";
 153                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 154                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 155                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 156                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 157         };
 158
 159         xin24m: xin24m {
 160                 compatible = "fixed-clock";
 161                 #clock-cells = <0>;
 162                 clock-frequency = <24000000>;
 163                 clock-output-names = "xin24m";
 164         };
 165
 166         i2s0: i2s@ff000000 {
 167                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 168                 reg = <0x0 0xff000000 0x0 0x1000>;
 169                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 170                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 171                 clock-names = "i2s_clk", "i2s_hclk";
 172                 dmas = <&dmac 11>, <&dmac 12>;
 173                 #dma-cells = <2>;
 174                 dma-names = "tx", "rx";
 175                 status = "disabled";
 176         };
 177
 178         i2s1: i2s@ff010000 {
 179                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 180                 reg = <0x0 0xff010000 0x0 0x1000>;
 181                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 182                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 dmas = <&dmac 14>, <&dmac 15>;
 185                 #dma-cells = <2>;
 186                 dma-names = "tx", "rx";
 187                 status = "disabled";
 188         };
 189
 190         i2s2: i2s@ff020000 {
 191                 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
 192                 reg = <0x0 0xff020000 0x0 0x1000>;
 193                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 194                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 195                 clock-names = "i2s_clk", "i2s_hclk";
 196                 dmas = <&dmac 0>, <&dmac 1>;
 197                 #dma-cells = <2>;
 198                 dma-names = "tx", "rx";
 199                 pinctrl-names = "default", "sleep";
 200                 pinctrl-0 = <&i2s2m0_mclk
 201                              &i2s2m0_sclk
 202                              &i2s2m0_lrcktx
 203                              &i2s2m0_lrckrx
 204                              &i2s2m0_sdo
 205                              &i2s2m0_sdi>;
 206                 pinctrl-1 = <&i2s2m0_sleep>;
 207                 status = "disabled";
 208         };
 209
 210         spdif: spdif@ff030000 {
 211                 compatible = "rockchip,rk3328-spdif";
 212                 reg = <0x0 0xff030000 0x0 0x1000>;
 213                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 214                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 215                 clock-names = "mclk", "hclk";
 216                 dmas = <&dmac 10>;
 217                 #dma-cells = <1>;
 218                 dma-names = "tx";
 219                 pinctrl-names = "default";
 220                 pinctrl-0 = <&spdifm2_tx>;
 221                 status = "disabled";
 222         };
 223
 224         grf: syscon@ff100000 {
 225                 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 226                 reg = <0x0 0xff100000 0x0 0x1000>;
 227                 #address-cells = <1>;
 228                 #size-cells = <1>;
 229
 230                 io_domains: io-domains {
 231                         compatible = "rockchip,rk3328-io-voltage-domain";
 232                         status = "disabled";
 233                 };
 234
 235                 power: power-controller {
 236                         compatible = "rockchip,rk3328-power-controller";
 237                         #power-domain-cells = <1>;
 238                         #address-cells = <1>;
 239                         #size-cells = <0>;
 240                         status = "disabled";
 241
 242                         pd_hevc@RK3328_PD_HEVC {
 243                                 reg = <RK3328_PD_HEVC>;
 244                         };
 245                         pd_video@RK3328_PD_VIDEO {
 246                                 reg = <RK3328_PD_VIDEO>;
 247                         };
 248                         pd_vpu@RK3328_PD_VPU {
 249                                 reg = <RK3328_PD_VPU>;
 250                         };
 251                 };
 252
 253                 reboot-mode {
 254                         compatible = "syscon-reboot-mode";
 255                         offset = <0x5c8>;
 256                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
 257                         mode-charge = <BOOT_CHARGING>;
 258                         mode-fastboot = <BOOT_FASTBOOT>;
 259                         mode-loader = <BOOT_BL_DOWNLOAD>;
 260                         mode-normal = <BOOT_NORMAL>;
 261                         mode-recovery = <BOOT_RECOVERY>;
 262                         mode-ums = <BOOT_UMS>;
 263                 };
 264         };
 265
 266         uart0: serial@ff110000 {
 267                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 268                 reg = <0x0 0xff110000 0x0 0x100>;
 269                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 270                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 271                 clock-names = "baudclk", "apb_pclk";
 272                 reg-shift = <2>;
 273                 reg-io-width = <4>;
 274                 dmas = <&dmac 2>, <&dmac 3>;
 275                 #dma-cells = <2>;
 276                 pinctrl-names = "default";
 277                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 278                 status = "disabled";
 279         };
 280
 281         uart1: serial@ff120000 {
 282                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 283                 reg = <0x0 0xff120000 0x0 0x100>;
 284                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 286                 clock-names = "sclk_uart", "pclk_uart";
 287                 reg-shift = <2>;
 288                 reg-io-width = <4>;
 289                 dmas = <&dmac 4>, <&dmac 5>;
 290                 #dma-cells = <2>;
 291                 pinctrl-names = "default";
 292                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 293                 status = "disabled";
 294         };
 295
 296         uart2: serial@ff130000 {
 297                 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
 298                 reg = <0x0 0xff130000 0x0 0x100>;
 299                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 300                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 301                 clock-names = "baudclk", "apb_pclk";
 302                 reg-shift = <2>;
 303                 reg-io-width = <4>;
 304                 dmas = <&dmac 6>, <&dmac 7>;
 305                 #dma-cells = <2>;
 306                 pinctrl-names = "default";
 307                 pinctrl-0 = <&uart2m1_xfer>;
 308                 status = "disabled";
 309         };
 310
 311         pmu: power-management@ff140000 {
 312                 compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
 313                 reg = <0x0 0xff140000 0x0 0x1000>;
 314         };
 315
 316         i2c0: i2c@ff150000 {
 317                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 318                 reg = <0x0 0xff150000 0x0 0x1000>;
 319                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 320                 #address-cells = <1>;
 321                 #size-cells = <0>;
 322                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
 323                 clock-names = "i2c", "pclk";
 324                 pinctrl-names = "default";
 325                 pinctrl-0 = <&i2c0_xfer>;
 326                 status = "disabled";
 327         };
 328
 329         i2c1: i2c@ff160000 {
 330                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 331                 reg = <0x0 0xff160000 0x0 0x1000>;
 332                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 333                 #address-cells = <1>;
 334                 #size-cells = <0>;
 335                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 336                 clock-names = "i2c", "pclk";
 337                 pinctrl-names = "default";
 338                 pinctrl-0 = <&i2c1_xfer>;
 339                 status = "disabled";
 340         };
 341
 342         i2c2: i2c@ff170000 {
 343                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 344                 reg = <0x0 0xff170000 0x0 0x1000>;
 345                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 349                 clock-names = "i2c", "pclk";
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c2_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff180000 {
 356                 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
 357                 reg = <0x0 0xff180000 0x0 0x1000>;
 358                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 362                 clock-names = "i2c", "pclk";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         spi0: spi@ff190000 {
 369                 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
 370                 reg = <0x0 0xff190000 0x0 0x1000>;
 371                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac 8>, <&dmac 9>;
 377                 #dma-cells = <2>;
 378                 dma-names = "tx", "rx";
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
 381                 status = "disabled";
 382         };
 383
 384         wdt: watchdog@ff1a0000 {
 385                 compatible = "snps,dw-wdt";
 386                 reg = <0x0 0xff1a0000 0x0 0x100>;
 387                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 388                 status = "disabled";
 389         };
 390
 391         pwm0: pwm@ff1b0000 {
 392                 compatible = "rockchip,rk3328-pwm";
 393                 reg = <0x0 0xff1b0000 0x0 0x10>;
 394                 #pwm-cells = <3>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&pwm0_pin>;
 397                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 398                 clock-names = "pwm", "pclk";
 399                 status = "disabled";
 400         };
 401
 402         pwm1: pwm@ff1b0010 {
 403                 compatible = "rockchip,rk3328-pwm";
 404                 reg = <0x0 0xff1b0010 0x0 0x10>;
 405                 #pwm-cells = <3>;
 406                 pinctrl-names = "default";
 407                 pinctrl-0 = <&pwm1_pin>;
 408                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 409                 clock-names = "pwm", "pclk";
 410                 status = "disabled";
 411         };
 412
 413         pwm2: pwm@ff1b0020 {
 414                 compatible = "rockchip,rk3328-pwm";
 415                 reg = <0x0 0xff1b0020 0x0 0x10>;
 416                 #pwm-cells = <3>;
 417                 pinctrl-names = "default";
 418                 pinctrl-0 = <&pwm2_pin>;
 419                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 420                 clock-names = "pwm", "pclk";
 421                 status = "disabled";
 422         };
 423
 424         pwm3: pwm@ff1b0030 {
 425                 compatible = "rockchip,rk3328-pwm";
 426                 reg = <0x0 0xff1b0030 0x0 0x10>;
 427                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 428                 #pwm-cells = <3>;
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&pwmir_pin>;
 431                 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
 432                 clock-names = "pwm", "pclk";
 433                 status = "disabled";
 434         };
 435
 436         amba {
 437                 compatible = "simple-bus";
 438                 #address-cells = <2>;
 439                 #size-cells = <2>;
 440                 ranges;
 441
 442                 dmac: dmac@ff1f0000 {
 443                         compatible = "arm,pl330", "arm,primecell";
 444                         reg = <0x0 0xff1f0000 0x0 0x4000>;
 445                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 446                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 447                         clocks = <&cru ACLK_DMAC>;
 448                         clock-names = "apb_pclk";
 449                         #dma-cells = <1>;
 450                 };
 451         };
 452
 453         saradc: saradc@ff280000 {
 454                 compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
 455                 reg = <0x0 0xff280000 0x0 0x100>;
 456                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 457                 #io-channel-cells = <1>;
 458                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 459                 clock-names = "saradc", "apb_pclk";
 460                 resets = <&cru SRST_SARADC_P>;
 461                 reset-names = "saradc-apb";
 462                 status = "disabled";
 463         };
 464
 465         cru: clock-controller@ff440000 {
 466                 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 467                 reg = <0x0 0xff440000 0x0 0x1000>;
 468                 rockchip,grf = <&grf>;
 469                 #clock-cells = <1>;
 470                 #reset-cells = <1>;
 471                 assigned-clocks =
 472                         <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
 473                         <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
 474                         <&cru SCLK_UART1>, <&cru SCLK_UART2>,
 475                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 476                         <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
 477                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 478                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 479                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 480                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 481                         <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
 482                         <&cru SCLK_WIFI>, <&cru ARMCLK>,
 483                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 484                         <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
 485                         <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
 486                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 487                         <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
 488                         <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
 489                         <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
 490                         <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
 491                         <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
 492                         <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
 493                         <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
 494                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
 495                         <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
 496                 assigned-clock-parents =
 497                         <&cru HDMIPHY>, <&cru PLL_APLL>,
 498                         <&cru PLL_GPLL>, <&xin24m>,
 499                         <&xin24m>, <&xin24m>;
 500                 assigned-clock-rates =
 501                         <0>, <61440000>,
 502                         <0>, <24000000>,
 503                         <24000000>, <24000000>,
 504                         <15000000>, <15000000>,
 505                         <100000000>, <100000000>,
 506                         <100000000>, <100000000>,
 507                         <50000000>, <100000000>,
 508                         <100000000>, <100000000>,
 509                         <50000000>, <50000000>,
 510                         <50000000>, <50000000>,
 511                         <24000000>, <600000000>,
 512                         <491520000>, <1200000000>,
 513                         <150000000>, <75000000>,
 514                         <75000000>, <150000000>,
 515                         <75000000>, <75000000>,
 516                         <300000000>, <100000000>,
 517                         <300000000>, <200000000>,
 518                         <400000000>, <500000000>,
 519                         <200000000>, <300000000>,
 520                         <300000000>, <250000000>,
 521                         <200000000>, <100000000>,
 522                         <24000000>, <100000000>,
 523                         <150000000>, <50000000>,
 524                         <32768>, <32768>;
 525         };
 526
 527         usb2phy_grf: syscon@ff450000 {
 528                 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
 529                              "simple-mfd";
 530                 reg = <0x0 0xff450000 0x0 0x10000>;
 531                 #address-cells = <1>;
 532                 #size-cells = <1>;
 533
 534                 u2phy: usb2-phy@100 {
 535                         compatible = "rockchip,rk3328-usb2phy";
 536                         reg = <0x100 0x10>;
 537                         clocks = <&xin24m>;
 538                         clock-names = "phyclk";
 539                         #clock-cells = <0>;
 540                         assigned-clocks = <&cru USB480M>;
 541                         assigned-clock-parents = <&u2phy>;
 542                         clock-output-names = "usb480m_phy";
 543                         status = "disabled";
 544
 545                         u2phy_host: host-port {
 546                                 #phy-cells = <0>;
 547                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 548                                 interrupt-names = "linestate";
 549                                 status = "disabled";
 550                         };
 551                 };
 552         };
 553
 554         usb3phy_grf: syscon@ff460000 {
 555                 compatible = "rockchip,usb3phy-grf", "syscon";
 556                 reg = <0x0 0xff460000 0x0 0x1000>;
 557         };
 558
 559         u3phy: usb3-phy@ff470000 {
 560                 compatible = "rockchip,rk3328-u3phy";
 561                 reg = <0x0 0xff470000 0x0 0x0>;
 562                 rockchip,u3phygrf = <&usb3phy_grf>;
 563                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 564                 interrupt-names = "linestate";
 565                 clocks = <&cru PCLK_USB3PHY_OTG>, <&cru PCLK_USB3PHY_PIPE>;
 566                 clock-names = "u3phy-otg", "u3phy-pipe";
 567                 resets = <&cru SRST_USB3PHY_U2>,
 568                          <&cru SRST_USB3PHY_U3>,
 569                          <&cru SRST_USB3PHY_PIPE>,
 570                          <&cru SRST_USB3OTG_UTMI>,
 571                          <&cru SRST_USB3PHY_OTG_P>,
 572                          <&cru SRST_USB3PHY_PIPE_P>;
 573                 reset-names = "u3phy-u2-por", "u3phy-u3-por",
 574                               "u3phy-pipe-mac", "u3phy-utmi-mac",
 575                               "u3phy-utmi-apb", "u3phy-pipe-apb";
 576                 #address-cells = <2>;
 577                 #size-cells = <2>;
 578                 ranges;
 579                 status = "disabled";
 580
 581                 u3phy_utmi: utmi@ff470000 {
 582                         reg = <0x0 0xff470000 0x0 0x8000>;
 583                         #phy-cells = <0>;
 584                         status = "disabled";
 585                 };
 586
 587                 u3phy_pipe: pipe@ff478000 {
 588                         reg = <0x0 0xff478000 0x0 0x8000>;
 589                         #phy-cells = <0>;
 590                         status = "disabled";
 591                 };
 592         };
 593
 594         sdmmc: rksdmmc@ff500000 {
 595                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 596                 reg = <0x0 0xff500000 0x0 0x4000>;
 597                 clock-freq-min-max = <400000 150000000>;
 598                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 599                 clock-names = "biu", "ciu";
 600                 fifo-depth = <0x100>;
 601                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 602                 status = "disabled";
 603         };
 604
 605         sdio: dwmmc@ff510000 {
 606                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 607                 reg = <0x0 0xff510000 0x0 0x4000>;
 608                 clock-freq-min-max = <400000 150000000>;
 609                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 610                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 611                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 612                 fifo-depth = <0x100>;
 613                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 614                 status = "disabled";
 615         };
 616
 617         emmc: rksdmmc@ff520000 {
 618                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 619                 reg = <0x0 0xff520000 0x0 0x4000>;
 620                 clock-freq-min-max = <400000 150000000>;
 621                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 622                 clock-names = "biu", "ciu";
 623                 fifo-depth = <0x100>;
 624                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 625                 status = "disabled";
 626         };
 627
 628         gmac2io: eth@ff540000 {
 629                 compatible = "rockchip,rk3328-gmac";
 630                 reg = <0x0 0xff540000 0x0 0x10000>;
 631                 rockchip,grf = <&grf>;
 632                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 633                 interrupt-names = "macirq";
 634                 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
 635                          <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
 636                          <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
 637                          <&cru PCLK_MAC2IO>;
 638                 clock-names = "stmmaceth", "mac_clk_rx",
 639                               "mac_clk_tx", "clk_mac_ref",
 640                               "clk_mac_refout", "aclk_mac",
 641                               "pclk_mac";
 642                 resets = <&cru SRST_GMAC2IO_A>;
 643                 reset-names = "stmmaceth";
 644                 status = "disabled";
 645         };
 646
 647         usb20_otg: usb@ff580000 {
 648                 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
 649                              "snps,dwc2";
 650                 reg = <0x0 0xff580000 0x0 0x40000>;
 651                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&cru HCLK_OTG>, <&cru HCLK_OTG_PMU>;
 653                 clock-names = "otg", "otg_pmu";
 654                 dr_mode = "otg";
 655                 g-np-tx-fifo-size = <16>;
 656                 g-rx-fifo-size = <275>;
 657                 g-tx-fifo-size = <256 128 128 64 64 32>;
 658                 g-use-dma;
 659                 status = "disabled";
 660         };
 661
 662         usb_host0_ehci: usb@ff5c0000 {
 663                 compatible = "generic-ehci";
 664                 reg = <0x0 0xff5c0000 0x0 0x10000>;
 665                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 666                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 667                          <&u2phy>;
 668                 clock-names = "usbhost", "arbiter", "utmi";
 669                 phys = <&u2phy_host>;
 670                 phy-names = "usb";
 671                 status = "disabled";
 672         };
 673
 674         usb_host0_ohci: usb@ff5d0000 {
 675                 compatible = "generic-ohci";
 676                 reg = <0x0 0xff5d0000 0x0 0x10000>;
 677                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 678                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 679                          <&u2phy>;
 680                 clock-names = "usbhost", "arbiter", "utmi";
 681                 phys = <&u2phy_host>;
 682                 phy-names = "usb";
 683                 status = "disabled";
 684         };
 685
 686         sdmmc_ext: rksdmmc@ff5f0000 {
 687                 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
 688                 reg = <0x0 0xff5f0000 0x0 0x4000>;
 689                 clock-freq-min-max = <400000 150000000>;
 690                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 691                 clock-names = "biu", "ciu";
 692                 fifo-depth = <0x100>;
 693                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 694                 status = "disabled";
 695         };
 696
 697         usbdrd3: usb@ff600000 {
 698                 compatible = "rockchip,rk3328-dwc3";
 699                 clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
 700                          <&cru ACLK_USB3OTG>;
 701                 clock-names = "ref_clk", "suspend_clk",
 702                               "bus_clk";
 703                 #address-cells = <2>;
 704                 #size-cells = <2>;
 705                 ranges;
 706                 status = "disabled";
 707
 708                 usbdrd_dwc3: dwc3@ff600000 {
 709                         compatible = "snps,dwc3";
 710                         reg = <0x0 0xff600000 0x0 0x100000>;
 711                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 712                         dr_mode = "host";
 713                         phys = <&u3phy_utmi>, <&u3phy_pipe>;
 714                         phy-names = "usb2-phy", "usb3-phy";
 715                         phy_type = "utmi_wide";
 716                         snps,dis_enblslpm_quirk;
 717                         snps,dis-u2-freeclk-exists-quirk;
 718                         snps,dis_u2_susphy_quirk;
 719                         snps,dis_u3_susphy_quirk;
 720                         snps,dis-del-phy-power-chg-quirk;
 721                         status = "disabled";
 722                 };
 723         };
 724
 725         gic: interrupt-controller@ff811000 {
 726                 compatible = "arm,gic-400";
 727                 #interrupt-cells = <3>;
 728                 #address-cells = <0>;
 729                 interrupt-controller;
 730                 reg = <0x0 0xff811000 0 0x1000>,
 731                       <0x0 0xff812000 0 0x2000>,
 732                       <0x0 0xff814000 0 0x2000>,
 733                       <0x0 0xff816000 0 0x2000>;
 734                 interrupts = <GIC_PPI 9
 735                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 736         };
 737
 738         pinctrl: pinctrl {
 739                 compatible = "rockchip,rk3328-pinctrl";
 740                 rockchip,grf = <&grf>;
 741                 #address-cells = <2>;
 742                 #size-cells = <2>;
 743                 ranges;
 744
 745                 gpio0: gpio0@ff210000 {
 746                         compatible = "rockchip,gpio-bank";
 747                         reg = <0x0 0xff210000 0x0 0x100>;
 748                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 749                         clocks = <&cru PCLK_GPIO0>;
 750
 751                         gpio-controller;
 752                         #gpio-cells = <2>;
 753
 754                         interrupt-controller;
 755                         #interrupt-cells = <2>;
 756                 };
 757
 758                 gpio1: gpio1@ff220000 {
 759                         compatible = "rockchip,gpio-bank";
 760                         reg = <0x0 0xff220000 0x0 0x100>;
 761                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&cru PCLK_GPIO1>;
 763
 764                         gpio-controller;
 765                         #gpio-cells = <2>;
 766
 767                         interrupt-controller;
 768                         #interrupt-cells = <2>;
 769                 };
 770
 771                 gpio2: gpio2@ff230000 {
 772                         compatible = "rockchip,gpio-bank";
 773                         reg = <0x0 0xff230000 0x0 0x100>;
 774                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 775                         clocks = <&cru PCLK_GPIO2>;
 776
 777                         gpio-controller;
 778                         #gpio-cells = <2>;
 779
 780                         interrupt-controller;
 781                         #interrupt-cells = <2>;
 782                 };
 783
 784                 gpio3: gpio3@ff240000 {
 785                         compatible = "rockchip,gpio-bank";
 786                         reg = <0x0 0xff240000 0x0 0x100>;
 787                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 788                         clocks = <&cru PCLK_GPIO3>;
 789
 790                         gpio-controller;
 791                         #gpio-cells = <2>;
 792
 793                         interrupt-controller;
 794                         #interrupt-cells = <2>;
 795                 };
 796
 797                 pcfg_pull_up: pcfg-pull-up {
 798                         bias-pull-up;
 799                 };
 800
 801                 pcfg_pull_down: pcfg-pull-down {
 802                         bias-pull-down;
 803                 };
 804
 805                 pcfg_pull_none: pcfg-pull-none {
 806                         bias-disable;
 807                 };
 808
 809                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
 810                         bias-disable;
 811                         drive-strength = <2>;
 812                 };
 813
 814                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
 815                         bias-pull-up;
 816                         drive-strength = <2>;
 817                 };
 818
 819                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
 820                         bias-pull-up;
 821                         drive-strength = <4>;
 822                 };
 823
 824                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
 825                         bias-disable;
 826                         drive-strength = <4>;
 827                 };
 828
 829                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
 830                         bias-pull-down;
 831                         drive-strength = <4>;
 832                 };
 833
 834                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
 835                         bias-disable;
 836                         drive-strength = <8>;
 837                 };
 838
 839                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
 840                         bias-pull-up;
 841                         drive-strength = <8>;
 842                 };
 843
 844                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 845                         bias-disable;
 846                         drive-strength = <12>;
 847                 };
 848
 849                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
 850                         bias-pull-up;
 851                         drive-strength = <12>;
 852                 };
 853
 854                 pcfg_output_high: pcfg-output-high {
 855                         output-high;
 856                 };
 857
 858                 pcfg_output_low: pcfg-output-low {
 859                         output-low;
 860                 };
 861
 862                 pcfg_input_high: pcfg-input-high {
 863                         bias-pull-up;
 864                         input-enable;
 865                 };
 866
 867                 pcfg_input: pcfg-input {
 868                         input-enable;
 869                 };
 870
 871                 i2c0 {
 872                         i2c0_xfer: i2c0-xfer {
 873                                 rockchip,pins =
 874                                         <2 24 RK_FUNC_1 &pcfg_pull_none>,
 875                                         <2 25 RK_FUNC_1 &pcfg_pull_none>;
 876                         };
 877                 };
 878
 879                 i2c1 {
 880                         i2c1_xfer: i2c1-xfer {
 881                                 rockchip,pins =
 882                                         <2 4 RK_FUNC_2 &pcfg_pull_none>,
 883                                         <2 5 RK_FUNC_2 &pcfg_pull_none>;
 884                         };
 885                 };
 886
 887                 i2c2 {
 888                         i2c2_xfer: i2c2-xfer {
 889                                 rockchip,pins =
 890                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
 891                                         <2 14 RK_FUNC_1 &pcfg_pull_none>;
 892                         };
 893                 };
 894
 895                 i2c3 {
 896                         i2c3_xfer: i2c3-xfer {
 897                                 rockchip,pins =
 898                                         <0 5 RK_FUNC_2 &pcfg_pull_none>,
 899                                         <0 6 RK_FUNC_2 &pcfg_pull_none>;
 900                         };
 901                         i2c3_gpio: i2c3-gpio {
 902                                 rockchip,pins =
 903                                         <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
 904                                         <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
 905                         };
 906                 };
 907
 908                 hdmi_i2c {
 909                         hdmii2c_xfer: hdmii2c-xfer {
 910                                 rockchip,pins =
 911                                         <0 5 RK_FUNC_1 &pcfg_pull_none>,
 912                                         <0 6 RK_FUNC_1 &pcfg_pull_none>;
 913                         };
 914                 };
 915
 916                 uart0 {
 917                         uart0_xfer: uart0-xfer {
 918                                 rockchip,pins =
 919                                         <1 9 RK_FUNC_1 &pcfg_pull_up>,
 920                                         <1 8 RK_FUNC_1 &pcfg_pull_none>;
 921                         };
 922
 923                         uart0_cts: uart0-cts {
 924                                 rockchip,pins =
 925                                         <1 11 RK_FUNC_1 &pcfg_pull_none>;
 926                         };
 927
 928                         uart0_rts: uart0-rts {
 929                                 rockchip,pins =
 930                                         <1 10 RK_FUNC_1 &pcfg_pull_none>;
 931                         };
 932
 933                         uart0_rts_gpio: uart0-rts-gpio {
 934                                 rockchip,pins =
 935                                         <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
 936                         };
 937                 };
 938
 939                 uart1 {
 940                         uart1_xfer: uart1-xfer {
 941                                 rockchip,pins =
 942                                         <3 4 RK_FUNC_4 &pcfg_pull_up>,
 943                                         <3 6 RK_FUNC_4 &pcfg_pull_none>;
 944                         };
 945
 946                         uart1_cts: uart1-cts {
 947                                 rockchip,pins =
 948                                         <3 7 RK_FUNC_4 &pcfg_pull_none>;
 949                         };
 950
 951                         uart1_rts: uart1-rts {
 952                                 rockchip,pins =
 953                                         <3 5 RK_FUNC_4 &pcfg_pull_none>;
 954                         };
 955
 956                         uart1_rts_gpio: uart1-rts-gpio {
 957                                 rockchip,pins =
 958                                         <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
 959                         };
 960                 };
 961
 962                 uart2-0 {
 963                         uart2m0_xfer: uart2m0-xfer {
 964                                 rockchip,pins =
 965                                         <1 0 RK_FUNC_2 &pcfg_pull_up>,
 966                                         <1 1 RK_FUNC_2 &pcfg_pull_none>;
 967                         };
 968                 };
 969
 970                 uart2-1 {
 971                         uart2m1_xfer: uart2m1-xfer {
 972                                 rockchip,pins =
 973                                         <2 0 RK_FUNC_1 &pcfg_pull_up>,
 974                                         <2 1 RK_FUNC_1 &pcfg_pull_none>;
 975                         };
 976                 };
 977
 978                 spi0-0 {
 979                         spi0m0_clk: spi0m0-clk {
 980                                 rockchip,pins =
 981                                         <2 8 RK_FUNC_1 &pcfg_pull_up>;
 982                         };
 983
 984                         spi0m0_cs0: spi0m0-cs0 {
 985                                 rockchip,pins =
 986                                         <2 11 RK_FUNC_1 &pcfg_pull_up>;
 987                         };
 988
 989                         spi0m0_tx: spi0m0-tx {
 990                                 rockchip,pins =
 991                                         <2 9 RK_FUNC_1 &pcfg_pull_up>;
 992                         };
 993
 994                         spi0m0_rx: spi0m0-rx {
 995                                 rockchip,pins =
 996                                         <2 10 RK_FUNC_1 &pcfg_pull_up>;
 997                         };
 998
 999                         spi0m0_cs1: spi0m0-cs1 {
1000                                 rockchip,pins =
1001                                         <2 12 RK_FUNC_1 &pcfg_pull_up>;
1002                         };
1003                 };
1004
1005                 spi0-1 {
1006                         spi0m1_clk: spi0m1-clk {
1007                                 rockchip,pins =
1008                                         <3 23 RK_FUNC_2 &pcfg_pull_up>;
1009                         };
1010
1011                         spi0m1_cs0: spi0m1-cs0 {
1012                                 rockchip,pins =
1013                                         <3 26 RK_FUNC_2 &pcfg_pull_up>;
1014                         };
1015
1016                         spi0m1_tx: spi0m1-tx {
1017                                 rockchip,pins =
1018                                         <3 25 RK_FUNC_2 &pcfg_pull_up>;
1019                         };
1020
1021                         spi0m1_rx: spi0m1-rx {
1022                                 rockchip,pins =
1023                                         <3 24 RK_FUNC_2 &pcfg_pull_up>;
1024                         };
1025
1026                         spi0m1_cs1: spi0m1-cs1 {
1027                                 rockchip,pins =
1028                                         <3 27 RK_FUNC_2 &pcfg_pull_up>;
1029                         };
1030                 };
1031
1032                 spi0-2 {
1033                         spi0m2_clk: spi0m2-clk {
1034                                 rockchip,pins =
1035                                         <3 0 RK_FUNC_4 &pcfg_pull_up>;
1036                         };
1037
1038                         spi0m2_cs0: spi0m2-cs0 {
1039                                 rockchip,pins =
1040                                         <3 8 RK_FUNC_3 &pcfg_pull_up>;
1041                         };
1042
1043                         spi0m2_tx: spi0m2-tx {
1044                                 rockchip,pins =
1045                                         <3 1 RK_FUNC_4 &pcfg_pull_up>;
1046                         };
1047
1048                         spi0m2_rx: spi0m2-rx {
1049                                 rockchip,pins =
1050                                         <3 2 RK_FUNC_4 &pcfg_pull_up>;
1051                         };
1052                 };
1053
1054                 i2s1 {
1055                         i2s1_mclk: i2s1-mclk {
1056                                 rockchip,pins =
1057                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
1058                         };
1059
1060                         i2s1_sclk: i2s1-sclk {
1061                                 rockchip,pins =
1062                                         <2 18 RK_FUNC_1 &pcfg_pull_none>;
1063                         };
1064
1065                         i2s1_lrckrx: i2s1-lrckrx {
1066                                 rockchip,pins =
1067                                         <2 16 RK_FUNC_1 &pcfg_pull_none>;
1068                         };
1069
1070                         i2s1_lrcktx: i2s1-lrcktx {
1071                                 rockchip,pins =
1072                                         <2 17 RK_FUNC_1 &pcfg_pull_none>;
1073                         };
1074
1075                         i2s1_sdi: i2s1-sdi {
1076                                 rockchip,pins =
1077                                         <2 19 RK_FUNC_1 &pcfg_pull_none>;
1078                         };
1079
1080                         i2s1_sdo: i2s1-sdo {
1081                                 rockchip,pins =
1082                                         <2 23 RK_FUNC_1 &pcfg_pull_none>;
1083                         };
1084
1085                         i2s1_sdio1: i2s1-sdio1 {
1086                                 rockchip,pins =
1087                                         <2 20 RK_FUNC_1 &pcfg_pull_none>;
1088                         };
1089
1090                         i2s1_sdio2: i2s1-sdio2 {
1091                                 rockchip,pins =
1092                                         <2 21 RK_FUNC_1 &pcfg_pull_none>;
1093                         };
1094
1095                         i2s1_sdio3: i2s1-sdio3 {
1096                                 rockchip,pins =
1097                                         <2 22 RK_FUNC_1 &pcfg_pull_none>;
1098                         };
1099
1100                         i2s1_sleep: i2s1-sleep {
1101                                 rockchip,pins =
1102                                         <2 15 RK_FUNC_GPIO &pcfg_input_high>,
1103                                         <2 16 RK_FUNC_GPIO &pcfg_input_high>,
1104                                         <2 17 RK_FUNC_GPIO &pcfg_input_high>,
1105                                         <2 18 RK_FUNC_GPIO &pcfg_input_high>,
1106                                         <2 19 RK_FUNC_GPIO &pcfg_input_high>,
1107                                         <2 20 RK_FUNC_GPIO &pcfg_input_high>,
1108                                         <2 21 RK_FUNC_GPIO &pcfg_input_high>,
1109                                         <2 22 RK_FUNC_GPIO &pcfg_input_high>,
1110                                         <2 23 RK_FUNC_GPIO &pcfg_input_high>;
1111                         };
1112                 };
1113
1114                 i2s2-0 {
1115                         i2s2m0_mclk: i2s2m0-mclk {
1116                                 rockchip,pins =
1117                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1118                         };
1119
1120                         i2s2m0_sclk: i2s2m0-sclk {
1121                                 rockchip,pins =
1122                                         <1 22 RK_FUNC_1 &pcfg_pull_none>;
1123                         };
1124
1125                         i2s2m0_lrckrx: i2s2m0-lrckrx {
1126                                 rockchip,pins =
1127                                         <1 26 RK_FUNC_1 &pcfg_pull_none>;
1128                         };
1129
1130                         i2s2m0_lrcktx: i2s2m0-lrcktx {
1131                                 rockchip,pins =
1132                                         <1 23 RK_FUNC_1 &pcfg_pull_none>;
1133                         };
1134
1135                         i2s2m0_sdi: i2s2m0-sdi {
1136                                 rockchip,pins =
1137                                         <1 24 RK_FUNC_1 &pcfg_pull_none>;
1138                         };
1139
1140                         i2s2m0_sdo: i2s2m0-sdo {
1141                                 rockchip,pins =
1142                                         <1 25 RK_FUNC_1 &pcfg_pull_none>;
1143                         };
1144
1145                         i2s2m0_sleep: i2s2m0-sleep {
1146                                 rockchip,pins =
1147                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1148                                         <1 22 RK_FUNC_GPIO &pcfg_input_high>,
1149                                         <1 26 RK_FUNC_GPIO &pcfg_input_high>,
1150                                         <1 23 RK_FUNC_GPIO &pcfg_input_high>,
1151                                         <1 24 RK_FUNC_GPIO &pcfg_input_high>,
1152                                         <1 25 RK_FUNC_GPIO &pcfg_input_high>;
1153                         };
1154                 };
1155
1156                 i2s2-1 {
1157                         i2s2m1_mclk: i2s2m1-mclk {
1158                                 rockchip,pins =
1159                                         <1 21 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         i2s2m1_sclk: i2s2m1-sclk {
1163                                 rockchip,pins =
1164                                         <3 0 RK_FUNC_6 &pcfg_pull_none>;
1165                         };
1166
1167                         i2s2m1_lrckrx: i2sm1-lrckrx {
1168                                 rockchip,pins =
1169                                         <3 8 RK_FUNC_6 &pcfg_pull_none>;
1170                         };
1171
1172                         i2s2m1_lrcktx: i2s2m1-lrcktx {
1173                                 rockchip,pins =
1174                                         <3 8 RK_FUNC_4 &pcfg_pull_none>;
1175                         };
1176
1177                         i2s2m1_sdi: i2s2m1-sdi {
1178                                 rockchip,pins =
1179                                         <3 2 RK_FUNC_6 &pcfg_pull_none>;
1180                         };
1181
1182                         i2s2m1_sdo: i2s2m1-sdo {
1183                                 rockchip,pins =
1184                                         <3 1 RK_FUNC_6 &pcfg_pull_none>;
1185                         };
1186
1187                         i2s2m1_sleep: i2s2m1-sleep {
1188                                 rockchip,pins =
1189                                         <1 21 RK_FUNC_GPIO &pcfg_input_high>,
1190                                         <3 0 RK_FUNC_GPIO &pcfg_input_high>,
1191                                         <3 8 RK_FUNC_GPIO &pcfg_input_high>,
1192                                         <3 2 RK_FUNC_GPIO &pcfg_input_high>,
1193                                         <3 1 RK_FUNC_GPIO &pcfg_input_high>;
1194                         };
1195                 };
1196
1197                 spdif-0 {
1198                         spdifm0_tx: spdifm0-tx {
1199                                 rockchip,pins =
1200                                         <0 27 RK_FUNC_1 &pcfg_pull_none>;
1201                         };
1202                 };
1203
1204                 spdif-1 {
1205                         spdifm1_tx: spdifm1-tx {
1206                                 rockchip,pins =
1207                                         <2 17 RK_FUNC_2 &pcfg_pull_none>;
1208                         };
1209                 };
1210
1211                 spdif-2 {
1212                         spdifm2_tx: spdifm2-tx {
1213                                 rockchip,pins =
1214                                         <0 2 RK_FUNC_2 &pcfg_pull_none>;
1215                         };
1216                 };
1217
1218                 sdmmc0-0 {
1219                         sdmmc0m0_pwren: sdmmc0m0-pwren {
1220                                 rockchip,pins =
1221                                         <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1222                         };
1223
1224                         sdmmc0m0_gpio: sdmmc0m0-gpio {
1225                                 rockchip,pins =
1226                                         <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1227                         };
1228                 };
1229
1230                 sdmmc0-1 {
1231                         sdmmc0m1_pwren: sdmmc0m1-pwren {
1232                                 rockchip,pins =
1233                                         <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
1234                         };
1235
1236                         sdmmc0m1_gpio: sdmmc0m1-gpio {
1237                                 rockchip,pins =
1238                                         <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1239                         };
1240                 };
1241
1242                 sdmmc0 {
1243                         sdmmc0_clk: sdmmc0-clk {
1244                                 rockchip,pins =
1245                                         <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
1246                         };
1247
1248                         sdmmc0_cmd: sdmmc0-cmd {
1249                                 rockchip,pins =
1250                                         <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
1251                         };
1252
1253                         sdmmc0_dectn: sdmmc0-dectn {
1254                                 rockchip,pins =
1255                                         <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
1256                         };
1257
1258                         sdmmc0_wrprt: sdmmc0-wrprt {
1259                                 rockchip,pins =
1260                                         <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
1261                         };
1262
1263                         sdmmc0_bus1: sdmmc0-bus1 {
1264                                 rockchip,pins =
1265                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
1266                         };
1267
1268                         sdmmc0_bus4: sdmmc0-bus4 {
1269                                 rockchip,pins =
1270                                         <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
1271                                         <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
1272                                         <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
1273                                         <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
1274                         };
1275
1276                         sdmmc0_gpio: sdmmc0-gpio {
1277                                 rockchip,pins =
1278                                         <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1279                                         <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1280                                         <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1281                                         <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1282                                         <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1283                                         <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1284                                         <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1285                                         <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1286                         };
1287                 };
1288
1289                 sdmmc0ext {
1290                         sdmmc0ext_clk: sdmmc0ext-clk {
1291                                 rockchip,pins =
1292                                         <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
1293                         };
1294
1295                         sdmmc0ext_cmd: sdmmc0ext-cmd {
1296                                 rockchip,pins =
1297                                         <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
1298                         };
1299
1300                         sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1301                                 rockchip,pins =
1302                                         <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
1303                         };
1304
1305                         sdmmc0ext_dectn: sdmmc0ext-dectn {
1306                                 rockchip,pins =
1307                                         <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
1308                         };
1309
1310                         sdmmc0ext_bus1: sdmmc0ext-bus1 {
1311                                 rockchip,pins =
1312                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
1313                         };
1314
1315                         sdmmc0ext_bus4: sdmmc0ext-bus4 {
1316                                 rockchip,pins =
1317                                         <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
1318                                         <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
1319                                         <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
1320                                         <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
1321                         };
1322
1323                         sdmmc0ext_gpio: sdmmc0ext-gpio {
1324                                 rockchip,pins =
1325                                         <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1326                                         <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1327                                         <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1328                                         <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1329                                         <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1330                                         <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1331                                         <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1332                                         <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1333                         };
1334                 };
1335
1336                 sdmmc1 {
1337                         sdmmc1_clk: sdmmc1-clk {
1338                                 rockchip,pins =
1339                                         <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
1340                         };
1341
1342                         sdmmc1_cmd: sdmmc1-cmd {
1343                                 rockchip,pins =
1344                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
1345                         };
1346
1347                         sdmmc1_pwren: sdmmc1-pwren {
1348                                 rockchip,pins =
1349                                         <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
1350                         };
1351
1352                         sdmmc1_wrprt: sdmmc1-wrprt {
1353                                 rockchip,pins =
1354                                         <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
1355                         };
1356
1357                         sdmmc1_dectn: sdmmc1-dectn {
1358                                 rockchip,pins =
1359                                         <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
1360                         };
1361
1362                         sdmmc1_bus1: sdmmc1-bus1 {
1363                                 rockchip,pins =
1364                                         <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
1365                         };
1366
1367                         sdmmc1_bus4: sdmmc1-bus4 {
1368                                 rockchip,pins =
1369                                         <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
1370                                         <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
1371                                         <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
1372                                         <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
1373                         };
1374
1375                         sdmmc1_gpio: sdmmc1-gpio {
1376                                 rockchip,pins =
1377                                         <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1378                                         <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1379                                         <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1380                                         <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1381                                         <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1382                                         <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1383                                         <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1384                                         <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1385                                         <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1386                         };
1387                 };
1388
1389                 emmc {
1390                         emmc_clk: emmc-clk {
1391                                 rockchip,pins =
1392                                         <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
1393                         };
1394
1395                         emmc_cmd: emmc-cmd {
1396                                 rockchip,pins =
1397                                         <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
1398                         };
1399
1400                         emmc_pwren: emmc-pwren {
1401                                 rockchip,pins =
1402                                         <3 22 RK_FUNC_2 &pcfg_pull_none>;
1403                         };
1404
1405                         emmc_rstnout: emmc-rstnout {
1406                                 rockchip,pins =
1407                                         <3 20 RK_FUNC_2 &pcfg_pull_none>;
1408                         };
1409
1410                         emmc_bus1: emmc-bus1 {
1411                                 rockchip,pins =
1412                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
1413                         };
1414
1415                         emmc_bus4: emmc-bus4 {
1416                                 rockchip,pins =
1417                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1418                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1419                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1420                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
1421                         };
1422
1423                         emmc_bus8: emmc-bus8 {
1424                                 rockchip,pins =
1425                                         <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
1426                                         <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
1427                                         <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
1428                                         <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
1429                                         <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
1430                                         <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
1431                                         <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
1432                                         <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
1433                         };
1434                 };
1435
1436                 pwm0 {
1437                         pwm0_pin: pwm0-pin {
1438                                 rockchip,pins =
1439                                         <2 4 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441                 };
1442
1443                 pwm1 {
1444                         pwm1_pin: pwm1-pin {
1445                                 rockchip,pins =
1446                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
1447                         };
1448                 };
1449
1450                 pwm2 {
1451                         pwm2_pin: pwm2-pin {
1452                                 rockchip,pins =
1453                                         <2 6 RK_FUNC_1 &pcfg_pull_none>;
1454                         };
1455                 };
1456
1457                 pwmir {
1458                         pwmir_pin: pwmir-pin {
1459                                 rockchip,pins =
1460                                         <2 2 RK_FUNC_1 &pcfg_pull_none>;
1461                         };
1462                 };
1463
1464                 gmac-0 {
1465                         rgmiim0_pins: rgmiim0-pins {
1466                                 rockchip,pins =
1467                                         /* mac_txclk */
1468                                         <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1469                                         /* mac_rxclk */
1470                                         <0 10 RK_FUNC_1 &pcfg_pull_none>,
1471                                         /* mac_mdio */
1472                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1473                                         /* mac_txen */
1474                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1475                                         /* mac_clk */
1476                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1477                                         /* mac_rxdv */
1478                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1479                                         /* mac_mdc */
1480                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1481                                         /* mac_rxd1 */
1482                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1483                                         /* mac_rxd0 */
1484                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1485                                         /* mac_txd1 */
1486                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1487                                         /* mac_txd0 */
1488                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
1489                                         /* mac_rxd3 */
1490                                         <0 20 RK_FUNC_1 &pcfg_pull_none>,
1491                                         /* mac_rxd2 */
1492                                         <0 21 RK_FUNC_1 &pcfg_pull_none>,
1493                                         /* mac_txd3 */
1494                                         <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
1495                                         /* mac_txd2 */
1496                                         <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
1497                         };
1498
1499                         rmiim0_pins: rmiim0-pins {
1500                                 rockchip,pins =
1501                                         /* mac_mdio */
1502                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1503                                         /* mac_txen */
1504                                         <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
1505                                         /* mac_clk */
1506                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1507                                         /* mac_rxer */
1508                                         <0 13 RK_FUNC_1 &pcfg_pull_none>,
1509                                         /* mac_rxdv */
1510                                         <0 25 RK_FUNC_1 &pcfg_pull_none>,
1511                                         /* mac_mdc */
1512                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1513                                         /* mac_rxd1 */
1514                                         <0 14 RK_FUNC_1 &pcfg_pull_none>,
1515                                         /* mac_rxd0 */
1516                                         <0 15 RK_FUNC_1 &pcfg_pull_none>,
1517                                         /* mac_txd1 */
1518                                         <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
1519                                         /* mac_txd0 */
1520                                         <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
1521                         };
1522                 };
1523
1524                 gmac-1 {
1525                         rgmiim1_pins: rgmiim1-pins {
1526                                 rockchip,pins =
1527                                         /* mac_txclk */
1528                                         <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
1529                                         /* mac_rxclk */
1530                                         <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
1531                                         /* mac_mdio */
1532                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1533                                         /* mac_txen */
1534                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1535                                         /* mac_clk */
1536                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1537                                         /* mac_rxdv */
1538                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1539                                         /* mac_mdc */
1540                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1541                                         /* mac_rxd1 */
1542                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1543                                         /* mac_rxd0 */
1544                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1545                                         /* mac_txd1 */
1546                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1547                                         /* mac_txd0 */
1548                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1549                                         /* mac_rxd3 */
1550                                         <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
1551                                         /* mac_rxd2 */
1552                                         <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
1553                                         /* mac_txd3 */
1554                                         <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
1555                                         /* mac_txd2 */
1556                                         <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
1557
1558                                         /* mac_txclk */
1559                                         <0 8 RK_FUNC_1 &pcfg_pull_none>,
1560                                         /* mac_txen */
1561                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1562                                         /* mac_clk */
1563                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1564                                         /* mac_txd1 */
1565                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1566                                         /* mac_txd0 */
1567                                         <0 17 RK_FUNC_1 &pcfg_pull_none>,
1568                                         /* mac_txd3 */
1569                                         <0 23 RK_FUNC_1 &pcfg_pull_none>,
1570                                         /* mac_txd2 */
1571                                         <0 22 RK_FUNC_1 &pcfg_pull_none>;
1572                         };
1573
1574                         rmiim1_pins: rmiim1-pins {
1575                                 rockchip,pins =
1576                                         /* mac_mdio */
1577                                         <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
1578                                         /* mac_txen */
1579                                         <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
1580                                         /* mac_clk */
1581                                         <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
1582                                         /* mac_rxer */
1583                                         <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
1584                                         /* mac_rxdv */
1585                                         <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
1586                                         /* mac_mdc */
1587                                         <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
1588                                         /* mac_rxd1 */
1589                                         <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
1590                                         /* mac_rxd0 */
1591                                         <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
1592                                         /* mac_txd1 */
1593                                         <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
1594                                         /* mac_txd0 */
1595                                         <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
1596
1597                                         /* mac_mdio */
1598                                         <0 11 RK_FUNC_1 &pcfg_pull_none>,
1599                                         /* mac_txen */
1600                                         <0 12 RK_FUNC_1 &pcfg_pull_none>,
1601                                         /* mac_clk */
1602                                         <0 24 RK_FUNC_1 &pcfg_pull_none>,
1603                                         /* mac_mdc */
1604                                         <0 19 RK_FUNC_1 &pcfg_pull_none>,
1605                                         /* mac_txd1 */
1606                                         <0 16 RK_FUNC_1 &pcfg_pull_none>,
1607                                         /* mac_txd0 */
1608                                         <0 17 RK_FUNC_1 &pcfg_pull_none>;
1609                         };
1610                 };
1611
1612                 gmac2phy {
1613                         fephyled_speed100: fephyled-speed100 {
1614                                 rockchip,pins =
1615                                         <0 31 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617
1618                         fephyled_speed10: fephyled-speed10 {
1619                                 rockchip,pins =
1620                                         <0 30 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622
1623                         fephyled_duplex: fephyled-duplex {
1624                                 rockchip,pins =
1625                                         <0 30 RK_FUNC_2 &pcfg_pull_none>;
1626                         };
1627
1628                         fephyled_rxm0: fephyled-rxm0 {
1629                                 rockchip,pins =
1630                                         <0 29 RK_FUNC_1 &pcfg_pull_none>;
1631                         };
1632
1633                         fephyled_txm0: fephyled-txm0 {
1634                                 rockchip,pins =
1635                                         <0 29 RK_FUNC_2 &pcfg_pull_none>;
1636                         };
1637
1638                         fephyled_linkm0: fephyled-linkm0 {
1639                                 rockchip,pins =
1640                                         <0 28 RK_FUNC_1 &pcfg_pull_none>;
1641                         };
1642
1643                         fephyled_rxm1: fephyled-rxm1 {
1644                                 rockchip,pins =
1645                                         <2 25 RK_FUNC_2 &pcfg_pull_none>;
1646                         };
1647
1648                         fephyled_txm1: fephyled-txm1 {
1649                                 rockchip,pins =
1650                                         <2 25 RK_FUNC_3 &pcfg_pull_none>;
1651                         };
1652
1653                         fephyled_linkm1: fephyled-linkm1 {
1654                                 rockchip,pins =
1655                                         <2 24 RK_FUNC_2 &pcfg_pull_none>;
1656                         };
1657                 };
1658
1659                 tsadc_pin {
1660                         tsadc_int: tsadc-int {
1661                                 rockchip,pins =
1662                                         <2 13 RK_FUNC_2 &pcfg_pull_none>;
1663                         };
1664                         tsadc_gpio: tsadc-gpio {
1665                                 rockchip,pins =
1666                                         <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
1667                         };
1668                 };
1669
1670                 hdmi_pin {
1671                         hdmi_cec: hdmi-cec {
1672                                 rockchip,pins =
1673                                         <0 3 RK_FUNC_1 &pcfg_pull_none>;
1674                         };
1675
1676                         hdmi_hpd: hdmi-hpd {
1677                                 rockchip,pins =
1678                                         <0 4 RK_FUNC_1 &pcfg_pull_down>;
1679                         };
1680                 };
1681
1682                 cif-0 {
1683                         dvp_d2d9_m0:dvp-d2d9-m0 {
1684                                 rockchip,pins =
1685                                         /* cif_d0 */
1686                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1687                                         /* cif_d1 */
1688                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1689                                         /* cif_d2 */
1690                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1691                                         /* cif_d3 */
1692                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1693                                         /* cif_d4 */
1694                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1695                                         /* cif_d5m0 */
1696                                         <3 9 RK_FUNC_2 &pcfg_pull_none>,
1697                                         /* cif_d6m0 */
1698                                         <3 10 RK_FUNC_2 &pcfg_pull_none>,
1699                                         /* cif_d7m0 */
1700                                         <3 11 RK_FUNC_2 &pcfg_pull_none>,
1701                                         /* cif_href */
1702                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1703                                         /* cif_vsync */
1704                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1705                                         /* cif_clkoutm0 */
1706                                         <3 3 RK_FUNC_2 &pcfg_pull_none>,
1707                                         /* cif_clkin */
1708                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1709                         };
1710                 };
1711
1712                 cif-1 {
1713                         dvp_d2d9_m1:dvp-d2d9-m1 {
1714                                 rockchip,pins =
1715                                         /* cif_d0 */
1716                                         <3 4 RK_FUNC_2 &pcfg_pull_none>,
1717                                         /* cif_d1 */
1718                                         <3 5 RK_FUNC_2 &pcfg_pull_none>,
1719                                         /* cif_d2 */
1720                                         <3 6 RK_FUNC_2 &pcfg_pull_none>,
1721                                         /* cif_d3 */
1722                                         <3 7 RK_FUNC_2 &pcfg_pull_none>,
1723                                         /* cif_d4 */
1724                                         <3 8 RK_FUNC_2 &pcfg_pull_none>,
1725                                         /* cif_d5m1 */
1726                                         <2 16 RK_FUNC_4 &pcfg_pull_none>,
1727                                         /* cif_d6m1 */
1728                                         <2 17 RK_FUNC_4 &pcfg_pull_none>,
1729                                         /* cif_d7m1 */
1730                                         <2 18 RK_FUNC_4 &pcfg_pull_none>,
1731                                         /* cif_href */
1732                                         <3 1 RK_FUNC_2 &pcfg_pull_none>,
1733                                         /* cif_vsync */
1734                                         <3 0 RK_FUNC_2 &pcfg_pull_none>,
1735                                         /* cif_clkoutm1 */
1736                                         <2 15 RK_FUNC_4 &pcfg_pull_none>,
1737                                         /* cif_clkin */
1738                                         <3 2 RK_FUNC_2 &pcfg_pull_none>;
1739                         };
1740                 };
1741         };
1742 };