1 #include <dt-bindings/interrupt-controller/arm-gic.h>
2 #include <dt-bindings/suspend/rockchip-pm.h>
3 #include <dt-bindings/pinctrl/rockchip.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/sensor-dev.h>
6 #include <dt-bindings/clock/rk_system_status.h>
8 #include "rk3368-clocks.dtsi"
11 compatible = "rockchip,rk3368";
13 rockchip,sram = <&sram>;
14 interrupt-parent = <&gic>;
41 entry-method = "arm,psci";
42 CPU_SLEEP_0: cpu-sleep-0 {
43 compatible = "arm,idle-state";
44 arm,psci-suspend-param = <0x1010000>;
45 entry-latency-us = <0x3fffffff>;
46 exit-latency-us = <0x40000000>;
47 min-residency-us = <0xffffffff>;
53 compatible = "arm,cortex-a53", "arm,armv8";
55 enable-method = "psci";
56 cpu-idle-states = <&CPU_SLEEP_0>;
60 compatible = "arm,cortex-a53", "arm,armv8";
62 enable-method = "psci";
63 cpu-idle-states = <&CPU_SLEEP_0>;
67 compatible = "arm,cortex-a53", "arm,armv8";
69 enable-method = "psci";
70 cpu-idle-states = <&CPU_SLEEP_0>;
74 compatible = "arm,cortex-a53", "arm,armv8";
76 enable-method = "psci";
77 cpu-idle-states = <&CPU_SLEEP_0>;
81 compatible = "arm,cortex-a53", "arm,armv8";
83 enable-method = "psci";
84 cpu-idle-states = <&CPU_SLEEP_0>;
88 compatible = "arm,cortex-a53", "arm,armv8";
90 enable-method = "psci";
91 cpu-idle-states = <&CPU_SLEEP_0>;
95 compatible = "arm,cortex-a53", "arm,armv8";
97 enable-method = "psci";
98 cpu-idle-states = <&CPU_SLEEP_0>;
102 compatible = "arm,cortex-a53", "arm,armv8";
104 enable-method = "psci";
105 cpu-idle-states = <&CPU_SLEEP_0>;
141 compatible = "arm,psci-0.2";
145 gic: interrupt-controller@ffb70000 {
146 compatible = "arm,cortex-a15-gic";
147 #interrupt-cells = <3>;
148 #address-cells = <0>;
149 interrupt-controller;
150 reg = <0x0 0xffb71000 0 0x1000>,
151 <0x0 0xffb72000 0 0x1000>;
154 pmu: syscon@ff730000 {
155 compatible = "rockchip,rk3368-pmu", "rockchip,pmu", "syscon";
156 reg = <0x0 0xff730000 0x0 0x1000>;
159 pmugrf: syscon@ff738000 {
160 compatible = "rockchip,rk3368-pmugrf", "rockchip,pmugrf", "syscon";
161 reg = <0x0 0xff738000 0x0 0x1000>;
164 sgrf: syscon@ff740000 {
165 compatible = "rockchip,rk3368-sgrf", "rockchip,sgrf", "syscon";
166 reg = <0x0 0xff740000 0x0 0x1000>;
170 cru: syscon@ff760000 {
171 compatible = "rockchip,rk3368-cru", "rockchip,cru", "syscon";
172 reg = <0x0 0xff760000 0x0 0x1000>;
175 grf: syscon@ff770000 {
176 compatible = "rockchip,rk3368-grf", "rockchip,grf", "syscon";
177 reg = <0x0 0xff770000 0x0 0x1000>;
181 compatible = "arm,armv8-pmuv3";
182 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
183 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
184 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
185 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
186 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
187 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
188 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
189 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
192 cpu_axi_bus: cpu_axi_bus {
193 compatible = "rockchip,cpu_axi_bus";
194 #address-cells = <2>;
199 #address-cells = <2>;
204 reg = <0x0 0xffa80000 0x0 0x20>;
207 reg = <0x0 0xffa80080 0x0 0x20>;
210 reg = <0x0 0xffa80280 0x0 0x20>;
213 reg = <0x0 0xffa90000 0x0 0x20>;
216 reg = <0x0 0xffaa0000 0x0 0x20>;
219 reg = <0x0 0xffaa0080 0x0 0x20>;
222 reg = <0x0 0xffab0000 0x0 0x20>;
223 rockchip,priority = <2 2>;
226 reg = <0x0 0xffad0000 0x0 0x20>;
229 reg = <0x0 0xffad0080 0x0 0x20>;
232 reg = <0x0 0xffad0100 0x0 0x20>;
235 reg = <0x0 0xffad0180 0x0 0x20>;
236 rockchip,priority = <2 2>;
239 reg = <0x0 0xffad0200 0x0 0x20>;
240 rockchip,priority = <2 2>;
243 reg = <0x0 0xffad0280 0x0 0x20>;
246 reg = <0x0 0xffad0300 0x0 0x20>;
247 rockchip,priority = <2 2>;
250 reg = <0x0 0xffad0380 0x0 0x20>;
253 reg = <0x0 0xffad0400 0x0 0x20>;
256 reg = <0x0 0xffae0000 0x0 0x20>;
259 reg = <0x0 0xffae0100 0x0 0x20>;
262 reg = <0x0 0xffae0180 0x0 0x20>;
265 reg = <0x0 0xffaf0000 0x0 0x20>;
270 #address-cells = <2>;
275 reg = <0x0 0xffac0000 0x0 0x3c>;
276 rockchip,read-latency = <0x34>;
282 compatible = "arm,armv8-timer";
283 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
284 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
285 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
286 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
287 clock-frequency = <24000000>;
291 compatible = "rockchip,timer";
292 reg = <0x0 0xff810000 0x0 0x20>;
293 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
294 rockchip,broadcast = <1>;
297 sram: sram@ff8c0000 {
298 compatible = "mmio-sram";
299 reg = <0x0 0xff8c0000 0x0 0xf000>; /* 60K (reserved 4K for mailbox)*/
303 watchdog: wdt@ff800000 {
304 compatible = "rockchip,watch dog";
305 reg = <0x0 0xff800000 0x0 0x100>;
306 clocks = <&pclk_alive_pre>;
307 clock-names = "pclk_wdt";
308 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
310 rockchip,timeout = <60>;
311 rockchip,atboot = <1>;
312 rockchip,debug = <0>;
317 #address-cells = <2>;
319 compatible = "arm,amba-bus";
320 interrupt-parent = <&gic>;
323 pdma0: pdma@ff600000 {
324 compatible = "arm,pl330", "arm,primecell";
325 reg = <0x0 0xff600000 0x0 0x4000>;
326 clocks = <&clk_gates12 11>;
327 clock-names = "apb_pclk";
328 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
334 pdma1: pdma@ff250000 {
335 compatible = "arm,pl330", "arm,primecell";
336 reg = <0x0 0xff250000 0x0 0x4000>;
337 clocks = <&clk_gates19 3>;
338 clock-names = "apb_pclk";
339 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
345 reset: reset@ff760300{
346 compatible = "rockchip,reset";
347 reg = <0x0 0xff760300 0x0 0x38>;
348 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
352 nandc0: nandc@ff400000 {
353 compatible = "rockchip,rk-nandc";
354 reg = <0x0 0xff400000 0x0 0x4000>;
355 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&clk_nandc0>, <&clk_gates7 8>, <&clk_gates20 11>;
358 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
361 nandc0reg: nandc0@ff400000 {
362 compatible = "rockchip,rk-nandc";
363 reg = <0x0 0xff400000 0x0 0x4000>;
366 emmc: rksdmmc@ff0f0000 {
367 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
368 reg = <0x0 0xff0f0000 0x0 0x4000>;
369 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
372 clocks = <&clk_emmc>, <&clk_gates21 2>, <&clk_gates20 10>;
373 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
374 rockchip,grf = <&grf>;
376 fifo-depth = <0x100>;
380 sdmmc: rksdmmc@ff0c0000 {
381 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
382 reg = <0x0 0xff0c0000 0x0 0x4000>;
383 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
384 #address-cells = <1>;
386 pinctrl-names = "default", "idle", "udbg";
387 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_dectn &sdmmc_bus4>;
388 pinctrl-1 = <&sdmmc_gpio>;
389 pinctrl-2 = <&uart2_xfer &cpu_jtag &sdmmc_dectn>;
390 cd-gpios = <&gpio2 GPIO_B3 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
391 clocks = <&clk_sdmmc0>, <&clk_gates21 0>, <&clk_gates20 10>;
392 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
393 rockchip,grf = <&grf>;
395 fifo-depth = <0x100>;
399 sdio: rksdmmc@ff0d0000 {
400 compatible = "rockchip,rk_mmc", "rockchip,rk3368-sdmmc";
401 reg = <0x0 0xff0d0000 0x0 0x4000>;
402 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
403 #address-cells = <1>;
405 pinctrl-names = "default","idle";
406 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwren &sdio0_bkpwr &sdio0_int &sdio0_bus4>;
407 pinctrl-1 = <&sdio0_gpio>;
408 clocks = <&clk_sdio0>, <&clk_gates21 1>, <&clk_gates20 10>;
409 clock-names = "clk_mmc", "hclk_mmc", "hpclk_mmc";
410 rockchip,grf = <&grf>;
412 fifo-depth = <0x100>;
417 compatible = "rockchip,rockchip-spi";
418 reg = <0x0 0xff110000 0x0 0x1000>;
419 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
420 #address-cells = <1>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
424 rockchip,spi-src-clk = <0>;
426 clocks =<&clk_spi0>, <&clk_gates19 4>;
427 clock-names = "spi", "pclk_spi0";
428 //dmas = <&pdma1 11>, <&pdma1 12>;
430 //dma-names = "tx", "rx";
435 compatible = "rockchip,rockchip-spi";
436 reg = <0x0 0xff120000 0x0 0x1000>;
437 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
438 #address-cells = <1>;
440 pinctrl-names = "default";
441 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0 &spi1_cs1>;
442 rockchip,spi-src-clk = <1>;
444 clocks = <&clk_spi1>, <&clk_gates19 5>;
445 clock-names = "spi", "pclk_spi1";
446 //dmas = <&pdma1 13>, <&pdma1 14>;
448 //dma-names = "tx", "rx";
453 compatible = "rockchip,rockchip-spi";
454 reg = <0x0 0xff130000 0x0 0x1000>;
455 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
456 #address-cells = <1>;
458 pinctrl-names = "default";
459 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
460 rockchip,spi-src-clk = <2>;
462 clocks = <&clk_spi2>, <&clk_gates19 6>;
463 clock-names = "spi", "pclk_spi2";
464 //dmas = <&pdma1 15>, <&pdma1 16>;
466 //dma-names = "tx", "rx";
470 uart_bt: serial@ff180000 {
471 compatible = "rockchip,serial";
472 reg = <0x0 0xff180000 0x0 0x100>;
473 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
474 clock-frequency = <24000000>;
475 clocks = <&clk_uart0>, <&clk_gates19 7>;
476 clock-names = "sclk_uart", "pclk_uart";
479 //dmas = <&pdma1 1>, <&pdma1 2>;
481 pinctrl-names = "default";
482 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
486 uart_bb: serial@ff190000 {
487 compatible = "rockchip,serial";
488 reg = <0x0 0xff190000 0x0 0x100>;
489 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
490 clock-frequency = <24000000>;
491 clocks = <&clk_uart1>, <&clk_gates19 8>;
492 clock-names = "sclk_uart", "pclk_uart";
495 //dmas = <&pdma1 3>, <&pdma1 4>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
502 uart_dbg: serial@ff690000 {
503 compatible = "rockchip,serial";
504 reg = <0x0 0xff690000 0x0 0x100>;
505 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
506 clock-frequency = <24000000>;
507 clocks = <&clk_uart2>, <&clk_gates13 5>;
508 clock-names = "sclk_uart", "pclk_uart";
511 //dmas = <&pdma0 4>, <&pdma0 5>;
513 //pinctrl-names = "default";
514 //pinctrl-0 = <&uart2_xfer>;
518 uart_gps: serial@ff1b0000 {
519 compatible = "rockchip,serial";
520 reg = <0x0 0xff1b0000 0x0 0x100>;
521 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
522 clock-frequency = <24000000>;
523 clocks = <&clk_uart3>, <&clk_gates19 9>;
524 clock-names = "sclk_uart", "pclk_uart";
525 current-speed = <115200>;
528 //dmas = <&pdma1 7>, <&pdma1 8>;
530 pinctrl-names = "default";
531 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
535 uart_exp: serial@ff1c0000 {
536 compatible = "rockchip,serial";
537 reg = <0x0 0xff1c0000 0x0 0x100>;
538 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
539 clock-frequency = <24000000>;
540 clocks = <&clk_uart4>, <&clk_gates19 10>;
541 clock-names = "sclk_uart", "pclk_uart";
544 //dmas = <&pdma1 9>, <&pdma1 10>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
551 mbox: mbox@ff6b0000 {
552 compatible = "rockchip,rk3368-mailbox";
553 reg = <0x0 0xff6b0000 0x0 0x1000>,
554 <0x0 0xff8cf000 0x0 0x1000>; /* the end 4k of sram */
555 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk_gates12 1>;
560 clock-names = "pclk_mailbox";
564 mbox_scpi: mbox-scpi {
565 compatible = "rockchip,mbox-scpi";
566 mboxes = <&mbox 0 &mbox 1>;
569 rockchip_clocks_init: clocks-init{
570 compatible = "rockchip,clocks-init";
571 rockchip,clocks-init-parent =
572 <&i2s_pll &clk_gpll>, <&spdif_8ch_pll &clk_gpll>,
573 <&i2s_2ch_pll &clk_gpll>, <&usbphy_480m &usbotg_480m_out>,
574 <&clk_uart_pll &clk_gpll>, <&aclk_gpu &clk_cpll>,
575 <&clk_cs &clk_gpll>, <&clk_32k_mux &pvtm_clkout>;
576 rockchip,clocks-init-rate =
577 <&clk_gpll 576000000>, <&clk_core_b 792000000>,
578 <&clk_core_l 600000000>, <&clk_cpll 400000000>,
579 /*<&clk_npll 500000000>,*/ <&aclk_bus 300000000>,
580 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
581 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
582 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
583 <&pclk_alive_pre 100000000>, <&pclk_pmu_pre 100000000>,
584 <&clk_cs 300000000>, <&clkin_trace 300000000>,
585 <&aclk_cci 600000000>, <&clk_mac 125000000>,
586 <&aclk_vio0 400000000>, <&hclk_vio 100000000>,
587 <&aclk_rga_pre 400000000>, <&clk_rga 400000000>,
588 <&clk_isp 400000000>, <&clk_edp 200000000>,
589 <&clk_gpu_core 400000000>, <&aclk_gpu_mem 400000000>,
590 <&aclk_gpu_cfg 400000000>, <&aclk_vepu 400000000>,
591 <&aclk_vdpu 400000000>, <&clk_hevc_core 300000000>,
592 <&clk_hevc_cabac 300000000>;
594 rockchip,clocks-uboot-has-init =
599 rockchip_clocks_enable: clocks-enable {
600 compatible = "rockchip,clocks-enable";
623 <&clk_gates12 12>,/*aclk_strc_sys*/
624 <&clk_gates12 6>,/*aclk_intmem1*/
625 <&clk_gates12 5>,/*aclk_intmem0*/
626 <&clk_gates12 4>,/*aclk_intmem*/
627 <&clk_gates13 9>,/*aclk_gic400*/
628 <&clk_gates12 9>,/*hclk_rom*/
631 <&clk_gates22 13>,/*pclk_timer1*/
632 <&clk_gates22 12>,/*pclk_timer0*/
633 <&clk_gates22 9>,/*pclk_alive_niu*/
634 <&clk_gates22 8>,/*pclk_grf*/
637 <&clk_gates23 5>,/*pclk_pmugrf*/
638 <&clk_gates23 3>,/*pclk_sgrf*/
639 <&clk_gates23 2>,/*pclk_pmu_noc*/
640 <&clk_gates23 1>,/*pclk_intmem1*/
641 <&clk_gates23 0>,/*pclk_pmu*/
644 <&clk_gates19 2>,/*aclk_peri_axi_matrix*/
645 <&clk_gates20 8>,/*aclk_peri_niu*/
646 <&clk_gates21 4>,/*aclk_peri_mmu*/
647 <&clk_gates19 0>,/*hclk_peri_axi_matrix*/
648 <&clk_gates20 7>,/*hclk_peri_ahb_arbi*/
649 <&clk_gates19 1>,/*pclk_peri_axi_matrix*/
653 <&clk_gates7 0>;/*clk_jtag*/
658 compatible = "rockchip,rk30-i2c";
659 reg = <0x0 0xff650000 0x0 0x1000>;
660 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
661 #address-cells = <1>;
663 pinctrl-names = "default", "gpio";
664 pinctrl-0 = <&i2c0_xfer>;
665 pinctrl-1 = <&i2c0_gpio>;
666 gpios = <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>;
667 clocks = <&clk_gates12 2>;
668 rockchip,check-idle = <1>;
674 compatible = "rockchip,rk30-i2c";
675 reg = <0x0 0xff660000 0x0 0x1000>;
676 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>;
679 pinctrl-names = "default", "gpio";
680 pinctrl-0 = <&i2c1_xfer>;
681 pinctrl-1 = <&i2c1_gpio>;
682 gpios = <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C6 GPIO_ACTIVE_LOW>;
683 clocks = <&clk_gates12 3>;
684 rockchip,check-idle = <1>;
690 compatible = "rockchip,rk30-i2c";
691 reg = <0x0 0xff140000 0x0 0x1000>;
692 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
693 #address-cells = <1>;
695 pinctrl-names = "default", "gpio";
696 pinctrl-0 = <&i2c2_xfer>;
697 pinctrl-1 = <&i2c2_gpio>;
698 gpios = <&gpio3 GPIO_D7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_B1 GPIO_ACTIVE_LOW>;
699 clocks = <&clk_gates19 11>;
700 rockchip,check-idle = <1>;
706 compatible = "rockchip,rk30-i2c";
707 reg = <0x0 0xff150000 0x0 0x1000>;
708 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
709 #address-cells = <1>;
711 pinctrl-names = "default", "gpio";
712 pinctrl-0 = <&i2c3_xfer>;
713 pinctrl-1 = <&i2c3_gpio>;
714 gpios = <&gpio1 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio1 GPIO_C0 GPIO_ACTIVE_LOW>;
715 clocks = <&clk_gates19 12>;
716 rockchip,check-idle = <1>;
722 compatible = "rockchip,rk30-i2c";
723 reg = <0x0 0xff160000 0x0 0x1000>;
724 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
725 #address-cells = <1>;
727 pinctrl-names = "default", "gpio";
728 pinctrl-0 = <&i2c4_xfer>;
729 pinctrl-1 = <&i2c4_gpio>;
730 gpios = <&gpio3 GPIO_D0 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D1 GPIO_ACTIVE_LOW>;
731 clocks = <&clk_gates19 13>;
732 rockchip,check-idle = <1>;
738 compatible = "rockchip,rk30-i2c";
739 reg = <0x0 0xff170000 0x0 0x1000>;
740 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
741 #address-cells = <1>;
743 pinctrl-names = "default", "gpio";
744 pinctrl-0 = <&i2c5_xfer>;
745 pinctrl-1 = <&i2c5_gpio>;
746 gpios = <&gpio3 GPIO_D2 GPIO_ACTIVE_LOW>, <&gpio3 GPIO_D3 GPIO_ACTIVE_LOW>;
747 clocks = <&clk_gates19 14>;
748 rockchip,check-idle = <1>;
753 compatible = "rockchip,rk-fb";
754 rockchip,disp-mode = <NO_DUAL>;
758 rk_screen: rk_screen {
759 compatible = "rockchip,screen";
762 dsihost0: mipi@ff960000{
763 compatible = "rockchip,rk3368-dsi";
765 reg = <0x0 0xff960000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
766 reg-names = "mipi_dsi_host" ,"mipi_dsi_phy";
767 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clk_gates4 14>, <&clk_gates22 10>, <&clk_gates17 3>, <&pd_mipidsi>;
769 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pclk_mipi_dsi_host", "pd_mipi_dsi";
773 lvds: lvds@ff968000 {
774 compatible = "rockchip,rk3368-lvds";
775 rockchip,grf = <&grf>;
776 reg = <0x0 0xff968000 0x0 0x4000>, <0x0 0xff9600a0 0x0 0x20>;
777 reg-names = "mipi_lvds_phy", "mipi_lvds_ctl";
778 clocks = <&clk_gates22 10>, <&clk_gates17 3>, <&pd_lvds>;
779 clock-names = "pclk_lvds", "pclk_lvds_ctl", "pd_lvds";
784 compatible = "rockchip,rk32-edp";
785 reg = <0x0 0xff970000 0x0 0x4000>;
786 rockchip,grf = <&grf>;
787 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates17 9>;
789 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
790 resets = <&reset RK3368_SRST_EDP_24M>, <&reset RK3368_SRST_EDP_P>;
791 reset-names = "edp_24m", "edp_apb";
794 hdmi: hdmi@ff980000 {
795 compatible = "rockchip,rk3368-hdmi";
796 reg = <0x0 0xff980000 0x0 0x20000>;
797 rockchip,grf = <&grf>;
798 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
799 pinctrl-names = "default", "gpio";
800 pinctrl-0 = <&hdmii2c_xfer &hdmi_cec>;
801 pinctrl-1 = <&i2c5_gpio>;
802 clocks = <&clk_gates17 6>, <&clk_gates4 13>, <&clk_gates4 12>;
803 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
807 hdmi_hdcp2: hdmi_hdcp2@ff978000 {
808 compatible = "rockchip,rk3368-hdmi-hdcp2";
809 reg = <0x0 0xff978000 0x0 0x2000>;
810 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clk_gates17 10>, <&clk_gates17 12>, <&clk_gates17 11>, <&clk_hdcp>;
812 clock-names ="aclk_hdcp2", "hclk_hdcp2_mmu", "pclk_hdcp2", "hdcp2_clk_hdmi";
816 lcdc: lcdc@ff930000 {
817 compatible = "rockchip,rk3368-lcdc";
818 rockchip,grf = <&grf>;
819 rockchip,pmugrf = <&pmugrf>;
820 rockchip,cru = <&cru>;
821 rockchip,prop = <PRMRY>;
822 rockchip,pwr18 = <0>;
823 rockchip,iommu-enabled = <0>;
824 reg = <0x0 0xff930000 0x0 0x10000>;
825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
826 /*pinctrl-names = "default", "gpio";
827 *pinctrl-0 = <&lcdc_lcdc>;
828 *pinctrl-1 = <&lcdc_gpio>;
831 clocks = <&clk_gates16 5>, <&dclk_vop0>, <&clk_gates16 6>, <&clk_npll>, <&pd_vop>;
832 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "sclk_pll", "pd_lcdc";
836 compatible = "rockchip,saradc";
837 reg = <0x0 0xff100000 0x0 0x100>;
838 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
839 #io-channel-cells = <1>;
841 rockchip,adc-vref = <1800>;
842 clock-frequency = <1000000>;
843 clocks = <&clk_saradc>, <&clk_gates19 15>;
844 clock-names = "saradc", "pclk_saradc";
849 compatible = "rockchip,rk3368-rga2";
850 reg = <0x0 0xff920000 0x0 0x1000>;
851 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&clk_gates16 1>, <&clk_gates16 0>, <&clk_rga>;
853 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
856 i2s0: i2s0@ff898000 {
857 compatible = "rockchip-i2s";
858 reg = <0x0 0xff898000 0x0 0x1000>;
860 clocks = <&clk_i2s>, <&i2s_out>, <&clk_gates12 7>;
861 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
862 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
863 dmas = <&pdma0 0>, <&pdma0 1>;
865 dma-names = "tx", "rx";
866 pinctrl-names = "default", "sleep";
867 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
868 pinctrl-1 = <&i2s_gpio>;
871 i2s1: i2s1@ff890000 {
872 compatible = "rockchip-i2s";
873 reg = <0x0 0xff890000 0x0 0x1000>;
875 clocks = <&clk_i2s_2ch>, <&clk_gates12 8>;
876 clock-names = "i2s_clk", "i2s_hclk";
877 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
878 dmas = <&pdma0 6>, <&pdma0 7>;
880 dma-names = "tx", "rx";
883 spdif: spdif@ff880000 {
884 compatible = "rockchip-spdif";
885 reg = <0x0 0xff880000 0x0 0x1000>;
886 clocks = <&clk_spidf_8ch>, <&clk_gates12 10>;
887 clock-names = "spdif_mclk", "spdif_hclk";
888 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&spdif_tx>;
897 compatible = "rockchip,rk-pwm";
898 reg = <0x0 0xff680000 0x0 0x10>;
900 pinctrl-names = "default";
901 pinctrl-0 = <&pwm0_pin>;
902 clocks = <&clk_gates13 6>;
903 clock-names = "pclk_pwm";
908 compatible = "rockchip,rk-pwm";
909 reg = <0x0 0xff680010 0x0 0x10>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&pwm1_pin>;
913 clocks = <&clk_gates13 6>;
914 clock-names = "pclk_pwm";
919 compatible = "rockchip,rk-pwm";
920 reg = <0x0 0xff680020 0x0 0x10>;
922 //pinctrl-names = "default";
923 //pinctrl-0 = <&pwm1_pin>;
924 clocks = <&clk_gates13 6>;
925 clock-names = "pclk_pwm";
930 compatible = "rockchip,rk-pwm";
931 reg = <0x0 0xff680030 0x0 0x10>;
933 pinctrl-names = "default";
934 pinctrl-0 = <&pwm3_pin>;
935 clocks = <&clk_gates13 6>;
936 clock-names = "pclk_pwm";
940 remotectl: pwm@ff680030 {
941 compatible = "rockchip,remotectl-pwm";
942 reg = <0x0 0xff680030 0x0 0x50>;
944 pinctrl-names = "default";
945 pinctrl-0 = <&pwm3_pin>;
946 clocks = <&clk_gates13 6>;
947 clock-names = "pclk_pwm";
952 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
956 voppwm: pwm@ff9301a0 {
957 compatible = "rockchip,vop-pwm";
958 reg = <0x0 0xff9301a0 0x0 0x10>;
960 pinctrl-names = "default";
961 pinctrl-0 = <&vop_pwm_pin>;
962 clocks = <&clk_gates4 2>, <&clk_gates16 5>, <&clk_gates16 6>;
963 clock-names = "pclk_pwm", "aclk_lcdc", "hclk_lcdc";
968 compatible = "rockchip,rk3368-pvtm";
969 rockchip,grf = <&grf>;
970 rockchip,pmugrf = <&pmugrf>;
971 rockchip,pvtm-clk-out = <1>;
975 compatible = "rockchip,rk3368-cpufreq";
976 rockchip,grf = <&grf>;
982 regulator_name = "vdd_arm";
983 suspend_volt = <1000>; //mV
985 clk_core_b_dvfs_table: clk_core_b {
994 temp-limit-enable = <1>;
996 min_temp_limit = <216>;
997 normal-temp-limit = <
998 /*delta-temp delta-freq*/
1004 performance-temp-limit = <
1009 clk_core_l_dvfs_table: clk_core_l {
1010 operating-points = <
1018 temp-limit-enable = <1>;
1020 min_temp_limit = <216>;
1021 normal-temp-limit = <
1022 /*delta-temp delta-freq*/
1028 performance-temp-limit = <
1036 vd_logic: vd_logic {
1037 regulator_name = "vdd_logic";
1038 suspend_volt = <1000>; //mV
1040 clk_ddr_dvfs_table: clk_ddr {
1041 operating-points = <
1048 status = "disabled";
1053 clk_gpu_dvfs_table: clk_gpu {
1054 operating-points = <
1074 compatible = "rockchip,ion";
1075 #address-cells = <1>;
1078 ion_cma: rockchip,ion-heap@4 { /* CMA HEAP */
1079 compatible = "rockchip,ion-heap";
1080 rockchip,ion_heap = <4>;
1081 reg = <0x00000000 0x08000000>; /* 512MB */
1083 rockchip,ion-heap@0 { /* VMALLOC HEAP */
1084 compatible = "rockchip,ion-heap";
1085 rockchip,ion_heap = <0>;
1090 compatible = "rockchip,vpu_sub";
1091 iommu_enabled = <0>;
1092 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1094 interrupt-names = "irq_enc", "irq_dec";
1096 name = "vpu_service";
1099 hevc: hevc_service {
1100 compatible = "rockchip,hevc_sub";
1101 iommu_enabled = <0>;
1102 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1103 interrupt-names = "irq_dec";
1105 name = "hevc_service";
1108 vpu_combo: vpu_combo@ff9a0000 {
1109 compatible = "rockchip,vpu_combo";
1110 reg = <0x0 0xff9a0000 0x0 0x800>;
1111 rockchip,grf = <&grf>;
1113 rockchip,sub = <&vpu>, <&hevc>;
1114 clocks = <&aclk_vdpu>, <&hclk_vdpu>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1115 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1117 mode_ctrl = <0x418>;
1123 compatible = "rockchip,iep";
1124 iommu_enabled = <0>;
1125 reg = <0x0 0xff900000 0x0 0x800>;
1126 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1127 clocks = <&clk_gates16 2>, <&clk_gates16 3>;
1128 clock-names = "aclk_iep", "hclk_iep";
1132 gmac: eth@ff290000 {
1133 compatible = "rockchip,rk3368-gmac";
1134 reg = <0x0 0xff290000 0x0 0x10000>;
1135 rockchip,grf = <&grf>;
1136 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1137 interrupt-names = "macirq";
1139 clocks = <&clk_mac>, <&clk_gates7 4>,
1140 <&clk_gates7 5>, <&clk_gates7 6>,
1141 <&clk_gates7 7>, <&clk_gates20 13>,
1143 clock-names = "clk_mac", "mac_clk_rx",
1144 "mac_clk_tx", "clk_mac_ref",
1145 "clk_mac_refout", "aclk_mac",
1149 pinctrl-names = "default";
1150 pinctrl-0 = <&rgmii_pins>;
1151 status = "disabled";
1155 compatible = "arm,rogue-G6110", "arm,rk3368-gpu";
1156 reg = <0x0 0xffa30000 0x0 0x10000>;
1157 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1158 interrupt-names = "GPU";
1163 compatible = "rockchip,iep_mmu";
1164 reg = <0x0 0xff900800 0x0 0x100>;
1165 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1166 interrupt-names = "iep_mmu";
1171 compatible = "rockchip,vip_mmu";
1172 reg = <0x0 0xff950800 0x0 0x100>;
1173 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1174 interrupt-names = "vip_mmu";
1179 compatible = "rockchip,vopb_mmu";
1180 reg = <0x0 0xff930300 0x0 0x100>;
1181 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1182 interrupt-names = "vop_mmu";
1186 dbgname = "isp_mmu";
1187 compatible = "rockchip,isp_mmu";
1188 reg = <0x0 0xff914000 0x0 0x100>,
1189 <0x0 0xff915000 0x0 0x100>;
1190 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1191 interrupt-names = "isp_mmu";
1195 dbgname = "hdcp_mmu";
1196 compatible = "rockchip,hdcp_mmu";
1197 reg = <0x0 0xff940000 0x0 0x100>;
1198 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1199 interrupt-names = "hdcp_mmu";
1204 compatible = "rockchip,hevc_mmu";
1205 reg = <0x0 0xff9a0440 0x0 0x40>, /*need to fix*/
1206 <0x0 0xff9a0480 0x0 0x40>;
1207 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1208 interrupt-names = "hevc_mmu";
1213 compatible = "rockchip,vpu_mmu";
1214 reg = <0x0 0xff9a0800 0x0 0x100>; /*need to fix*/
1215 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; /*need to fix*/
1216 interrupt-names = "vpu_mmu";
1220 rockchip,ctrbits = <
1227 |RKPM_CTR_SYSCLK_DIV
1228 |RKPM_CTR_IDLEAUTO_MD
1229 |RKPM_CTR_ARMOFF_LPMD
1231 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1234 rockchip,pmic-suspend_gpios = <
1235 /* RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H) */
1237 rockchip,pmic-resume_gpios = <
1238 /* RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN) */
1243 compatible = "rockchip,isp";
1244 reg = <0x0 0xff910000 0x0 0x10000>;
1245 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&clk_gates16 0>, <&clk_gates16 14>, <&clk_isp>, <&clk_isp>, <&pclk_isp>, <&clk_vip>, <&clk_vip_pll>, <&clk_gates17 4>, <&clk_gates22 11>, <&pd_isp>;
1247 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_cif_pll", "hclk_mipiphy1", "pclk_dphyrx", "pd_isp";
1248 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1249 pinctrl-0 = <&cif_clkout>;
1250 pinctrl-1 = <&cif_clkout &isp_dvp_d2d9>;
1251 pinctrl-2 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1>;
1252 pinctrl-3 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1253 pinctrl-4 = <&cif_clkout &isp_dvp_d0d7>;
1254 pinctrl-5 = <&cif_clkout>;
1255 pinctrl-6 = <&cif_clkout &isp_prelight>;
1256 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1257 pinctrl-8 = <&isp_flash_trigger>;
1258 rockchip,isp,mipiphy = <2>;
1259 rockchip,isp,cifphy = <1>;
1260 rockchip,isp,mipiphy1,reg = <0xff964000 0x4000>;
1261 rockchip,isp,csiphy,reg = <0xff96C000 0x4000>;
1262 rockchip,grf = <&grf>;
1263 rockchip,cru = <&cru>;
1264 rockchip,gpios = <&gpio3 GPIO_C4 GPIO_ACTIVE_HIGH>;
1265 rockchip,isp,iommu_enable = <0>;
1270 compatible = "rockchip,cif";
1271 reg = <0x0 0xff950000 0x0 0x10000>;
1272 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1273 //clocks = <&pd_isp>,<&clk_gates15 14>,<&clk_gates15 15>,<&pclkin_vip>,<&clk_gates16 0>,<&clk_cif_out>;
1274 clocks = <&clk_gates16 11>,<&clk_gates16 12>,<&pclkin_vip>,<&clk_vip>;
1275 clock-names = "aclk_cif0","hclk_cif0","cif0_in","cif0_out";
1276 pinctrl-names = "cif_pin_all";
1277 pinctrl-0 = <&cif_clkout &isp_dvp_d2d9 &isp_dvp_d10d11>;
1278 rockchip,grf = <&grf>;
1279 rockchip,cru = <&cru>;
1285 #include "rk3368-thermal.dtsi"
1289 tsadc: tsadc@ff280000 {
1290 compatible = "rockchip,rk3368-tsadc";
1291 reg = <0x0 0xff280000 0x0 0x100>;
1292 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1293 clocks = <&clk_tsadc>, <&clk_gates20 0>;
1294 rockchip,grf = <&grf>;
1295 rockchip,cru = <&cru>;
1296 rockchip,pmu = <&pmu>;
1297 clock-names = "tsadc", "apb_pclk";
1298 clock-frequency = <32000>;
1299 resets = <&reset RK3368_SRST_TSADC_P>;
1300 reset-names = "tsadc-apb";
1301 //pinctrl-names = "default";
1302 //pinctrl-0 = <&tsadc_int>;
1303 #thermal-sensor-cells = <1>;
1304 hw-shut-temp = <120000>;
1305 status = "disabled";
1309 compatible = "rockchip,rk3368-tsp";
1310 reg = <0x0 0xFF8B0000 0x0 0x10000>;
1311 clocks = <&clk_tsp>, <&clk_gates13 10>, <&clk_gates13 7>;
1312 clock-names = "clk_tsp", "hclk_tsp", "clk_hsadc0_tsp";
1313 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1314 interrupt-names = "irq_tsp";
1315 // pinctrl-names = "default";
1316 // pinctrl-0 = <&isp_hsadc>;
1320 crypto: crypto@FF8A0000{
1321 compatible = "rockchip,rk3368-crypto";
1322 reg = <0x0 0xFF8A0000 0x0 0x10000>;
1323 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1324 interrupt-names = "irq_crypto";
1325 clocks = <&clk_crypto>, <&clk_gates13 4>, <&clk_gates13 3>;
1326 clock-names = "clk_crypto", "sclk_crypto", "mclk_crypto";
1330 dwc_control_usb: dwc-control-usb {
1331 compatible = "rockchip,rk3368-dwc-control-usb";
1332 rockchip,grf = <&grf>;
1333 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1334 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1335 interrupt-names = "otg_id", "otg_bvalid",
1336 "otg_linestate", "host0_linestate";
1337 clocks = <&clk_gates20 6>, <&usbphy_480m>;
1338 clock-names = "hclk_usb_peri", "usbphy_480m";
1339 //resets = <&reset RK3128_RST_USBPOR>;
1340 //reset-names = "usbphy_por";
1342 compatible = "inno,phy";
1343 regbase = &dwc_control_usb;
1344 rk_usb,bvalid = <0x4bc 23 1>;
1345 rk_usb,iddig = <0x4bc 26 1>;
1346 rk_usb,vdmsrcen = <0x718 12 1>;
1347 rk_usb,vdpsrcen = <0x718 11 1>;
1348 rk_usb,rdmpden = <0x718 10 1>;
1349 rk_usb,idpsrcen = <0x718 9 1>;
1350 rk_usb,idmsinken = <0x718 8 1>;
1351 rk_usb,idpsinken = <0x718 7 1>;
1352 rk_usb,dpattach = <0x4b8 31 1>;
1353 rk_usb,cpdet = <0x4b8 30 1>;
1354 rk_usb,dcpattach = <0x4b8 29 1>;
1358 usb0: usb@ff580000 {
1359 compatible = "rockchip,rk3368_usb20_otg";
1360 reg = <0x0 0xff580000 0x0 0x40000>;
1361 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1362 clocks = <&clk_gates8 1>, <&clk_gates20 1>;
1363 clock-names = "clk_usbphy0", "hclk_otg";
1364 resets = <&reset RK3368_SRST_USBOTG0_H>, <&reset RK3368_SRST_USBOTGPHY0>,
1365 <&reset RK3368_SRST_USBOTGC0>;
1366 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1367 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1368 rockchip,usb-mode = <0>;
1371 usb_ehci: usb@ff500000 {
1372 compatible = "generic-ehci";
1373 reg = <0x0 0xff500000 0x0 0x20000>;
1374 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1375 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1376 clock-names = "clk_usbphy0", "hclk_ehci";
1377 //resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1378 // <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1379 //reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1382 usb_ohci: usb@ff520000 {
1383 compatible = "generic-ohci";
1384 reg = <0x0 0xff520000 0x0 0x20000>;
1385 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1386 clocks = <&clk_gates8 1>, <&clk_gates20 3>;
1387 clock-names = "clk_usbphy0", "hclk_ohci";
1390 usb_hsic: usb@ff5c0000 {
1391 compatible = "rockchip,rk3288_rk_hsic_host";
1392 reg = <0x0 0xff5c0000 0x0 0x40000>;
1393 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1395 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1396 <&hsicphy_12m>, <&usbphy_480m>,
1397 <&otgphy1_480m>, <&otgphy2_480m>;
1398 clock-names = "hsicphy_480m", "hclk_hsic",
1399 "hsicphy_12m", "usbphy_480m",
1400 "hsic_usbphy1", "hsic_usbphy2";
1401 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1402 <&reset RK3288_SOFT_RST_HSICPHY>;
1403 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1405 status = "disabled";
1409 compatible = "rockchip,rk3368-pinctrl";
1410 rockchip,grf = <&grf>;
1411 rockchip,pmugrf = <&pmugrf>;
1412 #address-cells = <2>;
1416 gpio0: gpio0@ff750000 {
1417 compatible = "rockchip,gpio-bank";
1418 reg = <0x0 0xff750000 0x0 0x100>;
1419 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1420 clocks = <&clk_gates23 4>;
1425 interrupt-controller;
1426 #interrupt-cells = <2>;
1429 gpio1: gpio1@ff780000 {
1430 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff780000 0x0 0x100>;
1432 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&clk_gates22 1>;
1438 interrupt-controller;
1439 #interrupt-cells = <2>;
1442 gpio2: gpio2@ff790000 {
1443 compatible = "rockchip,gpio-bank";
1444 reg = <0x0 0xff790000 0x0 0x100>;
1445 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1446 clocks = <&clk_gates22 2>;
1451 interrupt-controller;
1452 #interrupt-cells = <2>;
1455 gpio3: gpio3@ff7a0000 {
1456 compatible = "rockchip,gpio-bank";
1457 reg = <0x0 0xff7a0000 0x0 0x100>;
1458 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&clk_gates22 3>;
1464 interrupt-controller;
1465 #interrupt-cells = <2>;
1468 pcfg_pull_up: pcfg-pull-up {
1472 pcfg_pull_down: pcfg-pull-down {
1476 pcfg_pull_none: pcfg-pull-none {
1480 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
1481 drive-strength = <8>;
1484 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
1485 drive-strength = <12>;
1488 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
1490 drive-strength = <8>;
1493 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
1494 drive-strength = <4>;
1497 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
1499 drive-strength = <4>;
1502 pcfg_output_high: pcfg-output-high {
1506 pcfg_output_low: pcfg-output-low {
1511 i2c0_xfer: i2c0-xfer {
1512 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
1513 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
1515 i2c0_gpio: i2c0-gpio {
1516 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
1517 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
1522 i2c1_xfer: i2c1-xfer {
1523 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1524 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>;
1526 i2c1_gpio: i2c1-gpio {
1527 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
1528 <2 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>;
1533 i2c2_xfer: i2c2-xfer {
1534 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>,
1535 <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
1537 i2c2_gpio: i2c2-gpio {
1538 rockchip,pins = <3 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,
1539 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>;
1544 i2c3_xfer: i2c3-xfer {
1545 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1546 <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1548 i2c3_gpio: i2c3-gpio {
1549 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1550 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
1555 i2c4_xfer: i2c4-xfer {
1556 rockchip,pins = <3 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>,
1557 <3 GPIO_D1 RK_FUNC_2 &pcfg_pull_none>;
1559 i2c4_gpio: i2c4-gpio {
1560 rockchip,pins = <3 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,
1561 <3 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>;
1566 i2c5_xfer: i2c5-xfer {
1567 rockchip,pins = <3 GPIO_D2 RK_FUNC_2 &pcfg_pull_none>,
1568 <3 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1570 i2c5_gpio: i2c5-gpio {
1571 rockchip,pins = <3 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,
1572 <3 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1577 uart0_xfer: uart0-xfer {
1578 rockchip,pins = <2 GPIO_D0 RK_FUNC_1 &pcfg_pull_up>,
1579 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
1582 uart0_cts: uart0-cts {
1583 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1586 uart0_rts: uart0-rts {
1587 rockchip,pins = <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1590 uart0_rts_gpio: uart0-rts-gpio {
1591 rockchip,pins = <2 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>;
1596 uart1_xfer: uart1-xfer {
1597 rockchip,pins = <0 GPIO_C4 RK_FUNC_3 &pcfg_pull_up>,
1598 <0 GPIO_C5 RK_FUNC_3 &pcfg_pull_none>;
1601 uart1_cts: uart1-cts {
1602 rockchip,pins = <0 GPIO_C6 RK_FUNC_3 &pcfg_pull_none>;
1605 uart1_rts: uart1-rts {
1606 rockchip,pins = <0 GPIO_C7 RK_FUNC_3 &pcfg_pull_none>;
1611 uart2_xfer: uart2-xfer {
1612 rockchip,pins = <2 GPIO_A6 RK_FUNC_2 &pcfg_pull_up>,
1613 <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1618 uart3_xfer: uart3-xfer {
1619 rockchip,pins = <3 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>,
1620 <3 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1623 uart3_cts: uart3-cts {
1624 rockchip,pins = <3 GPIO_C0 RK_FUNC_2 &pcfg_pull_none>;
1627 uart3_rts: uart3-rts {
1628 rockchip,pins = <3 GPIO_C1 RK_FUNC_2 &pcfg_pull_none>;
1633 uart4_xfer: uart4-xfer {
1634 rockchip,pins = <0 GPIO_D3 RK_FUNC_3 &pcfg_pull_up>,
1635 <0 GPIO_D2 RK_FUNC_3 &pcfg_pull_none>;
1638 uart4_cts: uart4-cts {
1639 rockchip,pins = <0 GPIO_D0 RK_FUNC_3 &pcfg_pull_none>;
1642 uart4_rts: uart4-rts {
1643 rockchip,pins = <0 GPIO_D1 RK_FUNC_3 &pcfg_pull_none>;
1648 spi0_clk: spi0-clk {
1649 rockchip,pins = <1 GPIO_D5 RK_FUNC_2 &pcfg_pull_up>;
1651 spi0_cs0: spi0-cs0 {
1652 rockchip,pins = <1 GPIO_D0 RK_FUNC_3 &pcfg_pull_up>;
1655 rockchip,pins = <1 GPIO_C7 RK_FUNC_3 &pcfg_pull_up>;
1658 rockchip,pins = <1 GPIO_C6 RK_FUNC_3 &pcfg_pull_up>;
1660 spi0_cs1: spi0-cs1 {
1661 rockchip,pins = <1 GPIO_D1 RK_FUNC_3 &pcfg_pull_up>;
1666 spi1_clk: spi1-clk {
1667 rockchip,pins = <1 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
1669 spi1_cs0: spi1-cs0 {
1670 rockchip,pins = <1 GPIO_B7 RK_FUNC_2 &pcfg_pull_up>;
1673 rockchip,pins = <1 GPIO_C0 RK_FUNC_2 &pcfg_pull_up>;
1676 rockchip,pins = <1 GPIO_C1 RK_FUNC_2 &pcfg_pull_up>;
1678 spi1_cs1: spi1-cs1 {
1679 rockchip,pins = <3 GPIO_D4 RK_FUNC_2 &pcfg_pull_up>;
1684 spi2_clk: spi2-clk {
1685 rockchip,pins = <0 GPIO_B4 RK_FUNC_2 &pcfg_pull_up>;
1687 spi2_cs0: spi2-cs0 {
1688 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
1691 rockchip,pins = <0 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>;
1694 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
1699 i2s_mclk: i2s-mclk {
1700 rockchip,pins = <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1704 rockchip,pins = <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
1707 i2s_lrckrx:i2s-lrckrx {
1708 rockchip,pins = <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
1711 i2s_lrcktx:i2s-lrcktx {
1712 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
1716 rockchip,pins = <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1720 rockchip,pins = <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>;
1724 rockchip,pins = <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
1728 rockchip,pins = <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>;
1732 rockchip,pins = <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>;
1735 i2s_gpio: i2s-gpio {
1736 rockchip,pins = <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,
1737 <2 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
1738 <2 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
1739 <2 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
1740 <2 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,
1741 <2 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,
1742 <2 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,
1743 <2 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,
1744 <2 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>;
1749 spdif_tx: spdif-tx {
1750 rockchip,pins = <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
1755 sdmmc_clk: sdmmc-clk {
1756 rockchip,pins = <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1759 sdmmc_cmd: sdmmc-cmd {
1760 rockchip,pins = <2 GPIO_B2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1763 sdmmc_dectn: sdmmc-dectn {
1764 rockchip,pins = <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1767 sdmmc_bus1: sdmmc-bus1 {
1768 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1771 sdmmc_bus4: sdmmc-bus4 {
1772 rockchip,pins = <2 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1773 <2 GPIO_A6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1774 <2 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1775 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1778 sdmmc_gpio: sdmmc-gpio {
1779 rockchip,pins = <2 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1780 <2 GPIO_B2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1781 <2 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1782 <2 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1783 <2 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1784 <2 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1785 <2 GPIO_B0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1790 sdio0_bus1: sdio0-bus1 {
1791 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1794 sdio0_bus4: sdio0-bus4 {
1795 rockchip,pins = <2 GPIO_D4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1796 <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1797 <2 GPIO_D6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1798 <2 GPIO_D7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1801 sdio0_cmd: sdio0-cmd {
1802 rockchip,pins = <3 GPIO_A0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1805 sdio0_clk: sdio0-clk {
1806 rockchip,pins = <3 GPIO_A1 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1809 sdio0_dectn: sdio0-dectn {
1810 rockchip,pins = <3 GPIO_A2 RK_FUNC_1 &pcfg_pull_up>;
1813 sdio0_wrprt: sdio0-wrprt {
1814 rockchip,pins = <3 GPIO_A3 RK_FUNC_1 &pcfg_pull_up>;
1817 sdio0_pwren: sdio0-pwren {
1818 rockchip,pins = <3 GPIO_A4 RK_FUNC_1 &pcfg_pull_up>;
1821 sdio0_bkpwr: sdio0-bkpwr {
1822 rockchip,pins = <3 GPIO_A5 RK_FUNC_1 &pcfg_pull_up>;
1825 sdio0_int: sdio0-int {
1826 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_up>;
1829 sdio0_gpio: sdio0-gpio {
1830 rockchip,pins = <3 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CMD
1831 <3 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//CLK
1832 <3 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DET
1833 <3 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//wrprt
1834 <3 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//PWREN
1835 <3 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//BKPWR
1836 <3 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//INTN
1837 <2 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//DO
1838 <2 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D1
1839 <2 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,//D2
1840 <2 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;//D3
1845 emmc_clk: emmc-clk {
1846 rockchip,pins = <2 GPIO_A4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1849 emmc_cmd: emmc-cmd {
1850 rockchip,pins = <1 GPIO_D2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1853 emmc_pwren: emmc-pwren {
1854 rockchip,pins = <1 GPIO_D3 RK_FUNC_2 &pcfg_pull_none>;
1857 emmc_rstnout: emmc_rstnout {
1858 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_none>;
1861 emmc_bus1: emmc-bus1 {
1862 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//DO
1865 emmc_bus4: emmc-bus4 {
1866 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//DO
1867 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D1
1868 <1 GPIO_C4 RK_FUNC_2 &pcfg_pull_up_drv_8ma>,//D2
1869 <1 GPIO_C5 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;//D3
1874 pwm0_pin: pwm0-pin {
1875 rockchip,pins = <3 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1878 vop_pwm_pin:vop-pwm {
1879 rockchip,pins = <3 GPIO_B0 RK_FUNC_3 &pcfg_pull_none>;
1884 pwm1_pin: pwm1-pin {
1885 rockchip,pins = <0 GPIO_B0 RK_FUNC_2 &pcfg_pull_none>;
1890 pwm3_pin: pwm3-pin {
1891 rockchip,pins = <3 GPIO_D6 RK_FUNC_3 &pcfg_pull_none>;
1896 lcdc_lcdc: lcdc-lcdc {
1898 <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D10
1899 <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D11
1900 <0 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D12
1901 <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D13
1902 <0 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D14
1903 <0 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D15
1904 <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D16
1905 <0 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D17
1906 <0 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D18
1907 <0 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D19
1908 <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D20
1909 <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D21
1910 <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D22
1911 <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>,//LCDC_D23
1912 <0 GPIO_D7 RK_FUNC_1 &pcfg_pull_none>,//DCLK
1913 <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_none>,//DEN
1914 <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>,//HSYNC
1915 <0 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;//VSYN
1918 lcdc_gpio: lcdc-gpio {
1920 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D10
1921 <0 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D11
1922 <0 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D12
1923 <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D13
1924 <0 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D14
1925 <0 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D15
1926 <0 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D16
1927 <0 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D17
1928 <0 GPIO_C6 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D18
1929 <0 GPIO_C7 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D19
1930 <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D20
1931 <0 GPIO_D1 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D21
1932 <0 GPIO_D2 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D22
1933 <0 GPIO_D3 RK_FUNC_GPIO &pcfg_pull_none>,//LCDC_D23
1934 <0 GPIO_D7 RK_FUNC_GPIO &pcfg_pull_none>,//DCLK
1935 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_none>,//DEN
1936 <0 GPIO_D4 RK_FUNC_GPIO &pcfg_pull_none>,//HSYNC
1937 <0 GPIO_D5 RK_FUNC_GPIO &pcfg_pull_none>;//VSYN
1942 cif_clkout: cif-clkout {
1943 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1946 isp_dvp_d2d9: isp-dvp-d2d9 {
1947 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1948 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1949 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1950 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1951 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1952 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>,//cif_data7
1953 <1 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,//cif_data8
1954 <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>,//cif_data9
1955 <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,//cif_sync
1956 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>,//cif_href
1957 <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_none>,//cif_clkin
1958 <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;//cif_clkout
1961 isp_dvp_d0d1: isp-dvp-d0d1 {
1962 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1963 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;//cif_data1
1966 isp_dvp_d10d11:isp_d10d11 {
1967 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,//cif_data10
1968 <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;//cif_data11
1971 isp_dvp_d0d7: isp-dvp-d0d7 {
1972 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,//cif_data0
1973 <1 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>,//cif_data1
1974 <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,//cif_data2
1975 <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>,//cif_data3
1976 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,//cif_data4
1977 <1 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>,//cif_data5
1978 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_none>,//cif_data6
1979 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_none>;//cif_data7
1982 isp_shutter: isp-shutter {
1983 rockchip,pins = <3 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>, //SHUTTEREN
1984 <3 GPIO_C6 RK_FUNC_2 &pcfg_pull_none>;//SHUTTERTRIG
1987 isp_flash_trigger: isp-flash-trigger {
1988 rockchip,pins = <3 GPIO_C4 RK_FUNC_2 &pcfg_pull_none>; //ISP_FLASHTRIGOU
1991 isp_prelight: isp-prelight {
1992 rockchip,pins = <3 GPIO_C5 RK_FUNC_2 &pcfg_pull_none>;//ISP_PRELIGHTTRIG
1995 isp_flash_trigger_as_gpio: isp_flash_trigger_as_gpio {
1996 rockchip,pins = <3 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;//ISP_FLASHTRIGOU
2002 rockchip,pins = <3 GPIO_B6 RK_FUNC_2 &pcfg_pull_none>;
2006 rockchip,pins = <3 GPIO_B7 RK_FUNC_2 &pcfg_pull_none>;
2010 gps_rfclk: gps-rfclk {
2011 rockchip,pins = <3 GPIO_C0 RK_FUNC_3 &pcfg_pull_none>;
2016 rgmii_pins: rgmii-pins {
2017 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2018 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2019 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2020 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2021 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2022 <3 GPIO_B2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD2
2023 <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD3
2024 <3 GPIO_D4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXCLK
2025 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2026 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2027 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2028 <3 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,//RXD2
2029 <3 GPIO_C2 RK_FUNC_1 &pcfg_pull_none>,//RXD3
2030 <3 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,//RXCLK
2031 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;//RXDV
2034 rmii_pins: rmii-pins {
2035 rockchip,pins = <3 GPIO_C6 RK_FUNC_1 &pcfg_pull_none>,//MAC_CLK
2036 <3 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>,//MDIO
2037 <3 GPIO_C3 RK_FUNC_1 &pcfg_pull_none>,//MDC
2038 <3 GPIO_B0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD0
2039 <3 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXD1
2040 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,//TXEN
2041 <3 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>,//RXD0
2042 <3 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,//RXD1
2043 <3 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,//RXDV
2044 <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;//RXER
2049 tsadc_int: tsadc-int {
2050 rockchip,pins = <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
2052 tsadc_gpio: tsadc-gpio {
2053 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
2058 hdmi_cec: hdmi-cec {
2059 rockchip,pins = <3 GPIO_C7 RK_FUNC_1 &pcfg_pull_none>;
2064 hdmii2c_xfer: hdmii2c-xfer {
2065 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>,
2066 <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
2071 cpu_jtag: cpu-jtag {
2072 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_up>,
2073 <2 GPIO_B0 RK_FUNC_2 &pcfg_pull_up>;
2079 compatible = "rockchip,rk3368-reboot";
2080 rockchip,cru = <&cru>;
2081 rockchip,pmugrf = <&pmugrf>;