arch/arm/mach-rockchip/vcodec_service.c

   1 /**
   2  * Copyright (C) 2014 ROCKCHIP, Inc.
   3  * author: chenhengming chm@rock-chips.com
   4  *         Alpha Lin, alpha.lin@rock-chips.com
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19 #include <linux/clk.h>
  20 #include <linux/compat.h>
  21 #include <linux/delay.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/fs.h>
  28 #include <linux/ioport.h>
  29 #include <linux/miscdevice.h>
  30 #include <linux/mm.h>
  31 #include <linux/poll.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/reset.h>
  34 #include <linux/sched.h>
  35 #include <linux/slab.h>
  36 #include <linux/wakelock.h>
  37 #include <linux/cdev.h>
  38 #include <linux/of.h>
  39 #include <linux/of_platform.h>
  40 #include <linux/of_irq.h>
  41 #include <linux/rockchip/cpu.h>
  42 #include <linux/rockchip/cru.h>
  43 #include <linux/rockchip/pmu.h>
  44 #include <linux/regmap.h>
  45 #include <linux/mfd/syscon.h>
  46
  47 #include <asm/cacheflush.h>
  48 #include <linux/uaccess.h>
  49 #include <linux/rockchip/grf.h>
  50
  51 #if defined(CONFIG_ION_ROCKCHIP)
  52 #include <linux/rockchip_ion.h>
  53 #endif
  54
  55 #if defined(CONFIG_ROCKCHIP_IOMMU) & defined(CONFIG_ION_ROCKCHIP)
  56 #define CONFIG_VCODEC_MMU
  57 #endif
  58
  59 #ifdef CONFIG_VCODEC_MMU
  60 #include <linux/rockchip-iovmm.h>
  61 #include <linux/dma-buf.h>
  62 #endif
  63
  64 #ifdef CONFIG_DEBUG_FS
  65 #include <linux/debugfs.h>
  66 #endif
  67
  68 #if defined(CONFIG_ARCH_RK319X)
  69 #include <mach/grf.h>
  70 #endif
  71
  72 #include "vcodec_service.h"
  73
  74 /*
  75  * debug flag usage:
  76  * +------+-------------------+
  77  * | 8bit |      24bit        |
  78  * +------+-------------------+
  79  *  0~23 bit is for different information type
  80  * 24~31 bit is for information print format
  81  */
  82
  83 #define DEBUG_POWER                             0x00000001
  84 #define DEBUG_CLOCK                             0x00000002
  85 #define DEBUG_IRQ_STATUS                        0x00000004
  86 #define DEBUG_IOMMU                             0x00000008
  87 #define DEBUG_IOCTL                             0x00000010
  88 #define DEBUG_FUNCTION                          0x00000020
  89 #define DEBUG_REGISTER                          0x00000040
  90 #define DEBUG_EXTRA_INFO                        0x00000080
  91 #define DEBUG_TIMING                            0x00000100
  92
  93 #define PRINT_FUNCTION                          0x80000000
  94 #define PRINT_LINE                              0x40000000
  95
  96 static int debug;
  97 module_param(debug, int, S_IRUGO | S_IWUSR);
  98 MODULE_PARM_DESC(debug,
  99                  "Debug level - higher value produces more verbose messages");
 100
 101 #define HEVC_TEST_ENABLE        0
 102 #define VCODEC_CLOCK_ENABLE     1
 103
 104 typedef enum {
 105         VPU_DEC_ID_9190         = 0x6731,
 106         VPU_ID_8270             = 0x8270,
 107         VPU_ID_4831             = 0x4831,
 108         HEVC_ID                 = 0x6867,
 109 } VPU_HW_ID;
 110
 111 enum VPU_HW_SPEC {
 112         VPU_TYPE_VPU,
 113         VPU_TYPE_HEVC,
 114         VPU_TYPE_COMBO_NOENC,
 115         VPU_TYPE_COMBO
 116 };
 117
 118 typedef enum {
 119         VPU_DEC_TYPE_9190       = 0,
 120         VPU_ENC_TYPE_8270       = 0x100,
 121         VPU_ENC_TYPE_4831       ,
 122 } VPU_HW_TYPE_E;
 123
 124 typedef enum VPU_FREQ {
 125         VPU_FREQ_200M,
 126         VPU_FREQ_266M,
 127         VPU_FREQ_300M,
 128         VPU_FREQ_400M,
 129         VPU_FREQ_500M,
 130         VPU_FREQ_600M,
 131         VPU_FREQ_DEFAULT,
 132         VPU_FREQ_BUT,
 133 } VPU_FREQ;
 134
 135 typedef struct {
 136         VPU_HW_ID               hw_id;
 137         unsigned long           hw_addr;
 138         unsigned long           enc_offset;
 139         unsigned long           enc_reg_num;
 140         unsigned long           enc_io_size;
 141         unsigned long           dec_offset;
 142         unsigned long           dec_reg_num;
 143         unsigned long           dec_io_size;
 144 } VPU_HW_INFO_E;
 145
 146 struct extra_info_elem {
 147         u32 index;
 148         u32 offset;
 149 };
 150
 151 #define EXTRA_INFO_MAGIC        0x4C4A46
 152
 153 struct extra_info_for_iommu {
 154         u32 magic;
 155         u32 cnt;
 156         struct extra_info_elem elem[20];
 157 };
 158
 159 #define MHZ                                     (1000*1000)
 160
 161 #define REG_NUM_9190_DEC                        (60)
 162 #define REG_NUM_9190_PP                         (41)
 163 #define REG_NUM_9190_DEC_PP                     (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 164
 165 #define REG_NUM_DEC_PP                          (REG_NUM_9190_DEC+REG_NUM_9190_PP)
 166
 167 #define REG_NUM_ENC_8270                        (96)
 168 #define REG_SIZE_ENC_8270                       (0x200)
 169 #define REG_NUM_ENC_4831                        (164)
 170 #define REG_SIZE_ENC_4831                       (0x400)
 171
 172 #define REG_NUM_HEVC_DEC                        (68)
 173
 174 #define SIZE_REG(reg)                           ((reg)*4)
 175
 176 static VPU_HW_INFO_E vpu_hw_set[] = {
 177         [0] = {
 178                 .hw_id          = VPU_ID_8270,
 179                 .hw_addr        = 0,
 180                 .enc_offset     = 0x0,
 181                 .enc_reg_num    = REG_NUM_ENC_8270,
 182                 .enc_io_size    = REG_NUM_ENC_8270 * 4,
 183                 .dec_offset     = REG_SIZE_ENC_8270,
 184                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 185                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 186         },
 187         [1] = {
 188                 .hw_id          = VPU_ID_4831,
 189                 .hw_addr        = 0,
 190                 .enc_offset     = 0x0,
 191                 .enc_reg_num    = REG_NUM_ENC_4831,
 192                 .enc_io_size    = REG_NUM_ENC_4831 * 4,
 193                 .dec_offset     = REG_SIZE_ENC_4831,
 194                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 195                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 196         },
 197         [2] = {
 198                 .hw_id          = HEVC_ID,
 199                 .hw_addr        = 0,
 200                 .dec_offset     = 0x0,
 201                 .dec_reg_num    = REG_NUM_HEVC_DEC,
 202                 .dec_io_size    = REG_NUM_HEVC_DEC * 4,
 203         },
 204         [3] = {
 205                 .hw_id          = VPU_DEC_ID_9190,
 206                 .hw_addr        = 0,
 207                 .enc_offset     = 0x0,
 208                 .enc_reg_num    = 0,
 209                 .enc_io_size    = 0,
 210                 .dec_offset     = 0,
 211                 .dec_reg_num    = REG_NUM_9190_DEC_PP,
 212                 .dec_io_size    = REG_NUM_9190_DEC_PP * 4,
 213         },
 214 };
 215
 216 #ifndef BIT
 217 #define BIT(x)                                  (1<<(x))
 218 #endif
 219
 220 // interrupt and error status register
 221 #define DEC_INTERRUPT_REGISTER                  1
 222 #define DEC_INTERRUPT_BIT                       BIT(8)
 223 #define DEC_READY_BIT                           BIT(12)
 224 #define DEC_BUS_ERROR_BIT                       BIT(13)
 225 #define DEC_BUFFER_EMPTY_BIT                    BIT(14)
 226 #define DEC_ASO_ERROR_BIT                       BIT(15)
 227 #define DEC_STREAM_ERROR_BIT                    BIT(16)
 228 #define DEC_SLICE_DONE_BIT                      BIT(17)
 229 #define DEC_TIMEOUT_BIT                         BIT(18)
 230 #define DEC_ERR_MASK                            DEC_BUS_ERROR_BIT \
 231                                                 |DEC_BUFFER_EMPTY_BIT \
 232                                                 |DEC_STREAM_ERROR_BIT \
 233                                                 |DEC_TIMEOUT_BIT
 234
 235 #define PP_INTERRUPT_REGISTER                   60
 236 #define PP_INTERRUPT_BIT                        BIT(8)
 237 #define PP_READY_BIT                            BIT(12)
 238 #define PP_BUS_ERROR_BIT                        BIT(13)
 239 #define PP_ERR_MASK                             PP_BUS_ERROR_BIT
 240
 241 #define ENC_INTERRUPT_REGISTER                  1
 242 #define ENC_INTERRUPT_BIT                       BIT(0)
 243 #define ENC_READY_BIT                           BIT(2)
 244 #define ENC_BUS_ERROR_BIT                       BIT(3)
 245 #define ENC_BUFFER_FULL_BIT                     BIT(5)
 246 #define ENC_TIMEOUT_BIT                         BIT(6)
 247 #define ENC_ERR_MASK                            ENC_BUS_ERROR_BIT \
 248                                                 |ENC_BUFFER_FULL_BIT \
 249                                                 |ENC_TIMEOUT_BIT
 250
 251 #define HEVC_INTERRUPT_REGISTER                 1
 252 #define HEVC_DEC_INT_RAW_BIT                    BIT(9)
 253 #define HEVC_DEC_BUS_ERROR_BIT                  BIT(13)
 254 #define HEVC_DEC_STR_ERROR_BIT                  BIT(14)
 255 #define HEVC_DEC_TIMEOUT_BIT                    BIT(15)
 256 #define HEVC_DEC_BUFFER_EMPTY_BIT               BIT(16)
 257 #define HEVC_DEC_COLMV_ERROR_BIT                BIT(17)
 258 #define HEVC_DEC_ERR_MASK                       HEVC_DEC_BUS_ERROR_BIT \
 259                                                 |HEVC_DEC_STR_ERROR_BIT \
 260                                                 |HEVC_DEC_TIMEOUT_BIT \
 261                                                 |HEVC_DEC_BUFFER_EMPTY_BIT \
 262                                                 |HEVC_DEC_COLMV_ERROR_BIT
 263
 264
 265 // gating configuration set
 266 #define VPU_REG_EN_ENC                          14
 267 #define VPU_REG_ENC_GATE                        2
 268 #define VPU_REG_ENC_GATE_BIT                    (1<<4)
 269
 270 #define VPU_REG_EN_DEC                          1
 271 #define VPU_REG_DEC_GATE                        2
 272 #define VPU_REG_DEC_GATE_BIT                    (1<<10)
 273 #define VPU_REG_EN_PP                           0
 274 #define VPU_REG_PP_GATE                         1
 275 #define VPU_REG_PP_GATE_BIT                     (1<<8)
 276 #define VPU_REG_EN_DEC_PP                       1
 277 #define VPU_REG_DEC_PP_GATE                     61
 278 #define VPU_REG_DEC_PP_GATE_BIT                 (1<<8)
 279
 280 #define DEBUG
 281 #ifdef DEBUG
 282 #define vpu_debug_func(type, fmt, args...)                      \
 283         do {                                                    \
 284                 if (unlikely(debug & type)) {                   \
 285                         pr_info("%s:%d: " fmt,                  \
 286                                  __func__, __LINE__, ##args);   \
 287                 }                                               \
 288         } while (0)
 289 #define vpu_debug(type, fmt, args...)                           \
 290         do {                                                    \
 291                 if (unlikely(debug & type)) {                   \
 292                         pr_info(fmt, ##args);                   \
 293                 }                                               \
 294         } while (0)
 295 #else
 296 #define vpu_debug_func(level, fmt, args...)
 297 #define vpu_debug(level, fmt, args...)
 298 #endif
 299
 300 #define vpu_debug_enter() vpu_debug_func(DEBUG_FUNCTION, "enter\n")
 301 #define vpu_debug_leave() vpu_debug_func(DEBUG_FUNCTION, "leave\n")
 302
 303 #define vpu_err(fmt, args...)                           \
 304                 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
 305
 306 #if defined(CONFIG_VCODEC_MMU)
 307 static u8 addr_tbl_vpu_h264dec[] = {
 308         12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24,
 309         25, 26, 27, 28, 29, 40, 41
 310 };
 311
 312 static u8 addr_tbl_vpu_vp8dec[] = {
 313         10, 12, 13, 14, 18, 19, 22, 23, 24, 25, 26, 27, 28, 29, 40
 314 };
 315
 316 static u8 addr_tbl_vpu_vp6dec[] = {
 317         12, 13, 14, 18, 27, 40
 318 };
 319
 320 static u8 addr_tbl_vpu_vc1dec[] = {
 321         12, 13, 14, 15, 16, 17, 27, 41
 322 };
 323
 324 static u8 addr_tbl_vpu_jpegdec[] = {
 325         12, 40, 66, 67
 326 };
 327
 328 static u8 addr_tbl_vpu_defaultdec[] = {
 329         12, 13, 14, 15, 16, 17, 40, 41
 330 };
 331
 332 static u8 addr_tbl_vpu_enc[] = {
 333         5, 6, 7, 8, 9, 10, 11, 12, 13, 51
 334 };
 335
 336 static u8 addr_tbl_hevc_dec[] = {
 337         4, 6, 7, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
 338         21, 22, 23, 24, 42, 43
 339 };
 340 #endif
 341
 342 enum VPU_DEC_FMT {
 343         VPU_DEC_FMT_H264,
 344         VPU_DEC_FMT_MPEG4,
 345         VPU_DEC_FMT_H263,
 346         VPU_DEC_FMT_JPEG,
 347         VPU_DEC_FMT_VC1,
 348         VPU_DEC_FMT_MPEG2,
 349         VPU_DEC_FMT_MPEG1,
 350         VPU_DEC_FMT_VP6,
 351         VPU_DEC_FMT_RV,
 352         VPU_DEC_FMT_VP7,
 353         VPU_DEC_FMT_VP8,
 354         VPU_DEC_FMT_AVS,
 355         VPU_DEC_FMT_SVC,
 356         VPU_DEC_FMT_VC2,
 357         VPU_DEC_FMT_MVC,
 358         VPU_DEC_FMT_THEORA,
 359         VPU_DEC_FMT_RES
 360 };
 361
 362 /**
 363  * struct for process session which connect to vpu
 364  *
 365  * @author ChenHengming (2011-5-3)
 366  */
 367 typedef struct vpu_session {
 368         enum VPU_CLIENT_TYPE type;
 369         /* a linked list of data so we can access them for debugging */
 370         struct list_head list_session;
 371         /* a linked list of register data waiting for process */
 372         struct list_head waiting;
 373         /* a linked list of register data in processing */
 374         struct list_head running;
 375         /* a linked list of register data processed */
 376         struct list_head done;
 377         wait_queue_head_t wait;
 378         pid_t pid;
 379         atomic_t task_running;
 380 } vpu_session;
 381
 382 /**
 383  * struct for process register set
 384  *
 385  * @author ChenHengming (2011-5-4)
 386  */
 387 typedef struct vpu_reg {
 388         enum VPU_CLIENT_TYPE type;
 389         VPU_FREQ freq;
 390         vpu_session *session;
 391         struct vpu_subdev_data *data;
 392         struct list_head session_link;          /* link to vpu service session */
 393         struct list_head status_link;           /* link to register set list */
 394         unsigned long size;
 395 #if defined(CONFIG_VCODEC_MMU)
 396         struct list_head mem_region_list;
 397         u32 dec_base;
 398 #endif
 399         u32 *reg;
 400 } vpu_reg;
 401
 402 typedef struct vpu_device {
 403         atomic_t                irq_count_codec;
 404         atomic_t                irq_count_pp;
 405         unsigned long           iobaseaddr;
 406         unsigned int            iosize;
 407         volatile u32            *hwregs;
 408 } vpu_device;
 409
 410 enum vcodec_device_id {
 411         VCODEC_DEVICE_ID_VPU,
 412         VCODEC_DEVICE_ID_HEVC,
 413         VCODEC_DEVICE_ID_COMBO
 414 };
 415
 416 enum VCODEC_RUNNING_MODE {
 417         VCODEC_RUNNING_MODE_NONE = -1,
 418         VCODEC_RUNNING_MODE_VPU,
 419         VCODEC_RUNNING_MODE_HEVC,
 420 };
 421
 422 struct vcodec_mem_region {
 423         struct list_head srv_lnk;
 424         struct list_head reg_lnk;
 425         struct list_head session_lnk;
 426         unsigned long iova;     /* virtual address for iommu */
 427         unsigned long len;
 428         u32 reg_idx;
 429         struct ion_handle *hdl;
 430 };
 431
 432 enum vpu_ctx_state {
 433         MMU_ACTIVATED   = BIT(0)
 434 };
 435
 436 struct vpu_subdev_data {
 437         struct cdev cdev;
 438         dev_t dev_t;
 439         struct class *cls;
 440         struct device *child_dev;
 441
 442         int irq_enc;
 443         int irq_dec;
 444         struct vpu_service_info *pservice;
 445
 446         u32 *regs;
 447         enum VCODEC_RUNNING_MODE mode;
 448         struct list_head lnk_service;
 449
 450         struct device *dev;
 451
 452         vpu_device enc_dev;
 453         vpu_device dec_dev;
 454         VPU_HW_INFO_E *hw_info;
 455
 456         u32 reg_size;
 457         unsigned long state;
 458
 459 #ifdef CONFIG_DEBUG_FS
 460         struct dentry *debugfs_dir;
 461         struct dentry *debugfs_file_regs;
 462 #endif
 463
 464 #if defined(CONFIG_VCODEC_MMU)
 465         struct device *mmu_dev;
 466 #endif
 467 };
 468
 469 typedef struct vpu_service_info {
 470         struct wake_lock wake_lock;
 471         struct delayed_work power_off_work;
 472         struct mutex lock;
 473         struct list_head waiting;               /* link to link_reg in struct vpu_reg */
 474         struct list_head running;               /* link to link_reg in struct vpu_reg */
 475         struct list_head done;                  /* link to link_reg in struct vpu_reg */
 476         struct list_head session;               /* link to list_session in struct vpu_session */
 477         atomic_t total_running;
 478         atomic_t enabled;
 479         atomic_t power_on_cnt;
 480         atomic_t power_off_cnt;
 481         vpu_reg *reg_codec;
 482         vpu_reg *reg_pproc;
 483         vpu_reg *reg_resev;
 484         struct vpu_dec_config dec_config;
 485         struct vpu_enc_config enc_config;
 486
 487         bool auto_freq;
 488         bool bug_dec_addr;
 489         atomic_t freq_status;
 490
 491         struct clk *aclk_vcodec;
 492         struct clk *hclk_vcodec;
 493         struct clk *clk_core;
 494         struct clk *clk_cabac;
 495         struct clk *pd_video;
 496
 497 #ifdef CONFIG_RESET_CONTROLLER
 498         struct reset_control *rst_a;
 499         struct reset_control *rst_h;
 500         struct reset_control *rst_v;
 501 #endif
 502         struct device *dev;
 503
 504         u32 irq_status;
 505         atomic_t reset_request;
 506 #if defined(CONFIG_VCODEC_MMU)
 507         struct ion_client *ion_client;
 508         struct list_head mem_region_list;
 509 #endif
 510
 511         enum vcodec_device_id dev_id;
 512
 513         enum VCODEC_RUNNING_MODE curr_mode;
 514         u32 prev_mode;
 515
 516         struct delayed_work simulate_work;
 517
 518         u32 mode_bit;
 519         u32 mode_ctrl;
 520         u32 *reg_base;
 521         u32 ioaddr;
 522         struct regmap *grf;
 523         u32 *grf_base;
 524
 525         char *name;
 526
 527         u32 subcnt;
 528         struct list_head subdev_list;
 529 } vpu_service_info;
 530
 531 struct vcodec_combo {
 532         struct vpu_service_info *vpu_srv;
 533         struct vpu_service_info *hevc_srv;
 534         struct list_head waiting;
 535         struct list_head running;
 536         struct mutex run_lock;
 537         vpu_reg *reg_codec;
 538         enum vcodec_device_id current_hw_mode;
 539 };
 540
 541 struct vpu_request {
 542         u32 *req;
 543         u32 size;
 544 };
 545
 546 #ifdef CONFIG_COMPAT
 547 struct compat_vpu_request {
 548         compat_uptr_t req;
 549         u32 size;
 550 };
 551 #endif
 552
 553 /* debugfs root directory for all device (vpu, hevc).*/
 554 static struct dentry *parent;
 555
 556 #ifdef CONFIG_DEBUG_FS
 557 static int vcodec_debugfs_init(void);
 558 static void vcodec_debugfs_exit(void);
 559 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent);
 560 static int debug_vcodec_open(struct inode *inode, struct file *file);
 561
 562 static const struct file_operations debug_vcodec_fops = {
 563         .open = debug_vcodec_open,
 564         .read = seq_read,
 565         .llseek = seq_lseek,
 566         .release = single_release,
 567 };
 568 #endif
 569
 570 #define VDPU_SOFT_RESET_REG     101
 571 #define VDPU_CLEAN_CACHE_REG    516
 572 #define VEPU_CLEAN_CACHE_REG    772
 573 #define HEVC_CLEAN_CACHE_REG    260
 574
 575 #define VPU_REG_ENABLE(base, reg)       do { \
 576                                                 base[reg] = 1; \
 577                                         } while (0)
 578
 579 #define VDPU_SOFT_RESET(base)   VPU_REG_ENABLE(base, VDPU_SOFT_RESET_REG)
 580 #define VDPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VDPU_CLEAN_CACHE_REG)
 581 #define VEPU_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, VEPU_CLEAN_CACHE_REG)
 582 #define HEVC_CLEAN_CACHE(base)  VPU_REG_ENABLE(base, HEVC_CLEAN_CACHE_REG)
 583
 584 #define VPU_POWER_OFF_DELAY             4*HZ /* 4s */
 585 #define VPU_TIMEOUT_DELAY               2*HZ /* 2s */
 586
 587 typedef struct {
 588         char *name;
 589         struct timeval start;
 590         struct timeval end;
 591         u32 error_mask;
 592 } task_info;
 593
 594 typedef enum {
 595         TASK_VPU_ENC,
 596         TASK_VPU_DEC,
 597         TASK_VPU_PP,
 598         TASK_RKDEC_HEVC,
 599         TASK_TYPE_BUTT,
 600 } TASK_TYPE;
 601
 602 task_info tasks[TASK_TYPE_BUTT] = {
 603         {
 604                 .name = "enc",
 605                 .error_mask = ENC_ERR_MASK
 606         },
 607         {
 608                 .name = "dec",
 609                 .error_mask = DEC_ERR_MASK
 610         },
 611         {
 612                 .name = "pp",
 613                 .error_mask = PP_ERR_MASK
 614         },
 615         {
 616                 .name = "hevc",
 617                 .error_mask = HEVC_DEC_ERR_MASK
 618         },
 619 };
 620
 621 static void time_record(task_info *task, int is_end)
 622 {
 623         if (unlikely(debug & DEBUG_TIMING)) {
 624                 do_gettimeofday((is_end)?(&task->end):(&task->start));
 625         }
 626 }
 627
 628 static void time_diff(task_info *task)
 629 {
 630         vpu_debug(DEBUG_TIMING, "%s task: %ld ms\n", task->name,
 631                         (task->end.tv_sec  - task->start.tv_sec)  * 1000 +
 632                         (task->end.tv_usec - task->start.tv_usec) / 1000);
 633 }
 634
 635 static void vcodec_enter_mode(struct vpu_subdev_data *data)
 636 {
 637         int bits;
 638         u32 raw = 0;
 639         struct vpu_service_info *pservice = data->pservice;
 640         struct vpu_subdev_data *subdata, *n;
 641         if (pservice->subcnt < 2) {
 642 #if defined(CONFIG_VCODEC_MMU)
 643                 if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 644                         set_bit(MMU_ACTIVATED, &data->state);
 645                         if (atomic_read(&pservice->enabled))
 646                                 rockchip_iovmm_activate(data->dev);
 647                         else
 648                                 BUG_ON(!atomic_read(&pservice->enabled));
 649                 }
 650 #endif
 651                 return;
 652         }
 653
 654         if (pservice->curr_mode == data->mode)
 655                 return;
 656
 657         vpu_debug(DEBUG_IOMMU, "vcodec enter mode %d\n", data->mode);
 658 #if defined(CONFIG_VCODEC_MMU)
 659         list_for_each_entry_safe(subdata, n, &pservice->subdev_list, lnk_service) {
 660                 if (data != subdata && subdata->mmu_dev &&
 661                     test_bit(MMU_ACTIVATED, &subdata->state)) {
 662                         clear_bit(MMU_ACTIVATED, &subdata->state);
 663                         rockchip_iovmm_deactivate(subdata->dev);
 664                 }
 665         }
 666 #endif
 667         bits = 1 << pservice->mode_bit;
 668 #ifdef CONFIG_MFD_SYSCON
 669         if (pservice->grf) {
 670                 regmap_read(pservice->grf, pservice->mode_ctrl, &raw);
 671
 672                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 673                         regmap_write(pservice->grf, pservice->mode_ctrl,
 674                                 raw | bits | (bits << 16));
 675                 else
 676                         regmap_write(pservice->grf, pservice->mode_ctrl,
 677                                 (raw & (~bits)) | (bits << 16));
 678         } else if (pservice->grf_base) {
 679                 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 680                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 681                         writel_relaxed(raw | bits | (bits << 16),
 682                                 pservice->grf_base + pservice->mode_ctrl / 4);
 683                 else
 684                         writel_relaxed((raw & (~bits)) | (bits << 16),
 685                                 pservice->grf_base + pservice->mode_ctrl / 4);
 686         } else {
 687                 vpu_err("no grf resource define, switch decoder failed\n");
 688                 return;
 689         }
 690 #else
 691         if (pervice->grf_base) {
 692                 raw = readl_relaxed(pservice->grf_base + pservice->mode_ctrl / 4);
 693                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
 694                         writel_relaxed(raw | bits | (bits << 16),
 695                                 pservice->grf_base + pservice->mode_ctrl / 4);
 696                 else
 697                         writel_relaxed((raw & (~bits)) | (bits << 16),
 698                                 pservice->grf_base + pservice->mode_ctrl / 4);
 699         } else {
 700                 vpu_err("no grf resource define, switch decoder failed\n");
 701                 return;
 702         }
 703 #endif
 704 #if defined(CONFIG_VCODEC_MMU)
 705         if (data->mmu_dev && !test_bit(MMU_ACTIVATED, &data->state)) {
 706                 set_bit(MMU_ACTIVATED, &data->state);
 707                 if (atomic_read(&pservice->enabled))
 708                         rockchip_iovmm_activate(data->dev);
 709                 else
 710                         BUG_ON(!atomic_read(&pservice->enabled));
 711         }
 712 #endif
 713         pservice->prev_mode = pservice->curr_mode;
 714         pservice->curr_mode = data->mode;
 715 }
 716
 717 static void vcodec_exit_mode(struct vpu_subdev_data *data)
 718 {
 719         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 720                 clear_bit(MMU_ACTIVATED, &data->state);
 721                 rockchip_iovmm_deactivate(data->dev);
 722                 data->pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 723         }
 724 }
 725
 726 static int vpu_get_clk(struct vpu_service_info *pservice)
 727 {
 728 #if VCODEC_CLOCK_ENABLE
 729         switch (pservice->dev_id) {
 730         case VCODEC_DEVICE_ID_HEVC:
 731                 pservice->pd_video = devm_clk_get(pservice->dev, "pd_hevc");
 732                 if (IS_ERR(pservice->pd_video)) {
 733                         dev_err(pservice->dev, "failed on clk_get pd_hevc\n");
 734                         return -1;
 735                 }
 736         case VCODEC_DEVICE_ID_COMBO:
 737                 pservice->clk_cabac = devm_clk_get(pservice->dev, "clk_cabac");
 738                 if (IS_ERR(pservice->clk_cabac)) {
 739                         dev_err(pservice->dev, "failed on clk_get clk_cabac\n");
 740                         pservice->clk_cabac = NULL;
 741                 }
 742                 pservice->clk_core = devm_clk_get(pservice->dev, "clk_core");
 743                 if (IS_ERR(pservice->clk_core)) {
 744                         dev_err(pservice->dev, "failed on clk_get clk_core\n");
 745                         return -1;
 746                 }
 747         case VCODEC_DEVICE_ID_VPU:
 748                 pservice->aclk_vcodec = devm_clk_get(pservice->dev, "aclk_vcodec");
 749                 if (IS_ERR(pservice->aclk_vcodec)) {
 750                         dev_err(pservice->dev, "failed on clk_get aclk_vcodec\n");
 751                         return -1;
 752                 }
 753
 754                 pservice->hclk_vcodec = devm_clk_get(pservice->dev, "hclk_vcodec");
 755                 if (IS_ERR(pservice->hclk_vcodec)) {
 756                         dev_err(pservice->dev, "failed on clk_get hclk_vcodec\n");
 757                         return -1;
 758                 }
 759                 if (pservice->pd_video == NULL) {
 760                         pservice->pd_video = devm_clk_get(pservice->dev, "pd_video");
 761                         if (IS_ERR(pservice->pd_video)) {
 762                                 pservice->pd_video = NULL;
 763                                 dev_info(pservice->dev, "do not have pd_video\n");
 764                         }
 765                 }
 766                 break;
 767         default:
 768                 ;
 769         }
 770
 771         return 0;
 772 #else
 773         return 0;
 774 #endif
 775 }
 776
 777 static void vpu_put_clk(struct vpu_service_info *pservice)
 778 {
 779 #if VCODEC_CLOCK_ENABLE
 780         if (pservice->pd_video)
 781                 devm_clk_put(pservice->dev, pservice->pd_video);
 782         if (pservice->aclk_vcodec)
 783                 devm_clk_put(pservice->dev, pservice->aclk_vcodec);
 784         if (pservice->hclk_vcodec)
 785                 devm_clk_put(pservice->dev, pservice->hclk_vcodec);
 786         if (pservice->clk_core)
 787                 devm_clk_put(pservice->dev, pservice->clk_core);
 788         if (pservice->clk_cabac)
 789                 devm_clk_put(pservice->dev, pservice->clk_cabac);
 790 #endif
 791 }
 792
 793 static void vpu_reset(struct vpu_subdev_data *data)
 794 {
 795         struct vpu_service_info *pservice = data->pservice;
 796         enum pmu_idle_req type = IDLE_REQ_VIDEO;
 797
 798         if (pservice->dev_id == VCODEC_DEVICE_ID_HEVC)
 799                 type = IDLE_REQ_HEVC;
 800
 801         pr_info("%s: resetting...", dev_name(pservice->dev));
 802
 803 #if defined(CONFIG_ARCH_RK29)
 804         clk_disable(aclk_ddr_vepu);
 805         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, true);
 806         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, true);
 807         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, true);
 808         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, true);
 809         mdelay(10);
 810         cru_set_soft_reset(SOFT_RST_VCODEC_AXI_BUS, false);
 811         cru_set_soft_reset(SOFT_RST_VCODEC_AHB_BUS, false);
 812         cru_set_soft_reset(SOFT_RST_DDR_VCODEC_PORT, false);
 813         cru_set_soft_reset(SOFT_RST_CPU_VODEC_A2A_AHB, false);
 814         clk_enable(aclk_ddr_vepu);
 815 #elif defined(CONFIG_ARCH_RK30)
 816         pmu_set_idle_request(IDLE_REQ_VIDEO, true);
 817         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, true);
 818         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, true);
 819         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, true);
 820         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, true);
 821         mdelay(1);
 822         cru_set_soft_reset(SOFT_RST_VCODEC_AXI, false);
 823         cru_set_soft_reset(SOFT_RST_VCODEC_AHB, false);
 824         cru_set_soft_reset(SOFT_RST_VCODEC_NIU_AXI, false);
 825         cru_set_soft_reset(SOFT_RST_CPU_VCODEC, false);
 826         pmu_set_idle_request(IDLE_REQ_VIDEO, false);
 827 #else
 828 #endif
 829         WARN_ON(pservice->reg_codec != NULL);
 830         WARN_ON(pservice->reg_pproc != NULL);
 831         WARN_ON(pservice->reg_resev != NULL);
 832         pservice->reg_codec = NULL;
 833         pservice->reg_pproc = NULL;
 834         pservice->reg_resev = NULL;
 835
 836         pr_info("for 3288/3368...");
 837 #ifdef CONFIG_RESET_CONTROLLER
 838         if (pservice->rst_a && pservice->rst_h) {
 839                 if (rockchip_pmu_ops.set_idle_request)
 840                         rockchip_pmu_ops.set_idle_request(type, true);
 841                 pr_info("reset in\n");
 842                 if (pservice->rst_v)
 843                         reset_control_assert(pservice->rst_v);
 844                 reset_control_assert(pservice->rst_a);
 845                 reset_control_assert(pservice->rst_h);
 846                 usleep_range(10, 20);
 847                 reset_control_deassert(pservice->rst_h);
 848                 reset_control_deassert(pservice->rst_a);
 849                 if (pservice->rst_v)
 850                         reset_control_deassert(pservice->rst_v);
 851                 if (rockchip_pmu_ops.set_idle_request)
 852                         rockchip_pmu_ops.set_idle_request(type, false);
 853         }
 854 #endif
 855
 856 #if defined(CONFIG_VCODEC_MMU)
 857         if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 858                 clear_bit(MMU_ACTIVATED, &data->state);
 859                 if (atomic_read(&pservice->enabled))
 860                         rockchip_iovmm_deactivate(data->dev);
 861                 else
 862                         BUG_ON(!atomic_read(&pservice->enabled));
 863         }
 864 #endif
 865         atomic_set(&pservice->reset_request, 0);
 866         pr_info("done\n");
 867 }
 868
 869 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg);
 870 static void vpu_service_session_clear(struct vpu_subdev_data *data, vpu_session *session)
 871 {
 872         vpu_reg *reg, *n;
 873         list_for_each_entry_safe(reg, n, &session->waiting, session_link) {
 874                 reg_deinit(data, reg);
 875         }
 876         list_for_each_entry_safe(reg, n, &session->running, session_link) {
 877                 reg_deinit(data, reg);
 878         }
 879         list_for_each_entry_safe(reg, n, &session->done, session_link) {
 880                 reg_deinit(data, reg);
 881         }
 882 }
 883
 884 static void vpu_service_dump(struct vpu_service_info *pservice)
 885 {
 886 }
 887
 888 static void vpu_service_power_off(struct vpu_service_info *pservice)
 889 {
 890         int total_running;
 891         struct vpu_subdev_data *data = NULL, *n;
 892         int ret = atomic_add_unless(&pservice->enabled, -1, 0);
 893         if (!ret)
 894                 return;
 895
 896         total_running = atomic_read(&pservice->total_running);
 897         if (total_running) {
 898                 pr_alert("alert: power off when %d task running!!\n", total_running);
 899                 mdelay(50);
 900                 pr_alert("alert: delay 50 ms for running task\n");
 901                 vpu_service_dump(pservice);
 902         }
 903
 904         pr_info("%s: power off...", dev_name(pservice->dev));
 905         udelay(10);
 906 #if defined(CONFIG_VCODEC_MMU)
 907         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
 908                 if (data->mmu_dev && test_bit(MMU_ACTIVATED, &data->state)) {
 909                         clear_bit(MMU_ACTIVATED, &data->state);
 910                         rockchip_iovmm_deactivate(data->dev);
 911                 }
 912         }
 913         pservice->curr_mode = VCODEC_RUNNING_MODE_NONE;
 914 #endif
 915
 916 #if VCODEC_CLOCK_ENABLE
 917         if (pservice->pd_video)
 918                 clk_disable_unprepare(pservice->pd_video);
 919         if (pservice->hclk_vcodec)
 920                 clk_disable_unprepare(pservice->hclk_vcodec);
 921         if (pservice->aclk_vcodec)
 922                 clk_disable_unprepare(pservice->aclk_vcodec);
 923         if (pservice->clk_core)
 924                 clk_disable_unprepare(pservice->clk_core);
 925         if (pservice->clk_cabac)
 926                 clk_disable_unprepare(pservice->clk_cabac);
 927 #endif
 928
 929         atomic_add(1, &pservice->power_off_cnt);
 930         wake_unlock(&pservice->wake_lock);
 931         pr_info("done\n");
 932 }
 933
 934 static inline void vpu_queue_power_off_work(struct vpu_service_info *pservice)
 935 {
 936         queue_delayed_work(system_nrt_wq, &pservice->power_off_work, VPU_POWER_OFF_DELAY);
 937 }
 938
 939 static void vpu_power_off_work(struct work_struct *work_s)
 940 {
 941         struct delayed_work *dlwork = container_of(work_s, struct delayed_work, work);
 942         struct vpu_service_info *pservice = container_of(dlwork, struct vpu_service_info, power_off_work);
 943
 944         if (mutex_trylock(&pservice->lock)) {
 945                 vpu_service_power_off(pservice);
 946                 mutex_unlock(&pservice->lock);
 947         } else {
 948                 /* Come back later if the device is busy... */
 949                 vpu_queue_power_off_work(pservice);
 950         }
 951 }
 952
 953 static void vpu_service_power_on(struct vpu_service_info *pservice)
 954 {
 955         int ret;
 956         static ktime_t last;
 957         ktime_t now = ktime_get();
 958         if (ktime_to_ns(ktime_sub(now, last)) > NSEC_PER_SEC) {
 959                 cancel_delayed_work_sync(&pservice->power_off_work);
 960                 vpu_queue_power_off_work(pservice);
 961                 last = now;
 962         }
 963         ret = atomic_add_unless(&pservice->enabled, 1, 1);
 964         if (!ret)
 965                 return ;
 966
 967         pr_info("%s: power on\n", dev_name(pservice->dev));
 968
 969 #define BIT_VCODEC_CLK_SEL      (1<<10)
 970         if (cpu_is_rk312x())
 971                 writel_relaxed(readl_relaxed(RK_GRF_VIRT + RK312X_GRF_SOC_CON1) |
 972                         BIT_VCODEC_CLK_SEL | (BIT_VCODEC_CLK_SEL << 16),
 973                         RK_GRF_VIRT + RK312X_GRF_SOC_CON1);
 974
 975 #if VCODEC_CLOCK_ENABLE
 976         if (pservice->aclk_vcodec)
 977                 clk_prepare_enable(pservice->aclk_vcodec);
 978         if (pservice->hclk_vcodec)
 979                 clk_prepare_enable(pservice->hclk_vcodec);
 980         if (pservice->clk_core)
 981                 clk_prepare_enable(pservice->clk_core);
 982         if (pservice->clk_cabac)
 983                 clk_prepare_enable(pservice->clk_cabac);
 984         if (pservice->pd_video)
 985                 clk_prepare_enable(pservice->pd_video);
 986 #endif
 987
 988         udelay(10);
 989         atomic_add(1, &pservice->power_on_cnt);
 990         wake_lock(&pservice->wake_lock);
 991 }
 992
 993 static inline bool reg_check_rmvb_wmv(vpu_reg *reg)
 994 {
 995         u32 type = (reg->reg[3] & 0xF0000000) >> 28;
 996         return ((type == 8) || (type == 4));
 997 }
 998
 999 static inline bool reg_check_interlace(vpu_reg *reg)
1000 {
1001         u32 type = (reg->reg[3] & (1 << 23));
1002         return (type > 0);
1003 }
1004
1005 static inline enum VPU_DEC_FMT reg_check_fmt(vpu_reg *reg)
1006 {
1007         enum VPU_DEC_FMT type = (enum VPU_DEC_FMT)((reg->reg[3] & 0xF0000000) >> 28);
1008         return type;
1009 }
1010
1011 static inline int reg_probe_width(vpu_reg *reg)
1012 {
1013         int width_in_mb = reg->reg[4] >> 23;
1014         return width_in_mb * 16;
1015 }
1016
1017 static inline int reg_probe_hevc_y_stride(vpu_reg *reg)
1018 {
1019         int y_virstride = reg->reg[8];
1020         return y_virstride;
1021 }
1022
1023 #if defined(CONFIG_VCODEC_MMU)
1024 static int vcodec_fd_to_iova(struct vpu_subdev_data *data, vpu_reg *reg,int fd)
1025 {
1026         struct vpu_service_info *pservice = data->pservice;
1027         struct ion_handle *hdl;
1028         int ret = 0;
1029         struct vcodec_mem_region *mem_region;
1030
1031         hdl = ion_import_dma_buf(pservice->ion_client, fd);
1032         if (IS_ERR(hdl)) {
1033                 vpu_err("import dma-buf from fd %d failed\n", fd);
1034                 return PTR_ERR(hdl);
1035         }
1036         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1037
1038         if (mem_region == NULL) {
1039                 vpu_err("allocate memory for iommu memory region failed\n");
1040                 ion_free(pservice->ion_client, hdl);
1041                 return -1;
1042         }
1043
1044         mem_region->hdl = hdl;
1045         ret = ion_map_iommu(data->dev, pservice->ion_client,
1046                 mem_region->hdl, &mem_region->iova, &mem_region->len);
1047
1048         if (ret < 0) {
1049                 vpu_err("ion map iommu failed\n");
1050                 kfree(mem_region);
1051                 ion_free(pservice->ion_client, hdl);
1052                 return ret;
1053         }
1054         INIT_LIST_HEAD(&mem_region->reg_lnk);
1055         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1056         return mem_region->iova;
1057 }
1058
1059 static int vcodec_bufid_to_iova(struct vpu_subdev_data *data, u8 *tbl,
1060                                 int size, vpu_reg *reg,
1061                                 struct extra_info_for_iommu *ext_inf)
1062 {
1063         struct vpu_service_info *pservice = data->pservice;
1064         int i;
1065         int usr_fd = 0;
1066         int offset = 0;
1067
1068         if (tbl == NULL || size <= 0) {
1069                 dev_err(pservice->dev, "input arguments invalidate\n");
1070                 return -1;
1071         }
1072
1073         for (i = 0; i < size; i++) {
1074                 usr_fd = reg->reg[tbl[i]] & 0x3FF;
1075
1076                 if (tbl[i] == 41 && data->hw_info->hw_id != HEVC_ID &&
1077                     (reg->type == VPU_DEC || reg->type == VPU_DEC_PP))
1078                         /* special for vpu dec num 41 regitster */
1079                         offset = reg->reg[tbl[i]] >> 10 << 4;
1080                 else
1081                         offset = reg->reg[tbl[i]] >> 10;
1082
1083                 if (usr_fd != 0) {
1084                         struct ion_handle *hdl;
1085                         int ret = 0;
1086                         struct vcodec_mem_region *mem_region;
1087
1088                         hdl = ion_import_dma_buf(pservice->ion_client, usr_fd);
1089                         if (IS_ERR(hdl)) {
1090                                 dev_err(pservice->dev, "import dma-buf from fd %d failed, reg[%d]\n", usr_fd, tbl[i]);
1091                                 return PTR_ERR(hdl);
1092                         }
1093
1094                         if (tbl[i] == 42 && data->hw_info->hw_id == HEVC_ID){
1095                                 int i = 0;
1096                                 char *pps;
1097                                 pps = (char *)ion_map_kernel(pservice->ion_client,hdl);
1098                                 for (i=0; i<64; i++) {
1099                                         u32 scaling_offset;
1100                                         u32 tmp;
1101                                         int scaling_fd= 0;
1102                                         scaling_offset = (u32)pps[i*80+74];
1103                                         scaling_offset += (u32)pps[i*80+75] << 8;
1104                                         scaling_offset += (u32)pps[i*80+76] << 16;
1105                                         scaling_offset += (u32)pps[i*80+77] << 24;
1106                                         scaling_fd = scaling_offset&0x3ff;
1107                                         scaling_offset = scaling_offset >> 10;
1108                                         if(scaling_fd > 0) {
1109                                                 tmp = vcodec_fd_to_iova(data, reg, scaling_fd);
1110                                                 tmp += scaling_offset;
1111                                                 pps[i*80+74] = tmp & 0xff;
1112                                                 pps[i*80+75] = (tmp >> 8) & 0xff;
1113                                                 pps[i*80+76] = (tmp >> 16) & 0xff;
1114                                                 pps[i*80+77] = (tmp >> 24) & 0xff;
1115                                         }
1116                                 }
1117                         }
1118
1119                         mem_region = kzalloc(sizeof(struct vcodec_mem_region), GFP_KERNEL);
1120
1121                         if (mem_region == NULL) {
1122                                 dev_err(pservice->dev, "allocate memory for iommu memory region failed\n");
1123                                 ion_free(pservice->ion_client, hdl);
1124                                 return -1;
1125                         }
1126
1127                         mem_region->hdl = hdl;
1128                         mem_region->reg_idx = tbl[i];
1129                         ret = ion_map_iommu(data->dev,
1130                                             pservice->ion_client,
1131                                             mem_region->hdl,
1132                                             &mem_region->iova,
1133                                             &mem_region->len);
1134
1135                         if (ret < 0) {
1136                                 dev_err(pservice->dev, "ion map iommu failed\n");
1137                                 kfree(mem_region);
1138                                 ion_free(pservice->ion_client, hdl);
1139                                 return ret;
1140                         }
1141
1142                         /* special for vpu dec num 12: record decoded length
1143                            hacking for decoded length
1144                            NOTE: not a perfect fix, the fd is not recorded */
1145                         if (tbl[i] == 12 && data->hw_info->hw_id != HEVC_ID &&
1146                                         (reg->type == VPU_DEC || reg->type == VPU_DEC_PP)) {
1147                                 reg->dec_base = mem_region->iova + offset;
1148                                 vpu_debug(DEBUG_REGISTER, "dec_set %08x\n", reg->dec_base);
1149                         }
1150
1151                         reg->reg[tbl[i]] = mem_region->iova + offset;
1152                         INIT_LIST_HEAD(&mem_region->reg_lnk);
1153                         list_add_tail(&mem_region->reg_lnk, &reg->mem_region_list);
1154                 }
1155         }
1156
1157         if (ext_inf != NULL && ext_inf->magic == EXTRA_INFO_MAGIC) {
1158                 for (i=0; i<ext_inf->cnt; i++) {
1159                         vpu_debug(DEBUG_IOMMU, "reg[%d] + offset %d\n",
1160                                   ext_inf->elem[i].index,
1161                                   ext_inf->elem[i].offset);
1162                         reg->reg[ext_inf->elem[i].index] +=
1163                                 ext_inf->elem[i].offset;
1164                 }
1165         }
1166
1167         return 0;
1168 }
1169
1170 static int vcodec_reg_address_translate(struct vpu_subdev_data *data,
1171                                         vpu_reg *reg,
1172                                         struct extra_info_for_iommu *ext_inf)
1173 {
1174         VPU_HW_ID hw_id;
1175         u8 *tbl;
1176         int size = 0;
1177
1178         hw_id = data->hw_info->hw_id;
1179
1180         if (hw_id == HEVC_ID) {
1181                 tbl = addr_tbl_hevc_dec;
1182                 size = sizeof(addr_tbl_hevc_dec);
1183         } else {
1184                 if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1185                         switch (reg_check_fmt(reg)) {
1186                         case VPU_DEC_FMT_H264:
1187                                 {
1188                                         tbl = addr_tbl_vpu_h264dec;
1189                                         size = sizeof(addr_tbl_vpu_h264dec);
1190                                         break;
1191                                 }
1192                         case VPU_DEC_FMT_VP8:
1193                         case VPU_DEC_FMT_VP7:
1194                                 {
1195                                         tbl = addr_tbl_vpu_vp8dec;
1196                                         size = sizeof(addr_tbl_vpu_vp8dec);
1197                                         break;
1198                                 }
1199
1200                         case VPU_DEC_FMT_VP6:
1201                                 {
1202                                         tbl = addr_tbl_vpu_vp6dec;
1203                                         size = sizeof(addr_tbl_vpu_vp6dec);
1204                                         break;
1205                                 }
1206                         case VPU_DEC_FMT_VC1:
1207                                 {
1208                                         tbl = addr_tbl_vpu_vc1dec;
1209                                         size = sizeof(addr_tbl_vpu_vc1dec);
1210                                         break;
1211                                 }
1212
1213                         case VPU_DEC_FMT_JPEG:
1214                                 {
1215                                         tbl = addr_tbl_vpu_jpegdec;
1216                                         size = sizeof(addr_tbl_vpu_jpegdec);
1217                                         break;
1218                                 }
1219                         default:
1220                                 tbl = addr_tbl_vpu_defaultdec;
1221                                 size = sizeof(addr_tbl_vpu_defaultdec);
1222                                 break;
1223                         }
1224                 } else if (reg->type == VPU_ENC) {
1225                         tbl = addr_tbl_vpu_enc;
1226                         size = sizeof(addr_tbl_vpu_enc);
1227                 }
1228         }
1229
1230         if (size != 0) {
1231                 return vcodec_bufid_to_iova(data, tbl, size, reg, ext_inf);
1232         } else {
1233                 return -1;
1234         }
1235 }
1236 #endif
1237
1238 static vpu_reg *reg_init(struct vpu_subdev_data *data,
1239         vpu_session *session, void __user *src, u32 size)
1240 {
1241         struct vpu_service_info *pservice = data->pservice;
1242         int extra_size = 0;
1243         struct extra_info_for_iommu extra_info;
1244         vpu_reg *reg = kmalloc(sizeof(vpu_reg) + data->reg_size, GFP_KERNEL);
1245
1246         vpu_debug_enter();
1247
1248         if (NULL == reg) {
1249                 vpu_err("error: kmalloc fail in reg_init\n");
1250                 return NULL;
1251         }
1252
1253         if (size > data->reg_size) {
1254                 /*printk("warning: vpu reg size %u is larger than hw reg size %u\n",
1255                   size, data->reg_size);*/
1256                 extra_size = size - data->reg_size;
1257                 size = data->reg_size;
1258         }
1259         reg->session = session;
1260         reg->data = data;
1261         reg->type = session->type;
1262         reg->size = size;
1263         reg->freq = VPU_FREQ_DEFAULT;
1264         reg->reg = (u32 *)&reg[1];
1265         INIT_LIST_HEAD(&reg->session_link);
1266         INIT_LIST_HEAD(&reg->status_link);
1267
1268 #if defined(CONFIG_VCODEC_MMU)
1269         if (data->mmu_dev)
1270                 INIT_LIST_HEAD(&reg->mem_region_list);
1271 #endif
1272
1273         if (copy_from_user(&reg->reg[0], (void __user *)src, size)) {
1274                 vpu_err("error: copy_from_user failed in reg_init\n");
1275                 kfree(reg);
1276                 return NULL;
1277         }
1278
1279         if (copy_from_user(&extra_info, (u8 *)src + size, extra_size)) {
1280                 vpu_err("error: copy_from_user failed in reg_init\n");
1281                 kfree(reg);
1282                 return NULL;
1283         }
1284
1285 #if defined(CONFIG_VCODEC_MMU)
1286         if (data->mmu_dev &&
1287             0 > vcodec_reg_address_translate(data, reg, &extra_info)) {
1288                 vpu_err("error: translate reg address failed\n");
1289                 kfree(reg);
1290                 return NULL;
1291         }
1292 #endif
1293
1294         mutex_lock(&pservice->lock);
1295         list_add_tail(&reg->status_link, &pservice->waiting);
1296         list_add_tail(&reg->session_link, &session->waiting);
1297         mutex_unlock(&pservice->lock);
1298
1299         if (pservice->auto_freq) {
1300                 if (!soc_is_rk2928g()) {
1301                         if (reg->type == VPU_DEC || reg->type == VPU_DEC_PP) {
1302                                 if (reg_check_rmvb_wmv(reg)) {
1303                                         reg->freq = VPU_FREQ_200M;
1304                                 } else if (reg_check_fmt(reg) == VPU_DEC_FMT_H264) {
1305                                         if (reg_probe_width(reg) > 3200) {
1306                                                 /*raise frequency for 4k avc.*/
1307                                                 reg->freq = VPU_FREQ_600M;
1308                                         }
1309                                 } else {
1310                                         if (reg_check_interlace(reg)) {
1311                                                 reg->freq = VPU_FREQ_400M;
1312                                         }
1313                                 }
1314                         }
1315                         if (data->hw_info->hw_id == HEVC_ID) {
1316                                 if (reg_probe_hevc_y_stride(reg) > 60000)
1317                                         reg->freq = VPU_FREQ_400M;
1318                         }
1319                         if (reg->type == VPU_PP) {
1320                                 reg->freq = VPU_FREQ_400M;
1321                         }
1322                 }
1323         }
1324         vpu_debug_leave();
1325         return reg;
1326 }
1327
1328 static void reg_deinit(struct vpu_subdev_data *data, vpu_reg *reg)
1329 {
1330         struct vpu_service_info *pservice = data->pservice;
1331 #if defined(CONFIG_VCODEC_MMU)
1332         struct vcodec_mem_region *mem_region = NULL, *n;
1333 #endif
1334
1335         list_del_init(&reg->session_link);
1336         list_del_init(&reg->status_link);
1337         if (reg == pservice->reg_codec)
1338                 pservice->reg_codec = NULL;
1339         if (reg == pservice->reg_pproc)
1340                 pservice->reg_pproc = NULL;
1341
1342 #if defined(CONFIG_VCODEC_MMU)
1343         /* release memory region attach to this registers table. */
1344         if (data->mmu_dev) {
1345                 list_for_each_entry_safe(mem_region, n,
1346                         &reg->mem_region_list, reg_lnk) {
1347                         /* do not unmap iommu manually,
1348                            unmap will proccess when memory release */
1349                         /*vcodec_enter_mode(data);
1350                         ion_unmap_iommu(data->dev,
1351                                         pservice->ion_client,
1352                                         mem_region->hdl);
1353                         vcodec_exit_mode();*/
1354                         ion_free(pservice->ion_client, mem_region->hdl);
1355                         list_del_init(&mem_region->reg_lnk);
1356                         kfree(mem_region);
1357                 }
1358         }
1359 #endif
1360
1361         kfree(reg);
1362 }
1363
1364 static void reg_from_wait_to_run(struct vpu_service_info *pservice, vpu_reg *reg)
1365 {
1366         vpu_debug_enter();
1367         list_del_init(&reg->status_link);
1368         list_add_tail(&reg->status_link, &pservice->running);
1369
1370         list_del_init(&reg->session_link);
1371         list_add_tail(&reg->session_link, &reg->session->running);
1372         vpu_debug_leave();
1373 }
1374
1375 static void reg_copy_from_hw(vpu_reg *reg, volatile u32 *src, u32 count)
1376 {
1377         int i;
1378         u32 *dst = (u32 *)&reg->reg[0];
1379         vpu_debug_enter();
1380         for (i = 0; i < count; i++)
1381                 *dst++ = *src++;
1382         vpu_debug_leave();
1383 }
1384
1385 static void reg_from_run_to_done(struct vpu_subdev_data *data,
1386         vpu_reg *reg)
1387 {
1388         struct vpu_service_info *pservice = data->pservice;
1389         int irq_reg = -1;
1390
1391         vpu_debug_enter();
1392
1393         list_del_init(&reg->status_link);
1394         list_add_tail(&reg->status_link, &pservice->done);
1395
1396         list_del_init(&reg->session_link);
1397         list_add_tail(&reg->session_link, &reg->session->done);
1398
1399         /*vcodec_enter_mode(data);*/
1400         switch (reg->type) {
1401         case VPU_ENC : {
1402                 pservice->reg_codec = NULL;
1403                 reg_copy_from_hw(reg, data->enc_dev.hwregs, data->hw_info->enc_reg_num);
1404                 irq_reg = ENC_INTERRUPT_REGISTER;
1405                 break;
1406         }
1407         case VPU_DEC : {
1408                 int reg_len = REG_NUM_9190_DEC;
1409                 pservice->reg_codec = NULL;
1410                 reg_copy_from_hw(reg, data->dec_dev.hwregs, reg_len);
1411 #if defined(CONFIG_VCODEC_MMU)
1412                 /* revert hack for decoded length */
1413                 if (data->hw_info->hw_id != HEVC_ID) {
1414                         u32 dec_get = reg->reg[12];
1415                         s32 dec_length = dec_get - reg->dec_base;
1416                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1417                         reg->reg[12] = dec_length << 10;
1418                 }
1419 #endif
1420                 irq_reg = DEC_INTERRUPT_REGISTER;
1421                 break;
1422         }
1423         case VPU_PP : {
1424                 pservice->reg_pproc = NULL;
1425                 reg_copy_from_hw(reg, data->dec_dev.hwregs + PP_INTERRUPT_REGISTER, REG_NUM_9190_PP);
1426                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1427                 break;
1428         }
1429         case VPU_DEC_PP : {
1430                 pservice->reg_codec = NULL;
1431                 pservice->reg_pproc = NULL;
1432                 reg_copy_from_hw(reg, data->dec_dev.hwregs, REG_NUM_9190_DEC_PP);
1433                 data->dec_dev.hwregs[PP_INTERRUPT_REGISTER] = 0;
1434 #if defined(CONFIG_VCODEC_MMU)
1435                 /* revert hack for decoded length */
1436                 if (data->hw_info->hw_id != HEVC_ID) {
1437                         u32 dec_get = reg->reg[12];
1438                         s32 dec_length = dec_get - reg->dec_base;
1439                         vpu_debug(DEBUG_REGISTER, "dec_get %08x dec_length %d\n", dec_get, dec_length);
1440                         reg->reg[12] = dec_length << 10;
1441                 }
1442 #endif
1443                 break;
1444         }
1445         default : {
1446                 vpu_err("error: copy reg from hw with unknown type %d\n", reg->type);
1447                 break;
1448         }
1449         }
1450         vcodec_exit_mode(data);
1451
1452         if (irq_reg != -1)
1453                 reg->reg[irq_reg] = pservice->irq_status;
1454
1455         atomic_sub(1, &reg->session->task_running);
1456         atomic_sub(1, &pservice->total_running);
1457         wake_up(&reg->session->wait);
1458
1459         vpu_debug_leave();
1460 }
1461
1462 static void vpu_service_set_freq(struct vpu_service_info *pservice, vpu_reg *reg)
1463 {
1464         VPU_FREQ curr = atomic_read(&pservice->freq_status);
1465         if (curr == reg->freq)
1466                 return;
1467         atomic_set(&pservice->freq_status, reg->freq);
1468         switch (reg->freq) {
1469         case VPU_FREQ_200M : {
1470                 clk_set_rate(pservice->aclk_vcodec, 200*MHZ);
1471         } break;
1472         case VPU_FREQ_266M : {
1473                 clk_set_rate(pservice->aclk_vcodec, 266*MHZ);
1474         } break;
1475         case VPU_FREQ_300M : {
1476                 clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1477         } break;
1478         case VPU_FREQ_400M : {
1479                 clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1480         } break;
1481         case VPU_FREQ_500M : {
1482                 clk_set_rate(pservice->aclk_vcodec, 500*MHZ);
1483         } break;
1484         case VPU_FREQ_600M : {
1485                 clk_set_rate(pservice->aclk_vcodec, 600*MHZ);
1486         } break;
1487         default : {
1488                 if (soc_is_rk2928g())
1489                         clk_set_rate(pservice->aclk_vcodec, 400*MHZ);
1490                 else
1491                         clk_set_rate(pservice->aclk_vcodec, 300*MHZ);
1492         } break;
1493         }
1494 }
1495
1496 static void reg_copy_to_hw(struct vpu_subdev_data *data, vpu_reg *reg)
1497 {
1498         struct vpu_service_info *pservice = data->pservice;
1499         int i;
1500         u32 *src = (u32 *)&reg->reg[0];
1501         vpu_debug_enter();
1502
1503         atomic_add(1, &pservice->total_running);
1504         atomic_add(1, &reg->session->task_running);
1505         if (pservice->auto_freq)
1506                 vpu_service_set_freq(pservice, reg);
1507
1508         vcodec_enter_mode(data);
1509
1510         switch (reg->type) {
1511         case VPU_ENC : {
1512                 int enc_count = data->hw_info->enc_reg_num;
1513                 u32 *dst = (u32 *)data->enc_dev.hwregs;
1514
1515                 pservice->reg_codec = reg;
1516
1517                 dst[VPU_REG_EN_ENC] = src[VPU_REG_EN_ENC] & 0x6;
1518
1519                 for (i = 0; i < VPU_REG_EN_ENC; i++)
1520                         dst[i] = src[i];
1521
1522                 for (i = VPU_REG_EN_ENC + 1; i < enc_count; i++)
1523                         dst[i] = src[i];
1524
1525                 VEPU_CLEAN_CACHE(dst);
1526
1527                 dsb(sy);
1528
1529                 dst[VPU_REG_ENC_GATE] = src[VPU_REG_ENC_GATE] | VPU_REG_ENC_GATE_BIT;
1530                 dst[VPU_REG_EN_ENC]   = src[VPU_REG_EN_ENC];
1531
1532                 time_record(&tasks[TASK_VPU_ENC], 0);
1533         } break;
1534         case VPU_DEC : {
1535                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1536
1537                 pservice->reg_codec = reg;
1538
1539                 if (data->hw_info->hw_id != HEVC_ID) {
1540                         for (i = REG_NUM_9190_DEC - 1; i > VPU_REG_DEC_GATE; i--)
1541                                 dst[i] = src[i];
1542                         VDPU_CLEAN_CACHE(dst);
1543                 } else {
1544                         for (i = REG_NUM_HEVC_DEC - 1; i > VPU_REG_EN_DEC; i--)
1545                                 dst[i] = src[i];
1546                         HEVC_CLEAN_CACHE(dst);
1547                 }
1548
1549                 dsb(sy);
1550
1551                 if (data->hw_info->hw_id != HEVC_ID) {
1552                         dst[VPU_REG_DEC_GATE] = src[VPU_REG_DEC_GATE] | VPU_REG_DEC_GATE_BIT;
1553                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1554                 } else {
1555                         dst[VPU_REG_EN_DEC] = src[VPU_REG_EN_DEC];
1556                 }
1557                 dsb(sy);
1558                 dmb(sy);
1559
1560                 time_record(&tasks[TASK_VPU_DEC], 0);
1561         } break;
1562         case VPU_PP : {
1563                 u32 *dst = (u32 *)data->dec_dev.hwregs + PP_INTERRUPT_REGISTER;
1564                 pservice->reg_pproc = reg;
1565
1566                 dst[VPU_REG_PP_GATE] = src[VPU_REG_PP_GATE] | VPU_REG_PP_GATE_BIT;
1567
1568                 for (i = VPU_REG_PP_GATE + 1; i < REG_NUM_9190_PP; i++)
1569                         dst[i] = src[i];
1570
1571                 dsb(sy);
1572
1573                 dst[VPU_REG_EN_PP] = src[VPU_REG_EN_PP];
1574
1575                 time_record(&tasks[TASK_VPU_PP], 0);
1576         } break;
1577         case VPU_DEC_PP : {
1578                 u32 *dst = (u32 *)data->dec_dev.hwregs;
1579                 pservice->reg_codec = reg;
1580                 pservice->reg_pproc = reg;
1581
1582                 VDPU_SOFT_RESET(dst);
1583                 VDPU_CLEAN_CACHE(dst);
1584
1585                 for (i = VPU_REG_EN_DEC_PP + 1; i < REG_NUM_9190_DEC_PP; i++)
1586                         dst[i] = src[i];
1587
1588                 dst[VPU_REG_EN_DEC_PP]   = src[VPU_REG_EN_DEC_PP] | 0x2;
1589                 dsb(sy);
1590
1591                 dst[VPU_REG_DEC_PP_GATE] = src[VPU_REG_DEC_PP_GATE] | VPU_REG_PP_GATE_BIT;
1592                 dst[VPU_REG_DEC_GATE]    = src[VPU_REG_DEC_GATE]    | VPU_REG_DEC_GATE_BIT;
1593                 dst[VPU_REG_EN_DEC]      = src[VPU_REG_EN_DEC];
1594
1595                 time_record(&tasks[TASK_VPU_DEC], 0);
1596         } break;
1597         default : {
1598                 vpu_err("error: unsupport session type %d", reg->type);
1599                 atomic_sub(1, &pservice->total_running);
1600                 atomic_sub(1, &reg->session->task_running);
1601         } break;
1602         }
1603
1604         /*vcodec_exit_mode(data);*/
1605         vpu_debug_leave();
1606 }
1607
1608 static void try_set_reg(struct vpu_subdev_data *data)
1609 {
1610         struct vpu_service_info *pservice = data->pservice;
1611         vpu_debug_enter();
1612         if (!list_empty(&pservice->waiting)) {
1613                 int can_set = 0;
1614                 bool change_able = (NULL == pservice->reg_codec) && (NULL == pservice->reg_pproc);
1615                 int reset_request = atomic_read(&pservice->reset_request);
1616                 vpu_reg *reg = list_entry(pservice->waiting.next, vpu_reg, status_link);
1617
1618                 vpu_service_power_on(pservice);
1619
1620                 // first check can_set flag
1621                 if (change_able || !reset_request) {
1622                         switch (reg->type) {
1623                         case VPU_ENC : {
1624                                 if (change_able)
1625                                         can_set = 1;
1626                         } break;
1627                         case VPU_DEC : {
1628                                 if (NULL == pservice->reg_codec)
1629                                         can_set = 1;
1630                                 if (pservice->auto_freq && (NULL != pservice->reg_pproc))
1631                                         can_set = 0;
1632                         } break;
1633                         case VPU_PP : {
1634                                 if (NULL == pservice->reg_codec) {
1635                                         if (NULL == pservice->reg_pproc)
1636                                                 can_set = 1;
1637                                 } else {
1638                                         if ((VPU_DEC == pservice->reg_codec->type) && (NULL == pservice->reg_pproc))
1639                                                 can_set = 1;
1640                                         /* can not charge frequency when vpu is working */
1641                                         if (pservice->auto_freq)
1642                                                 can_set = 0;
1643                                 }
1644                         } break;
1645                         case VPU_DEC_PP : {
1646                                 if (change_able)
1647                                         can_set = 1;
1648                                 } break;
1649                         default : {
1650                                 printk("undefined reg type %d\n", reg->type);
1651                         } break;
1652                         }
1653                 }
1654
1655                 // then check reset request
1656                 if (reset_request && !change_able)
1657                         reset_request = 0;
1658
1659                 // do reset before setting registers
1660                 if (reset_request)
1661                         vpu_reset(data);
1662
1663                 if (can_set) {
1664                         reg_from_wait_to_run(pservice, reg);
1665                         reg_copy_to_hw(reg->data, reg);
1666                 }
1667         }
1668         vpu_debug_leave();
1669 }
1670
1671 static int return_reg(struct vpu_subdev_data *data,
1672         vpu_reg *reg, u32 __user *dst)
1673 {
1674         int ret = 0;
1675         vpu_debug_enter();
1676         switch (reg->type) {
1677         case VPU_ENC : {
1678                 if (copy_to_user(dst, &reg->reg[0], data->hw_info->enc_io_size))
1679                         ret = -EFAULT;
1680                 break;
1681         }
1682         case VPU_DEC : {
1683                 int reg_len = data->hw_info->hw_id == HEVC_ID ? REG_NUM_HEVC_DEC : REG_NUM_9190_DEC;
1684                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(reg_len)))
1685                         ret = -EFAULT;
1686                 break;
1687         }
1688         case VPU_PP : {
1689                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_PP)))
1690                         ret = -EFAULT;
1691                 break;
1692         }
1693         case VPU_DEC_PP : {
1694                 if (copy_to_user(dst, &reg->reg[0], SIZE_REG(REG_NUM_9190_DEC_PP)))
1695                         ret = -EFAULT;
1696                 break;
1697         }
1698         default : {
1699                 ret = -EFAULT;
1700                 vpu_err("error: copy reg to user with unknown type %d\n", reg->type);
1701                 break;
1702         }
1703         }
1704         reg_deinit(data, reg);
1705         vpu_debug_leave();
1706         return ret;
1707 }
1708
1709 static long vpu_service_ioctl(struct file *filp, unsigned int cmd,
1710         unsigned long arg)
1711 {
1712         struct vpu_subdev_data *data =
1713                 container_of(filp->f_dentry->d_inode->i_cdev,
1714                         struct vpu_subdev_data, cdev);
1715         struct vpu_service_info *pservice = data->pservice;
1716         vpu_session *session = (vpu_session *)filp->private_data;
1717         vpu_debug_enter();
1718         if (NULL == session)
1719                 return -EINVAL;
1720
1721         switch (cmd) {
1722         case VPU_IOC_SET_CLIENT_TYPE : {
1723                 session->type = (enum VPU_CLIENT_TYPE)arg;
1724                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_CLIENT_TYPE %d\n", session->type);
1725                 break;
1726         }
1727         case VPU_IOC_GET_HW_FUSE_STATUS : {
1728                 struct vpu_request req;
1729                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1730                 if (copy_from_user(&req, (void __user *)arg, sizeof(struct vpu_request))) {
1731                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_from_user failed\n");
1732                         return -EFAULT;
1733                 } else {
1734                         if (VPU_ENC != session->type) {
1735                                 if (copy_to_user((void __user *)req.req,
1736                                         &pservice->dec_config,
1737                                         sizeof(struct vpu_dec_config))) {
1738                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1739                                                 session->type);
1740                                         return -EFAULT;
1741                                 }
1742                         } else {
1743                                 if (copy_to_user((void __user *)req.req,
1744                                         &pservice->enc_config,
1745                                         sizeof(struct vpu_enc_config ))) {
1746                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS copy_to_user failed type %d\n",
1747                                                 session->type);
1748                                         return -EFAULT;
1749                                 }
1750                         }
1751                 }
1752
1753                 break;
1754         }
1755         case VPU_IOC_SET_REG : {
1756                 struct vpu_request req;
1757                 vpu_reg *reg;
1758                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_SET_REG type %d\n", session->type);
1759                 if (copy_from_user(&req, (void __user *)arg,
1760                         sizeof(struct vpu_request))) {
1761                         vpu_err("error: VPU_IOC_SET_REG copy_from_user failed\n");
1762                         return -EFAULT;
1763                 }
1764                 reg = reg_init(data, session,
1765                         (void __user *)req.req, req.size);
1766                 if (NULL == reg) {
1767                         return -EFAULT;
1768                 } else {
1769                         mutex_lock(&pservice->lock);
1770                         try_set_reg(data);
1771                         mutex_unlock(&pservice->lock);
1772                 }
1773
1774                 break;
1775         }
1776         case VPU_IOC_GET_REG : {
1777                 struct vpu_request req;
1778                 vpu_reg *reg;
1779                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_GET_REG type %d\n", session->type);
1780                 if (copy_from_user(&req, (void __user *)arg,
1781                         sizeof(struct vpu_request))) {
1782                         vpu_err("error: VPU_IOC_GET_REG copy_from_user failed\n");
1783                         return -EFAULT;
1784                 } else {
1785                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1786                         if (!list_empty(&session->done)) {
1787                                 if (ret < 0) {
1788                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1789                                 }
1790                                 ret = 0;
1791                         } else {
1792                                 if (unlikely(ret < 0)) {
1793                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1794                                 } else if (0 == ret) {
1795                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1796                                         ret = -ETIMEDOUT;
1797                                 }
1798                         }
1799                         if (ret < 0) {
1800                                 int task_running = atomic_read(&session->task_running);
1801                                 mutex_lock(&pservice->lock);
1802                                 vpu_service_dump(pservice);
1803                                 if (task_running) {
1804                                         atomic_set(&session->task_running, 0);
1805                                         atomic_sub(task_running, &pservice->total_running);
1806                                         printk("%d task is running but not return, reset hardware...", task_running);
1807                                         vpu_reset(data);
1808                                         printk("done\n");
1809                                 }
1810                                 vpu_service_session_clear(data, session);
1811                                 mutex_unlock(&pservice->lock);
1812                                 return ret;
1813                         }
1814                 }
1815                 mutex_lock(&pservice->lock);
1816                 reg = list_entry(session->done.next, vpu_reg, session_link);
1817                 return_reg(data, reg, (u32 __user *)req.req);
1818                 mutex_unlock(&pservice->lock);
1819                 break;
1820         }
1821         case VPU_IOC_PROBE_IOMMU_STATUS: {
1822                 int iommu_enable = 0;
1823
1824                 vpu_debug(DEBUG_IOCTL, "VPU_IOC_PROBE_IOMMU_STATUS\n");
1825
1826 #if defined(CONFIG_VCODEC_MMU)
1827                 iommu_enable = data->mmu_dev ? 1 : 0;
1828 #endif
1829
1830                 if (copy_to_user((void __user *)arg, &iommu_enable, sizeof(int))) {
1831                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1832                         return -EFAULT;
1833                 }
1834                 break;
1835         }
1836         default : {
1837                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1838                 break;
1839         }
1840         }
1841         vpu_debug_leave();
1842         return 0;
1843 }
1844
1845 #ifdef CONFIG_COMPAT
1846 static long compat_vpu_service_ioctl(struct file *filp, unsigned int cmd,
1847         unsigned long arg)
1848 {
1849         struct vpu_subdev_data *data =
1850                 container_of(filp->f_dentry->d_inode->i_cdev,
1851                         struct vpu_subdev_data, cdev);
1852         struct vpu_service_info *pservice = data->pservice;
1853         vpu_session *session = (vpu_session *)filp->private_data;
1854         vpu_debug_enter();
1855         vpu_debug(3, "cmd %x, COMPAT_VPU_IOC_SET_CLIENT_TYPE %x\n", cmd,
1856                   (u32)COMPAT_VPU_IOC_SET_CLIENT_TYPE);
1857         if (NULL == session)
1858                 return -EINVAL;
1859
1860         switch (cmd) {
1861         case COMPAT_VPU_IOC_SET_CLIENT_TYPE : {
1862                 session->type = (enum VPU_CLIENT_TYPE)arg;
1863                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_CLIENT_TYPE type %d\n", session->type);
1864                 break;
1865         }
1866         case COMPAT_VPU_IOC_GET_HW_FUSE_STATUS : {
1867                 struct compat_vpu_request req;
1868                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_HW_FUSE_STATUS type %d\n", session->type);
1869                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1870                                    sizeof(struct compat_vpu_request))) {
1871                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1872                                 " copy_from_user failed\n");
1873                         return -EFAULT;
1874                 } else {
1875                         if (VPU_ENC != session->type) {
1876                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1877                                                  &pservice->dec_config,
1878                                                  sizeof(struct vpu_dec_config))) {
1879                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS "
1880                                                 "copy_to_user failed type %d\n",
1881                                                 session->type);
1882                                         return -EFAULT;
1883                                 }
1884                         } else {
1885                                 if (copy_to_user(compat_ptr((compat_uptr_t)req.req),
1886                                                  &pservice->enc_config,
1887                                                  sizeof(struct vpu_enc_config ))) {
1888                                         vpu_err("error: VPU_IOC_GET_HW_FUSE_STATUS"
1889                                                 " copy_to_user failed type %d\n",
1890                                                 session->type);
1891                                         return -EFAULT;
1892                                 }
1893                         }
1894                 }
1895
1896                 break;
1897         }
1898         case COMPAT_VPU_IOC_SET_REG : {
1899                 struct compat_vpu_request req;
1900                 vpu_reg *reg;
1901                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_SET_REG type %d\n", session->type);
1902                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1903                                    sizeof(struct compat_vpu_request))) {
1904                         vpu_err("VPU_IOC_SET_REG copy_from_user failed\n");
1905                         return -EFAULT;
1906                 }
1907                 reg = reg_init(data, session,
1908                                compat_ptr((compat_uptr_t)req.req), req.size);
1909                 if (NULL == reg) {
1910                         return -EFAULT;
1911                 } else {
1912                         mutex_lock(&pservice->lock);
1913                         try_set_reg(data);
1914                         mutex_unlock(&pservice->lock);
1915                 }
1916
1917                 break;
1918         }
1919         case COMPAT_VPU_IOC_GET_REG : {
1920                 struct compat_vpu_request req;
1921                 vpu_reg *reg;
1922                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_GET_REG type %d\n", session->type);
1923                 if (copy_from_user(&req, compat_ptr((compat_uptr_t)arg),
1924                                    sizeof(struct compat_vpu_request))) {
1925                         vpu_err("VPU_IOC_GET_REG copy_from_user failed\n");
1926                         return -EFAULT;
1927                 } else {
1928                         int ret = wait_event_timeout(session->wait, !list_empty(&session->done), VPU_TIMEOUT_DELAY);
1929                         if (!list_empty(&session->done)) {
1930                                 if (ret < 0) {
1931                                         vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session->pid, ret);
1932                                 }
1933                                 ret = 0;
1934                         } else {
1935                                 if (unlikely(ret < 0)) {
1936                                         vpu_err("error: pid %d wait task ret %d\n", session->pid, ret);
1937                                 } else if (0 == ret) {
1938                                         vpu_err("error: pid %d wait %d task done timeout\n", session->pid, atomic_read(&session->task_running));
1939                                         ret = -ETIMEDOUT;
1940                                 }
1941                         }
1942                         if (ret < 0) {
1943                                 int task_running = atomic_read(&session->task_running);
1944                                 mutex_lock(&pservice->lock);
1945                                 vpu_service_dump(pservice);
1946                                 if (task_running) {
1947                                         atomic_set(&session->task_running, 0);
1948                                         atomic_sub(task_running, &pservice->total_running);
1949                                         printk("%d task is running but not return, reset hardware...", task_running);
1950                                         vpu_reset(data);
1951                                         printk("done\n");
1952                                 }
1953                                 vpu_service_session_clear(data, session);
1954                                 mutex_unlock(&pservice->lock);
1955                                 return ret;
1956                         }
1957                 }
1958                 mutex_lock(&pservice->lock);
1959                 reg = list_entry(session->done.next, vpu_reg, session_link);
1960                 return_reg(data, reg, compat_ptr((compat_uptr_t)req.req));
1961                 mutex_unlock(&pservice->lock);
1962                 break;
1963         }
1964         case COMPAT_VPU_IOC_PROBE_IOMMU_STATUS : {
1965                 int iommu_enable = 0;
1966
1967                 vpu_debug(DEBUG_IOCTL, "COMPAT_VPU_IOC_PROBE_IOMMU_STATUS\n");
1968 #if defined(CONFIG_VCODEC_MMU)
1969                 iommu_enable = data->mmu_dev ? 1 : 0;
1970 #endif
1971
1972                 if (copy_to_user(compat_ptr((compat_uptr_t)arg), &iommu_enable, sizeof(int))) {
1973                         vpu_err("error: VPU_IOC_PROBE_IOMMU_STATUS copy_to_user failed\n");
1974                         return -EFAULT;
1975                 }
1976                 break;
1977         }
1978         default : {
1979                 vpu_err("error: unknow vpu service ioctl cmd %x\n", cmd);
1980                 break;
1981         }
1982         }
1983         vpu_debug_leave();
1984         return 0;
1985 }
1986 #endif
1987
1988 static int vpu_service_check_hw(struct vpu_subdev_data *data, u32 hw_addr)
1989 {
1990         int ret = -EINVAL, i = 0;
1991         volatile u32 *tmp = (volatile u32 *)ioremap_nocache(hw_addr, 0x4);
1992         u32 enc_id = *tmp;
1993
1994         enc_id = (enc_id >> 16) & 0xFFFF;
1995         pr_info("checking hw id %x\n", enc_id);
1996         data->hw_info = NULL;
1997         for (i = 0; i < ARRAY_SIZE(vpu_hw_set); i++) {
1998                 if (enc_id == vpu_hw_set[i].hw_id) {
1999                         data->hw_info = &vpu_hw_set[i];
2000                         ret = 0;
2001                         break;
2002                 }
2003         }
2004         iounmap((void *)tmp);
2005         return ret;
2006 }
2007
2008 static int vpu_service_open(struct inode *inode, struct file *filp)
2009 {
2010         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
2011         struct vpu_service_info *pservice = data->pservice;
2012         vpu_session *session = (vpu_session *)kmalloc(sizeof(vpu_session), GFP_KERNEL);
2013
2014         vpu_debug_enter();
2015
2016         if (NULL == session) {
2017                 vpu_err("error: unable to allocate memory for vpu_session.");
2018                 return -ENOMEM;
2019         }
2020
2021         session->type   = VPU_TYPE_BUTT;
2022         session->pid    = current->pid;
2023         INIT_LIST_HEAD(&session->waiting);
2024         INIT_LIST_HEAD(&session->running);
2025         INIT_LIST_HEAD(&session->done);
2026         INIT_LIST_HEAD(&session->list_session);
2027         init_waitqueue_head(&session->wait);
2028         atomic_set(&session->task_running, 0);
2029         mutex_lock(&pservice->lock);
2030         list_add_tail(&session->list_session, &pservice->session);
2031         filp->private_data = (void *)session;
2032         mutex_unlock(&pservice->lock);
2033
2034         pr_debug("dev opened\n");
2035         vpu_debug_leave();
2036         return nonseekable_open(inode, filp);
2037 }
2038
2039 static int vpu_service_release(struct inode *inode, struct file *filp)
2040 {
2041         struct vpu_subdev_data *data = container_of(inode->i_cdev, struct vpu_subdev_data, cdev);
2042         struct vpu_service_info *pservice = data->pservice;
2043         int task_running;
2044         vpu_session *session = (vpu_session *)filp->private_data;
2045         vpu_debug_enter();
2046         if (NULL == session)
2047                 return -EINVAL;
2048
2049         task_running = atomic_read(&session->task_running);
2050         if (task_running) {
2051                 vpu_err("error: vpu_service session %d still has %d task running when closing\n", session->pid, task_running);
2052                 msleep(50);
2053         }
2054         wake_up(&session->wait);
2055
2056         mutex_lock(&pservice->lock);
2057         /* remove this filp from the asynchronusly notified filp's */
2058         list_del_init(&session->list_session);
2059         vpu_service_session_clear(data, session);
2060         kfree(session);
2061         filp->private_data = NULL;
2062         mutex_unlock(&pservice->lock);
2063
2064         pr_debug("dev closed\n");
2065         vpu_debug_leave();
2066         return 0;
2067 }
2068
2069 static const struct file_operations vpu_service_fops = {
2070         .unlocked_ioctl = vpu_service_ioctl,
2071         .open           = vpu_service_open,
2072         .release        = vpu_service_release,
2073 #ifdef CONFIG_COMPAT
2074         .compat_ioctl   = compat_vpu_service_ioctl,
2075 #endif
2076 };
2077
2078 static irqreturn_t vdpu_irq(int irq, void *dev_id);
2079 static irqreturn_t vdpu_isr(int irq, void *dev_id);
2080 static irqreturn_t vepu_irq(int irq, void *dev_id);
2081 static irqreturn_t vepu_isr(int irq, void *dev_id);
2082 static void get_hw_info(struct vpu_subdev_data *data);
2083
2084 #ifdef CONFIG_VCODEC_MMU
2085 static struct device *rockchip_get_sysmmu_dev(const char *compt)
2086 {
2087         struct device_node *dn = NULL;
2088         struct platform_device *pd = NULL;
2089         struct device *ret = NULL ;
2090
2091         dn = of_find_compatible_node(NULL,NULL,compt);
2092         if(!dn) {
2093                 printk("can't find device node %s \r\n",compt);
2094                 return NULL;
2095         }
2096
2097         pd = of_find_device_by_node(dn);
2098         if(!pd) {
2099                 printk("can't find platform device in device node %s\n",compt);
2100                 return  NULL;
2101         }
2102         ret = &pd->dev;
2103
2104         return ret;
2105
2106 }
2107 #ifdef CONFIG_IOMMU_API
2108 static inline void platform_set_sysmmu(struct device *iommu,
2109         struct device *dev)
2110 {
2111         dev->archdata.iommu = iommu;
2112 }
2113 #else
2114 static inline void platform_set_sysmmu(struct device *iommu,
2115         struct device *dev)
2116 {
2117 }
2118 #endif
2119
2120 int vcodec_sysmmu_fault_hdl(struct device *dev,
2121                                 enum rk_iommu_inttype itype,
2122                                 unsigned long pgtable_base,
2123                                 unsigned long fault_addr, unsigned int status)
2124 {
2125         struct platform_device *pdev;
2126         struct vpu_subdev_data *data;
2127         struct vpu_service_info *pservice;
2128
2129         vpu_debug_enter();
2130
2131         pdev = container_of(dev, struct platform_device, dev);
2132
2133         data = platform_get_drvdata(pdev);
2134         pservice = data->pservice;
2135
2136         if (pservice->reg_codec) {
2137                 struct vcodec_mem_region *mem, *n;
2138                 int i = 0;
2139                 vpu_debug(DEBUG_IOMMU, "vcodec, fault addr 0x%08x\n", (u32)fault_addr);
2140                 list_for_each_entry_safe(mem, n,
2141                                          &pservice->reg_codec->mem_region_list,
2142                                          reg_lnk) {
2143                         vpu_debug(DEBUG_IOMMU, "vcodec, reg[%02u] mem region [%02d] 0x%08x %ld\n",
2144                                 mem->reg_idx, i, (u32)mem->iova, mem->len);
2145                         i++;
2146                 }
2147
2148                 pr_alert("vcodec, page fault occur, reset hw\n");
2149                 pservice->reg_codec->reg[101] = 1;
2150                 vpu_reset(data);
2151         }
2152
2153         return 0;
2154 }
2155 #endif
2156
2157 #if HEVC_TEST_ENABLE
2158 static int hevc_test_case0(vpu_service_info *pservice);
2159 #endif
2160 #if defined(CONFIG_ION_ROCKCHIP)
2161 extern struct ion_client *rockchip_ion_client_create(const char * name);
2162 #endif
2163
2164 static int vcodec_subdev_probe(struct platform_device *pdev,
2165         struct vpu_service_info *pservice)
2166 {
2167         int ret = 0;
2168         struct resource *res = NULL;
2169         u32 ioaddr = 0;
2170         struct device *dev = &pdev->dev;
2171         char *name = (char*)dev_name(dev);
2172         struct device_node *np = pdev->dev.of_node;
2173         struct vpu_subdev_data *data =
2174                 devm_kzalloc(dev, sizeof(struct vpu_subdev_data), GFP_KERNEL);
2175 #if defined(CONFIG_VCODEC_MMU)
2176         u32 iommu_en = 0;
2177         char mmu_dev_dts_name[40];
2178         of_property_read_u32(np, "iommu_enabled", &iommu_en);
2179 #endif
2180         pr_info("probe device %s\n", dev_name(dev));
2181
2182         data->pservice = pservice;
2183         data->dev = dev;
2184
2185         of_property_read_string(np, "name", (const char**)&name);
2186         of_property_read_u32(np, "dev_mode", (u32*)&data->mode);
2187         /*dev_set_name(dev, name);*/
2188
2189         if (pservice->reg_base == 0) {
2190                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2191                 data->regs = devm_ioremap_resource(dev, res);
2192                 if (IS_ERR(data->regs)) {
2193                         ret = PTR_ERR(data->regs);
2194                         goto err;
2195                 }
2196                 ioaddr = res->start;
2197         } else {
2198                 data->regs = pservice->reg_base;
2199                 ioaddr = pservice->ioaddr;
2200         }
2201
2202         clear_bit(MMU_ACTIVATED, &data->state);
2203         vcodec_enter_mode(data);
2204         ret = vpu_service_check_hw(data, ioaddr);
2205         if (ret < 0) {
2206                 vpu_err("error: hw info check faild\n");
2207                 goto err;
2208         }
2209
2210         data->dec_dev.iosize = data->hw_info->dec_io_size;
2211         data->dec_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->dec_offset);
2212         data->reg_size = data->dec_dev.iosize;
2213
2214         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2215                 data->enc_dev.iosize = data->hw_info->enc_io_size;
2216                 data->reg_size = data->reg_size > data->enc_dev.iosize ? data->reg_size : data->enc_dev.iosize;
2217                 data->enc_dev.hwregs = (volatile u32 *)((u8 *)data->regs + data->hw_info->enc_offset);
2218         }
2219
2220         data->irq_enc = platform_get_irq_byname(pdev, "irq_enc");
2221         if (data->irq_enc > 0) {
2222                 ret = devm_request_threaded_irq(dev,
2223                         data->irq_enc, vepu_irq, vepu_isr,
2224                         IRQF_SHARED, dev_name(dev),
2225                         (void *)data);
2226                 if (ret) {
2227                         dev_err(dev,
2228                                 "error: can't request vepu irq %d\n",
2229                                 data->irq_enc);
2230                         goto err;
2231                 }
2232         }
2233         data->irq_dec = platform_get_irq_byname(pdev, "irq_dec");
2234         if (data->irq_dec > 0) {
2235                 ret = devm_request_threaded_irq(dev,
2236                         data->irq_dec, vdpu_irq, vdpu_isr,
2237                         IRQF_SHARED, dev_name(dev),
2238                         (void *)data);
2239                 if (ret) {
2240                         dev_err(dev,
2241                                 "error: can't request vdpu irq %d\n",
2242                                 data->irq_dec);
2243                         goto err;
2244                 }
2245         }
2246         atomic_set(&data->dec_dev.irq_count_codec, 0);
2247         atomic_set(&data->dec_dev.irq_count_pp, 0);
2248         atomic_set(&data->enc_dev.irq_count_codec, 0);
2249         atomic_set(&data->enc_dev.irq_count_pp, 0);
2250 #if defined(CONFIG_VCODEC_MMU)
2251         if (iommu_en) {
2252                 if (data->mode == VCODEC_RUNNING_MODE_HEVC)
2253                         sprintf(mmu_dev_dts_name,
2254                                 HEVC_IOMMU_COMPATIBLE_NAME);
2255                 else
2256                         sprintf(mmu_dev_dts_name,
2257                                 VPU_IOMMU_COMPATIBLE_NAME);
2258
2259                 data->mmu_dev =
2260                         rockchip_get_sysmmu_dev(mmu_dev_dts_name);
2261
2262                 if (data->mmu_dev)
2263                         platform_set_sysmmu(data->mmu_dev, dev);
2264
2265                 rockchip_iovmm_set_fault_handler(dev, vcodec_sysmmu_fault_hdl);
2266         }
2267 #endif
2268         get_hw_info(data);
2269         pservice->auto_freq = true;
2270
2271         vcodec_exit_mode(data);
2272         /* create device node */
2273         ret = alloc_chrdev_region(&data->dev_t, 0, 1, name);
2274         if (ret) {
2275                 dev_err(dev, "alloc dev_t failed\n");
2276                 goto err;
2277         }
2278
2279         cdev_init(&data->cdev, &vpu_service_fops);
2280
2281         data->cdev.owner = THIS_MODULE;
2282         data->cdev.ops = &vpu_service_fops;
2283
2284         ret = cdev_add(&data->cdev, data->dev_t, 1);
2285
2286         if (ret) {
2287                 dev_err(dev, "add dev_t failed\n");
2288                 goto err;
2289         }
2290
2291         data->cls = class_create(THIS_MODULE, name);
2292
2293         if (IS_ERR(data->cls)) {
2294                 ret = PTR_ERR(data->cls);
2295                 dev_err(dev, "class_create err:%d\n", ret);
2296                 goto err;
2297         }
2298
2299         data->child_dev = device_create(data->cls, dev,
2300                 data->dev_t, NULL, name);
2301
2302         platform_set_drvdata(pdev, data);
2303
2304         INIT_LIST_HEAD(&data->lnk_service);
2305         list_add_tail(&data->lnk_service, &pservice->subdev_list);
2306
2307 #ifdef CONFIG_DEBUG_FS
2308         data->debugfs_dir =
2309                 vcodec_debugfs_create_device_dir((char*)name, parent);
2310         if (data->debugfs_dir == NULL)
2311                 vpu_err("create debugfs dir %s failed\n", name);
2312
2313         data->debugfs_file_regs =
2314                 debugfs_create_file("regs", 0664,
2315                                     data->debugfs_dir, data,
2316                                     &debug_vcodec_fops);
2317 #endif
2318         return 0;
2319 err:
2320         if (data->irq_enc > 0)
2321                 free_irq(data->irq_enc, (void *)data);
2322         if (data->irq_dec > 0)
2323                 free_irq(data->irq_dec, (void *)data);
2324
2325         if (data->child_dev) {
2326                 device_destroy(data->cls, data->dev_t);
2327                 cdev_del(&data->cdev);
2328                 unregister_chrdev_region(data->dev_t, 1);
2329         }
2330
2331         if (data->cls)
2332                 class_destroy(data->cls);
2333         return -1;
2334 }
2335
2336 static void vcodec_subdev_remove(struct vpu_subdev_data *data)
2337 {
2338         device_destroy(data->cls, data->dev_t);
2339         class_destroy(data->cls);
2340         cdev_del(&data->cdev);
2341         unregister_chrdev_region(data->dev_t, 1);
2342
2343         free_irq(data->irq_enc, (void *)&data);
2344         free_irq(data->irq_dec, (void *)&data);
2345
2346 #ifdef CONFIG_DEBUG_FS
2347         debugfs_remove_recursive(data->debugfs_dir);
2348 #endif
2349 }
2350
2351 static void vcodec_read_property(struct device_node *np,
2352         struct vpu_service_info *pservice)
2353 {
2354         pservice->mode_bit = 0;
2355         pservice->mode_ctrl = 0;
2356         pservice->subcnt = 0;
2357         pservice->grf_base = NULL;
2358
2359         of_property_read_u32(np, "subcnt", &pservice->subcnt);
2360
2361         if (pservice->subcnt > 1) {
2362                 of_property_read_u32(np, "mode_bit", &pservice->mode_bit);
2363                 of_property_read_u32(np, "mode_ctrl", &pservice->mode_ctrl);
2364         }
2365 #ifdef CONFIG_MFD_SYSCON
2366         pservice->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
2367         if (IS_ERR_OR_NULL(pservice->grf)) {
2368                 pservice->grf = NULL;
2369 #ifdef CONFIG_ARM
2370                 pservice->grf_base = RK_GRF_VIRT;
2371 #else
2372                 vpu_err("can't find vpu grf property\n");
2373                 return;
2374 #endif
2375         }
2376 #else
2377 #ifdef CONFIG_ARM
2378         pservice->grf_base = RK_GRF_VIRT;
2379 #else
2380         vpu_err("can't find vpu grf property\n");
2381         return;
2382 #endif
2383 #endif
2384
2385 #ifdef CONFIG_RESET_CONTROLLER
2386         pservice->rst_a = devm_reset_control_get(pservice->dev, "video_a");
2387         pservice->rst_h = devm_reset_control_get(pservice->dev, "video_h");
2388         pservice->rst_v = devm_reset_control_get(pservice->dev, "video");
2389
2390         if (IS_ERR_OR_NULL(pservice->rst_a)) {
2391                 pr_warn("No reset resource define\n");
2392                 pservice->rst_a = NULL;
2393         }
2394
2395         if (IS_ERR_OR_NULL(pservice->rst_h)) {
2396                 pr_warn("No reset resource define\n");
2397                 pservice->rst_h = NULL;
2398         }
2399
2400         if (IS_ERR_OR_NULL(pservice->rst_v)) {
2401                 pr_warn("No reset resource define\n");
2402                 pservice->rst_v = NULL;
2403         }
2404 #endif
2405
2406         of_property_read_string(np, "name", (const char**)&pservice->name);
2407 }
2408
2409 static void vcodec_init_drvdata(struct vpu_service_info *pservice)
2410 {
2411         pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2412         pservice->curr_mode = -1;
2413
2414         wake_lock_init(&pservice->wake_lock, WAKE_LOCK_SUSPEND, "vpu");
2415         INIT_LIST_HEAD(&pservice->waiting);
2416         INIT_LIST_HEAD(&pservice->running);
2417         mutex_init(&pservice->lock);
2418
2419         INIT_LIST_HEAD(&pservice->done);
2420         INIT_LIST_HEAD(&pservice->session);
2421         INIT_LIST_HEAD(&pservice->subdev_list);
2422
2423         pservice->reg_pproc     = NULL;
2424         atomic_set(&pservice->total_running, 0);
2425         atomic_set(&pservice->enabled,       0);
2426         atomic_set(&pservice->power_on_cnt,  0);
2427         atomic_set(&pservice->power_off_cnt, 0);
2428         atomic_set(&pservice->reset_request, 0);
2429
2430         INIT_DELAYED_WORK(&pservice->power_off_work, vpu_power_off_work);
2431
2432         pservice->ion_client = rockchip_ion_client_create("vpu");
2433         if (IS_ERR(pservice->ion_client)) {
2434                 vpu_err("failed to create ion client for vcodec ret %ld\n",
2435                         PTR_ERR(pservice->ion_client));
2436         } else {
2437                 vpu_debug(DEBUG_IOMMU, "vcodec ion client create success!\n");
2438         }
2439 }
2440
2441 static int vcodec_probe(struct platform_device *pdev)
2442 {
2443         int i;
2444         int ret = 0;
2445         struct resource *res = NULL;
2446         struct device *dev = &pdev->dev;
2447         struct device_node *np = pdev->dev.of_node;
2448         struct vpu_service_info *pservice =
2449                 devm_kzalloc(dev, sizeof(struct vpu_service_info), GFP_KERNEL);
2450
2451         pr_info("probe device %s\n", dev_name(dev));
2452
2453         pservice->dev = dev;
2454
2455         vcodec_read_property(np, pservice);
2456         vcodec_init_drvdata(pservice);
2457
2458         if (strncmp(pservice->name, "hevc_service", 12) == 0)
2459                 pservice->dev_id = VCODEC_DEVICE_ID_HEVC;
2460         else if (strncmp(pservice->name, "vpu_service", 11) == 0)
2461                 pservice->dev_id = VCODEC_DEVICE_ID_VPU;
2462         else
2463                 pservice->dev_id = VCODEC_DEVICE_ID_COMBO;
2464
2465         if (0 > vpu_get_clk(pservice))
2466                 goto err;
2467
2468         vpu_service_power_on(pservice);
2469
2470         if (of_property_read_bool(np, "reg")) {
2471                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2472
2473                 pservice->reg_base = devm_ioremap_resource(pservice->dev, res);
2474                 if (IS_ERR(pservice->reg_base)) {
2475                         vpu_err("ioremap registers base failed\n");
2476                         ret = PTR_ERR(pservice->reg_base);
2477                         goto err;
2478                 }
2479                 pservice->ioaddr = res->start;
2480         } else {
2481                 pservice->reg_base = 0;
2482         }
2483
2484         if (of_property_read_bool(np, "subcnt")) {
2485                 for (i = 0; i<pservice->subcnt; i++) {
2486                         struct device_node *sub_np;
2487                         struct platform_device *sub_pdev;
2488                         sub_np = of_parse_phandle(np, "rockchip,sub", i);
2489                         sub_pdev = of_find_device_by_node(sub_np);
2490
2491                         vcodec_subdev_probe(sub_pdev, pservice);
2492                 }
2493         } else {
2494                 vcodec_subdev_probe(pdev, pservice);
2495         }
2496         platform_set_drvdata(pdev, pservice);
2497
2498         vpu_service_power_off(pservice);
2499
2500         pr_info("init success\n");
2501
2502         return 0;
2503
2504 err:
2505         pr_info("init failed\n");
2506         vpu_service_power_off(pservice);
2507         vpu_put_clk(pservice);
2508         wake_lock_destroy(&pservice->wake_lock);
2509
2510         if (res)
2511                 devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2512
2513         return ret;
2514 }
2515
2516 static int vcodec_remove(struct platform_device *pdev)
2517 {
2518         struct vpu_service_info *pservice = platform_get_drvdata(pdev);
2519         struct resource *res;
2520         struct vpu_subdev_data *data, *n;
2521
2522         list_for_each_entry_safe(data, n, &pservice->subdev_list, lnk_service) {
2523                 vcodec_subdev_remove(data);
2524         }
2525
2526         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2527         devm_release_mem_region(&pdev->dev, res->start, resource_size(res));
2528         vpu_put_clk(pservice);
2529         wake_lock_destroy(&pservice->wake_lock);
2530
2531         return 0;
2532 }
2533
2534 #if defined(CONFIG_OF)
2535 static const struct of_device_id vcodec_service_dt_ids[] = {
2536         {.compatible = "vpu_service",},
2537         {.compatible = "rockchip,hevc_service",},
2538         {.compatible = "rockchip,vpu_combo",},
2539         {},
2540 };
2541 #endif
2542
2543 static struct platform_driver vcodec_driver = {
2544         .probe = vcodec_probe,
2545         .remove = vcodec_remove,
2546         .driver = {
2547                 .name = "vcodec",
2548                 .owner = THIS_MODULE,
2549 #if defined(CONFIG_OF)
2550                 .of_match_table = of_match_ptr(vcodec_service_dt_ids),
2551 #endif
2552         },
2553 };
2554
2555 static void get_hw_info(struct vpu_subdev_data *data)
2556 {
2557         struct vpu_service_info *pservice = data->pservice;
2558         struct vpu_dec_config *dec = &pservice->dec_config;
2559         struct vpu_enc_config *enc = &pservice->enc_config;
2560         if (data->mode == VCODEC_RUNNING_MODE_VPU) {
2561                 u32 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG0];
2562                 u32 asicID      = data->dec_dev.hwregs[0];
2563
2564                 dec->h264_support    = (configReg >> DWL_H264_E) & 0x3U;
2565                 dec->jpegSupport    = (configReg >> DWL_JPEG_E) & 0x01U;
2566                 if (dec->jpegSupport && ((configReg >> DWL_PJPEG_E) & 0x01U))
2567                         dec->jpegSupport = JPEG_PROGRESSIVE;
2568                 dec->mpeg4Support   = (configReg >> DWL_MPEG4_E) & 0x3U;
2569                 dec->vc1Support     = (configReg >> DWL_VC1_E) & 0x3U;
2570                 dec->mpeg2Support   = (configReg >> DWL_MPEG2_E) & 0x01U;
2571                 dec->sorensonSparkSupport = (configReg >> DWL_SORENSONSPARK_E) & 0x01U;
2572                 dec->refBufSupport  = (configReg >> DWL_REF_BUFF_E) & 0x01U;
2573                 dec->vp6Support     = (configReg >> DWL_VP6_E) & 0x01U;
2574
2575                 dec->maxDecPicWidth = 4096;
2576
2577                 /* 2nd Config register */
2578                 configReg   = data->dec_dev.hwregs[VPU_DEC_HWCFG1];
2579                 if (dec->refBufSupport) {
2580                         if ((configReg >> DWL_REF_BUFF_ILACE_E) & 0x01U)
2581                                 dec->refBufSupport |= 2;
2582                         if ((configReg >> DWL_REF_BUFF_DOUBLE_E) & 0x01U)
2583                                 dec->refBufSupport |= 4;
2584                 }
2585                 dec->customMpeg4Support = (configReg >> DWL_MPEG4_CUSTOM_E) & 0x01U;
2586                 dec->vp7Support     = (configReg >> DWL_VP7_E) & 0x01U;
2587                 dec->vp8Support     = (configReg >> DWL_VP8_E) & 0x01U;
2588                 dec->avsSupport     = (configReg >> DWL_AVS_E) & 0x01U;
2589
2590                 /* JPEG xtensions */
2591                 if (((asicID >> 16) >= 0x8190U) || ((asicID >> 16) == 0x6731U))
2592                         dec->jpegESupport = (configReg >> DWL_JPEG_EXT_E) & 0x01U;
2593                 else
2594                         dec->jpegESupport = JPEG_EXT_NOT_SUPPORTED;
2595
2596                 if (((asicID >> 16) >= 0x9170U) || ((asicID >> 16) == 0x6731U) )
2597                         dec->rvSupport = (configReg >> DWL_RV_E) & 0x03U;
2598                 else
2599                         dec->rvSupport = RV_NOT_SUPPORTED;
2600                 dec->mvcSupport = (configReg >> DWL_MVC_E) & 0x03U;
2601
2602                 if (dec->refBufSupport && (asicID >> 16) == 0x6731U )
2603                         dec->refBufSupport |= 8; /* enable HW support for offset */
2604
2605                 if (!cpu_is_rk3036()) {
2606                         configReg = data->enc_dev.hwregs[63];
2607                         enc->maxEncodedWidth = configReg & ((1 << 11) - 1);
2608                         enc->h264Enabled = (configReg >> 27) & 1;
2609                         enc->mpeg4Enabled = (configReg >> 26) & 1;
2610                         enc->jpegEnabled = (configReg >> 25) & 1;
2611                         enc->vsEnabled = (configReg >> 24) & 1;
2612                         enc->rgbEnabled = (configReg >> 28) & 1;
2613                         enc->reg_size = data->reg_size;
2614                         enc->reserv[0] = enc->reserv[1] = 0;
2615                 }
2616                 pservice->auto_freq = true;
2617                 vpu_debug(DEBUG_EXTRA_INFO, "vpu_service set to auto frequency mode\n");
2618                 atomic_set(&pservice->freq_status, VPU_FREQ_BUT);
2619
2620                 pservice->bug_dec_addr = cpu_is_rk30xx();
2621         } else {
2622                 if (cpu_is_rk3036()  || cpu_is_rk312x())
2623                         dec->maxDecPicWidth = 1920;
2624                 else
2625                         dec->maxDecPicWidth = 4096;
2626                 /* disable frequency switch in hevc.*/
2627                 pservice->auto_freq = false;
2628         }
2629 }
2630
2631 static bool check_irq_err(task_info *task, u32 irq_status)
2632 {
2633         return (task->error_mask & irq_status) ? true : false;
2634 }
2635
2636 static irqreturn_t vdpu_irq(int irq, void *dev_id)
2637 {
2638         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2639         struct vpu_service_info *pservice = data->pservice;
2640         vpu_device *dev = &data->dec_dev;
2641         u32 raw_status;
2642         u32 dec_status;
2643
2644         /*vcodec_enter_mode(data);*/
2645
2646         dec_status = raw_status = readl(dev->hwregs + DEC_INTERRUPT_REGISTER);
2647
2648         if (dec_status & DEC_INTERRUPT_BIT) {
2649                 time_record(&tasks[TASK_VPU_DEC], 1);
2650                 vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq dec status %08x\n", dec_status);
2651                 if ((dec_status & 0x40001) == 0x40001) {
2652                         do {
2653                                 dec_status =
2654                                         readl(dev->hwregs +
2655                                                 DEC_INTERRUPT_REGISTER);
2656                         } while ((dec_status & 0x40001) == 0x40001);
2657                 }
2658
2659                 if (check_irq_err((data->hw_info->hw_id == HEVC_ID)?
2660                                         (&tasks[TASK_RKDEC_HEVC]) : (&tasks[TASK_VPU_DEC]),
2661                                         dec_status)) {
2662                         atomic_add(1, &pservice->reset_request);
2663                 }
2664
2665                 writel(0, dev->hwregs + DEC_INTERRUPT_REGISTER);
2666                 atomic_add(1, &dev->irq_count_codec);
2667                 time_diff(&tasks[TASK_VPU_DEC]);
2668         }
2669
2670         if (data->hw_info->hw_id != HEVC_ID) {
2671                 u32 pp_status = readl(dev->hwregs + PP_INTERRUPT_REGISTER);
2672                 if (pp_status & PP_INTERRUPT_BIT) {
2673                         time_record(&tasks[TASK_VPU_PP], 1);
2674                         vpu_debug(DEBUG_IRQ_STATUS, "vdpu_irq pp status %08x\n", pp_status);
2675
2676                         if (check_irq_err(&tasks[TASK_VPU_PP], dec_status))
2677                                 atomic_add(1, &pservice->reset_request);
2678
2679                         /* clear pp IRQ */
2680                         writel(pp_status & (~DEC_INTERRUPT_BIT), dev->hwregs + PP_INTERRUPT_REGISTER);
2681                         atomic_add(1, &dev->irq_count_pp);
2682                         time_diff(&tasks[TASK_VPU_PP]);
2683                 }
2684         }
2685
2686         pservice->irq_status = raw_status;
2687
2688         /*vcodec_exit_mode(pservice);*/
2689
2690         if (atomic_read(&dev->irq_count_pp) ||
2691             atomic_read(&dev->irq_count_codec))
2692                 return IRQ_WAKE_THREAD;
2693         else
2694                 return IRQ_NONE;
2695 }
2696
2697 static irqreturn_t vdpu_isr(int irq, void *dev_id)
2698 {
2699         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2700         struct vpu_service_info *pservice = data->pservice;
2701         vpu_device *dev = &data->dec_dev;
2702
2703         mutex_lock(&pservice->lock);
2704         if (atomic_read(&dev->irq_count_codec)) {
2705                 atomic_sub(1, &dev->irq_count_codec);
2706                 if (NULL == pservice->reg_codec) {
2707                         vpu_err("error: dec isr with no task waiting\n");
2708                 } else {
2709                         reg_from_run_to_done(data, pservice->reg_codec);
2710                         /* avoid vpu timeout and can't recover problem */
2711                         VDPU_SOFT_RESET(data->regs);
2712                 }
2713         }
2714
2715         if (atomic_read(&dev->irq_count_pp)) {
2716                 atomic_sub(1, &dev->irq_count_pp);
2717                 if (NULL == pservice->reg_pproc) {
2718                         vpu_err("error: pp isr with no task waiting\n");
2719                 } else {
2720                         reg_from_run_to_done(data, pservice->reg_pproc);
2721                 }
2722         }
2723         try_set_reg(data);
2724         mutex_unlock(&pservice->lock);
2725         return IRQ_HANDLED;
2726 }
2727
2728 static irqreturn_t vepu_irq(int irq, void *dev_id)
2729 {
2730         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2731         struct vpu_service_info *pservice = data->pservice;
2732         vpu_device *dev = &data->enc_dev;
2733         u32 irq_status;
2734
2735         /*vcodec_enter_mode(data);*/
2736         irq_status= readl(dev->hwregs + ENC_INTERRUPT_REGISTER);
2737
2738         vpu_debug(DEBUG_IRQ_STATUS, "vepu_irq irq status %x\n", irq_status);
2739
2740         if (likely(irq_status & ENC_INTERRUPT_BIT)) {
2741                 time_record(&tasks[TASK_VPU_ENC], 1);
2742
2743                 if (check_irq_err(&tasks[TASK_VPU_ENC], irq_status))
2744                         atomic_add(1, &pservice->reset_request);
2745
2746                 /* clear enc IRQ */
2747                 writel(irq_status & (~ENC_INTERRUPT_BIT), dev->hwregs + ENC_INTERRUPT_REGISTER);
2748                 atomic_add(1, &dev->irq_count_codec);
2749                 time_diff(&tasks[TASK_VPU_ENC]);
2750         }
2751
2752         pservice->irq_status = irq_status;
2753
2754         /*vcodec_exit_mode(pservice);*/
2755
2756         if (atomic_read(&dev->irq_count_codec))
2757                 return IRQ_WAKE_THREAD;
2758         else
2759                 return IRQ_NONE;
2760 }
2761
2762 static irqreturn_t vepu_isr(int irq, void *dev_id)
2763 {
2764         struct vpu_subdev_data *data = (struct vpu_subdev_data*)dev_id;
2765         struct vpu_service_info *pservice = data->pservice;
2766         vpu_device *dev = &data->enc_dev;
2767
2768         mutex_lock(&pservice->lock);
2769         if (atomic_read(&dev->irq_count_codec)) {
2770                 atomic_sub(1, &dev->irq_count_codec);
2771                 if (NULL == pservice->reg_codec) {
2772                         vpu_err("error: enc isr with no task waiting\n");
2773                 } else {
2774                         reg_from_run_to_done(data, pservice->reg_codec);
2775                 }
2776         }
2777         try_set_reg(data);
2778         mutex_unlock(&pservice->lock);
2779         return IRQ_HANDLED;
2780 }
2781
2782 static int __init vcodec_service_init(void)
2783 {
2784         int ret;
2785
2786         if ((ret = platform_driver_register(&vcodec_driver)) != 0) {
2787                 vpu_err("Platform device register failed (%d).\n", ret);
2788                 return ret;
2789         }
2790
2791 #ifdef CONFIG_DEBUG_FS
2792         vcodec_debugfs_init();
2793 #endif
2794
2795         return ret;
2796 }
2797
2798 static void __exit vcodec_service_exit(void)
2799 {
2800 #ifdef CONFIG_DEBUG_FS
2801         vcodec_debugfs_exit();
2802 #endif
2803
2804         platform_driver_unregister(&vcodec_driver);
2805 }
2806
2807 module_init(vcodec_service_init);
2808 module_exit(vcodec_service_exit);
2809
2810 #ifdef CONFIG_DEBUG_FS
2811 #include <linux/seq_file.h>
2812
2813 static int vcodec_debugfs_init()
2814 {
2815         parent = debugfs_create_dir("vcodec", NULL);
2816         if (!parent)
2817                 return -1;
2818
2819         return 0;
2820 }
2821
2822 static void vcodec_debugfs_exit()
2823 {
2824         debugfs_remove(parent);
2825 }
2826
2827 static struct dentry* vcodec_debugfs_create_device_dir(char *dirname, struct dentry *parent)
2828 {
2829         return debugfs_create_dir(dirname, parent);
2830 }
2831
2832 static int debug_vcodec_show(struct seq_file *s, void *unused)
2833 {
2834         struct vpu_subdev_data *data = s->private;
2835         struct vpu_service_info *pservice = data->pservice;
2836         unsigned int i, n;
2837         vpu_reg *reg, *reg_tmp;
2838         vpu_session *session, *session_tmp;
2839
2840         mutex_lock(&pservice->lock);
2841         vpu_service_power_on(pservice);
2842         if (data->hw_info->hw_id != HEVC_ID) {
2843                 seq_printf(s, "\nENC Registers:\n");
2844                 n = data->enc_dev.iosize >> 2;
2845                 for (i = 0; i < n; i++)
2846                         seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->enc_dev.hwregs + i));
2847         }
2848         seq_printf(s, "\nDEC Registers:\n");
2849         n = data->dec_dev.iosize >> 2;
2850         for (i = 0; i < n; i++)
2851                 seq_printf(s, "\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
2852
2853         seq_printf(s, "\nvpu service status:\n");
2854         list_for_each_entry_safe(session, session_tmp, &pservice->session, list_session) {
2855                 seq_printf(s, "session pid %d type %d:\n", session->pid, session->type);
2856                 /*seq_printf(s, "waiting reg set %d\n");*/
2857                 list_for_each_entry_safe(reg, reg_tmp, &session->waiting, session_link) {
2858                         seq_printf(s, "waiting register set\n");
2859                 }
2860                 list_for_each_entry_safe(reg, reg_tmp, &session->running, session_link) {
2861                         seq_printf(s, "running register set\n");
2862                 }
2863                 list_for_each_entry_safe(reg, reg_tmp, &session->done, session_link) {
2864                         seq_printf(s, "done    register set\n");
2865                 }
2866         }
2867
2868         seq_printf(s, "\npower counter: on %d off %d\n",
2869                         atomic_read(&pservice->power_on_cnt),
2870                         atomic_read(&pservice->power_off_cnt));
2871         mutex_unlock(&pservice->lock);
2872         vpu_service_power_off(pservice);
2873
2874         return 0;
2875 }
2876
2877 static int debug_vcodec_open(struct inode *inode, struct file *file)
2878 {
2879         return single_open(file, debug_vcodec_show, inode->i_private);
2880 }
2881
2882 #endif
2883
2884 #if HEVC_TEST_ENABLE & defined(CONFIG_ION_ROCKCHIP)
2885 #include "hevc_test_inc/pps_00.h"
2886 #include "hevc_test_inc/register_00.h"
2887 #include "hevc_test_inc/rps_00.h"
2888 #include "hevc_test_inc/scaling_list_00.h"
2889 #include "hevc_test_inc/stream_00.h"
2890
2891 #include "hevc_test_inc/pps_01.h"
2892 #include "hevc_test_inc/register_01.h"
2893 #include "hevc_test_inc/rps_01.h"
2894 #include "hevc_test_inc/scaling_list_01.h"
2895 #include "hevc_test_inc/stream_01.h"
2896
2897 #include "hevc_test_inc/cabac.h"
2898
2899 extern struct ion_client *rockchip_ion_client_create(const char * name);
2900
2901 static struct ion_client *ion_client = NULL;
2902 u8* get_align_ptr(u8* tbl, int len, u32 *phy)
2903 {
2904         int size = (len+15) & (~15);
2905         struct ion_handle *handle;
2906         u8 *ptr;
2907
2908         if (ion_client == NULL)
2909                 ion_client = rockchip_ion_client_create("vcodec");
2910
2911         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2912
2913         ptr = ion_map_kernel(ion_client, handle);
2914
2915         ion_phys(ion_client, handle, phy, &size);
2916
2917         memcpy(ptr, tbl, len);
2918
2919         return ptr;
2920 }
2921
2922 u8* get_align_ptr_no_copy(int len, u32 *phy)
2923 {
2924         int size = (len+15) & (~15);
2925         struct ion_handle *handle;
2926         u8 *ptr;
2927
2928         if (ion_client == NULL)
2929                 ion_client = rockchip_ion_client_create("vcodec");
2930
2931         handle = ion_alloc(ion_client, (size_t)len, 16, ION_HEAP(ION_CMA_HEAP_ID), 0);
2932
2933         ptr = ion_map_kernel(ion_client, handle);
2934
2935         ion_phys(ion_client, handle, phy, &size);
2936
2937         return ptr;
2938 }
2939
2940 #define TEST_CNT    2
2941 static int hevc_test_case0(vpu_service_info *pservice)
2942 {
2943         vpu_session session;
2944         vpu_reg *reg;
2945         unsigned long size = 272;
2946         int testidx = 0;
2947         int ret = 0;
2948         u8 *pps_tbl[TEST_CNT];
2949         u8 *register_tbl[TEST_CNT];
2950         u8 *rps_tbl[TEST_CNT];
2951         u8 *scaling_list_tbl[TEST_CNT];
2952         u8 *stream_tbl[TEST_CNT];
2953
2954         int stream_size[2];
2955         int pps_size[2];
2956         int rps_size[2];
2957         int scl_size[2];
2958         int cabac_size[2];
2959
2960         u32 phy_pps;
2961         u32 phy_rps;
2962         u32 phy_scl;
2963         u32 phy_str;
2964         u32 phy_yuv;
2965         u32 phy_ref;
2966         u32 phy_cabac;
2967
2968         volatile u8 *stream_buf;
2969         volatile u8 *pps_buf;
2970         volatile u8 *rps_buf;
2971         volatile u8 *scl_buf;
2972         volatile u8 *yuv_buf;
2973         volatile u8 *cabac_buf;
2974         volatile u8 *ref_buf;
2975
2976         u8 *pps;
2977         u8 *yuv[2];
2978         int i;
2979
2980         pps_tbl[0] = pps_00;
2981         pps_tbl[1] = pps_01;
2982
2983         register_tbl[0] = register_00;
2984         register_tbl[1] = register_01;
2985
2986         rps_tbl[0] = rps_00;
2987         rps_tbl[1] = rps_01;
2988
2989         scaling_list_tbl[0] = scaling_list_00;
2990         scaling_list_tbl[1] = scaling_list_01;
2991
2992         stream_tbl[0] = stream_00;
2993         stream_tbl[1] = stream_01;
2994
2995         stream_size[0] = sizeof(stream_00);
2996         stream_size[1] = sizeof(stream_01);
2997
2998         pps_size[0] = sizeof(pps_00);
2999         pps_size[1] = sizeof(pps_01);
3000
3001         rps_size[0] = sizeof(rps_00);
3002         rps_size[1] = sizeof(rps_01);
3003
3004         scl_size[0] = sizeof(scaling_list_00);
3005         scl_size[1] = sizeof(scaling_list_01);
3006
3007         cabac_size[0] = sizeof(Cabac_table);
3008         cabac_size[1] = sizeof(Cabac_table);
3009
3010         /* create session */
3011         session.pid = current->pid;
3012         session.type = VPU_DEC;
3013         INIT_LIST_HEAD(&session.waiting);
3014         INIT_LIST_HEAD(&session.running);
3015         INIT_LIST_HEAD(&session.done);
3016         INIT_LIST_HEAD(&session.list_session);
3017         init_waitqueue_head(&session.wait);
3018         atomic_set(&session.task_running, 0);
3019         list_add_tail(&session.list_session, &pservice->session);
3020
3021         yuv[0] = get_align_ptr_no_copy(256*256*2, &phy_yuv);
3022         yuv[1] = get_align_ptr_no_copy(256*256*2, &phy_ref);
3023
3024         while (testidx < TEST_CNT) {
3025                 /* create registers */
3026                 reg = kmalloc(sizeof(vpu_reg)+pservice->reg_size, GFP_KERNEL);
3027                 if (NULL == reg) {
3028                         vpu_err("error: kmalloc fail in reg_init\n");
3029                         return -1;
3030                 }
3031
3032                 if (size > pservice->reg_size) {
3033                         printk("warning: vpu reg size %lu is larger than hw reg size %lu\n", size, pservice->reg_size);
3034                         size = pservice->reg_size;
3035                 }
3036                 reg->session = &session;
3037                 reg->type = session.type;
3038                 reg->size = size;
3039                 reg->freq = VPU_FREQ_DEFAULT;
3040                 reg->reg = (unsigned long *)&reg[1];
3041                 INIT_LIST_HEAD(&reg->session_link);
3042                 INIT_LIST_HEAD(&reg->status_link);
3043
3044                 /* TODO: stuff registers */
3045                 memcpy(&reg->reg[0], register_tbl[testidx], /*sizeof(register_00)*/ 176);
3046
3047                 stream_buf = get_align_ptr(stream_tbl[testidx], stream_size[testidx], &phy_str);
3048                 pps_buf = get_align_ptr(pps_tbl[0], pps_size[0], &phy_pps);
3049                 rps_buf = get_align_ptr(rps_tbl[testidx], rps_size[testidx], &phy_rps);
3050                 scl_buf = get_align_ptr(scaling_list_tbl[testidx], scl_size[testidx], &phy_scl);
3051                 cabac_buf = get_align_ptr(Cabac_table, cabac_size[testidx], &phy_cabac);
3052
3053                 pps = pps_buf;
3054
3055                 /* TODO: replace reigster address */
3056                 for (i=0; i<64; i++) {
3057                         u32 scaling_offset;
3058                         u32 tmp;
3059
3060                         scaling_offset = (u32)pps[i*80+74];
3061                         scaling_offset += (u32)pps[i*80+75] << 8;
3062                         scaling_offset += (u32)pps[i*80+76] << 16;
3063                         scaling_offset += (u32)pps[i*80+77] << 24;
3064
3065                         tmp = phy_scl + scaling_offset;
3066
3067                         pps[i*80+74] = tmp & 0xff;
3068                         pps[i*80+75] = (tmp >> 8) & 0xff;
3069                         pps[i*80+76] = (tmp >> 16) & 0xff;
3070                         pps[i*80+77] = (tmp >> 24) & 0xff;
3071                 }
3072
3073                 printk("%s %d, phy stream %08x, phy pps %08x, phy rps %08x\n",
3074                         __func__, __LINE__, phy_str, phy_pps, phy_rps);
3075
3076                 reg->reg[1] = 0x21;
3077                 reg->reg[4] = phy_str;
3078                 reg->reg[5] = ((stream_size[testidx]+15)&(~15))+64;
3079                 reg->reg[6] = phy_cabac;
3080                 reg->reg[7] = testidx?phy_ref:phy_yuv;
3081                 reg->reg[42] = phy_pps;
3082                 reg->reg[43] = phy_rps;
3083                 for (i = 10; i <= 24; i++)
3084                         reg->reg[i] = phy_yuv;
3085
3086                 mutex_lock(pservice->lock);
3087                 list_add_tail(&reg->status_link, &pservice->waiting);
3088                 list_add_tail(&reg->session_link, &session.waiting);
3089                 mutex_unlock(pservice->lock);
3090
3091                 /* stuff hardware */
3092                 try_set_reg(data);
3093
3094                 /* wait for result */
3095                 ret = wait_event_timeout(session.wait, !list_empty(&session.done), VPU_TIMEOUT_DELAY);
3096                 if (!list_empty(&session.done)) {
3097                         if (ret < 0)
3098                                 vpu_err("warning: pid %d wait task sucess but wait_evernt ret %d\n", session.pid, ret);
3099                         ret = 0;
3100                 } else {
3101                         if (unlikely(ret < 0)) {
3102                                 vpu_err("error: pid %d wait task ret %d\n", session.pid, ret);
3103                         } else if (0 == ret) {
3104                                 vpu_err("error: pid %d wait %d task done timeout\n", session.pid, atomic_read(&session.task_running));
3105                                 ret = -ETIMEDOUT;
3106                         }
3107                 }
3108                 if (ret < 0) {
3109                         int task_running = atomic_read(&session.task_running);
3110                         int n;
3111                         mutex_lock(pservice->lock);
3112                         vpu_service_dump(pservice);
3113                         if (task_running) {
3114                                 atomic_set(&session.task_running, 0);
3115                                 atomic_sub(task_running, &pservice->total_running);
3116                                 printk("%d task is running but not return, reset hardware...", task_running);
3117                                 vpu_reset(data);
3118                                 printk("done\n");
3119                         }
3120                         vpu_service_session_clear(pservice, &session);
3121                         mutex_unlock(pservice->lock);
3122
3123                         printk("\nDEC Registers:\n");
3124                         n = data->dec_dev.iosize >> 2;
3125                         for (i=0; i<n; i++)
3126                                 printk("\tswreg%d = %08X\n", i, readl(data->dec_dev.hwregs + i));
3127
3128                         vpu_err("test index %d failed\n", testidx);
3129                         break;
3130                 } else {
3131                         vpu_debug(DEBUG_EXTRA_INFO, "test index %d success\n", testidx);
3132
3133                         vpu_reg *reg = list_entry(session.done.next, vpu_reg, session_link);
3134
3135                         for (i=0; i<68; i++) {
3136                                 if (i % 4 == 0)
3137                                         printk("%02d: ", i);
3138                                 printk("%08x ", reg->reg[i]);
3139                                 if ((i+1) % 4 == 0)
3140                                         printk("\n");
3141                         }
3142
3143                         testidx++;
3144                 }
3145
3146                 reg_deinit(data, reg);
3147         }
3148
3149         return 0;
3150 }
3151
3152 #endif
3153